2 * (C) Copyright 2012 SAMSUNG Electronics
3 * Jaehoon Chung <jh80.chung@samsung.com>
4 * Rajeshawari Shinde <rajeshwari.s@samsung.com>
6 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm-generic/errno.h>
18 #define PAGE_SIZE 4096
20 static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
22 unsigned long timeout = 1000;
25 dwmci_writel(host, DWMCI_CTRL, value);
28 ctrl = dwmci_readl(host, DWMCI_CTRL);
29 if (!(ctrl & DWMCI_RESET_ALL))
35 static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
36 u32 desc0, u32 desc1, u32 desc2)
38 struct dwmci_idmac *desc = idmac;
43 desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
46 static void dwmci_prepare_data(struct dwmci_host *host,
47 struct mmc_data *data,
48 struct dwmci_idmac *cur_idmac,
52 unsigned int i = 0, flags, cnt, blk_cnt;
53 ulong data_start, data_end;
56 blk_cnt = data->blocks;
58 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
60 data_start = (ulong)cur_idmac;
61 dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);
64 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
65 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
67 flags |= DWMCI_IDMAC_LD;
68 cnt = data->blocksize * blk_cnt;
70 cnt = data->blocksize * 8;
72 dwmci_set_idma_desc(cur_idmac, flags, cnt,
73 (ulong)bounce_buffer + (i * PAGE_SIZE));
82 data_end = (ulong)cur_idmac;
83 flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
85 ctrl = dwmci_readl(host, DWMCI_CTRL);
86 ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
87 dwmci_writel(host, DWMCI_CTRL, ctrl);
89 ctrl = dwmci_readl(host, DWMCI_BMOD);
90 ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
91 dwmci_writel(host, DWMCI_BMOD, ctrl);
93 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
94 dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
97 static int dwmci_data_transfer(struct dwmci_host *host)
100 unsigned int timeout = 240000;
102 ulong start = get_timer(0);
105 mask = dwmci_readl(host, DWMCI_RINTSTS);
106 /* Error during data transfer. */
107 if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
108 debug("%s: DATA ERROR!\n", __func__);
113 /* Data arrived correctly. */
114 if (mask & DWMCI_INTMSK_DTO) {
119 /* Check for timeout. */
120 if (get_timer(start) > timeout) {
121 debug("%s: Timeout waiting for data!\n",
128 dwmci_writel(host, DWMCI_RINTSTS, mask);
133 static int dwmci_set_transfer_mode(struct dwmci_host *host,
134 struct mmc_data *data)
138 mode = DWMCI_CMD_DATA_EXP;
139 if (data->flags & MMC_DATA_WRITE)
140 mode |= DWMCI_CMD_RW;
145 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
146 struct mmc_data *data)
148 struct dwmci_host *host = mmc->priv;
149 ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
150 data ? DIV_ROUND_UP(data->blocks, 8) : 0);
151 int ret = 0, flags = 0, i;
152 unsigned int timeout = 100000;
155 ulong start = get_timer(0);
156 struct bounce_buffer bbstate;
158 while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
159 if (get_timer(start) > timeout) {
160 debug("%s: Timeout on data busy\n", __func__);
165 dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
168 if (data->flags == MMC_DATA_READ) {
169 bounce_buffer_start(&bbstate, (void*)data->dest,
171 data->blocks, GEN_BB_WRITE);
173 bounce_buffer_start(&bbstate, (void*)data->src,
175 data->blocks, GEN_BB_READ);
177 dwmci_prepare_data(host, data, cur_idmac,
178 bbstate.bounce_buffer);
181 dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
184 flags = dwmci_set_transfer_mode(host, data);
186 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
189 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
190 flags |= DWMCI_CMD_ABORT_STOP;
192 flags |= DWMCI_CMD_PRV_DAT_WAIT;
194 if (cmd->resp_type & MMC_RSP_PRESENT) {
195 flags |= DWMCI_CMD_RESP_EXP;
196 if (cmd->resp_type & MMC_RSP_136)
197 flags |= DWMCI_CMD_RESP_LENGTH;
200 if (cmd->resp_type & MMC_RSP_CRC)
201 flags |= DWMCI_CMD_CHECK_CRC;
203 flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
205 debug("Sending CMD%d\n",cmd->cmdidx);
207 dwmci_writel(host, DWMCI_CMD, flags);
209 for (i = 0; i < retry; i++) {
210 mask = dwmci_readl(host, DWMCI_RINTSTS);
211 if (mask & DWMCI_INTMSK_CDONE) {
213 dwmci_writel(host, DWMCI_RINTSTS, mask);
219 debug("%s: Timeout.\n", __func__);
223 if (mask & DWMCI_INTMSK_RTO) {
225 * Timeout here is not necessarily fatal. (e)MMC cards
226 * will splat here when they receive CMD55 as they do
227 * not support this command and that is exactly the way
228 * to tell them apart from SD cards. Thus, this output
229 * below shall be debug(). eMMC cards also do not favor
230 * CMD8, please keep that in mind.
232 debug("%s: Response Timeout.\n", __func__);
234 } else if (mask & DWMCI_INTMSK_RE) {
235 debug("%s: Response Error.\n", __func__);
240 if (cmd->resp_type & MMC_RSP_PRESENT) {
241 if (cmd->resp_type & MMC_RSP_136) {
242 cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
243 cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
244 cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
245 cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
247 cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
252 ret = dwmci_data_transfer(host);
254 ctrl = dwmci_readl(host, DWMCI_CTRL);
255 ctrl &= ~(DWMCI_DMA_EN);
256 dwmci_writel(host, DWMCI_CTRL, ctrl);
257 bounce_buffer_stop(&bbstate);
265 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
271 if ((freq == host->clock) || (freq == 0))
274 * If host->get_mmc_clk isn't defined,
275 * then assume that host->bus_hz is source clock value.
276 * host->bus_hz should be set by user.
278 if (host->get_mmc_clk)
279 sclk = host->get_mmc_clk(host, freq);
280 else if (host->bus_hz)
283 debug("%s: Didn't get source clock value.\n", __func__);
288 div = 0; /* bypass mode */
290 div = DIV_ROUND_UP(sclk, 2 * freq);
292 dwmci_writel(host, DWMCI_CLKENA, 0);
293 dwmci_writel(host, DWMCI_CLKSRC, 0);
295 dwmci_writel(host, DWMCI_CLKDIV, div);
296 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
297 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
300 status = dwmci_readl(host, DWMCI_CMD);
302 debug("%s: Timeout!\n", __func__);
305 } while (status & DWMCI_CMD_START);
307 dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
308 DWMCI_CLKEN_LOW_PWR);
310 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
311 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
315 status = dwmci_readl(host, DWMCI_CMD);
317 debug("%s: Timeout!\n", __func__);
320 } while (status & DWMCI_CMD_START);
327 static void dwmci_set_ios(struct mmc *mmc)
329 struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
332 debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
334 dwmci_setup_bus(host, mmc->clock);
335 switch (mmc->bus_width) {
337 ctype = DWMCI_CTYPE_8BIT;
340 ctype = DWMCI_CTYPE_4BIT;
343 ctype = DWMCI_CTYPE_1BIT;
347 dwmci_writel(host, DWMCI_CTYPE, ctype);
349 regs = dwmci_readl(host, DWMCI_UHS_REG);
351 regs |= DWMCI_DDR_MODE;
353 regs &= ~DWMCI_DDR_MODE;
355 dwmci_writel(host, DWMCI_UHS_REG, regs);
361 static int dwmci_init(struct mmc *mmc)
363 struct dwmci_host *host = mmc->priv;
365 if (host->board_init)
366 host->board_init(host);
368 dwmci_writel(host, DWMCI_PWREN, 1);
370 if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
371 debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
375 /* Enumerate at 400KHz */
376 dwmci_setup_bus(host, mmc->cfg->f_min);
378 dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
379 dwmci_writel(host, DWMCI_INTMASK, 0);
381 dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
383 dwmci_writel(host, DWMCI_IDINTEN, 0);
384 dwmci_writel(host, DWMCI_BMOD, 1);
386 if (!host->fifoth_val) {
389 fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
390 fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
391 host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
392 TX_WMARK(fifo_size / 2);
394 dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
396 dwmci_writel(host, DWMCI_CLKENA, 0);
397 dwmci_writel(host, DWMCI_CLKSRC, 0);
402 static const struct mmc_ops dwmci_ops = {
403 .send_cmd = dwmci_send_cmd,
404 .set_ios = dwmci_set_ios,
408 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
410 host->cfg.name = host->name;
411 host->cfg.ops = &dwmci_ops;
412 host->cfg.f_min = min_clk;
413 host->cfg.f_max = max_clk;
415 host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
417 host->cfg.host_caps = host->caps;
419 if (host->buswidth == 8) {
420 host->cfg.host_caps |= MMC_MODE_8BIT;
421 host->cfg.host_caps &= ~MMC_MODE_4BIT;
423 host->cfg.host_caps |= MMC_MODE_4BIT;
424 host->cfg.host_caps &= ~MMC_MODE_8BIT;
426 host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
428 host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
430 host->mmc = mmc_create(&host->cfg, host);
431 if (host->mmc == NULL)