2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
5 * Based vaguely on the pxa mmc code:
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #include <fsl_esdhc.h>
37 #include <fdt_support.h>
40 DECLARE_GLOBAL_DATA_PTR;
69 /* Return the XFERTYP flags for a given command and data packet */
70 uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
75 xfertyp |= XFERTYP_DPSEL;
76 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
77 xfertyp |= XFERTYP_DMAEN;
79 if (data->blocks > 1) {
80 xfertyp |= XFERTYP_MSBSEL;
81 xfertyp |= XFERTYP_BCEN;
82 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
83 xfertyp |= XFERTYP_AC12EN;
87 if (data->flags & MMC_DATA_READ)
88 xfertyp |= XFERTYP_DTDSEL;
91 if (cmd->resp_type & MMC_RSP_CRC)
92 xfertyp |= XFERTYP_CCCEN;
93 if (cmd->resp_type & MMC_RSP_OPCODE)
94 xfertyp |= XFERTYP_CICEN;
95 if (cmd->resp_type & MMC_RSP_136)
96 xfertyp |= XFERTYP_RSPTYP_136;
97 else if (cmd->resp_type & MMC_RSP_BUSY)
98 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
99 else if (cmd->resp_type & MMC_RSP_PRESENT)
100 xfertyp |= XFERTYP_RSPTYP_48;
103 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
104 xfertyp |= XFERTYP_CMDTYP_ABORT;
106 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
109 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
111 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
114 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
116 struct fsl_esdhc *regs = mmc->priv;
124 if (data->flags & MMC_DATA_READ) {
125 blocks = data->blocks;
128 timeout = PIO_TIMEOUT;
129 size = data->blocksize;
130 irqstat = esdhc_read32(®s->irqstat);
131 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)
134 printf("\nData Read Failed in PIO Mode.");
137 while (size && (!(irqstat & IRQSTAT_TC))) {
138 udelay(100); /* Wait before last byte transfer complete */
139 irqstat = esdhc_read32(®s->irqstat);
140 databuf = in_le32(®s->datport);
141 *((uint *)buffer) = databuf;
148 blocks = data->blocks;
149 buffer = (char *)data->src;
151 timeout = PIO_TIMEOUT;
152 size = data->blocksize;
153 irqstat = esdhc_read32(®s->irqstat);
154 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)
157 printf("\nData Write Failed in PIO Mode.");
160 while (size && (!(irqstat & IRQSTAT_TC))) {
161 udelay(100); /* Wait before last byte transfer complete */
162 databuf = *((uint *)buffer);
165 irqstat = esdhc_read32(®s->irqstat);
166 out_le32(®s->datport, databuf);
174 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
177 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
178 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
179 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
182 wml_value = data->blocksize/4;
184 if (data->flags & MMC_DATA_READ) {
185 if (wml_value > WML_RD_WML_MAX)
186 wml_value = WML_RD_WML_MAX_VAL;
188 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
189 esdhc_write32(®s->dsaddr, (u32)data->dest);
191 if (wml_value > WML_WR_WML_MAX)
192 wml_value = WML_WR_WML_MAX_VAL;
193 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
194 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
198 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
200 esdhc_write32(®s->dsaddr, (u32)data->src);
202 #else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
203 if (!(data->flags & MMC_DATA_READ)) {
204 if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
205 printf("\nThe SD card is locked. "
206 "Can not write to a locked card.\n\n");
209 esdhc_write32(®s->dsaddr, (u32)data->src);
211 esdhc_write32(®s->dsaddr, (u32)data->dest);
212 #endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
214 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
216 /* Calculate the timeout period for data transactions */
218 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
219 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
220 * So, Number of SD Clock cycles for 0.25sec should be minimum
221 * (SD Clock/sec * 0.25 sec) SD Clock cycles
222 * = (mmc->tran_speed * 1/4) SD Clock cycles
224 * => (2^(timeout+13)) >= mmc->tran_speed * 1/4
225 * Taking log2 both the sides
226 * => timeout + 13 >= log2(mmc->tran_speed/4)
227 * Rounding up to next power of 2
228 * => timeout + 13 = log2(mmc->tran_speed/4) + 1
229 * => timeout + 13 = fls(mmc->tran_speed/4)
231 timeout = fls(mmc->tran_speed/4);
240 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
241 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
245 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
252 * Sends a command out on the bus. Takes the mmc pointer,
253 * a command pointer, and an optional data pointer.
256 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
260 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
261 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
263 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
264 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
268 esdhc_write32(®s->irqstat, -1);
272 /* Wait for the bus to be idle */
273 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
274 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
277 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
280 /* Wait at least 8 SD clock cycles before the next command */
282 * Note: This is way more than 8 cycles, but 1ms seems to
283 * resolve timing issues with some cards
287 /* Set up for a data transfer if we have one */
291 err = esdhc_setup_data(mmc, data);
296 /* Figure out the transfer arguments */
297 xfertyp = esdhc_xfertyp(cmd, data);
299 /* Send the command */
300 esdhc_write32(®s->cmdarg, cmd->cmdarg);
301 esdhc_write32(®s->xfertyp, xfertyp);
303 /* Wait for the command to complete */
304 while (!(esdhc_read32(®s->irqstat) & IRQSTAT_CC))
307 irqstat = esdhc_read32(®s->irqstat);
308 esdhc_write32(®s->irqstat, irqstat);
310 if (irqstat & CMD_ERR)
313 if (irqstat & IRQSTAT_CTOE)
316 /* Copy the response to the response buffer */
317 if (cmd->resp_type & MMC_RSP_136) {
318 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
320 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
321 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
322 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
323 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
324 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
325 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
326 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
327 cmd->response[3] = (cmdrsp0 << 8);
329 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
331 /* Wait until all of the blocks are transferred */
333 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
334 esdhc_pio_read_write(mmc, data);
337 irqstat = esdhc_read32(®s->irqstat);
339 if (irqstat & IRQSTAT_DTOE)
342 if (irqstat & DATA_ERR)
344 } while (!(irqstat & IRQSTAT_TC) &&
345 (esdhc_read32(®s->prsstat) & PRSSTAT_DLA));
349 esdhc_write32(®s->irqstat, -1);
354 void set_sysctl(struct mmc *mmc, uint clock)
356 int sdhc_clk = gd->sdhc_clk;
358 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
359 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
362 if (clock < mmc->f_min)
365 if (sdhc_clk / 16 > clock) {
366 for (pre_div = 2; pre_div < 256; pre_div *= 2)
367 if ((sdhc_clk / pre_div) <= (clock * 16))
372 for (div = 1; div <= 16; div++)
373 if ((sdhc_clk / (div * pre_div)) <= clock)
379 clk = (pre_div << 8) | (div << 4);
381 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
383 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
387 clk = SYSCTL_PEREN | SYSCTL_CKEN;
389 esdhc_setbits32(®s->sysctl, clk);
392 static void esdhc_set_ios(struct mmc *mmc)
394 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
395 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
397 /* Set the clock speed */
398 set_sysctl(mmc, mmc->clock);
400 /* Set the bus width */
401 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
403 if (mmc->bus_width == 4)
404 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
405 else if (mmc->bus_width == 8)
406 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
410 static int esdhc_init(struct mmc *mmc)
412 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
413 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
418 /* Reset the entire host controller */
419 esdhc_write32(®s->sysctl, SYSCTL_RSTA);
421 /* Wait until the controller is available */
422 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
425 /* Enable cache snooping */
426 if (cfg && !cfg->no_snoop)
427 esdhc_write32(®s->scr, 0x00000040);
429 esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
431 /* Set the initial clock speed */
432 mmc_set_clock(mmc, 400000);
434 /* Disable the BRR and BWR bits in IRQSTAT */
435 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
437 /* Put the PROCTL reg back to the default */
438 esdhc_write32(®s->proctl, PROCTL_INIT);
440 /* Set timout to the maximum value */
441 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
443 /* Check if there is a callback for detecting the card */
444 if (board_mmc_getcd(&card_absent, mmc)) {
446 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) &&
460 static void esdhc_reset(struct fsl_esdhc *regs)
462 unsigned long timeout = 100; /* wait max 100 ms */
464 /* reset the controller */
465 esdhc_write32(®s->sysctl, SYSCTL_RSTA);
467 /* hardware clears the bit when it is done */
468 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
471 printf("MMC/SD: Reset never completed.\n");
474 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
476 struct fsl_esdhc *regs;
478 u32 caps, voltage_caps;
483 mmc = malloc(sizeof(struct mmc));
485 sprintf(mmc->name, "FSL_ESDHC");
486 regs = (struct fsl_esdhc *)cfg->esdhc_base;
488 /* First reset the eSDHC controller */
492 mmc->send_cmd = esdhc_send_cmd;
493 mmc->set_ios = esdhc_set_ios;
494 mmc->init = esdhc_init;
497 caps = regs->hostcapblt;
499 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
500 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
501 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
503 if (caps & ESDHC_HOSTCAPBLT_VS18)
504 voltage_caps |= MMC_VDD_165_195;
505 if (caps & ESDHC_HOSTCAPBLT_VS30)
506 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
507 if (caps & ESDHC_HOSTCAPBLT_VS33)
508 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
510 #ifdef CONFIG_SYS_SD_VOLTAGE
511 mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
513 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
515 if ((mmc->voltages & voltage_caps) == 0) {
516 printf("voltage not supported by controller\n");
520 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
522 if (caps & ESDHC_HOSTCAPBLT_HSS)
523 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
526 mmc->f_max = MIN(gd->sdhc_clk, 52000000);
533 int fsl_esdhc_mmc_init(bd_t *bis)
535 struct fsl_esdhc_cfg *cfg;
537 cfg = malloc(sizeof(struct fsl_esdhc_cfg));
538 memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
539 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
540 return fsl_esdhc_initialize(bis, cfg);
543 #ifdef CONFIG_OF_LIBFDT
544 void fdt_fixup_esdhc(void *blob, bd_t *bd)
546 const char *compat = "fsl,esdhc";
548 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
549 if (!hwconfig("esdhc")) {
550 do_fixup_by_compat(blob, compat, "status", "disabled",
556 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
559 do_fixup_by_compat(blob, compat, "status", "okay",