2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
5 * Based vaguely on the pxa mmc code:
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * SPDX-License-Identifier: GPL-2.0+
19 #include <power/regulator.h>
21 #include <fsl_esdhc.h>
22 #include <fdt_support.h>
25 #include <asm-generic/gpio.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
31 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
32 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
33 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
37 uint dsaddr; /* SDMA system address register */
38 uint blkattr; /* Block attributes register */
39 uint cmdarg; /* Command argument register */
40 uint xfertyp; /* Transfer type register */
41 uint cmdrsp0; /* Command response 0 register */
42 uint cmdrsp1; /* Command response 1 register */
43 uint cmdrsp2; /* Command response 2 register */
44 uint cmdrsp3; /* Command response 3 register */
45 uint datport; /* Buffer data port register */
46 uint prsstat; /* Present state register */
47 uint proctl; /* Protocol control register */
48 uint sysctl; /* System Control Register */
49 uint irqstat; /* Interrupt status register */
50 uint irqstaten; /* Interrupt status enable register */
51 uint irqsigen; /* Interrupt signal enable register */
52 uint autoc12err; /* Auto CMD error status register */
53 uint hostcapblt; /* Host controller capabilities register */
54 uint wml; /* Watermark level register */
55 uint mixctrl; /* For USDHC */
56 char reserved1[4]; /* reserved */
57 uint fevt; /* Force event register */
58 uint admaes; /* ADMA error status register */
59 uint adsaddr; /* ADMA system address register */
63 uint clktunectrlstatus;
69 uint hostver; /* Host controller version register */
70 char reserved5[4]; /* reserved */
71 uint dmaerraddr; /* DMA error address register */
72 char reserved6[4]; /* reserved */
73 uint dmaerrattr; /* DMA error attribute register */
74 char reserved7[4]; /* reserved */
75 uint hostcapblt2; /* Host controller capabilities register 2 */
76 char reserved8[8]; /* reserved */
77 uint tcr; /* Tuning control register */
78 char reserved9[28]; /* reserved */
79 uint sddirctl; /* SD direction control register */
80 char reserved10[712];/* reserved */
81 uint scr; /* eSDHC control register */
84 struct fsl_esdhc_plat {
85 struct mmc_config cfg;
90 * struct fsl_esdhc_priv
92 * @esdhc_regs: registers of the sdhc controller
93 * @sdhc_clk: Current clk of the sdhc controller
94 * @bus_width: bus width, 1bit, 4bit or 8bit
97 * Following is used when Driver Model is enabled for MMC
98 * @dev: pointer for the device
99 * @non_removable: 0: removable; 1: non-removable
100 * @wp_enable: 1: enable checking wp; 0: no check
101 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
102 * @cd_gpio: gpio for card detection
103 * @wp_gpio: gpio for write protection
105 struct fsl_esdhc_priv {
106 struct fsl_esdhc *esdhc_regs;
107 unsigned int sdhc_clk;
108 unsigned int bus_width;
114 #ifdef CONFIG_DM_GPIO
115 struct gpio_desc cd_gpio;
116 struct gpio_desc wp_gpio;
120 /* Return the XFERTYP flags for a given command and data packet */
121 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
126 xfertyp |= XFERTYP_DPSEL;
127 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
128 xfertyp |= XFERTYP_DMAEN;
130 if (data->blocks > 1) {
131 xfertyp |= XFERTYP_MSBSEL;
132 xfertyp |= XFERTYP_BCEN;
133 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
134 xfertyp |= XFERTYP_AC12EN;
138 if (data->flags & MMC_DATA_READ)
139 xfertyp |= XFERTYP_DTDSEL;
142 if (cmd->resp_type & MMC_RSP_CRC)
143 xfertyp |= XFERTYP_CCCEN;
144 if (cmd->resp_type & MMC_RSP_OPCODE)
145 xfertyp |= XFERTYP_CICEN;
146 if (cmd->resp_type & MMC_RSP_136)
147 xfertyp |= XFERTYP_RSPTYP_136;
148 else if (cmd->resp_type & MMC_RSP_BUSY)
149 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
150 else if (cmd->resp_type & MMC_RSP_PRESENT)
151 xfertyp |= XFERTYP_RSPTYP_48;
153 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
154 xfertyp |= XFERTYP_CMDTYP_ABORT;
156 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
159 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
161 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
163 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
164 struct mmc_data *data)
166 struct fsl_esdhc *regs = priv->esdhc_regs;
174 if (data->flags & MMC_DATA_READ) {
175 blocks = data->blocks;
178 timeout = PIO_TIMEOUT;
179 size = data->blocksize;
180 irqstat = esdhc_read32(®s->irqstat);
181 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)
184 printf("\nData Read Failed in PIO Mode.");
187 while (size && (!(irqstat & IRQSTAT_TC))) {
188 udelay(100); /* Wait before last byte transfer complete */
189 irqstat = esdhc_read32(®s->irqstat);
190 databuf = in_le32(®s->datport);
191 *((uint *)buffer) = databuf;
198 blocks = data->blocks;
199 buffer = (char *)data->src;
201 timeout = PIO_TIMEOUT;
202 size = data->blocksize;
203 irqstat = esdhc_read32(®s->irqstat);
204 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)
207 printf("\nData Write Failed in PIO Mode.");
210 while (size && (!(irqstat & IRQSTAT_TC))) {
211 udelay(100); /* Wait before last byte transfer complete */
212 databuf = *((uint *)buffer);
215 irqstat = esdhc_read32(®s->irqstat);
216 out_le32(®s->datport, databuf);
224 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
225 struct mmc_data *data)
228 struct fsl_esdhc *regs = priv->esdhc_regs;
229 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
234 wml_value = data->blocksize/4;
236 if (data->flags & MMC_DATA_READ) {
237 if (wml_value > WML_RD_WML_MAX)
238 wml_value = WML_RD_WML_MAX_VAL;
240 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
241 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
242 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
243 addr = virt_to_phys((void *)(data->dest));
244 if (upper_32_bits(addr))
245 printf("Error found for upper 32 bits\n");
247 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
249 esdhc_write32(®s->dsaddr, (u32)data->dest);
253 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
254 flush_dcache_range((ulong)data->src,
255 (ulong)data->src+data->blocks
258 if (wml_value > WML_WR_WML_MAX)
259 wml_value = WML_WR_WML_MAX_VAL;
260 if (priv->wp_enable) {
261 if ((esdhc_read32(®s->prsstat) &
262 PRSSTAT_WPSPL) == 0) {
263 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
268 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
270 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
271 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
272 addr = virt_to_phys((void *)(data->src));
273 if (upper_32_bits(addr))
274 printf("Error found for upper 32 bits\n");
276 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
278 esdhc_write32(®s->dsaddr, (u32)data->src);
283 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
285 /* Calculate the timeout period for data transactions */
287 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
288 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
289 * So, Number of SD Clock cycles for 0.25sec should be minimum
290 * (SD Clock/sec * 0.25 sec) SD Clock cycles
291 * = (mmc->clock * 1/4) SD Clock cycles
293 * => (2^(timeout+13)) >= mmc->clock * 1/4
294 * Taking log2 both the sides
295 * => timeout + 13 >= log2(mmc->clock/4)
296 * Rounding up to next power of 2
297 * => timeout + 13 = log2(mmc->clock/4) + 1
298 * => timeout + 13 = fls(mmc->clock/4)
300 * However, the MMC spec "It is strongly recommended for hosts to
301 * implement more than 500ms timeout value even if the card
302 * indicates the 250ms maximum busy length." Even the previous
303 * value of 300ms is known to be insufficient for some cards.
305 * => timeout + 13 = fls(mmc->clock/2)
307 timeout = fls(mmc->clock/2);
316 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
317 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
321 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
324 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
329 static void check_and_invalidate_dcache_range
330 (struct mmc_cmd *cmd,
331 struct mmc_data *data) {
334 unsigned size = roundup(ARCH_DMA_MINALIGN,
335 data->blocks*data->blocksize);
336 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
339 addr = virt_to_phys((void *)(data->dest));
340 if (upper_32_bits(addr))
341 printf("Error found for upper 32 bits\n");
343 start = lower_32_bits(addr);
345 start = (unsigned)data->dest;
348 invalidate_dcache_range(start, end);
352 * Sends a command out on the bus. Takes the mmc pointer,
353 * a command pointer, and an optional data pointer.
355 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
356 struct mmc_cmd *cmd, struct mmc_data *data)
361 struct fsl_esdhc *regs = priv->esdhc_regs;
363 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
364 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
368 esdhc_write32(®s->irqstat, -1);
372 /* Wait for the bus to be idle */
373 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
374 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
377 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
380 /* Wait at least 8 SD clock cycles before the next command */
382 * Note: This is way more than 8 cycles, but 1ms seems to
383 * resolve timing issues with some cards
387 /* Set up for a data transfer if we have one */
389 err = esdhc_setup_data(priv, mmc, data);
393 if (data->flags & MMC_DATA_READ)
394 check_and_invalidate_dcache_range(cmd, data);
397 /* Figure out the transfer arguments */
398 xfertyp = esdhc_xfertyp(cmd, data);
401 esdhc_write32(®s->irqsigen, 0);
403 /* Send the command */
404 esdhc_write32(®s->cmdarg, cmd->cmdarg);
405 #if defined(CONFIG_FSL_USDHC)
406 esdhc_write32(®s->mixctrl,
407 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
408 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
409 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
411 esdhc_write32(®s->xfertyp, xfertyp);
414 /* Wait for the command to complete */
415 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
418 irqstat = esdhc_read32(®s->irqstat);
420 if (irqstat & CMD_ERR) {
425 if (irqstat & IRQSTAT_CTOE) {
430 /* Switch voltage to 1.8V if CMD11 succeeded */
431 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
432 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
434 printf("Run CMD11 1.8V switch\n");
435 /* Sleep for 5 ms - max time for card to switch to 1.8V */
439 /* Workaround for ESDHC errata ENGcm03648 */
440 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
443 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
444 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
451 printf("Timeout waiting for DAT0 to go high!\n");
457 /* Copy the response to the response buffer */
458 if (cmd->resp_type & MMC_RSP_136) {
459 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
461 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
462 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
463 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
464 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
465 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
466 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
467 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
468 cmd->response[3] = (cmdrsp0 << 8);
470 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
472 /* Wait until all of the blocks are transferred */
474 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
475 esdhc_pio_read_write(priv, data);
478 irqstat = esdhc_read32(®s->irqstat);
480 if (irqstat & IRQSTAT_DTOE) {
485 if (irqstat & DATA_ERR) {
489 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
492 * Need invalidate the dcache here again to avoid any
493 * cache-fill during the DMA operations such as the
494 * speculative pre-fetching etc.
496 if (data->flags & MMC_DATA_READ)
497 check_and_invalidate_dcache_range(cmd, data);
502 /* Reset CMD and DATA portions on error */
504 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
506 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
510 esdhc_write32(®s->sysctl,
511 esdhc_read32(®s->sysctl) |
513 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
517 /* If this was CMD11, then notify that power cycle is needed */
518 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
519 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
522 esdhc_write32(®s->irqstat, -1);
527 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
535 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
536 struct fsl_esdhc *regs = priv->esdhc_regs;
537 int sdhc_clk = priv->sdhc_clk;
540 if (clock < mmc->cfg->f_min)
541 clock = mmc->cfg->f_min;
543 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
546 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
552 clk = (pre_div << 8) | (div << 4);
554 #ifdef CONFIG_FSL_USDHC
555 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
557 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
560 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
564 #ifdef CONFIG_FSL_USDHC
565 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
567 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
572 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
573 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
575 struct fsl_esdhc *regs = priv->esdhc_regs;
579 value = esdhc_read32(®s->sysctl);
582 value |= SYSCTL_CKEN;
584 value &= ~SYSCTL_CKEN;
586 esdhc_write32(®s->sysctl, value);
589 value = PRSSTAT_SDSTB;
590 while (!(esdhc_read32(®s->prsstat) & value)) {
592 printf("fsl_esdhc: Internal clock never stabilised.\n");
601 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
603 struct fsl_esdhc *regs = priv->esdhc_regs;
605 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
606 /* Select to use peripheral clock */
607 esdhc_clock_control(priv, false);
608 esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
609 esdhc_clock_control(priv, true);
611 /* Set the clock speed */
612 set_sysctl(priv, mmc, mmc->clock);
614 /* Set the bus width */
615 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
617 if (mmc->bus_width == 4)
618 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
619 else if (mmc->bus_width == 8)
620 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
625 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
627 struct fsl_esdhc *regs = priv->esdhc_regs;
630 /* Reset the entire host controller */
631 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
633 /* Wait until the controller is available */
634 start = get_timer(0);
635 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
636 if (get_timer(start) > 1000)
640 #if defined(CONFIG_FSL_USDHC)
641 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
642 esdhc_write32(®s->mmcboot, 0x0);
643 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
644 esdhc_write32(®s->mixctrl, 0x0);
645 esdhc_write32(®s->clktunectrlstatus, 0x0);
647 /* Put VEND_SPEC to default value */
648 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
650 /* Disable DLL_CTRL delay line */
651 esdhc_write32(®s->dllctrl, 0x0);
655 /* Enable cache snooping */
656 esdhc_write32(®s->scr, 0x00000040);
659 #ifndef CONFIG_FSL_USDHC
660 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
662 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
665 /* Set the initial clock speed */
666 mmc_set_clock(mmc, 400000);
668 /* Disable the BRR and BWR bits in IRQSTAT */
669 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
671 /* Put the PROCTL reg back to the default */
672 esdhc_write32(®s->proctl, PROCTL_INIT);
674 /* Set timout to the maximum value */
675 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
677 if (priv->vs18_enable)
678 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
683 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
685 struct fsl_esdhc *regs = priv->esdhc_regs;
688 #ifdef CONFIG_ESDHC_DETECT_QUIRK
689 if (CONFIG_ESDHC_DETECT_QUIRK)
694 if (priv->non_removable)
696 #ifdef CONFIG_DM_GPIO
697 if (dm_gpio_is_valid(&priv->cd_gpio))
698 return dm_gpio_get_value(&priv->cd_gpio);
702 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
708 static int esdhc_reset(struct fsl_esdhc *regs)
712 /* reset the controller */
713 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
715 /* hardware clears the bit when it is done */
716 start = get_timer(0);
717 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
718 if (get_timer(start) > 100) {
719 printf("MMC/SD: Reset never completed.\n");
727 static int esdhc_getcd(struct mmc *mmc)
729 struct fsl_esdhc_priv *priv = mmc->priv;
731 return esdhc_getcd_common(priv);
734 static int esdhc_init(struct mmc *mmc)
736 struct fsl_esdhc_priv *priv = mmc->priv;
738 return esdhc_init_common(priv, mmc);
741 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
742 struct mmc_data *data)
744 struct fsl_esdhc_priv *priv = mmc->priv;
746 return esdhc_send_cmd_common(priv, mmc, cmd, data);
749 static int esdhc_set_ios(struct mmc *mmc)
751 struct fsl_esdhc_priv *priv = mmc->priv;
753 return esdhc_set_ios_common(priv, mmc);
756 static const struct mmc_ops esdhc_ops = {
757 .getcd = esdhc_getcd,
759 .send_cmd = esdhc_send_cmd,
760 .set_ios = esdhc_set_ios,
763 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
764 struct fsl_esdhc_plat *plat)
766 struct mmc_config *cfg;
767 struct fsl_esdhc *regs;
769 u32 caps, voltage_caps;
775 regs = priv->esdhc_regs;
777 /* First reset the eSDHC controller */
778 ret = esdhc_reset(regs);
782 #ifndef CONFIG_FSL_USDHC
783 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
784 | SYSCTL_IPGEN | SYSCTL_CKEN);
786 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
787 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
790 if (priv->vs18_enable)
791 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
793 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
795 memset(cfg, '\0', sizeof(*cfg));
798 caps = esdhc_read32(®s->hostcapblt);
800 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
801 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
802 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
805 /* T4240 host controller capabilities register should have VS33 bit */
806 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
807 caps = caps | ESDHC_HOSTCAPBLT_VS33;
810 if (caps & ESDHC_HOSTCAPBLT_VS18)
811 voltage_caps |= MMC_VDD_165_195;
812 if (caps & ESDHC_HOSTCAPBLT_VS30)
813 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
814 if (caps & ESDHC_HOSTCAPBLT_VS33)
815 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
817 cfg->name = "FSL_SDHC";
818 cfg->ops = &esdhc_ops;
819 #ifdef CONFIG_SYS_SD_VOLTAGE
820 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
822 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
824 if ((cfg->voltages & voltage_caps) == 0) {
825 printf("voltage not supported by controller\n");
829 if (priv->bus_width == 8)
830 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
831 else if (priv->bus_width == 4)
832 cfg->host_caps = MMC_MODE_4BIT;
834 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
835 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
836 cfg->host_caps |= MMC_MODE_DDR_52MHz;
839 if (priv->bus_width > 0) {
840 if (priv->bus_width < 8)
841 cfg->host_caps &= ~MMC_MODE_8BIT;
842 if (priv->bus_width < 4)
843 cfg->host_caps &= ~MMC_MODE_4BIT;
846 if (caps & ESDHC_HOSTCAPBLT_HSS)
847 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
849 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
850 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
851 cfg->host_caps &= ~MMC_MODE_8BIT;
855 cfg->f_max = min(priv->sdhc_clk, (u32)52000000);
857 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
859 mmc = mmc_create(cfg, priv);
868 #ifndef CONFIG_DM_MMC
869 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
870 struct fsl_esdhc_priv *priv)
875 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
876 priv->bus_width = cfg->max_bus_width;
877 priv->sdhc_clk = cfg->sdhc_clk;
878 priv->wp_enable = cfg->wp_enable;
879 priv->vs18_enable = cfg->vs18_enable;
884 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
886 struct fsl_esdhc_plat *plat;
887 struct fsl_esdhc_priv *priv;
893 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
896 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
902 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
904 debug("%s xlate failure\n", __func__);
910 ret = fsl_esdhc_init(priv, plat);
912 debug("%s init failure\n", __func__);
921 int fsl_esdhc_mmc_init(bd_t *bis)
923 struct fsl_esdhc_cfg *cfg;
925 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
926 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
927 cfg->sdhc_clk = gd->arch.sdhc_clk;
928 return fsl_esdhc_initialize(bis, cfg);
932 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
933 void mmc_adapter_card_type_ident(void)
938 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
939 gd->arch.sdhc_adapter = card_id;
942 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
943 value = QIXIS_READ(brdcfg[5]);
944 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
945 QIXIS_WRITE(brdcfg[5], value);
947 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
948 value = QIXIS_READ(pwr_ctl[1]);
949 value |= QIXIS_EVDD_BY_SDHC_VS;
950 QIXIS_WRITE(pwr_ctl[1], value);
952 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
953 value = QIXIS_READ(brdcfg[5]);
954 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
955 QIXIS_WRITE(brdcfg[5], value);
957 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
959 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
961 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
963 case QIXIS_ESDHC_NO_ADAPTER:
971 #ifdef CONFIG_OF_LIBFDT
972 __weak int esdhc_status_fixup(void *blob, const char *compat)
974 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
975 if (!hwconfig("esdhc")) {
976 do_fixup_by_compat(blob, compat, "status", "disabled",
977 sizeof("disabled"), 1);
984 void fdt_fixup_esdhc(void *blob, bd_t *bd)
986 const char *compat = "fsl,esdhc";
988 if (esdhc_status_fixup(blob, compat))
991 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
992 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
993 gd->arch.sdhc_clk, 1);
995 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
996 gd->arch.sdhc_clk, 1);
998 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
999 do_fixup_by_compat_u32(blob, compat, "adapter-type",
1000 (u32)(gd->arch.sdhc_adapter), 1);
1005 #ifdef CONFIG_DM_MMC
1006 #include <asm/arch/clock.h>
1007 __weak void init_clk_usdhc(u32 index)
1011 static int fsl_esdhc_probe(struct udevice *dev)
1013 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1014 struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1015 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1016 const void *fdt = gd->fdt_blob;
1017 int node = dev_of_offset(dev);
1018 #ifdef CONFIG_DM_REGULATOR
1019 struct udevice *vqmmc_dev;
1025 addr = devfdt_get_addr(dev);
1026 if (addr == FDT_ADDR_T_NONE)
1029 priv->esdhc_regs = (struct fsl_esdhc *)addr;
1032 val = fdtdec_get_int(fdt, node, "bus-width", -1);
1034 priv->bus_width = 8;
1036 priv->bus_width = 4;
1038 priv->bus_width = 1;
1040 if (fdt_get_property(fdt, node, "non-removable", NULL)) {
1041 priv->non_removable = 1;
1043 priv->non_removable = 0;
1044 #ifdef CONFIG_DM_GPIO
1045 gpio_request_by_name_nodev(offset_to_ofnode(node), "cd-gpios",
1046 0, &priv->cd_gpio, GPIOD_IS_IN);
1050 priv->wp_enable = 1;
1052 #ifdef CONFIG_DM_GPIO
1053 ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "wp-gpios", 0,
1054 &priv->wp_gpio, GPIOD_IS_IN);
1056 priv->wp_enable = 0;
1059 priv->vs18_enable = 0;
1061 #ifdef CONFIG_DM_REGULATOR
1063 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1064 * otherwise, emmc will work abnormally.
1066 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1068 dev_dbg(dev, "no vqmmc-supply\n");
1070 ret = regulator_set_enable(vqmmc_dev, true);
1072 dev_err(dev, "fail to enable vqmmc-supply\n");
1076 if (regulator_get_value(vqmmc_dev) == 1800000)
1077 priv->vs18_enable = 1;
1083 * Because lack of clk driver, if SDHC clk is not enabled,
1084 * need to enable it first before this driver is invoked.
1086 * we use MXC_ESDHC_CLK to get clk freq.
1087 * If one would like to make this function work,
1088 * the aliases should be provided in dts as this:
1096 * Then if your board only supports mmc2 and mmc3, but we can
1097 * correctly get the seq as 2 and 3, then let mxc_get_clock
1101 init_clk_usdhc(dev->seq);
1103 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1104 if (priv->sdhc_clk <= 0) {
1105 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1109 ret = fsl_esdhc_init(priv, plat);
1111 dev_err(dev, "fsl_esdhc_init failure\n");
1115 upriv->mmc = priv->mmc;
1116 priv->mmc->dev = dev;
1121 static const struct udevice_id fsl_esdhc_ids[] = {
1122 { .compatible = "fsl,imx6ul-usdhc", },
1123 { .compatible = "fsl,imx6sx-usdhc", },
1124 { .compatible = "fsl,imx6sl-usdhc", },
1125 { .compatible = "fsl,imx6q-usdhc", },
1126 { .compatible = "fsl,imx7d-usdhc", },
1127 { .compatible = "fsl,imx7ulp-usdhc", },
1128 { .compatible = "fsl,esdhc", },
1132 U_BOOT_DRIVER(fsl_esdhc) = {
1133 .name = "fsl-esdhc-mmc",
1135 .of_match = fsl_esdhc_ids,
1136 .probe = fsl_esdhc_probe,
1137 .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
1138 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),