2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
5 * Based vaguely on the pxa mmc code:
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
9 * SPDX-License-Identifier: GPL-2.0+
20 #include <fsl_esdhc.h>
21 #include <fdt_support.h>
24 #include <asm-generic/gpio.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
30 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
31 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
32 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
36 uint dsaddr; /* SDMA system address register */
37 uint blkattr; /* Block attributes register */
38 uint cmdarg; /* Command argument register */
39 uint xfertyp; /* Transfer type register */
40 uint cmdrsp0; /* Command response 0 register */
41 uint cmdrsp1; /* Command response 1 register */
42 uint cmdrsp2; /* Command response 2 register */
43 uint cmdrsp3; /* Command response 3 register */
44 uint datport; /* Buffer data port register */
45 uint prsstat; /* Present state register */
46 uint proctl; /* Protocol control register */
47 uint sysctl; /* System Control Register */
48 uint irqstat; /* Interrupt status register */
49 uint irqstaten; /* Interrupt status enable register */
50 uint irqsigen; /* Interrupt signal enable register */
51 uint autoc12err; /* Auto CMD error status register */
52 uint hostcapblt; /* Host controller capabilities register */
53 uint wml; /* Watermark level register */
54 uint mixctrl; /* For USDHC */
55 char reserved1[4]; /* reserved */
56 uint fevt; /* Force event register */
57 uint admaes; /* ADMA error status register */
58 uint adsaddr; /* ADMA system address register */
62 uint clktunectrlstatus;
68 uint hostver; /* Host controller version register */
69 char reserved5[4]; /* reserved */
70 uint dmaerraddr; /* DMA error address register */
71 char reserved6[4]; /* reserved */
72 uint dmaerrattr; /* DMA error attribute register */
73 char reserved7[4]; /* reserved */
74 uint hostcapblt2; /* Host controller capabilities register 2 */
75 char reserved8[8]; /* reserved */
76 uint tcr; /* Tuning control register */
77 char reserved9[28]; /* reserved */
78 uint sddirctl; /* SD direction control register */
79 char reserved10[712];/* reserved */
80 uint scr; /* eSDHC control register */
84 * struct fsl_esdhc_priv
86 * @esdhc_regs: registers of the sdhc controller
87 * @sdhc_clk: Current clk of the sdhc controller
88 * @bus_width: bus width, 1bit, 4bit or 8bit
91 * Following is used when Driver Model is enabled for MMC
92 * @dev: pointer for the device
93 * @non_removable: 0: removable; 1: non-removable
94 * @wp_enable: 1: enable checking wp; 0: no check
95 * @cd_gpio: gpio for card detection
96 * @wp_gpio: gpio for write protection
98 struct fsl_esdhc_priv {
99 struct fsl_esdhc *esdhc_regs;
100 unsigned int sdhc_clk;
101 unsigned int bus_width;
102 struct mmc_config cfg;
107 struct gpio_desc cd_gpio;
108 struct gpio_desc wp_gpio;
111 /* Return the XFERTYP flags for a given command and data packet */
112 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
117 xfertyp |= XFERTYP_DPSEL;
118 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
119 xfertyp |= XFERTYP_DMAEN;
121 if (data->blocks > 1) {
122 xfertyp |= XFERTYP_MSBSEL;
123 xfertyp |= XFERTYP_BCEN;
124 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
125 xfertyp |= XFERTYP_AC12EN;
129 if (data->flags & MMC_DATA_READ)
130 xfertyp |= XFERTYP_DTDSEL;
133 if (cmd->resp_type & MMC_RSP_CRC)
134 xfertyp |= XFERTYP_CCCEN;
135 if (cmd->resp_type & MMC_RSP_OPCODE)
136 xfertyp |= XFERTYP_CICEN;
137 if (cmd->resp_type & MMC_RSP_136)
138 xfertyp |= XFERTYP_RSPTYP_136;
139 else if (cmd->resp_type & MMC_RSP_BUSY)
140 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
141 else if (cmd->resp_type & MMC_RSP_PRESENT)
142 xfertyp |= XFERTYP_RSPTYP_48;
144 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
145 xfertyp |= XFERTYP_CMDTYP_ABORT;
147 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
150 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
152 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
155 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
157 struct fsl_esdhc_priv *priv = mmc->priv;
158 struct fsl_esdhc *regs = priv->esdhc_regs;
166 if (data->flags & MMC_DATA_READ) {
167 blocks = data->blocks;
170 timeout = PIO_TIMEOUT;
171 size = data->blocksize;
172 irqstat = esdhc_read32(®s->irqstat);
173 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)
176 printf("\nData Read Failed in PIO Mode.");
179 while (size && (!(irqstat & IRQSTAT_TC))) {
180 udelay(100); /* Wait before last byte transfer complete */
181 irqstat = esdhc_read32(®s->irqstat);
182 databuf = in_le32(®s->datport);
183 *((uint *)buffer) = databuf;
190 blocks = data->blocks;
191 buffer = (char *)data->src;
193 timeout = PIO_TIMEOUT;
194 size = data->blocksize;
195 irqstat = esdhc_read32(®s->irqstat);
196 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)
199 printf("\nData Write Failed in PIO Mode.");
202 while (size && (!(irqstat & IRQSTAT_TC))) {
203 udelay(100); /* Wait before last byte transfer complete */
204 databuf = *((uint *)buffer);
207 irqstat = esdhc_read32(®s->irqstat);
208 out_le32(®s->datport, databuf);
216 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
219 struct fsl_esdhc_priv *priv = mmc->priv;
220 struct fsl_esdhc *regs = priv->esdhc_regs;
221 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
226 wml_value = data->blocksize/4;
228 if (data->flags & MMC_DATA_READ) {
229 if (wml_value > WML_RD_WML_MAX)
230 wml_value = WML_RD_WML_MAX_VAL;
232 esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
233 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
234 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
235 addr = virt_to_phys((void *)(data->dest));
236 if (upper_32_bits(addr))
237 printf("Error found for upper 32 bits\n");
239 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
241 esdhc_write32(®s->dsaddr, (u32)data->dest);
245 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
246 flush_dcache_range((ulong)data->src,
247 (ulong)data->src+data->blocks
250 if (wml_value > WML_WR_WML_MAX)
251 wml_value = WML_WR_WML_MAX_VAL;
252 if (priv->wp_enable) {
253 if ((esdhc_read32(®s->prsstat) &
254 PRSSTAT_WPSPL) == 0) {
255 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
260 esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
262 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
263 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
264 addr = virt_to_phys((void *)(data->src));
265 if (upper_32_bits(addr))
266 printf("Error found for upper 32 bits\n");
268 esdhc_write32(®s->dsaddr, lower_32_bits(addr));
270 esdhc_write32(®s->dsaddr, (u32)data->src);
275 esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
277 /* Calculate the timeout period for data transactions */
279 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
280 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
281 * So, Number of SD Clock cycles for 0.25sec should be minimum
282 * (SD Clock/sec * 0.25 sec) SD Clock cycles
283 * = (mmc->clock * 1/4) SD Clock cycles
285 * => (2^(timeout+13)) >= mmc->clock * 1/4
286 * Taking log2 both the sides
287 * => timeout + 13 >= log2(mmc->clock/4)
288 * Rounding up to next power of 2
289 * => timeout + 13 = log2(mmc->clock/4) + 1
290 * => timeout + 13 = fls(mmc->clock/4)
292 * However, the MMC spec "It is strongly recommended for hosts to
293 * implement more than 500ms timeout value even if the card
294 * indicates the 250ms maximum busy length." Even the previous
295 * value of 300ms is known to be insufficient for some cards.
297 * => timeout + 13 = fls(mmc->clock/2)
299 timeout = fls(mmc->clock/2);
308 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
309 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
313 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
316 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
321 static void check_and_invalidate_dcache_range
322 (struct mmc_cmd *cmd,
323 struct mmc_data *data) {
326 unsigned size = roundup(ARCH_DMA_MINALIGN,
327 data->blocks*data->blocksize);
328 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234)
331 addr = virt_to_phys((void *)(data->dest));
332 if (upper_32_bits(addr))
333 printf("Error found for upper 32 bits\n");
335 start = lower_32_bits(addr);
337 start = (unsigned)data->dest;
340 invalidate_dcache_range(start, end);
344 * Sends a command out on the bus. Takes the mmc pointer,
345 * a command pointer, and an optional data pointer.
348 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
353 struct fsl_esdhc_priv *priv = mmc->priv;
354 struct fsl_esdhc *regs = priv->esdhc_regs;
356 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
357 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
361 esdhc_write32(®s->irqstat, -1);
365 /* Wait for the bus to be idle */
366 while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
367 (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
370 while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
373 /* Wait at least 8 SD clock cycles before the next command */
375 * Note: This is way more than 8 cycles, but 1ms seems to
376 * resolve timing issues with some cards
380 /* Set up for a data transfer if we have one */
382 err = esdhc_setup_data(mmc, data);
386 if (data->flags & MMC_DATA_READ)
387 check_and_invalidate_dcache_range(cmd, data);
390 /* Figure out the transfer arguments */
391 xfertyp = esdhc_xfertyp(cmd, data);
394 esdhc_write32(®s->irqsigen, 0);
396 /* Send the command */
397 esdhc_write32(®s->cmdarg, cmd->cmdarg);
398 #if defined(CONFIG_FSL_USDHC)
399 esdhc_write32(®s->mixctrl,
400 (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
401 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
402 esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000);
404 esdhc_write32(®s->xfertyp, xfertyp);
407 /* Wait for the command to complete */
408 while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
411 irqstat = esdhc_read32(®s->irqstat);
413 if (irqstat & CMD_ERR) {
418 if (irqstat & IRQSTAT_CTOE) {
423 /* Switch voltage to 1.8V if CMD11 succeeded */
424 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
425 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
427 printf("Run CMD11 1.8V switch\n");
428 /* Sleep for 5 ms - max time for card to switch to 1.8V */
432 /* Workaround for ESDHC errata ENGcm03648 */
433 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
436 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
437 while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
444 printf("Timeout waiting for DAT0 to go high!\n");
450 /* Copy the response to the response buffer */
451 if (cmd->resp_type & MMC_RSP_136) {
452 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
454 cmdrsp3 = esdhc_read32(®s->cmdrsp3);
455 cmdrsp2 = esdhc_read32(®s->cmdrsp2);
456 cmdrsp1 = esdhc_read32(®s->cmdrsp1);
457 cmdrsp0 = esdhc_read32(®s->cmdrsp0);
458 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
459 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
460 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
461 cmd->response[3] = (cmdrsp0 << 8);
463 cmd->response[0] = esdhc_read32(®s->cmdrsp0);
465 /* Wait until all of the blocks are transferred */
467 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
468 esdhc_pio_read_write(mmc, data);
471 irqstat = esdhc_read32(®s->irqstat);
473 if (irqstat & IRQSTAT_DTOE) {
478 if (irqstat & DATA_ERR) {
482 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
485 * Need invalidate the dcache here again to avoid any
486 * cache-fill during the DMA operations such as the
487 * speculative pre-fetching etc.
489 if (data->flags & MMC_DATA_READ)
490 check_and_invalidate_dcache_range(cmd, data);
495 /* Reset CMD and DATA portions on error */
497 esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
499 while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
503 esdhc_write32(®s->sysctl,
504 esdhc_read32(®s->sysctl) |
506 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
510 /* If this was CMD11, then notify that power cycle is needed */
511 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
512 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
515 esdhc_write32(®s->irqstat, -1);
520 static void set_sysctl(struct mmc *mmc, uint clock)
523 struct fsl_esdhc_priv *priv = mmc->priv;
524 struct fsl_esdhc *regs = priv->esdhc_regs;
525 int sdhc_clk = priv->sdhc_clk;
528 if (clock < mmc->cfg->f_min)
529 clock = mmc->cfg->f_min;
531 if (sdhc_clk / 16 > clock) {
532 for (pre_div = 2; pre_div < 256; pre_div *= 2)
533 if ((sdhc_clk / pre_div) <= (clock * 16))
538 for (div = 1; div <= 16; div++)
539 if ((sdhc_clk / (div * pre_div)) <= clock)
542 pre_div >>= mmc->ddr_mode ? 2 : 1;
545 clk = (pre_div << 8) | (div << 4);
547 #ifdef CONFIG_FSL_USDHC
548 esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
550 esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
553 esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
557 #ifdef CONFIG_FSL_USDHC
558 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
560 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
565 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
566 static void esdhc_clock_control(struct mmc *mmc, bool enable)
568 struct fsl_esdhc_priv *priv = mmc->priv;
569 struct fsl_esdhc *regs = priv->esdhc_regs;
573 value = esdhc_read32(®s->sysctl);
576 value |= SYSCTL_CKEN;
578 value &= ~SYSCTL_CKEN;
580 esdhc_write32(®s->sysctl, value);
583 value = PRSSTAT_SDSTB;
584 while (!(esdhc_read32(®s->prsstat) & value)) {
586 printf("fsl_esdhc: Internal clock never stabilised.\n");
595 static int esdhc_set_ios(struct mmc *mmc)
597 struct fsl_esdhc_priv *priv = mmc->priv;
598 struct fsl_esdhc *regs = priv->esdhc_regs;
600 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
601 /* Select to use peripheral clock */
602 esdhc_clock_control(mmc, false);
603 esdhc_setbits32(®s->scr, ESDHCCTL_PCS);
604 esdhc_clock_control(mmc, true);
606 /* Set the clock speed */
607 set_sysctl(mmc, mmc->clock);
609 /* Set the bus width */
610 esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
612 if (mmc->bus_width == 4)
613 esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
614 else if (mmc->bus_width == 8)
615 esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
620 static int esdhc_init(struct mmc *mmc)
622 struct fsl_esdhc_priv *priv = mmc->priv;
623 struct fsl_esdhc *regs = priv->esdhc_regs;
626 /* Reset the entire host controller */
627 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
629 /* Wait until the controller is available */
630 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
633 #if defined(CONFIG_FSL_USDHC)
634 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
635 esdhc_write32(®s->mmcboot, 0x0);
636 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
637 esdhc_write32(®s->mixctrl, 0x0);
638 esdhc_write32(®s->clktunectrlstatus, 0x0);
640 /* Put VEND_SPEC to default value */
641 esdhc_write32(®s->vendorspec, VENDORSPEC_INIT);
643 /* Disable DLL_CTRL delay line */
644 esdhc_write32(®s->dllctrl, 0x0);
648 /* Enable cache snooping */
649 esdhc_write32(®s->scr, 0x00000040);
652 #ifndef CONFIG_FSL_USDHC
653 esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
655 esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
658 /* Set the initial clock speed */
659 mmc_set_clock(mmc, 400000);
661 /* Disable the BRR and BWR bits in IRQSTAT */
662 esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
664 /* Put the PROCTL reg back to the default */
665 esdhc_write32(®s->proctl, PROCTL_INIT);
667 /* Set timout to the maximum value */
668 esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
670 #ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
671 esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT);
677 static int esdhc_getcd(struct mmc *mmc)
679 struct fsl_esdhc_priv *priv = mmc->priv;
680 struct fsl_esdhc *regs = priv->esdhc_regs;
683 #ifdef CONFIG_ESDHC_DETECT_QUIRK
684 if (CONFIG_ESDHC_DETECT_QUIRK)
689 if (priv->non_removable)
692 if (dm_gpio_is_valid(&priv->cd_gpio))
693 return dm_gpio_get_value(&priv->cd_gpio);
696 while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
702 static void esdhc_reset(struct fsl_esdhc *regs)
704 unsigned long timeout = 100; /* wait max 100 ms */
706 /* reset the controller */
707 esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
709 /* hardware clears the bit when it is done */
710 while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
713 printf("MMC/SD: Reset never completed.\n");
716 static const struct mmc_ops esdhc_ops = {
717 .send_cmd = esdhc_send_cmd,
718 .set_ios = esdhc_set_ios,
720 .getcd = esdhc_getcd,
723 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
724 struct fsl_esdhc_priv *priv)
729 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
730 priv->bus_width = cfg->max_bus_width;
731 priv->sdhc_clk = cfg->sdhc_clk;
732 priv->wp_enable = cfg->wp_enable;
737 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
739 struct fsl_esdhc *regs;
741 u32 caps, voltage_caps;
746 regs = priv->esdhc_regs;
748 /* First reset the eSDHC controller */
751 #ifndef CONFIG_FSL_USDHC
752 esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
753 | SYSCTL_IPGEN | SYSCTL_CKEN);
755 esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
756 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
759 writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
760 memset(&priv->cfg, 0, sizeof(priv->cfg));
763 caps = esdhc_read32(®s->hostcapblt);
765 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
766 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
767 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
770 /* T4240 host controller capabilities register should have VS33 bit */
771 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
772 caps = caps | ESDHC_HOSTCAPBLT_VS33;
775 if (caps & ESDHC_HOSTCAPBLT_VS18)
776 voltage_caps |= MMC_VDD_165_195;
777 if (caps & ESDHC_HOSTCAPBLT_VS30)
778 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
779 if (caps & ESDHC_HOSTCAPBLT_VS33)
780 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
782 priv->cfg.name = "FSL_SDHC";
783 priv->cfg.ops = &esdhc_ops;
784 #ifdef CONFIG_SYS_SD_VOLTAGE
785 priv->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
787 priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
789 if ((priv->cfg.voltages & voltage_caps) == 0) {
790 printf("voltage not supported by controller\n");
794 if (priv->bus_width == 8)
795 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
796 else if (priv->bus_width == 4)
797 priv->cfg.host_caps = MMC_MODE_4BIT;
799 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
800 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
801 priv->cfg.host_caps |= MMC_MODE_DDR_52MHz;
804 if (priv->bus_width > 0) {
805 if (priv->bus_width < 8)
806 priv->cfg.host_caps &= ~MMC_MODE_8BIT;
807 if (priv->bus_width < 4)
808 priv->cfg.host_caps &= ~MMC_MODE_4BIT;
811 if (caps & ESDHC_HOSTCAPBLT_HSS)
812 priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
814 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
815 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
816 priv->cfg.host_caps &= ~MMC_MODE_8BIT;
819 priv->cfg.f_min = 400000;
820 priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000);
822 priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
824 mmc = mmc_create(&priv->cfg, priv);
833 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
835 struct fsl_esdhc_priv *priv;
841 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
845 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
847 debug("%s xlate failure\n", __func__);
852 ret = fsl_esdhc_init(priv);
854 debug("%s init failure\n", __func__);
862 int fsl_esdhc_mmc_init(bd_t *bis)
864 struct fsl_esdhc_cfg *cfg;
866 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
867 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
868 cfg->sdhc_clk = gd->arch.sdhc_clk;
869 return fsl_esdhc_initialize(bis, cfg);
872 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
873 void mmc_adapter_card_type_ident(void)
878 card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
879 gd->arch.sdhc_adapter = card_id;
882 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
883 value = QIXIS_READ(brdcfg[5]);
884 value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
885 QIXIS_WRITE(brdcfg[5], value);
887 case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
888 value = QIXIS_READ(pwr_ctl[1]);
889 value |= QIXIS_EVDD_BY_SDHC_VS;
890 QIXIS_WRITE(pwr_ctl[1], value);
892 case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
893 value = QIXIS_READ(brdcfg[5]);
894 value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
895 QIXIS_WRITE(brdcfg[5], value);
897 case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
899 case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
901 case QIXIS_ESDHC_ADAPTER_TYPE_SD:
903 case QIXIS_ESDHC_NO_ADAPTER:
911 #ifdef CONFIG_OF_LIBFDT
912 void fdt_fixup_esdhc(void *blob, bd_t *bd)
914 const char *compat = "fsl,esdhc";
916 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
917 if (!hwconfig("esdhc")) {
918 do_fixup_by_compat(blob, compat, "status", "disabled",
924 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
925 do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
926 gd->arch.sdhc_clk, 1);
928 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
929 gd->arch.sdhc_clk, 1);
931 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
932 do_fixup_by_compat_u32(blob, compat, "adapter-type",
933 (u32)(gd->arch.sdhc_adapter), 1);
935 do_fixup_by_compat(blob, compat, "status", "okay",
941 #include <asm/arch/clock.h>
942 static int fsl_esdhc_probe(struct udevice *dev)
944 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
945 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
946 const void *fdt = gd->fdt_blob;
947 int node = dev->of_offset;
952 addr = dev_get_addr(dev);
953 if (addr == FDT_ADDR_T_NONE)
956 priv->esdhc_regs = (struct fsl_esdhc *)addr;
959 val = fdtdec_get_int(fdt, node, "bus-width", -1);
967 if (fdt_get_property(fdt, node, "non-removable", NULL)) {
968 priv->non_removable = 1;
970 priv->non_removable = 0;
971 gpio_request_by_name_nodev(fdt, node, "cd-gpios", 0,
972 &priv->cd_gpio, GPIOD_IS_IN);
977 ret = gpio_request_by_name_nodev(fdt, node, "wp-gpios", 0,
978 &priv->wp_gpio, GPIOD_IS_IN);
984 * Because lack of clk driver, if SDHC clk is not enabled,
985 * need to enable it first before this driver is invoked.
987 * we use MXC_ESDHC_CLK to get clk freq.
988 * If one would like to make this function work,
989 * the aliases should be provided in dts as this:
997 * Then if your board only supports mmc2 and mmc3, but we can
998 * correctly get the seq as 2 and 3, then let mxc_get_clock
1001 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1002 if (priv->sdhc_clk <= 0) {
1003 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1007 ret = fsl_esdhc_init(priv);
1009 dev_err(dev, "fsl_esdhc_init failure\n");
1013 upriv->mmc = priv->mmc;
1014 priv->mmc->dev = dev;
1019 static const struct udevice_id fsl_esdhc_ids[] = {
1020 { .compatible = "fsl,imx6ul-usdhc", },
1021 { .compatible = "fsl,imx6sx-usdhc", },
1022 { .compatible = "fsl,imx6sl-usdhc", },
1023 { .compatible = "fsl,imx6q-usdhc", },
1024 { .compatible = "fsl,imx7d-usdhc", },
1028 U_BOOT_DRIVER(fsl_esdhc) = {
1029 .name = "fsl-esdhc-mmc",
1031 .of_match = fsl_esdhc_ids,
1032 .probe = fsl_esdhc_probe,
1033 .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),