3 * Rob Emanuele <rob@emanuele.us>
4 * Reinhard Meyer, EMK Elektronik <reinhard.meyer@emk-elektronik.de>
7 * Copyright (C) 2004-2006 Atmel Corporation
9 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/errno.h>
18 #include <asm/byteorder.h>
19 #include <asm/arch/clk.h>
20 #include <asm/arch/hardware.h>
21 #include "atmel_mci.h"
23 #ifndef CONFIG_SYS_MMC_CLK_OD
24 # define CONFIG_SYS_MMC_CLK_OD 150000
27 #define MMC_DEFAULT_BLKLEN 512
29 #if defined(CONFIG_ATMEL_MCI_PORTB)
35 struct atmel_mci_priv {
36 struct mmc_config cfg;
37 struct atmel_mci *mci;
40 static int initialized = 0;
42 /* Read Atmel MCI IP version */
43 static unsigned int atmel_mci_get_version(struct atmel_mci *mci)
45 return readl(&mci->version) & 0x00000fff;
49 * Print command and status:
51 * - always when DEBUG is defined
54 static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg)
56 debug("gen_atmel_mci: CMDR %08x (%2u) ARGR %08x (SR: %08x) %s\n",
57 cmdr, cmdr & 0x3F, arg, status, msg);
60 /* Setup for MCI Clock and Block Size */
61 static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
63 struct atmel_mci_priv *priv = mmc->priv;
64 atmel_mci_t *mci = priv->mci;
65 u32 bus_hz = get_mci_clk_rate();
67 unsigned int version = atmel_mci_get_version(mci);
71 debug("mci: bus_hz is %u, setting clock %u Hz, block size %u\n",
74 if (version >= 0x500) {
75 clkdiv = DIV_ROUND_UP(bus_hz, hz) - 2;
82 debug("mci: setting clock %u Hz, block size %u\n",
83 bus_hz / (clkdiv * 2 + clkodd + 2), blklen);
85 /* find clkdiv yielding a rate <= than requested */
86 for (clkdiv = 0; clkdiv < 255; clkdiv++) {
87 if ((bus_hz / (clkdiv + 1) / 2) <= hz)
90 debug("mci: setting clock %u Hz, block size %u\n",
91 (bus_hz / (clkdiv + 1)) / 2, blklen);
98 mr = MMCI_BF(CLKDIV, clkdiv);
100 /* MCI IP version >= 0x200 has R/WPROOF */
101 if (version >= 0x200)
102 mr |= MMCI_BIT(RDPROOF) | MMCI_BIT(WRPROOF);
105 * MCI IP version >= 0x500 use bit 16 as clkodd.
106 * MCI IP version < 0x500 use upper 16 bits for blklen.
108 if (version >= 0x500)
109 mr |= MMCI_BF(CLKODD, clkodd);
111 mr |= MMCI_BF(BLKLEN, blklen);
113 writel(mr, &mci->mr);
115 /* MCI IP version >= 0x200 has blkr */
116 if (version >= 0x200)
117 writel(MMCI_BF(BLKLEN, blklen), &mci->blkr);
119 if (mmc->card_caps & mmc->cfg->host_caps & MMC_MODE_HS)
120 writel(MMCI_BIT(HSMODE), &mci->cfg);
127 /* Return the CMDR with flags for a given command and data packet */
128 static u32 mci_encode_cmd(
129 struct mmc_cmd *cmd, struct mmc_data *data, u32* error_flags)
133 /* Default Flags for Errors */
134 *error_flags |= (MMCI_BIT(DTOE) | MMCI_BIT(RDIRE) | MMCI_BIT(RENDE) |
135 MMCI_BIT(RINDE) | MMCI_BIT(RTOE));
137 /* Default Flags for the Command */
138 cmdr |= MMCI_BIT(MAXLAT);
141 cmdr |= MMCI_BF(TRCMD, 1);
142 if (data->blocks > 1)
143 cmdr |= MMCI_BF(TRTYP, 1);
144 if (data->flags & MMC_DATA_READ)
145 cmdr |= MMCI_BIT(TRDIR);
148 if (cmd->resp_type & MMC_RSP_CRC)
149 *error_flags |= MMCI_BIT(RCRCE);
150 if (cmd->resp_type & MMC_RSP_136)
151 cmdr |= MMCI_BF(RSPTYP, 2);
152 else if (cmd->resp_type & MMC_RSP_BUSY)
153 cmdr |= MMCI_BF(RSPTYP, 3);
154 else if (cmd->resp_type & MMC_RSP_PRESENT)
155 cmdr |= MMCI_BF(RSPTYP, 1);
157 return cmdr | MMCI_BF(CMDNB, cmd->cmdidx);
160 /* Entered into function pointer in mci_send_cmd */
161 static u32 mci_data_read(atmel_mci_t *mci, u32* data, u32 error_flags)
166 status = readl(&mci->sr);
167 if (status & (error_flags | MMCI_BIT(OVRE)))
169 } while (!(status & MMCI_BIT(RXRDY)));
171 if (status & MMCI_BIT(RXRDY)) {
172 *data = readl(&mci->rdr);
179 /* Entered into function pointer in mci_send_cmd */
180 static u32 mci_data_write(atmel_mci_t *mci, u32* data, u32 error_flags)
185 status = readl(&mci->sr);
186 if (status & (error_flags | MMCI_BIT(UNRE)))
188 } while (!(status & MMCI_BIT(TXRDY)));
190 if (status & MMCI_BIT(TXRDY)) {
191 writel(*data, &mci->tdr);
199 * Entered into mmc structure during driver init
201 * Sends a command out on the bus and deals with the block data.
202 * Takes the mmc pointer, a command pointer, and an optional data pointer.
205 mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
207 struct atmel_mci_priv *priv = mmc->priv;
208 atmel_mci_t *mci = priv->mci;
214 puts ("MCI not initialized!\n");
218 /* Figure out the transfer arguments */
219 cmdr = mci_encode_cmd(cmd, data, &error_flags);
221 /* For multi blocks read/write, set the block register */
222 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK)
223 || (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK))
224 writel(data->blocks | MMCI_BF(BLKLEN, mmc->read_bl_len),
227 /* Send the command */
228 writel(cmd->cmdarg, &mci->argr);
229 writel(cmdr, &mci->cmdr);
232 dump_cmd(cmdr, cmd->cmdarg, 0, "DEBUG");
235 /* Wait for the command to complete */
236 while (!((status = readl(&mci->sr)) & MMCI_BIT(CMDRDY)));
238 if ((status & error_flags) & MMCI_BIT(RTOE)) {
239 dump_cmd(cmdr, cmd->cmdarg, status, "Command Time Out");
241 } else if (status & error_flags) {
242 dump_cmd(cmdr, cmd->cmdarg, status, "Command Failed");
246 /* Copy the response to the response buffer */
247 if (cmd->resp_type & MMC_RSP_136) {
248 cmd->response[0] = readl(&mci->rspr);
249 cmd->response[1] = readl(&mci->rspr1);
250 cmd->response[2] = readl(&mci->rspr2);
251 cmd->response[3] = readl(&mci->rspr3);
253 cmd->response[0] = readl(&mci->rspr);
255 /* transfer all of the blocks */
257 u32 word_count, block_count;
259 u32 sys_blocksize, dummy, i;
261 (atmel_mci_t *mci, u32* data, u32 error_flags);
263 if (data->flags & MMC_DATA_READ) {
264 mci_data_op = mci_data_read;
265 sys_blocksize = mmc->read_bl_len;
266 ioptr = (u32*)data->dest;
268 mci_data_op = mci_data_write;
269 sys_blocksize = mmc->write_bl_len;
270 ioptr = (u32*)data->src;
274 for (block_count = 0;
275 block_count < data->blocks && !status;
279 status = mci_data_op(mci, ioptr, error_flags);
282 } while (!status && word_count < (data->blocksize/4));
284 if (data->flags & MMC_DATA_READ)
286 u32 cnt = word_count * 4;
287 printf("Read Data:\n");
288 print_buffer(0, data->dest + cnt * block_count,
293 if (!status && word_count < (sys_blocksize / 4))
294 printf("filling rest of block...\n");
296 /* fill the rest of a full block */
297 while (!status && word_count < (sys_blocksize / 4)) {
298 status = mci_data_op(mci, &dummy,
303 dump_cmd(cmdr, cmd->cmdarg, status,
304 "Data Transfer Failed");
309 /* Wait for Transfer End */
312 status = readl(&mci->sr);
314 if (status & error_flags) {
315 dump_cmd(cmdr, cmd->cmdarg, status,
320 } while ((status & MMCI_BIT(DTIP)) && i < 10000);
321 if (status & MMCI_BIT(DTIP)) {
322 dump_cmd(cmdr, cmd->cmdarg, status,
323 "XFER DTIP never unset, ignoring");
330 /* Entered into mmc structure during driver init */
331 static void mci_set_ios(struct mmc *mmc)
333 struct atmel_mci_priv *priv = mmc->priv;
334 atmel_mci_t *mci = priv->mci;
335 int bus_width = mmc->bus_width;
336 unsigned int version = atmel_mci_get_version(mci);
339 /* Set the clock speed */
340 mci_set_mode(mmc, mmc->clock, MMC_DEFAULT_BLKLEN);
343 * set the bus width and select slot for this interface
344 * there is no capability for multiple slots on the same interface yet
346 if ((version & 0xf00) >= 0x300) {
359 writel(busw << 6 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
361 busw = (bus_width == 4) ? 1 : 0;
363 writel(busw << 7 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
367 /* Entered into mmc structure during driver init */
368 static int mci_init(struct mmc *mmc)
370 struct atmel_mci_priv *priv = mmc->priv;
371 atmel_mci_t *mci = priv->mci;
373 /* Initialize controller */
374 writel(MMCI_BIT(SWRST), &mci->cr); /* soft reset */
375 writel(MMCI_BIT(PWSDIS), &mci->cr); /* disable power save */
376 writel(MMCI_BIT(MCIEN), &mci->cr); /* enable mci */
377 writel(MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); /* select port */
379 /* This delay can be optimized, but stick with max value */
380 writel(0x7f, &mci->dtor);
381 /* Disable Interrupts */
382 writel(~0UL, &mci->idr);
384 /* Set default clocks and blocklen */
385 mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
390 static const struct mmc_ops atmel_mci_ops = {
391 .send_cmd = mci_send_cmd,
392 .set_ios = mci_set_ios,
397 * This is the only exported function
399 * Call it with the MCI register base address
401 int atmel_mci_init(void *regs)
404 struct mmc_config *cfg;
405 struct atmel_mci_priv *priv;
406 unsigned int version;
408 priv = calloc(1, sizeof(*priv));
415 cfg->ops = &atmel_mci_ops;
417 priv->mci = (struct atmel_mci *)regs;
419 /* need to be able to pass these in on a board by board basis */
420 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
421 version = atmel_mci_get_version(priv->mci);
422 if ((version & 0xf00) >= 0x300) {
423 cfg->host_caps = MMC_MODE_8BIT;
424 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
427 cfg->host_caps |= MMC_MODE_4BIT;
430 * min and max frequencies determined by
431 * max and min of clock divider
433 cfg->f_min = get_mci_clk_rate() / (2*256);
434 cfg->f_max = get_mci_clk_rate() / (2*1);
436 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
438 mmc = mmc_create(cfg, priv);
444 /* NOTE: possibly leaking the priv structure */