2 * Copyright 2008, Freescale Semiconductor, Inc
5 * Based vaguely on the Linux code
7 * SPDX-License-Identifier: GPL-2.0+
17 #include <linux/list.h>
19 #include "mmc_private.h"
21 static struct list_head mmc_devices;
22 static int cur_dev_num = -1;
24 __weak int board_mmc_getwp(struct mmc *mmc)
29 int mmc_getwp(struct mmc *mmc)
33 wp = board_mmc_getwp(mmc);
36 if (mmc->cfg->ops->getwp)
37 wp = mmc->cfg->ops->getwp(mmc);
45 __weak int board_mmc_getcd(struct mmc *mmc)
50 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
54 #ifdef CONFIG_MMC_TRACE
58 printf("CMD_SEND:%d\n", cmd->cmdidx);
59 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
60 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
61 switch (cmd->resp_type) {
63 printf("\t\tMMC_RSP_NONE\n");
66 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
70 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
74 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
76 printf("\t\t \t\t 0x%08X \n",
78 printf("\t\t \t\t 0x%08X \n",
80 printf("\t\t \t\t 0x%08X \n",
83 printf("\t\t\t\t\tDUMPING DATA\n");
84 for (i = 0; i < 4; i++) {
86 printf("\t\t\t\t\t%03d - ", i*4);
87 ptr = (u8 *)&cmd->response[i];
89 for (j = 0; j < 4; j++)
90 printf("%02X ", *ptr--);
95 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
99 printf("\t\tERROR MMC rsp not supported\n");
103 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
108 int mmc_send_status(struct mmc *mmc, int timeout)
111 int err, retries = 5;
112 #ifdef CONFIG_MMC_TRACE
116 cmd.cmdidx = MMC_CMD_SEND_STATUS;
117 cmd.resp_type = MMC_RSP_R1;
118 if (!mmc_host_is_spi(mmc))
119 cmd.cmdarg = mmc->rca << 16;
122 err = mmc_send_cmd(mmc, &cmd, NULL);
124 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
125 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
128 else if (cmd.response[0] & MMC_STATUS_MASK) {
129 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
130 printf("Status Error: 0x%08X\n",
135 } else if (--retries < 0)
142 #ifdef CONFIG_MMC_TRACE
143 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
144 printf("CURR STATE:%d\n", status);
147 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
148 printf("Timeout waiting card ready\n");
152 if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
158 int mmc_set_blocklen(struct mmc *mmc, int len)
165 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
166 cmd.resp_type = MMC_RSP_R1;
169 return mmc_send_cmd(mmc, &cmd, NULL);
172 struct mmc *find_mmc_device(int dev_num)
175 struct list_head *entry;
177 list_for_each(entry, &mmc_devices) {
178 m = list_entry(entry, struct mmc, link);
180 if (m->block_dev.dev == dev_num)
184 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
185 printf("MMC Device %d not found\n", dev_num);
191 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
195 struct mmc_data data;
198 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
200 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
202 if (mmc->high_capacity)
205 cmd.cmdarg = start * mmc->read_bl_len;
207 cmd.resp_type = MMC_RSP_R1;
210 data.blocks = blkcnt;
211 data.blocksize = mmc->read_bl_len;
212 data.flags = MMC_DATA_READ;
214 if (mmc_send_cmd(mmc, &cmd, &data))
218 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
220 cmd.resp_type = MMC_RSP_R1b;
221 if (mmc_send_cmd(mmc, &cmd, NULL)) {
222 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
223 printf("mmc fail to send stop cmd\n");
232 static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst)
234 lbaint_t cur, blocks_todo = blkcnt;
239 struct mmc *mmc = find_mmc_device(dev_num);
243 if ((start + blkcnt) > mmc->block_dev.lba) {
244 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
245 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
246 start + blkcnt, mmc->block_dev.lba);
251 if (mmc_set_blocklen(mmc, mmc->read_bl_len))
255 cur = (blocks_todo > mmc->cfg->b_max) ?
256 mmc->cfg->b_max : blocks_todo;
257 if(mmc_read_blocks(mmc, dst, start, cur) != cur)
261 dst += cur * mmc->read_bl_len;
262 } while (blocks_todo > 0);
267 static int mmc_go_idle(struct mmc *mmc)
274 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
276 cmd.resp_type = MMC_RSP_NONE;
278 err = mmc_send_cmd(mmc, &cmd, NULL);
288 static int sd_send_op_cond(struct mmc *mmc)
295 cmd.cmdidx = MMC_CMD_APP_CMD;
296 cmd.resp_type = MMC_RSP_R1;
299 err = mmc_send_cmd(mmc, &cmd, NULL);
304 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
305 cmd.resp_type = MMC_RSP_R3;
308 * Most cards do not answer if some reserved bits
309 * in the ocr are set. However, Some controller
310 * can set bit 7 (reserved for low voltages), but
311 * how to manage low voltages SD card is not yet
314 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
315 (mmc->cfg->voltages & 0xff8000);
317 if (mmc->version == SD_VERSION_2)
318 cmd.cmdarg |= OCR_HCS;
320 err = mmc_send_cmd(mmc, &cmd, NULL);
326 } while ((!(cmd.response[0] & OCR_BUSY)) && timeout--);
331 if (mmc->version != SD_VERSION_2)
332 mmc->version = SD_VERSION_1_0;
334 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
335 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
336 cmd.resp_type = MMC_RSP_R3;
339 err = mmc_send_cmd(mmc, &cmd, NULL);
345 mmc->ocr = cmd.response[0];
347 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
353 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
358 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
359 cmd.resp_type = MMC_RSP_R3;
361 if (use_arg && !mmc_host_is_spi(mmc)) {
363 (mmc->cfg->voltages &
364 (mmc->ocr & OCR_VOLTAGE_MASK)) |
365 (mmc->ocr & OCR_ACCESS_MODE);
367 if (mmc->cfg->host_caps & MMC_MODE_HC)
368 cmd.cmdarg |= OCR_HCS;
370 err = mmc_send_cmd(mmc, &cmd, NULL);
373 mmc->ocr = cmd.response[0];
377 static int mmc_send_op_cond(struct mmc *mmc)
381 /* Some cards seem to need this */
384 /* Asking to the card its capabilities */
385 mmc->op_cond_pending = 1;
386 for (i = 0; i < 2; i++) {
387 err = mmc_send_op_cond_iter(mmc, i != 0);
391 /* exit if not busy (flag seems to be inverted) */
392 if (mmc->ocr & OCR_BUSY)
398 static int mmc_complete_op_cond(struct mmc *mmc)
405 mmc->op_cond_pending = 0;
406 if (!(mmc->ocr & OCR_BUSY)) {
407 start = get_timer(0);
409 err = mmc_send_op_cond_iter(mmc, 1);
412 if (get_timer(start) > timeout)
415 } while (!(mmc->ocr & OCR_BUSY));
418 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
419 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
420 cmd.resp_type = MMC_RSP_R3;
423 err = mmc_send_cmd(mmc, &cmd, NULL);
428 mmc->ocr = cmd.response[0];
431 mmc->version = MMC_VERSION_UNKNOWN;
433 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
440 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
443 struct mmc_data data;
446 /* Get the Card Status Register */
447 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
448 cmd.resp_type = MMC_RSP_R1;
451 data.dest = (char *)ext_csd;
453 data.blocksize = MMC_MAX_BLOCK_LEN;
454 data.flags = MMC_DATA_READ;
456 err = mmc_send_cmd(mmc, &cmd, &data);
462 static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
468 cmd.cmdidx = MMC_CMD_SWITCH;
469 cmd.resp_type = MMC_RSP_R1b;
470 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
474 ret = mmc_send_cmd(mmc, &cmd, NULL);
476 /* Waiting for the ready status */
478 ret = mmc_send_status(mmc, timeout);
484 static int mmc_change_freq(struct mmc *mmc)
486 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
492 if (mmc_host_is_spi(mmc))
495 /* Only version 4 supports high-speed */
496 if (mmc->version < MMC_VERSION_4)
499 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
501 err = mmc_send_ext_csd(mmc, ext_csd);
506 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
508 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
511 return err == SWITCH_ERR ? 0 : err;
513 /* Now check to see that it worked */
514 err = mmc_send_ext_csd(mmc, ext_csd);
519 /* No high-speed support */
520 if (!ext_csd[EXT_CSD_HS_TIMING])
523 /* High Speed is set, there are two types: 52MHz and 26MHz */
524 if (cardtype & EXT_CSD_CARD_TYPE_52) {
525 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
526 mmc->card_caps |= MMC_MODE_DDR_52MHz;
527 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
529 mmc->card_caps |= MMC_MODE_HS;
535 static int mmc_set_capacity(struct mmc *mmc, int part_num)
539 mmc->capacity = mmc->capacity_user;
543 mmc->capacity = mmc->capacity_boot;
546 mmc->capacity = mmc->capacity_rpmb;
552 mmc->capacity = mmc->capacity_gp[part_num - 4];
558 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
563 int mmc_select_hwpart(int dev_num, int hwpart)
565 struct mmc *mmc = find_mmc_device(dev_num);
571 if (mmc->part_num == hwpart)
574 if (mmc->part_config == MMCPART_NOAVAILABLE) {
575 printf("Card doesn't support part_switch\n");
579 ret = mmc_switch_part(dev_num, hwpart);
583 mmc->part_num = hwpart;
589 int mmc_switch_part(int dev_num, unsigned int part_num)
591 struct mmc *mmc = find_mmc_device(dev_num);
597 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
598 (mmc->part_config & ~PART_ACCESS_MASK)
599 | (part_num & PART_ACCESS_MASK));
602 * Set the capacity if the switch succeeded or was intended
603 * to return to representing the raw device.
605 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0)))
606 ret = mmc_set_capacity(mmc, part_num);
611 int mmc_hwpart_config(struct mmc *mmc,
612 const struct mmc_hwpart_conf *conf,
613 enum mmc_hwpart_conf_mode mode)
619 u32 max_enh_size_mult;
620 u32 tot_enh_size_mult = 0;
623 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
625 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
628 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
629 printf("eMMC >= 4.4 required for enhanced user data area\n");
633 if (!(mmc->part_support & PART_SUPPORT)) {
634 printf("Card does not support partitioning\n");
638 if (!mmc->hc_wp_grp_size) {
639 printf("Card does not define HC WP group size\n");
643 /* check partition alignment and total enhanced size */
644 if (conf->user.enh_size) {
645 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
646 conf->user.enh_start % mmc->hc_wp_grp_size) {
647 printf("User data enhanced area not HC WP group "
651 part_attrs |= EXT_CSD_ENH_USR;
652 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
653 if (mmc->high_capacity) {
654 enh_start_addr = conf->user.enh_start;
656 enh_start_addr = (conf->user.enh_start << 9);
662 tot_enh_size_mult += enh_size_mult;
664 for (pidx = 0; pidx < 4; pidx++) {
665 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
666 printf("GP%i partition not HC WP group size "
667 "aligned\n", pidx+1);
670 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
671 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
672 part_attrs |= EXT_CSD_ENH_GP(pidx);
673 tot_enh_size_mult += gp_size_mult[pidx];
677 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
678 printf("Card does not support enhanced attribute\n");
682 err = mmc_send_ext_csd(mmc, ext_csd);
687 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
688 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
689 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
690 if (tot_enh_size_mult > max_enh_size_mult) {
691 printf("Total enhanced size exceeds maximum (%u > %u)\n",
692 tot_enh_size_mult, max_enh_size_mult);
696 /* The default value of EXT_CSD_WR_REL_SET is device
697 * dependent, the values can only be changed if the
698 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
699 * changed only once and before partitioning is completed. */
700 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
701 if (conf->user.wr_rel_change) {
702 if (conf->user.wr_rel_set)
703 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
705 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
707 for (pidx = 0; pidx < 4; pidx++) {
708 if (conf->gp_part[pidx].wr_rel_change) {
709 if (conf->gp_part[pidx].wr_rel_set)
710 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
712 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
716 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
717 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
718 puts("Card does not support host controlled partition write "
719 "reliability settings\n");
723 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
724 EXT_CSD_PARTITION_SETTING_COMPLETED) {
725 printf("Card already partitioned\n");
729 if (mode == MMC_HWPART_CONF_CHECK)
732 /* Partitioning requires high-capacity size definitions */
733 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
734 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
735 EXT_CSD_ERASE_GROUP_DEF, 1);
740 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
742 /* update erase group size to be high-capacity */
743 mmc->erase_grp_size =
744 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
748 /* all OK, write the configuration */
749 for (i = 0; i < 4; i++) {
750 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
751 EXT_CSD_ENH_START_ADDR+i,
752 (enh_start_addr >> (i*8)) & 0xFF);
756 for (i = 0; i < 3; i++) {
757 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
758 EXT_CSD_ENH_SIZE_MULT+i,
759 (enh_size_mult >> (i*8)) & 0xFF);
763 for (pidx = 0; pidx < 4; pidx++) {
764 for (i = 0; i < 3; i++) {
765 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
766 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
767 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
772 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
773 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
777 if (mode == MMC_HWPART_CONF_SET)
780 /* The WR_REL_SET is a write-once register but shall be
781 * written before setting PART_SETTING_COMPLETED. As it is
782 * write-once we can only write it when completing the
784 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
785 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
786 EXT_CSD_WR_REL_SET, wr_rel_set);
791 /* Setting PART_SETTING_COMPLETED confirms the partition
792 * configuration but it only becomes effective after power
793 * cycle, so we do not adjust the partition related settings
794 * in the mmc struct. */
796 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
797 EXT_CSD_PARTITION_SETTING,
798 EXT_CSD_PARTITION_SETTING_COMPLETED);
805 int mmc_getcd(struct mmc *mmc)
809 cd = board_mmc_getcd(mmc);
812 if (mmc->cfg->ops->getcd)
813 cd = mmc->cfg->ops->getcd(mmc);
821 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
824 struct mmc_data data;
826 /* Switch the frequency */
827 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
828 cmd.resp_type = MMC_RSP_R1;
829 cmd.cmdarg = (mode << 31) | 0xffffff;
830 cmd.cmdarg &= ~(0xf << (group * 4));
831 cmd.cmdarg |= value << (group * 4);
833 data.dest = (char *)resp;
836 data.flags = MMC_DATA_READ;
838 return mmc_send_cmd(mmc, &cmd, &data);
842 static int sd_change_freq(struct mmc *mmc)
846 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
847 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
848 struct mmc_data data;
853 if (mmc_host_is_spi(mmc))
856 /* Read the SCR to find out if this card supports higher speeds */
857 cmd.cmdidx = MMC_CMD_APP_CMD;
858 cmd.resp_type = MMC_RSP_R1;
859 cmd.cmdarg = mmc->rca << 16;
861 err = mmc_send_cmd(mmc, &cmd, NULL);
866 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
867 cmd.resp_type = MMC_RSP_R1;
873 data.dest = (char *)scr;
876 data.flags = MMC_DATA_READ;
878 err = mmc_send_cmd(mmc, &cmd, &data);
887 mmc->scr[0] = __be32_to_cpu(scr[0]);
888 mmc->scr[1] = __be32_to_cpu(scr[1]);
890 switch ((mmc->scr[0] >> 24) & 0xf) {
892 mmc->version = SD_VERSION_1_0;
895 mmc->version = SD_VERSION_1_10;
898 mmc->version = SD_VERSION_2;
899 if ((mmc->scr[0] >> 15) & 0x1)
900 mmc->version = SD_VERSION_3;
903 mmc->version = SD_VERSION_1_0;
907 if (mmc->scr[0] & SD_DATA_4BIT)
908 mmc->card_caps |= MMC_MODE_4BIT;
910 /* Version 1.0 doesn't support switching */
911 if (mmc->version == SD_VERSION_1_0)
916 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
917 (u8 *)switch_status);
922 /* The high-speed function is busy. Try again */
923 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
927 /* If high-speed isn't supported, we return */
928 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
932 * If the host doesn't support SD_HIGHSPEED, do not switch card to
933 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
934 * This can avoid furthur problem when the card runs in different
935 * mode between the host.
937 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
938 (mmc->cfg->host_caps & MMC_MODE_HS)))
941 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
946 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
947 mmc->card_caps |= MMC_MODE_HS;
952 /* frequency bases */
953 /* divided by 10 to be nice to platforms without floating point */
954 static const int fbase[] = {
961 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
962 * to platforms without floating point.
964 static const int multipliers[] = {
983 static void mmc_set_ios(struct mmc *mmc)
985 if (mmc->cfg->ops->set_ios)
986 mmc->cfg->ops->set_ios(mmc);
989 void mmc_set_clock(struct mmc *mmc, uint clock)
991 if (clock > mmc->cfg->f_max)
992 clock = mmc->cfg->f_max;
994 if (clock < mmc->cfg->f_min)
995 clock = mmc->cfg->f_min;
1002 static void mmc_set_bus_width(struct mmc *mmc, uint width)
1004 mmc->bus_width = width;
1009 static int mmc_startup(struct mmc *mmc)
1013 u64 cmult, csize, capacity;
1015 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1016 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1018 bool has_parts = false;
1019 bool part_completed;
1021 #ifdef CONFIG_MMC_SPI_CRC_ON
1022 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1023 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1024 cmd.resp_type = MMC_RSP_R1;
1026 err = mmc_send_cmd(mmc, &cmd, NULL);
1033 /* Put the Card in Identify Mode */
1034 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1035 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
1036 cmd.resp_type = MMC_RSP_R2;
1039 err = mmc_send_cmd(mmc, &cmd, NULL);
1044 memcpy(mmc->cid, cmd.response, 16);
1047 * For MMC cards, set the Relative Address.
1048 * For SD cards, get the Relatvie Address.
1049 * This also puts the cards into Standby State
1051 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1052 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1053 cmd.cmdarg = mmc->rca << 16;
1054 cmd.resp_type = MMC_RSP_R6;
1056 err = mmc_send_cmd(mmc, &cmd, NULL);
1062 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1065 /* Get the Card-Specific Data */
1066 cmd.cmdidx = MMC_CMD_SEND_CSD;
1067 cmd.resp_type = MMC_RSP_R2;
1068 cmd.cmdarg = mmc->rca << 16;
1070 err = mmc_send_cmd(mmc, &cmd, NULL);
1072 /* Waiting for the ready status */
1073 mmc_send_status(mmc, timeout);
1078 mmc->csd[0] = cmd.response[0];
1079 mmc->csd[1] = cmd.response[1];
1080 mmc->csd[2] = cmd.response[2];
1081 mmc->csd[3] = cmd.response[3];
1083 if (mmc->version == MMC_VERSION_UNKNOWN) {
1084 int version = (cmd.response[0] >> 26) & 0xf;
1088 mmc->version = MMC_VERSION_1_2;
1091 mmc->version = MMC_VERSION_1_4;
1094 mmc->version = MMC_VERSION_2_2;
1097 mmc->version = MMC_VERSION_3;
1100 mmc->version = MMC_VERSION_4;
1103 mmc->version = MMC_VERSION_1_2;
1108 /* divide frequency by 10, since the mults are 10x bigger */
1109 freq = fbase[(cmd.response[0] & 0x7)];
1110 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
1112 mmc->tran_speed = freq * mult;
1114 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
1115 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
1118 mmc->write_bl_len = mmc->read_bl_len;
1120 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
1122 if (mmc->high_capacity) {
1123 csize = (mmc->csd[1] & 0x3f) << 16
1124 | (mmc->csd[2] & 0xffff0000) >> 16;
1127 csize = (mmc->csd[1] & 0x3ff) << 2
1128 | (mmc->csd[2] & 0xc0000000) >> 30;
1129 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1132 mmc->capacity_user = (csize + 1) << (cmult + 2);
1133 mmc->capacity_user *= mmc->read_bl_len;
1134 mmc->capacity_boot = 0;
1135 mmc->capacity_rpmb = 0;
1136 for (i = 0; i < 4; i++)
1137 mmc->capacity_gp[i] = 0;
1139 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1140 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1142 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1143 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1145 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1146 cmd.cmdidx = MMC_CMD_SET_DSR;
1147 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1148 cmd.resp_type = MMC_RSP_NONE;
1149 if (mmc_send_cmd(mmc, &cmd, NULL))
1150 printf("MMC: SET_DSR failed\n");
1153 /* Select the card, and put it into Transfer Mode */
1154 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1155 cmd.cmdidx = MMC_CMD_SELECT_CARD;
1156 cmd.resp_type = MMC_RSP_R1;
1157 cmd.cmdarg = mmc->rca << 16;
1158 err = mmc_send_cmd(mmc, &cmd, NULL);
1165 * For SD, its erase group is always one sector
1167 mmc->erase_grp_size = 1;
1168 mmc->part_config = MMCPART_NOAVAILABLE;
1169 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
1170 /* check ext_csd version and capacity */
1171 err = mmc_send_ext_csd(mmc, ext_csd);
1174 if (ext_csd[EXT_CSD_REV] >= 2) {
1176 * According to the JEDEC Standard, the value of
1177 * ext_csd's capacity is valid if the value is more
1180 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1181 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1182 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1183 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1184 capacity *= MMC_MAX_BLOCK_LEN;
1185 if ((capacity >> 20) > 2 * 1024)
1186 mmc->capacity_user = capacity;
1189 switch (ext_csd[EXT_CSD_REV]) {
1191 mmc->version = MMC_VERSION_4_1;
1194 mmc->version = MMC_VERSION_4_2;
1197 mmc->version = MMC_VERSION_4_3;
1200 mmc->version = MMC_VERSION_4_41;
1203 mmc->version = MMC_VERSION_4_5;
1206 mmc->version = MMC_VERSION_5_0;
1210 /* The partition data may be non-zero but it is only
1211 * effective if PARTITION_SETTING_COMPLETED is set in
1212 * EXT_CSD, so ignore any data if this bit is not set,
1213 * except for enabling the high-capacity group size
1214 * definition (see below). */
1215 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1216 EXT_CSD_PARTITION_SETTING_COMPLETED);
1218 /* store the partition info of emmc */
1219 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1220 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1221 ext_csd[EXT_CSD_BOOT_MULT])
1222 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1223 if (part_completed &&
1224 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1225 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1227 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1229 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1231 for (i = 0; i < 4; i++) {
1232 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1233 uint mult = (ext_csd[idx + 2] << 16) +
1234 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1237 if (!part_completed)
1239 mmc->capacity_gp[i] = mult;
1240 mmc->capacity_gp[i] *=
1241 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1242 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1243 mmc->capacity_gp[i] <<= 19;
1246 if (part_completed) {
1247 mmc->enh_user_size =
1248 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
1249 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
1250 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1251 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1252 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1253 mmc->enh_user_size <<= 19;
1254 mmc->enh_user_start =
1255 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
1256 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
1257 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
1258 ext_csd[EXT_CSD_ENH_START_ADDR];
1259 if (mmc->high_capacity)
1260 mmc->enh_user_start <<= 9;
1264 * Host needs to enable ERASE_GRP_DEF bit if device is
1265 * partitioned. This bit will be lost every time after a reset
1266 * or power off. This will affect erase size.
1270 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1271 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1274 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1275 EXT_CSD_ERASE_GROUP_DEF, 1);
1280 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1283 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1284 /* Read out group size from ext_csd */
1285 mmc->erase_grp_size =
1286 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1288 * if high capacity and partition setting completed
1289 * SEC_COUNT is valid even if it is smaller than 2 GiB
1290 * JEDEC Standard JESD84-B45, 6.2.4
1292 if (mmc->high_capacity && part_completed) {
1293 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1294 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1295 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1296 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1297 capacity *= MMC_MAX_BLOCK_LEN;
1298 mmc->capacity_user = capacity;
1301 /* Calculate the group size from the csd value. */
1302 int erase_gsz, erase_gmul;
1303 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1304 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1305 mmc->erase_grp_size = (erase_gsz + 1)
1309 mmc->hc_wp_grp_size = 1024
1310 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1311 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1313 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1316 err = mmc_set_capacity(mmc, mmc->part_num);
1321 err = sd_change_freq(mmc);
1323 err = mmc_change_freq(mmc);
1328 /* Restrict card's capabilities by what the host can do */
1329 mmc->card_caps &= mmc->cfg->host_caps;
1332 if (mmc->card_caps & MMC_MODE_4BIT) {
1333 cmd.cmdidx = MMC_CMD_APP_CMD;
1334 cmd.resp_type = MMC_RSP_R1;
1335 cmd.cmdarg = mmc->rca << 16;
1337 err = mmc_send_cmd(mmc, &cmd, NULL);
1341 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1342 cmd.resp_type = MMC_RSP_R1;
1344 err = mmc_send_cmd(mmc, &cmd, NULL);
1348 mmc_set_bus_width(mmc, 4);
1351 if (mmc->card_caps & MMC_MODE_HS)
1352 mmc->tran_speed = 50000000;
1354 mmc->tran_speed = 25000000;
1355 } else if (mmc->version >= MMC_VERSION_4) {
1356 /* Only version 4 of MMC supports wider bus widths */
1359 /* An array of possible bus widths in order of preference */
1360 static unsigned ext_csd_bits[] = {
1361 EXT_CSD_DDR_BUS_WIDTH_8,
1362 EXT_CSD_DDR_BUS_WIDTH_4,
1363 EXT_CSD_BUS_WIDTH_8,
1364 EXT_CSD_BUS_WIDTH_4,
1365 EXT_CSD_BUS_WIDTH_1,
1368 /* An array to map CSD bus widths to host cap bits */
1369 static unsigned ext_to_hostcaps[] = {
1370 [EXT_CSD_DDR_BUS_WIDTH_4] =
1371 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1372 [EXT_CSD_DDR_BUS_WIDTH_8] =
1373 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
1374 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1375 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1378 /* An array to map chosen bus width to an integer */
1379 static unsigned widths[] = {
1383 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1384 unsigned int extw = ext_csd_bits[idx];
1385 unsigned int caps = ext_to_hostcaps[extw];
1388 * If the bus width is still not changed,
1389 * don't try to set the default again.
1390 * Otherwise, recover from switch attempts
1391 * by switching to 1-bit bus width.
1393 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1394 mmc->bus_width == 1) {
1400 * Check to make sure the card and controller support
1401 * these capabilities
1403 if ((mmc->card_caps & caps) != caps)
1406 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1407 EXT_CSD_BUS_WIDTH, extw);
1412 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
1413 mmc_set_bus_width(mmc, widths[idx]);
1415 err = mmc_send_ext_csd(mmc, test_csd);
1420 /* Only compare read only fields */
1421 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1422 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1423 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1424 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1425 ext_csd[EXT_CSD_REV]
1426 == test_csd[EXT_CSD_REV] &&
1427 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1428 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1429 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1430 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1439 if (mmc->card_caps & MMC_MODE_HS) {
1440 if (mmc->card_caps & MMC_MODE_HS_52MHz)
1441 mmc->tran_speed = 52000000;
1443 mmc->tran_speed = 26000000;
1447 mmc_set_clock(mmc, mmc->tran_speed);
1449 /* Fix the block length for DDR mode */
1450 if (mmc->ddr_mode) {
1451 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1452 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1455 /* fill in device description */
1456 mmc->block_dev.lun = 0;
1457 mmc->block_dev.type = 0;
1458 mmc->block_dev.blksz = mmc->read_bl_len;
1459 mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
1460 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
1461 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1462 sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x",
1463 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1464 (mmc->cid[3] >> 16) & 0xffff);
1465 sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1466 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1467 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1468 (mmc->cid[2] >> 24) & 0xff);
1469 sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1470 (mmc->cid[2] >> 16) & 0xf);
1472 mmc->block_dev.vendor[0] = 0;
1473 mmc->block_dev.product[0] = 0;
1474 mmc->block_dev.revision[0] = 0;
1476 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
1477 init_part(&mmc->block_dev);
1483 static int mmc_send_if_cond(struct mmc *mmc)
1488 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1489 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
1490 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
1491 cmd.resp_type = MMC_RSP_R7;
1493 err = mmc_send_cmd(mmc, &cmd, NULL);
1498 if ((cmd.response[0] & 0xff) != 0xaa)
1499 return UNUSABLE_ERR;
1501 mmc->version = SD_VERSION_2;
1506 /* not used any more */
1507 int __deprecated mmc_register(struct mmc *mmc)
1509 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1510 printf("%s is deprecated! use mmc_create() instead.\n", __func__);
1515 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
1519 /* quick validation */
1520 if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL ||
1521 cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0)
1524 mmc = calloc(1, sizeof(*mmc));
1531 /* the following chunk was mmc_register() */
1533 /* Setup dsr related values */
1535 mmc->dsr = 0xffffffff;
1536 /* Setup the universal parts of the block interface just once */
1537 mmc->block_dev.if_type = IF_TYPE_MMC;
1538 mmc->block_dev.dev = cur_dev_num++;
1539 mmc->block_dev.removable = 1;
1540 mmc->block_dev.block_read = mmc_bread;
1541 mmc->block_dev.block_write = mmc_bwrite;
1542 mmc->block_dev.block_erase = mmc_berase;
1544 /* setup initial part type */
1545 mmc->block_dev.part_type = mmc->cfg->part_type;
1547 INIT_LIST_HEAD(&mmc->link);
1549 list_add_tail(&mmc->link, &mmc_devices);
1554 void mmc_destroy(struct mmc *mmc)
1556 /* only freeing memory for now */
1560 #ifdef CONFIG_PARTITIONS
1561 block_dev_desc_t *mmc_get_dev(int dev)
1563 struct mmc *mmc = find_mmc_device(dev);
1564 if (!mmc || mmc_init(mmc))
1567 return &mmc->block_dev;
1571 /* board-specific MMC power initializations. */
1572 __weak void board_mmc_power_init(void)
1576 int mmc_start_init(struct mmc *mmc)
1580 /* we pretend there's no card when init is NULL */
1581 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
1583 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1584 printf("MMC: no card present\n");
1592 board_mmc_power_init();
1594 /* made sure it's not NULL earlier */
1595 err = mmc->cfg->ops->init(mmc);
1601 mmc_set_bus_width(mmc, 1);
1602 mmc_set_clock(mmc, 1);
1604 /* Reset the Card */
1605 err = mmc_go_idle(mmc);
1610 /* The internal partition reset to user partition(0) at every CMD0*/
1613 /* Test for SD version 2 */
1614 err = mmc_send_if_cond(mmc);
1616 /* Now try to get the SD card's operating condition */
1617 err = sd_send_op_cond(mmc);
1619 /* If the command timed out, we check for an MMC card */
1620 if (err == TIMEOUT) {
1621 err = mmc_send_op_cond(mmc);
1623 if (err && err != IN_PROGRESS) {
1624 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1625 printf("Card did not respond to voltage select!\n");
1627 return UNUSABLE_ERR;
1631 if (err == IN_PROGRESS)
1632 mmc->init_in_progress = 1;
1637 static int mmc_complete_init(struct mmc *mmc)
1641 if (mmc->op_cond_pending)
1642 err = mmc_complete_op_cond(mmc);
1645 err = mmc_startup(mmc);
1650 mmc->init_in_progress = 0;
1654 int mmc_init(struct mmc *mmc)
1656 int err = IN_PROGRESS;
1662 start = get_timer(0);
1664 if (!mmc->init_in_progress)
1665 err = mmc_start_init(mmc);
1667 if (!err || err == IN_PROGRESS)
1668 err = mmc_complete_init(mmc);
1669 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
1673 int mmc_set_dsr(struct mmc *mmc, u16 val)
1679 /* CPU-specific MMC initializations */
1680 __weak int cpu_mmc_init(bd_t *bis)
1685 /* board-specific MMC initializations. */
1686 __weak int board_mmc_init(bd_t *bis)
1691 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1693 void print_mmc_devices(char separator)
1696 struct list_head *entry;
1699 list_for_each(entry, &mmc_devices) {
1700 m = list_entry(entry, struct mmc, link);
1703 mmc_type = IS_SD(m) ? "SD" : "eMMC";
1707 printf("%s: %d", m->cfg->name, m->block_dev.dev);
1709 printf(" (%s)", mmc_type);
1711 if (entry->next != &mmc_devices) {
1712 printf("%c", separator);
1713 if (separator != '\n')
1722 void print_mmc_devices(char separator) { }
1725 int get_mmc_num(void)
1730 void mmc_set_preinit(struct mmc *mmc, int preinit)
1732 mmc->preinit = preinit;
1735 static void do_preinit(void)
1738 struct list_head *entry;
1740 list_for_each(entry, &mmc_devices) {
1741 m = list_entry(entry, struct mmc, link);
1749 int mmc_initialize(bd_t *bis)
1751 INIT_LIST_HEAD (&mmc_devices);
1754 if (board_mmc_init(bis) < 0)
1757 #ifndef CONFIG_SPL_BUILD
1758 print_mmc_devices(',');
1765 #ifdef CONFIG_SUPPORT_EMMC_BOOT
1767 * This function changes the size of boot partition and the size of rpmb
1768 * partition present on EMMC devices.
1771 * struct *mmc: pointer for the mmc device strcuture
1772 * bootsize: size of boot partition
1773 * rpmbsize: size of rpmb partition
1775 * Returns 0 on success.
1778 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
1779 unsigned long rpmbsize)
1784 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
1785 cmd.cmdidx = MMC_CMD_RES_MAN;
1786 cmd.resp_type = MMC_RSP_R1b;
1787 cmd.cmdarg = MMC_CMD62_ARG1;
1789 err = mmc_send_cmd(mmc, &cmd, NULL);
1791 debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
1795 /* Boot partition changing mode */
1796 cmd.cmdidx = MMC_CMD_RES_MAN;
1797 cmd.resp_type = MMC_RSP_R1b;
1798 cmd.cmdarg = MMC_CMD62_ARG2;
1800 err = mmc_send_cmd(mmc, &cmd, NULL);
1802 debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
1805 /* boot partition size is multiple of 128KB */
1806 bootsize = (bootsize * 1024) / 128;
1808 /* Arg: boot partition size */
1809 cmd.cmdidx = MMC_CMD_RES_MAN;
1810 cmd.resp_type = MMC_RSP_R1b;
1811 cmd.cmdarg = bootsize;
1813 err = mmc_send_cmd(mmc, &cmd, NULL);
1815 debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
1818 /* RPMB partition size is multiple of 128KB */
1819 rpmbsize = (rpmbsize * 1024) / 128;
1820 /* Arg: RPMB partition size */
1821 cmd.cmdidx = MMC_CMD_RES_MAN;
1822 cmd.resp_type = MMC_RSP_R1b;
1823 cmd.cmdarg = rpmbsize;
1825 err = mmc_send_cmd(mmc, &cmd, NULL);
1827 debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
1834 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
1835 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
1838 * Returns 0 on success.
1840 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
1844 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
1845 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
1846 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
1847 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
1855 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
1856 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
1859 * Returns 0 on success.
1861 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
1865 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
1866 EXT_CSD_BOOT_ACK(ack) |
1867 EXT_CSD_BOOT_PART_NUM(part_num) |
1868 EXT_CSD_PARTITION_ACCESS(access));
1876 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
1877 * for enable. Note that this is a write-once field for non-zero values.
1879 * Returns 0 on success.
1881 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
1883 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION,