3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
36 #include <asm/arch/mmc_host_def.h>
37 #ifdef CONFIG_OMAP54XX
38 #include <asm/arch/mux_dra7xx.h>
39 #include <asm/arch/dra7xx_iodelay.h>
41 #if !defined(CONFIG_SOC_KEYSTONE)
43 #include <asm/arch/sys_proto.h>
45 #ifdef CONFIG_MMC_OMAP36XX_PINS
46 #include <asm/arch/mux.h>
50 DECLARE_GLOBAL_DATA_PTR;
52 /* simplify defines to OMAP_HSMMC_USE_GPIO */
53 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
54 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
55 #define OMAP_HSMMC_USE_GPIO
57 #undef OMAP_HSMMC_USE_GPIO
60 /* common definitions for all OMAPs */
61 #define SYSCTL_SRC (1 << 25)
62 #define SYSCTL_SRD (1 << 26)
64 #ifdef CONFIG_IODELAY_RECALIBRATION
65 struct omap_hsmmc_pinctrl_state {
66 struct pad_conf_entry *padconf;
68 struct iodelay_cfg_entry *iodelay;
73 struct omap_hsmmc_data {
74 struct hsmmc *base_addr;
75 #if !CONFIG_IS_ENABLED(DM_MMC)
76 struct mmc_config cfg;
80 #ifdef OMAP_HSMMC_USE_GPIO
81 #if CONFIG_IS_ENABLED(DM_MMC)
82 struct gpio_desc cd_gpio; /* Change Detect GPIO */
83 struct gpio_desc wp_gpio; /* Write Protect GPIO */
90 #if CONFIG_IS_ENABLED(DM_MMC)
95 #ifndef CONFIG_OMAP34XX
96 struct omap_hsmmc_adma_desc *adma_desc_table;
100 #ifdef CONFIG_IODELAY_RECALIBRATION
101 struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
102 struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
103 struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
104 struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
105 struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
106 struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
107 struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
108 struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
109 struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
113 struct omap_mmc_of_data {
117 #ifndef CONFIG_OMAP34XX
118 struct omap_hsmmc_adma_desc {
125 #define ADMA_MAX_LEN 63488
127 /* Decriptor table defines */
128 #define ADMA_DESC_ATTR_VALID BIT(0)
129 #define ADMA_DESC_ATTR_END BIT(1)
130 #define ADMA_DESC_ATTR_INT BIT(2)
131 #define ADMA_DESC_ATTR_ACT1 BIT(4)
132 #define ADMA_DESC_ATTR_ACT2 BIT(5)
134 #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
135 #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
138 /* If we fail after 1 second wait, something is really bad */
139 #define MAX_RETRY_MS 1000
140 #define MMC_TIMEOUT_MS 20
142 /* DMA transfers can take a long time if a lot a data is transferred.
143 * The timeout must take in account the amount of data. Let's assume
144 * that the time will never exceed 333 ms per MB (in other word we assume
145 * that the bandwidth is always above 3MB/s).
147 #define DMA_TIMEOUT_PER_MB 333
148 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)
149 #define OMAP_HSMMC_NO_1_8_V BIT(1)
150 #define OMAP_HSMMC_USE_ADMA BIT(2)
151 #define OMAP_HSMMC_REQUIRE_IODELAY BIT(3)
153 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
154 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
156 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
157 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
158 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
160 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
162 #if CONFIG_IS_ENABLED(DM_MMC)
163 return dev_get_priv(mmc->dev);
165 return (struct omap_hsmmc_data *)mmc->priv;
168 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
170 #if CONFIG_IS_ENABLED(DM_MMC)
171 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
174 return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
178 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
179 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
183 #ifndef CONFIG_DM_GPIO
184 if (!gpio_is_valid(gpio))
187 ret = gpio_request(gpio, label);
191 ret = gpio_direction_input(gpio);
199 static unsigned char mmc_board_init(struct mmc *mmc)
201 #if defined(CONFIG_OMAP34XX)
202 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
203 t2_t *t2_base = (t2_t *)T2_BASE;
204 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
206 #ifdef CONFIG_MMC_OMAP36XX_PINS
207 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
210 pbias_lite = readl(&t2_base->pbias_lite);
211 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
212 #ifdef CONFIG_TARGET_OMAP3_CAIRO
213 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
214 pbias_lite &= ~PBIASLITEVMODE0;
216 #ifdef CONFIG_MMC_OMAP36XX_PINS
217 if (get_cpu_family() == CPU_OMAP36XX) {
218 /* Disable extended drain IO before changing PBIAS */
219 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
220 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
223 writel(pbias_lite, &t2_base->pbias_lite);
225 writel(pbias_lite | PBIASLITEPWRDNZ1 |
226 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
227 &t2_base->pbias_lite);
229 #ifdef CONFIG_MMC_OMAP36XX_PINS
230 if (get_cpu_family() == CPU_OMAP36XX)
231 /* Enable extended drain IO after changing PBIAS */
233 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
234 OMAP34XX_CTRL_WKUP_CTRL);
236 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
239 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
242 /* Change from default of 52MHz to 26MHz if necessary */
243 if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
244 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
245 &t2_base->ctl_prog_io1);
247 writel(readl(&prcm_base->fclken1_core) |
248 EN_MMC1 | EN_MMC2 | EN_MMC3,
249 &prcm_base->fclken1_core);
251 writel(readl(&prcm_base->iclken1_core) |
252 EN_MMC1 | EN_MMC2 | EN_MMC3,
253 &prcm_base->iclken1_core);
256 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
257 /* PBIAS config needed for MMC1 only */
258 if (mmc_get_blk_desc(mmc)->devnum == 0)
259 vmmc_pbias_config(LDO_VOLT_3V0);
265 void mmc_init_stream(struct hsmmc *mmc_base)
269 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
271 writel(MMC_CMD0, &mmc_base->cmd);
272 start = get_timer(0);
273 while (!(readl(&mmc_base->stat) & CC_MASK)) {
274 if (get_timer(0) - start > MAX_RETRY_MS) {
275 printf("%s: timedout waiting for cc!\n", __func__);
279 writel(CC_MASK, &mmc_base->stat)
281 writel(MMC_CMD0, &mmc_base->cmd)
283 start = get_timer(0);
284 while (!(readl(&mmc_base->stat) & CC_MASK)) {
285 if (get_timer(0) - start > MAX_RETRY_MS) {
286 printf("%s: timedout waiting for cc2!\n", __func__);
290 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
293 #if CONFIG_IS_ENABLED(DM_MMC)
294 #ifdef CONFIG_IODELAY_RECALIBRATION
295 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
297 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
298 struct omap_hsmmc_pinctrl_state *pinctrl_state;
300 switch (priv->mode) {
302 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
305 pinctrl_state = priv->sdr104_pinctrl_state;
308 pinctrl_state = priv->sdr50_pinctrl_state;
311 pinctrl_state = priv->ddr50_pinctrl_state;
314 pinctrl_state = priv->sdr25_pinctrl_state;
317 pinctrl_state = priv->sdr12_pinctrl_state;
322 pinctrl_state = priv->hs_pinctrl_state;
325 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
327 pinctrl_state = priv->default_pinctrl_state;
332 pinctrl_state = priv->default_pinctrl_state;
334 if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
335 if (pinctrl_state->iodelay)
336 late_recalibrate_iodelay(pinctrl_state->padconf,
337 pinctrl_state->npads,
338 pinctrl_state->iodelay,
339 pinctrl_state->niodelays);
341 do_set_mux32((*ctrl)->control_padconf_core_base,
342 pinctrl_state->padconf,
343 pinctrl_state->npads);
347 static void omap_hsmmc_set_timing(struct mmc *mmc)
350 struct hsmmc *mmc_base;
351 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
353 mmc_base = priv->base_addr;
355 omap_hsmmc_stop_clock(mmc_base);
356 val = readl(&mmc_base->ac12);
357 val &= ~AC12_UHSMC_MASK;
358 priv->mode = mmc->selected_mode;
360 if (mmc_is_mode_ddr(priv->mode))
361 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
363 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
365 switch (priv->mode) {
368 val |= AC12_UHSMC_SDR104;
371 val |= AC12_UHSMC_SDR50;
375 val |= AC12_UHSMC_DDR50;
380 val |= AC12_UHSMC_SDR25;
386 val |= AC12_UHSMC_SDR12;
389 val |= AC12_UHSMC_RES;
392 writel(val, &mmc_base->ac12);
394 #ifdef CONFIG_IODELAY_RECALIBRATION
395 omap_hsmmc_io_recalibrate(mmc);
397 omap_hsmmc_start_clock(mmc_base);
400 static void omap_hsmmc_conf_bus_power(struct mmc *mmc)
402 struct hsmmc *mmc_base;
403 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
406 mmc_base = priv->base_addr;
408 val = readl(&mmc_base->hctl) & ~SDVS_MASK;
422 writel(val, &mmc_base->hctl);
425 static void omap_hsmmc_set_capabilities(struct mmc *mmc)
427 struct hsmmc *mmc_base;
428 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
431 mmc_base = priv->base_addr;
432 val = readl(&mmc_base->capa);
434 if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
435 val |= (VS30_3V0SUP | VS18_1V8SUP);
437 } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
447 writel(val, &mmc_base->capa);
450 #ifdef MMC_SUPPORTS_TUNING
451 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
453 struct hsmmc *mmc_base;
454 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
457 mmc_base = priv->base_addr;
458 val = readl(&mmc_base->ac12);
459 val &= ~(AC12_SCLK_SEL);
460 writel(val, &mmc_base->ac12);
462 val = readl(&mmc_base->dll);
463 val &= ~(DLL_FORCE_VALUE | DLL_SWT);
464 writel(val, &mmc_base->dll);
467 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
470 struct hsmmc *mmc_base;
471 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
474 mmc_base = priv->base_addr;
475 val = readl(&mmc_base->dll);
476 val |= DLL_FORCE_VALUE;
477 val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
478 val |= (count << DLL_FORCE_SR_C_SHIFT);
479 writel(val, &mmc_base->dll);
482 writel(val, &mmc_base->dll);
483 for (i = 0; i < 1000; i++) {
484 if (readl(&mmc_base->dll) & DLL_CALIB)
488 writel(val, &mmc_base->dll);
491 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
493 struct omap_hsmmc_data *priv = dev_get_priv(dev);
494 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
495 struct mmc *mmc = upriv->mmc;
496 struct hsmmc *mmc_base;
498 u8 cur_match, prev_match = 0;
501 u32 start_window = 0, max_window = 0;
502 u32 length = 0, max_len = 0;
504 mmc_base = priv->base_addr;
505 val = readl(&mmc_base->capa2);
507 /* clock tuning is not needed for upto 52MHz */
508 if (!((mmc->selected_mode == MMC_HS_200) ||
509 (mmc->selected_mode == UHS_SDR104) ||
510 ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
513 val = readl(&mmc_base->dll);
515 writel(val, &mmc_base->dll);
516 while (phase_delay <= MAX_PHASE_DELAY) {
517 omap_hsmmc_set_dll(mmc, phase_delay);
519 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
525 start_window = phase_delay;
530 if (length > max_len) {
531 max_window = start_window;
535 prev_match = cur_match;
544 val = readl(&mmc_base->ac12);
545 if (!(val & AC12_SCLK_SEL)) {
550 phase_delay = max_window + 4 * ((3 * max_len) >> 2);
551 omap_hsmmc_set_dll(mmc, phase_delay);
553 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
554 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
560 omap_hsmmc_disable_tuning(mmc);
561 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
562 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
569 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
571 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
572 struct hsmmc *mmc_base = priv->base_addr;
573 u32 irq_mask = INT_EN_MASK;
576 * TODO: Errata i802 indicates only DCRC interrupts can occur during
577 * tuning procedure and DCRC should be disabled. But see occurences
578 * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
579 * interrupts occur along with BRR, so the data is actually in the
580 * buffer. It has to be debugged why these interrutps occur
582 if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
583 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
585 writel(irq_mask, &mmc_base->ie);
588 static int omap_hsmmc_init_setup(struct mmc *mmc)
590 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
591 struct hsmmc *mmc_base;
592 unsigned int reg_val;
596 mmc_base = priv->base_addr;
599 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
600 &mmc_base->sysconfig);
601 start = get_timer(0);
602 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
603 if (get_timer(0) - start > MAX_RETRY_MS) {
604 printf("%s: timedout waiting for cc2!\n", __func__);
608 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
609 start = get_timer(0);
610 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
611 if (get_timer(0) - start > MAX_RETRY_MS) {
612 printf("%s: timedout waiting for softresetall!\n",
617 #ifndef CONFIG_OMAP34XX
618 reg_val = readl(&mmc_base->hl_hwinfo);
619 if (reg_val & MADMA_EN)
620 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
623 #if CONFIG_IS_ENABLED(DM_MMC)
624 omap_hsmmc_set_capabilities(mmc);
625 omap_hsmmc_conf_bus_power(mmc);
627 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
628 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
632 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
634 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
635 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
636 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
639 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
640 (ICE_STOP | DTO_15THDTO));
641 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
642 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
643 start = get_timer(0);
644 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
645 if (get_timer(0) - start > MAX_RETRY_MS) {
646 printf("%s: timedout waiting for ics!\n", __func__);
650 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
652 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
654 mmc_enable_irq(mmc, NULL);
655 mmc_init_stream(mmc_base);
661 * MMC controller internal finite state machine reset
663 * Used to reset command or data internal state machines, using respectively
664 * SRC or SRD bit of SYSCTL register
666 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
670 mmc_reg_out(&mmc_base->sysctl, bit, bit);
673 * CMD(DAT) lines reset procedures are slightly different
674 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
675 * According to OMAP3 TRM:
676 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
678 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
679 * procedure steps must be as follows:
680 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
681 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
682 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
683 * 3. Wait until the SRC (SRD) bit returns to 0x0
684 * (reset procedure is completed).
686 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
687 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
688 if (!(readl(&mmc_base->sysctl) & bit)) {
689 start = get_timer(0);
690 while (!(readl(&mmc_base->sysctl) & bit)) {
691 if (get_timer(0) - start > MMC_TIMEOUT_MS)
696 start = get_timer(0);
697 while ((readl(&mmc_base->sysctl) & bit) != 0) {
698 if (get_timer(0) - start > MAX_RETRY_MS) {
699 printf("%s: timedout waiting for sysctl %x to clear\n",
706 #ifndef CONFIG_OMAP34XX
707 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
709 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
710 struct omap_hsmmc_adma_desc *desc;
713 desc = &priv->adma_desc_table[priv->desc_slot];
715 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
719 attr |= ADMA_DESC_ATTR_END;
722 desc->addr = (u32)buf;
727 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
728 struct mmc_data *data)
730 uint total_len = data->blocksize * data->blocks;
731 uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
732 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
737 priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
738 memalign(ARCH_DMA_MINALIGN, desc_count *
739 sizeof(struct omap_hsmmc_adma_desc));
741 if (data->flags & MMC_DATA_READ)
744 buf = (char *)data->src;
747 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
749 total_len -= ADMA_MAX_LEN;
752 omap_hsmmc_adma_desc(mmc, buf, total_len, true);
754 flush_dcache_range((long)priv->adma_desc_table,
755 (long)priv->adma_desc_table +
757 sizeof(struct omap_hsmmc_adma_desc),
761 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
763 struct hsmmc *mmc_base;
764 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
768 mmc_base = priv->base_addr;
769 omap_hsmmc_prepare_adma_table(mmc, data);
771 if (data->flags & MMC_DATA_READ)
774 buf = (char *)data->src;
776 val = readl(&mmc_base->hctl);
778 writel(val, &mmc_base->hctl);
780 val = readl(&mmc_base->con);
782 writel(val, &mmc_base->con);
784 writel((u32)priv->adma_desc_table, &mmc_base->admasal);
786 flush_dcache_range((u32)buf,
788 ROUND(data->blocksize * data->blocks,
792 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
794 struct hsmmc *mmc_base;
795 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
798 mmc_base = priv->base_addr;
800 val = readl(&mmc_base->con);
802 writel(val, &mmc_base->con);
804 val = readl(&mmc_base->hctl);
806 writel(val, &mmc_base->hctl);
808 kfree(priv->adma_desc_table);
811 #define omap_hsmmc_adma_desc
812 #define omap_hsmmc_prepare_adma_table
813 #define omap_hsmmc_prepare_data
814 #define omap_hsmmc_dma_cleanup
817 #if !CONFIG_IS_ENABLED(DM_MMC)
818 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
819 struct mmc_data *data)
821 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
823 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
824 struct mmc_data *data)
826 struct omap_hsmmc_data *priv = dev_get_priv(dev);
827 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
828 struct mmc *mmc = upriv->mmc;
830 struct hsmmc *mmc_base;
831 unsigned int flags, mmc_stat;
834 mmc_base = priv->base_addr;
836 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
839 start = get_timer(0);
840 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
841 if (get_timer(0) - start > MAX_RETRY_MS) {
842 printf("%s: timedout waiting on cmd inhibit to clear\n",
847 writel(0xFFFFFFFF, &mmc_base->stat);
848 start = get_timer(0);
849 while (readl(&mmc_base->stat)) {
850 if (get_timer(0) - start > MAX_RETRY_MS) {
851 printf("%s: timedout waiting for STAT (%x) to clear\n",
852 __func__, readl(&mmc_base->stat));
858 * CMDIDX[13:8] : Command index
859 * DATAPRNT[5] : Data Present Select
860 * ENCMDIDX[4] : Command Index Check Enable
861 * ENCMDCRC[3] : Command CRC Check Enable
866 * 11 = Length 48 Check busy after response
868 /* Delay added before checking the status of frq change
869 * retry not supported by mmc.c(core file)
871 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
872 udelay(50000); /* wait 50 ms */
874 if (!(cmd->resp_type & MMC_RSP_PRESENT))
876 else if (cmd->resp_type & MMC_RSP_136)
877 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
878 else if (cmd->resp_type & MMC_RSP_BUSY)
879 flags = RSP_TYPE_LGHT48B;
881 flags = RSP_TYPE_LGHT48;
883 /* enable default flags */
884 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
886 flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
888 if (cmd->resp_type & MMC_RSP_CRC)
890 if (cmd->resp_type & MMC_RSP_OPCODE)
894 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
895 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
896 flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
897 data->blocksize = 512;
898 writel(data->blocksize | (data->blocks << 16),
901 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
903 if (data->flags & MMC_DATA_READ)
904 flags |= (DP_DATA | DDIR_READ);
906 flags |= (DP_DATA | DDIR_WRITE);
908 #ifndef CONFIG_OMAP34XX
909 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
910 !mmc_is_tuning_cmd(cmd->cmdidx)) {
911 omap_hsmmc_prepare_data(mmc, data);
917 mmc_enable_irq(mmc, cmd);
919 writel(cmd->cmdarg, &mmc_base->arg);
920 udelay(20); /* To fix "No status update" error on eMMC */
921 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
923 start = get_timer(0);
925 mmc_stat = readl(&mmc_base->stat);
926 if (get_timer(start) > MAX_RETRY_MS) {
927 printf("%s : timeout: No status update\n", __func__);
932 if ((mmc_stat & IE_CTO) != 0) {
933 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
935 } else if ((mmc_stat & ERRI_MASK) != 0)
938 if (mmc_stat & CC_MASK) {
939 writel(CC_MASK, &mmc_base->stat);
940 if (cmd->resp_type & MMC_RSP_PRESENT) {
941 if (cmd->resp_type & MMC_RSP_136) {
942 /* response type 2 */
943 cmd->response[3] = readl(&mmc_base->rsp10);
944 cmd->response[2] = readl(&mmc_base->rsp32);
945 cmd->response[1] = readl(&mmc_base->rsp54);
946 cmd->response[0] = readl(&mmc_base->rsp76);
948 /* response types 1, 1b, 3, 4, 5, 6 */
949 cmd->response[0] = readl(&mmc_base->rsp10);
953 #ifndef CONFIG_OMAP34XX
954 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
955 !mmc_is_tuning_cmd(cmd->cmdidx)) {
958 if (mmc_stat & IE_ADMAE) {
959 omap_hsmmc_dma_cleanup(mmc);
963 sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
964 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
965 if (timeout < MAX_RETRY_MS)
966 timeout = MAX_RETRY_MS;
968 start = get_timer(0);
970 mmc_stat = readl(&mmc_base->stat);
971 if (mmc_stat & TC_MASK) {
972 writel(readl(&mmc_base->stat) | TC_MASK,
976 if (get_timer(start) > timeout) {
977 printf("%s : DMA timeout: No status update\n",
983 omap_hsmmc_dma_cleanup(mmc);
988 if (data && (data->flags & MMC_DATA_READ)) {
989 mmc_read_data(mmc_base, data->dest,
990 data->blocksize * data->blocks);
991 } else if (data && (data->flags & MMC_DATA_WRITE)) {
992 mmc_write_data(mmc_base, data->src,
993 data->blocksize * data->blocks);
998 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
1000 unsigned int *output_buf = (unsigned int *)buf;
1001 unsigned int mmc_stat;
1007 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1011 ulong start = get_timer(0);
1013 mmc_stat = readl(&mmc_base->stat);
1014 if (get_timer(0) - start > MAX_RETRY_MS) {
1015 printf("%s: timedout waiting for status!\n",
1019 } while (mmc_stat == 0);
1021 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1022 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1024 if ((mmc_stat & ERRI_MASK) != 0)
1027 if (mmc_stat & BRR_MASK) {
1030 writel(readl(&mmc_base->stat) | BRR_MASK,
1032 for (k = 0; k < count; k++) {
1033 *output_buf = readl(&mmc_base->data);
1039 if (mmc_stat & BWR_MASK)
1040 writel(readl(&mmc_base->stat) | BWR_MASK,
1043 if (mmc_stat & TC_MASK) {
1044 writel(readl(&mmc_base->stat) | TC_MASK,
1052 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1055 unsigned int *input_buf = (unsigned int *)buf;
1056 unsigned int mmc_stat;
1060 * Start Polled Write
1062 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1066 ulong start = get_timer(0);
1068 mmc_stat = readl(&mmc_base->stat);
1069 if (get_timer(0) - start > MAX_RETRY_MS) {
1070 printf("%s: timedout waiting for status!\n",
1074 } while (mmc_stat == 0);
1076 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1077 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1079 if ((mmc_stat & ERRI_MASK) != 0)
1082 if (mmc_stat & BWR_MASK) {
1085 writel(readl(&mmc_base->stat) | BWR_MASK,
1087 for (k = 0; k < count; k++) {
1088 writel(*input_buf, &mmc_base->data);
1094 if (mmc_stat & BRR_MASK)
1095 writel(readl(&mmc_base->stat) | BRR_MASK,
1098 if (mmc_stat & TC_MASK) {
1099 writel(readl(&mmc_base->stat) | TC_MASK,
1107 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1109 writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1112 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1114 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1117 static void omap_hsmmc_set_clock(struct mmc *mmc)
1119 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1120 struct hsmmc *mmc_base;
1121 unsigned int dsor = 0;
1124 mmc_base = priv->base_addr;
1125 omap_hsmmc_stop_clock(mmc_base);
1127 /* TODO: Is setting DTO required here? */
1128 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1129 (ICE_STOP | DTO_15THDTO));
1131 if (mmc->clock != 0) {
1132 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1133 if (dsor > CLKD_MAX)
1139 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1140 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1142 start = get_timer(0);
1143 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1144 if (get_timer(0) - start > MAX_RETRY_MS) {
1145 printf("%s: timedout waiting for ics!\n", __func__);
1150 priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1151 mmc->clock = priv->clock;
1152 omap_hsmmc_start_clock(mmc_base);
1155 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1157 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1158 struct hsmmc *mmc_base;
1160 mmc_base = priv->base_addr;
1161 /* configue bus width */
1162 switch (mmc->bus_width) {
1164 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1169 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1171 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1177 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1179 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1184 priv->bus_width = mmc->bus_width;
1187 #if !CONFIG_IS_ENABLED(DM_MMC)
1188 static int omap_hsmmc_set_ios(struct mmc *mmc)
1190 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1192 static int omap_hsmmc_set_ios(struct udevice *dev)
1194 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1195 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1196 struct mmc *mmc = upriv->mmc;
1199 if (priv->bus_width != mmc->bus_width)
1200 omap_hsmmc_set_bus_width(mmc);
1202 if (priv->clock != mmc->clock)
1203 omap_hsmmc_set_clock(mmc);
1205 #if CONFIG_IS_ENABLED(DM_MMC)
1206 if (priv->mode != mmc->selected_mode)
1207 omap_hsmmc_set_timing(mmc);
1212 #ifdef OMAP_HSMMC_USE_GPIO
1213 #if CONFIG_IS_ENABLED(DM_MMC)
1214 static int omap_hsmmc_getcd(struct udevice *dev)
1216 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1219 value = dm_gpio_get_value(&priv->cd_gpio);
1220 /* if no CD return as 1 */
1224 if (priv->cd_inverted)
1229 static int omap_hsmmc_getwp(struct udevice *dev)
1231 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1234 value = dm_gpio_get_value(&priv->wp_gpio);
1235 /* if no WP return as 0 */
1241 static int omap_hsmmc_getcd(struct mmc *mmc)
1243 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1246 /* if no CD return as 1 */
1247 cd_gpio = priv->cd_gpio;
1251 /* NOTE: assumes card detect signal is active-low */
1252 return !gpio_get_value(cd_gpio);
1255 static int omap_hsmmc_getwp(struct mmc *mmc)
1257 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1260 /* if no WP return as 0 */
1261 wp_gpio = priv->wp_gpio;
1265 /* NOTE: assumes write protect signal is active-high */
1266 return gpio_get_value(wp_gpio);
1271 #if CONFIG_IS_ENABLED(DM_MMC)
1272 static const struct dm_mmc_ops omap_hsmmc_ops = {
1273 .send_cmd = omap_hsmmc_send_cmd,
1274 .set_ios = omap_hsmmc_set_ios,
1275 #ifdef OMAP_HSMMC_USE_GPIO
1276 .get_cd = omap_hsmmc_getcd,
1277 .get_wp = omap_hsmmc_getwp,
1279 #ifdef MMC_SUPPORTS_TUNING
1280 .execute_tuning = omap_hsmmc_execute_tuning,
1284 static const struct mmc_ops omap_hsmmc_ops = {
1285 .send_cmd = omap_hsmmc_send_cmd,
1286 .set_ios = omap_hsmmc_set_ios,
1287 .init = omap_hsmmc_init_setup,
1288 #ifdef OMAP_HSMMC_USE_GPIO
1289 .getcd = omap_hsmmc_getcd,
1290 .getwp = omap_hsmmc_getwp,
1295 #if !CONFIG_IS_ENABLED(DM_MMC)
1296 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1300 struct omap_hsmmc_data *priv;
1301 struct mmc_config *cfg;
1304 priv = malloc(sizeof(*priv));
1308 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1310 switch (dev_index) {
1312 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1314 #ifdef OMAP_HSMMC2_BASE
1316 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1317 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1318 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1319 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1320 defined(CONFIG_HSMMC2_8BIT)
1321 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1322 host_caps_val |= MMC_MODE_8BIT;
1326 #ifdef OMAP_HSMMC3_BASE
1328 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1329 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1330 /* Enable 8-bit interface for eMMC on DRA7XX */
1331 host_caps_val |= MMC_MODE_8BIT;
1336 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1339 #ifdef OMAP_HSMMC_USE_GPIO
1340 /* on error gpio values are set to -1, which is what we want */
1341 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1342 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1347 cfg->name = "OMAP SD/MMC";
1348 cfg->ops = &omap_hsmmc_ops;
1350 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1351 cfg->host_caps = host_caps_val & ~host_caps_mask;
1353 cfg->f_min = 400000;
1358 if (cfg->host_caps & MMC_MODE_HS) {
1359 if (cfg->host_caps & MMC_MODE_HS_52MHz)
1360 cfg->f_max = 52000000;
1362 cfg->f_max = 26000000;
1364 cfg->f_max = 20000000;
1367 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1369 #if defined(CONFIG_OMAP34XX)
1371 * Silicon revs 2.1 and older do not support multiblock transfers.
1373 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1377 mmc = mmc_create(cfg, priv);
1385 #ifdef CONFIG_IODELAY_RECALIBRATION
1386 static struct pad_conf_entry *
1387 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1390 struct pad_conf_entry *padconf;
1392 padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1394 debug("failed to allocate memory\n");
1398 while (index < count) {
1399 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1400 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1407 static struct iodelay_cfg_entry *
1408 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1411 struct iodelay_cfg_entry *iodelay;
1413 iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1415 debug("failed to allocate memory\n");
1419 while (index < count) {
1420 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1421 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1422 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1429 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32 phandle,
1430 const char *name, int *len)
1432 const void *fdt = gd->fdt_blob;
1434 const fdt32_t *pinctrl;
1436 offset = fdt_node_offset_by_phandle(fdt, phandle);
1438 debug("failed to get pinctrl node %s.\n",
1439 fdt_strerror(offset));
1443 pinctrl = fdt_getprop(fdt, offset, name, len);
1445 debug("failed to get property %s\n", name);
1452 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1455 const void *fdt = gd->fdt_blob;
1456 const __be32 *phandle;
1457 int node = dev_of_offset(mmc->dev);
1459 phandle = fdt_getprop(fdt, node, prop_name, NULL);
1461 debug("failed to get property %s\n", prop_name);
1465 return fdt32_to_cpu(*phandle);
1468 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1471 const void *fdt = gd->fdt_blob;
1472 const __be32 *phandle;
1475 int node = dev_of_offset(mmc->dev);
1477 phandle = fdt_getprop(fdt, node, prop_name, &len);
1479 debug("failed to get property %s\n", prop_name);
1483 /* No manual mode iodelay values if count < 2 */
1484 count = len / sizeof(*phandle);
1488 return fdt32_to_cpu(*(phandle + 1));
1491 static struct pad_conf_entry *
1492 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1496 struct pad_conf_entry *padconf;
1498 const fdt32_t *pinctrl;
1500 phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1502 return ERR_PTR(-EINVAL);
1504 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1507 return ERR_PTR(-EINVAL);
1509 count = (len / sizeof(*pinctrl)) / 2;
1510 padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1512 return ERR_PTR(-EINVAL);
1519 static struct iodelay_cfg_entry *
1520 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1524 struct iodelay_cfg_entry *iodelay;
1526 const fdt32_t *pinctrl;
1528 phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1529 /* Not all modes have manual mode iodelay values. So its not fatal */
1533 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1536 return ERR_PTR(-EINVAL);
1538 count = (len / sizeof(*pinctrl)) / 3;
1539 iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1541 return ERR_PTR(-EINVAL);
1548 static struct omap_hsmmc_pinctrl_state *
1549 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1554 const void *fdt = gd->fdt_blob;
1555 int node = dev_of_offset(mmc->dev);
1557 struct omap_hsmmc_pinctrl_state *pinctrl_state;
1559 pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1560 malloc(sizeof(*pinctrl_state));
1561 if (!pinctrl_state) {
1562 debug("failed to allocate memory\n");
1566 index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1568 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1569 goto err_pinctrl_state;
1572 sprintf(prop_name, "pinctrl-%d", index);
1574 pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1576 if (IS_ERR(pinctrl_state->padconf))
1577 goto err_pinctrl_state;
1578 pinctrl_state->npads = npads;
1580 pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1582 if (IS_ERR(pinctrl_state->iodelay))
1584 pinctrl_state->niodelays = niodelays;
1586 return pinctrl_state;
1589 kfree(pinctrl_state->padconf);
1592 kfree(pinctrl_state);
1596 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional) \
1598 struct omap_hsmmc_pinctrl_state *s = NULL; \
1600 if (!(cfg->host_caps & capmask)) \
1603 if (priv->hw_rev) { \
1604 sprintf(str, "%s-%s", #mode, priv->hw_rev); \
1605 s = omap_hsmmc_get_pinctrl_by_mode(mmc, str); \
1609 s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1611 if (!s && !optional) { \
1612 debug("%s: no pinctrl for %s\n", \
1613 mmc->dev->name, #mode); \
1614 cfg->host_caps &= ~(capmask); \
1616 priv->mode##_pinctrl_state = s; \
1620 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1622 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1623 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1624 struct omap_hsmmc_pinctrl_state *default_pinctrl;
1626 if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1629 default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1630 if (!default_pinctrl) {
1631 printf("no pinctrl state for default mode\n");
1635 priv->default_pinctrl_state = default_pinctrl;
1637 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1638 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1639 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1640 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1641 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
1643 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1644 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1645 OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
1651 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1652 #ifdef CONFIG_OMAP54XX
1653 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1659 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1661 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1662 struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1664 struct mmc_config *cfg = &plat->cfg;
1665 #ifdef CONFIG_OMAP54XX
1666 const struct mmc_platform_fixups *fixups;
1668 const void *fdt = gd->fdt_blob;
1669 int node = dev_of_offset(dev);
1672 plat->base_addr = map_physmem(devfdt_get_addr(dev),
1673 sizeof(struct hsmmc *),
1676 ret = mmc_of_parse(dev, cfg);
1680 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1681 cfg->f_min = 400000;
1682 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1683 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1684 if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1685 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1686 if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1687 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1689 plat->controller_flags |= of_data->controller_flags;
1691 #ifdef CONFIG_OMAP54XX
1692 fixups = platform_fixups_mmc(devfdt_get_addr(dev));
1694 plat->hw_rev = fixups->hw_rev;
1695 cfg->host_caps &= ~fixups->unsupported_caps;
1696 cfg->f_max = fixups->max_freq;
1700 #ifdef OMAP_HSMMC_USE_GPIO
1701 plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
1710 static int omap_hsmmc_bind(struct udevice *dev)
1712 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1714 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1717 static int omap_hsmmc_probe(struct udevice *dev)
1719 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1720 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1721 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1722 struct mmc_config *cfg = &plat->cfg;
1724 #ifdef CONFIG_IODELAY_RECALIBRATION
1728 cfg->name = "OMAP SD/MMC";
1729 priv->base_addr = plat->base_addr;
1730 priv->controller_flags = plat->controller_flags;
1731 priv->hw_rev = plat->hw_rev;
1732 #ifdef OMAP_HSMMC_USE_GPIO
1733 priv->cd_inverted = plat->cd_inverted;
1739 mmc = mmc_create(cfg, priv);
1744 #if defined(OMAP_HSMMC_USE_GPIO) && CONFIG_IS_ENABLED(OF_CONTROL)
1745 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1746 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1752 #ifdef CONFIG_IODELAY_RECALIBRATION
1753 ret = omap_hsmmc_get_pinctrl_state(mmc);
1755 * disable high speed modes for the platforms that require IO delay
1756 * and for which we don't have this information
1759 (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
1760 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
1761 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
1766 return omap_hsmmc_init_setup(mmc);
1769 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1771 static const struct omap_mmc_of_data dra7_mmc_of_data = {
1772 .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
1775 static const struct udevice_id omap_hsmmc_ids[] = {
1776 { .compatible = "ti,omap3-hsmmc" },
1777 { .compatible = "ti,omap4-hsmmc" },
1778 { .compatible = "ti,am33xx-hsmmc" },
1779 { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
1784 U_BOOT_DRIVER(omap_hsmmc) = {
1785 .name = "omap_hsmmc",
1787 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1788 .of_match = omap_hsmmc_ids,
1789 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
1790 .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
1793 .bind = omap_hsmmc_bind,
1795 .ops = &omap_hsmmc_ops,
1796 .probe = omap_hsmmc_probe,
1797 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
1798 .flags = DM_FLAG_PRE_RELOC,