2 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/compat.h>
13 #include <linux/dma-direction.h>
15 #include <linux/sizes.h>
16 #include <power/regulator.h>
17 #include <asm/unaligned.h>
19 #include "tmio-common.h"
21 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
24 #define RENESAS_SDHI_SCC_DTCNTL 0x800
25 #define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
26 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
27 #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
28 #define RENESAS_SDHI_SCC_TAPSET 0x804
29 #define RENESAS_SDHI_SCC_DT2FF 0x808
30 #define RENESAS_SDHI_SCC_CKSEL 0x80c
31 #define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
32 #define RENESAS_SDHI_SCC_RVSCNTL 0x810
33 #define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
34 #define RENESAS_SDHI_SCC_RVSREQ 0x814
35 #define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
36 #define RENESAS_SDHI_SCC_SMPCMP 0x818
37 #define RENESAS_SDHI_SCC_TMPPORT2 0x81c
39 #define RENESAS_SDHI_MAX_TAP 3
41 static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
46 tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
48 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
49 reg &= ~TMIO_SD_CLKCTL_SCLKEN;
50 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
52 /* Set sampling clock selection range */
53 tmio_sd_writel(priv, 0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT,
54 RENESAS_SDHI_SCC_DTCNTL);
56 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL);
57 reg |= RENESAS_SDHI_SCC_DTCNTL_TAPEN;
58 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_DTCNTL);
60 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
61 reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
62 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
64 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
65 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
66 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
68 tmio_sd_writel(priv, 0x300 /* scc_tappos */,
69 RENESAS_SDHI_SCC_DT2FF);
71 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
72 reg |= TMIO_SD_CLKCTL_SCLKEN;
73 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
76 return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
77 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
78 RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
81 static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
86 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
87 reg &= ~TMIO_SD_CLKCTL_SCLKEN;
88 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
90 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
91 reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
92 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
94 reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
95 reg |= TMIO_SD_CLKCTL_SCLKEN;
96 tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
98 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
99 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
100 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
102 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
103 reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
104 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
107 static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
110 /* Set sampling clock position */
111 tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
114 static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
116 /* Get comparison of sampling data */
117 return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
120 static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
121 unsigned int tap_num, unsigned int taps,
124 unsigned long tap_cnt; /* counter of tuning success */
125 unsigned long tap_set; /* tap position */
126 unsigned long tap_start;/* start position of tuning success */
127 unsigned long tap_end; /* end position of tuning success */
128 unsigned long ntap; /* temporary counter of tuning success */
129 unsigned long match_cnt;/* counter of matching data */
134 /* Clear SCC_RVSREQ */
135 tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
137 /* Merge the results */
138 for (i = 0; i < tap_num * 2; i++) {
139 if (!(taps & BIT(i))) {
140 taps &= ~BIT(i % tap_num);
141 taps &= ~BIT((i % tap_num) + tap_num);
143 if (!(smpcmp & BIT(i))) {
144 smpcmp &= ~BIT(i % tap_num);
145 smpcmp &= ~BIT((i % tap_num) + tap_num);
150 * Find the longest consecutive run of successful probes. If that
151 * is more than RENESAS_SDHI_MAX_TAP probes long then use the
152 * center index as the tap.
158 for (i = 0; i < tap_num * 2; i++) {
162 if (ntap > tap_cnt) {
163 tap_start = i - ntap;
171 if (ntap > tap_cnt) {
172 tap_start = i - ntap;
178 * If all of the TAP is OK, the sampling clock position is selected by
179 * identifying the change point of data.
181 if (tap_cnt == tap_num * 2) {
186 for (i = 0; i < tap_num * 2; i++) {
190 if (ntap > match_cnt) {
191 tap_start = i - ntap;
198 if (ntap > match_cnt) {
199 tap_start = i - ntap;
205 } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
209 tap_set = ((tap_start + tap_end) / 2) % tap_num;
214 tmio_sd_writel(priv, tap_set, RENESAS_SDHI_SCC_TAPSET);
216 /* Enable auto re-tuning */
217 reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
218 reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
219 tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
224 int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
226 struct tmio_sd_priv *priv = dev_get_priv(dev);
227 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
228 struct mmc *mmc = upriv->mmc;
229 unsigned int tap_num;
230 unsigned int taps = 0, smpcmp = 0;
234 /* Only supported on Renesas RCar */
235 if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
238 /* clock tuning is not needed for upto 52MHz */
239 if (!((mmc->selected_mode == MMC_HS_200) ||
240 (mmc->selected_mode == UHS_SDR104) ||
241 (mmc->selected_mode == UHS_SDR50)))
244 tap_num = renesas_sdhi_init_tuning(priv);
246 /* Tuning is not supported */
249 if (tap_num * 2 >= sizeof(taps) * 8) {
251 "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
255 /* Issue CMD19 twice for each tap */
256 for (i = 0; i < 2 * tap_num; i++) {
257 renesas_sdhi_prepare_tuning(priv, i % tap_num);
259 /* Force PIO for the tuning */
261 priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
263 ret = mmc_send_tuning(mmc, opcode, NULL);
270 ret = renesas_sdhi_compare_scc_data(priv);
277 ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp);
281 dev_warn(dev, "Tuning procedure failed\n");
282 renesas_sdhi_reset_tuning(priv);
289 static int renesas_sdhi_set_ios(struct udevice *dev)
291 int ret = tmio_sd_set_ios(dev);
295 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
296 struct tmio_sd_priv *priv = dev_get_priv(dev);
298 renesas_sdhi_reset_tuning(priv);
304 static const struct dm_mmc_ops renesas_sdhi_ops = {
305 .send_cmd = tmio_sd_send_cmd,
306 .set_ios = renesas_sdhi_set_ios,
307 .get_cd = tmio_sd_get_cd,
308 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
309 .execute_tuning = renesas_sdhi_execute_tuning,
313 #define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2
314 #define RENESAS_GEN3_QUIRKS \
315 TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
317 static const struct udevice_id renesas_sdhi_match[] = {
318 { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
319 { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
320 { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
321 { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
322 { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
323 { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
324 { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
325 { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
326 { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
327 { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
331 static int renesas_sdhi_probe(struct udevice *dev)
333 struct tmio_sd_priv *priv = dev_get_priv(dev);
334 u32 quirks = dev_get_driver_data(dev);
335 struct fdt_resource reg_res;
337 DECLARE_GLOBAL_DATA_PTR;
340 if (quirks == RENESAS_GEN2_QUIRKS) {
341 ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
344 dev_err(dev, "\"reg\" resource not found, ret=%i\n",
349 if (fdt_resource_size(®_res) == 0x100)
350 quirks |= TMIO_SD_CAP_16BIT;
353 ret = clk_get_by_index(dev, 0, &clk);
355 dev_err(dev, "failed to get host clock\n");
359 /* set to max rate */
360 priv->mclk = clk_set_rate(&clk, ULONG_MAX);
361 if (IS_ERR_VALUE(priv->mclk)) {
362 dev_err(dev, "failed to set rate for host clock\n");
367 ret = clk_enable(&clk);
370 dev_err(dev, "failed to enable host clock\n");
374 ret = tmio_sd_probe(dev, quirks);
375 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
377 renesas_sdhi_reset_tuning(dev_get_priv(dev));
382 U_BOOT_DRIVER(renesas_sdhi) = {
383 .name = "renesas-sdhi",
385 .of_match = renesas_sdhi_match,
386 .bind = tmio_sd_bind,
387 .probe = renesas_sdhi_probe,
388 .priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
389 .platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
390 .ops = &renesas_sdhi_ops,