2 * (C) Copyright 2009 SAMSUNG Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Jaehoon Chung <jh80.chung@samsung.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <asm/arch/mmc.h>
26 /* support 4 mmc hosts */
27 struct mmc mmc_dev[4];
28 struct mmc_host mmc_host[4];
30 static inline struct s5p_mmc *s5p_get_base_mmc(int dev_index)
32 unsigned long offset = dev_index * sizeof(struct s5p_mmc);
35 return (struct s5p_mmc *)(S5PC100_MMC_BASE + offset);
37 return (struct s5p_mmc *)(S5PC110_MMC_BASE + offset);
40 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
44 debug("data->dest: %08x\n", (u32)data->dest);
45 writel((u32)data->dest, &host->reg->sysad);
50 * 10 = Selects 32-bit Address ADMA2
51 * 11 = Selects 64-bit Address ADMA2
53 ctrl = readb(&host->reg->hostctl);
55 writeb(ctrl, &host->reg->hostctl);
57 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
58 writew((7 << 12) | (512 << 0), &host->reg->blksize);
59 writew(data->blocks, &host->reg->blkcnt);
62 static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
68 * MUL1SIN0[5] : Multi/Single Block Select
69 * RD1WT0[4] : Data Transfer Direction Select
72 * ENACMD12[2] : Auto CMD12 Enable
73 * ENBLKCNT[1] : Block Count Enable
74 * ENDMA[0] : DMA Enable
76 mode = (1 << 1) | (1 << 0);
79 if (data->flags & MMC_DATA_READ)
82 writew(mode, &host->reg->trnmod);
85 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
86 struct mmc_data *data)
88 struct mmc_host *host = (struct mmc_host *)mmc->priv;
92 unsigned int retry = 0x100000;
99 * CMDINHDAT[1] : Command Inhibit (DAT)
100 * CMDINHCMD[0] : Command Inhibit (CMD)
103 if ((data != NULL) || (cmd->resp_type & MMC_RSP_BUSY))
107 * We shouldn't wait for data inihibit for stop commands, even
108 * though they might use busy signaling
113 while (readl(&host->reg->prnsts) & mask) {
115 printf("%s: timeout error\n", __func__);
123 mmc_prepare_data(host, data);
125 debug("cmd->arg: %08x\n", cmd->cmdarg);
126 writel(cmd->cmdarg, &host->reg->argument);
129 mmc_set_transfer_mode(host, data);
131 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
136 * CMDIDX[13:8] : Command index
137 * DATAPRNT[5] : Data Present Select
138 * ENCMDIDX[4] : Command Index Check Enable
139 * ENCMDCRC[3] : Command CRC Check Enable
144 * 11 = Length 48 Check busy after response
146 if (!(cmd->resp_type & MMC_RSP_PRESENT))
148 else if (cmd->resp_type & MMC_RSP_136)
150 else if (cmd->resp_type & MMC_RSP_BUSY)
155 if (cmd->resp_type & MMC_RSP_CRC)
157 if (cmd->resp_type & MMC_RSP_OPCODE)
162 debug("cmd: %d\n", cmd->cmdidx);
164 writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
166 for (i = 0; i < retry; i++) {
167 mask = readl(&host->reg->norintsts);
168 /* Command Complete */
169 if (mask & (1 << 0)) {
171 writel(mask, &host->reg->norintsts);
177 printf("%s: waiting for status update\n", __func__);
181 if (mask & (1 << 16)) {
183 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
185 } else if (mask & (1 << 15)) {
186 /* Error Interrupt */
187 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
191 if (cmd->resp_type & MMC_RSP_PRESENT) {
192 if (cmd->resp_type & MMC_RSP_136) {
193 /* CRC is stripped so we need to do some shifting. */
194 for (i = 0; i < 4; i++) {
195 unsigned int offset =
196 (unsigned int)(&host->reg->rspreg3 - i);
197 cmd->response[i] = readl(offset) << 8;
203 debug("cmd->resp[%d]: %08x\n",
204 i, cmd->response[i]);
206 } else if (cmd->resp_type & MMC_RSP_BUSY) {
207 for (i = 0; i < retry; i++) {
208 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
209 if (readl(&host->reg->prnsts)
210 & (1 << 20)) /* DAT[0] */
215 printf("%s: card is still busy\n", __func__);
219 cmd->response[0] = readl(&host->reg->rspreg0);
220 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
222 cmd->response[0] = readl(&host->reg->rspreg0);
223 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
229 mask = readl(&host->reg->norintsts);
231 if (mask & (1 << 15)) {
232 /* Error Interrupt */
233 writel(mask, &host->reg->norintsts);
234 printf("%s: error during transfer: 0x%08x\n",
237 } else if (mask & (1 << 3)) {
241 } else if (mask & (1 << 1)) {
242 /* Transfer Complete */
243 debug("r/w is done\n");
247 writel(mask, &host->reg->norintsts);
254 static void mmc_change_clock(struct mmc_host *host, uint clock)
258 unsigned long timeout;
265 * 11 = XTI or XEXTCLK
267 ctrl2 = readl(&host->reg->control2);
270 writel(ctrl2, &host->reg->control2);
272 writew(0, &host->reg->clkcon);
274 /* XXX: we assume that clock is between 40MHz and 50MHz */
277 else if (clock <= 400000)
279 else if (clock <= 20000000)
281 else if (clock <= 26000000)
285 debug("div: %d\n", div);
290 * SELFREQ[15:8] : base clock divied by value
291 * ENSDCLK[2] : SD Clock Enable
292 * STBLINTCLK[1] : Internal Clock Stable
293 * ENINTCLK[0] : Internal Clock Enable
295 clk = (div << 8) | (1 << 0);
296 writew(clk, &host->reg->clkcon);
300 while (!(readw(&host->reg->clkcon) & (1 << 1))) {
302 printf("%s: timeout error\n", __func__);
310 writew(clk, &host->reg->clkcon);
316 static void mmc_set_ios(struct mmc *mmc)
318 struct mmc_host *host = mmc->priv;
322 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
331 writel(0x3 << 16, &host->reg->control4);
333 val = readl(&host->reg->control2);
336 val |= (1 << 31) | /* write status clear async mode enable */
337 (1 << 30) | /* command conflict mask enable */
338 (1 << 14) | /* Feedback Clock Enable for Rx Clock */
339 (1 << 8); /* SDCLK hold enable */
341 writel(val, &host->reg->control2);
344 * FCSEL1[15] FCSEL0[7]
345 * FCSel[1:0] : Rx Feedback Clock Delay Control
346 * Inverter delay means10ns delay if SDCLK 50MHz setting
347 * 01 = Delay1 (basic delay)
348 * 11 = Delay2 (basic delay + 2ns)
349 * 00 = Delay3 (inverter delay)
350 * 10 = Delay4 (inverter delay + 2ns)
352 writel(0x8080, &host->reg->control3);
354 mmc_change_clock(host, mmc->clock);
356 ctrl = readb(&host->reg->hostctl);
363 if (mmc->bus_width == 4)
370 * 1 = Riging edge output
371 * 0 = Falling edge output
375 writeb(ctrl, &host->reg->hostctl);
378 static void mmc_reset(struct mmc_host *host)
380 unsigned int timeout;
383 * RSTALL[0] : Software reset for all
387 writeb((1 << 0), &host->reg->swrst);
391 /* Wait max 100 ms */
394 /* hw clears the bit when it's done */
395 while (readb(&host->reg->swrst) & (1 << 0)) {
397 printf("%s: timeout error\n", __func__);
405 static int mmc_core_init(struct mmc *mmc)
407 struct mmc_host *host = (struct mmc_host *)mmc->priv;
412 host->version = readw(&host->reg->hcver);
415 writel(0xffffffff, &host->reg->norintstsen);
416 writel(0xffffffff, &host->reg->norintsigen);
418 writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */
421 * NORMAL Interrupt Status Enable Register init
422 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
423 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
424 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
425 * [0] ENSTACMDCMPLT : Command Complete Status Enable
427 mask = readl(&host->reg->norintstsen);
429 mask |= (1 << 5) | (1 << 4) | (1 << 1) | (1 << 0);
430 writel(mask, &host->reg->norintstsen);
433 * NORMAL Interrupt Signal Enable Register init
434 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
436 mask = readl(&host->reg->norintsigen);
439 writel(mask, &host->reg->norintsigen);
444 static int s5p_mmc_initialize(int dev_index)
448 mmc = &mmc_dev[dev_index];
450 sprintf(mmc->name, "SAMSUNG SD/MMC");
451 mmc->priv = &mmc_host[dev_index];
452 mmc->send_cmd = mmc_send_cmd;
453 mmc->set_ios = mmc_set_ios;
454 mmc->init = mmc_core_init;
456 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
457 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
460 mmc->f_max = 52000000;
462 mmc_host[dev_index].clock = 0;
463 mmc_host[dev_index].reg = s5p_get_base_mmc(dev_index);
469 int s5p_mmc_init(int dev_index)
471 return s5p_mmc_initialize(dev_index);