2 * (C) Copyright 2012 SAMSUNG Electronics
3 * Jaehoon Chung <jh80.chung@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/mmc.h>
16 #include <asm/arch/clk.h>
18 #include <asm/arch/pinmux.h>
21 struct s5p_sdhci_plat {
22 struct mmc_config cfg;
26 DECLARE_GLOBAL_DATA_PTR;
29 static char *S5P_NAME = "SAMSUNG SDHCI";
30 static void s5p_sdhci_set_control_reg(struct sdhci_host *host)
32 unsigned long val, ctrl;
40 sdhci_writel(host, SDHCI_CTRL4_DRIVE_MASK(0x3), SDHCI_CONTROL4);
42 val = sdhci_readl(host, SDHCI_CONTROL2);
43 val &= SDHCI_CTRL2_SELBASECLK_MASK(3);
45 val |= SDHCI_CTRL2_ENSTAASYNCCLR |
46 SDHCI_CTRL2_ENCMDCNFMSK |
47 SDHCI_CTRL2_ENFBCLKRX |
48 SDHCI_CTRL2_ENCLKOUTHOLD;
50 sdhci_writel(host, val, SDHCI_CONTROL2);
53 * FCSEL3[31] FCSEL2[23] FCSEL1[15] FCSEL0[7]
54 * FCSel[1:0] : Rx Feedback Clock Delay Control
55 * Inverter delay means10ns delay if SDCLK 50MHz setting
56 * 01 = Delay1 (basic delay)
57 * 11 = Delay2 (basic delay + 2ns)
58 * 00 = Delay3 (inverter delay)
59 * 10 = Delay4 (inverter delay + 2ns)
61 val = SDHCI_CTRL3_FCSEL0 | SDHCI_CTRL3_FCSEL1;
62 sdhci_writel(host, val, SDHCI_CONTROL3);
70 ctrl = sdhci_readl(host, SDHCI_CONTROL2);
71 ctrl &= ~SDHCI_CTRL2_SELBASECLK_MASK(0x3);
72 ctrl |= SDHCI_CTRL2_SELBASECLK_MASK(0x2);
73 sdhci_writel(host, ctrl, SDHCI_CONTROL2);
76 static void s5p_set_clock(struct sdhci_host *host, u32 div)
78 /* ToDo : Use the Clock Framework */
79 set_mmc_clk(host->index, div);
82 static int s5p_sdhci_core_init(struct sdhci_host *host)
84 host->name = S5P_NAME;
86 host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
87 SDHCI_QUIRK_32BIT_DMA_ADDR |
88 SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8;
89 host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
91 host->set_control_reg = &s5p_sdhci_set_control_reg;
92 host->set_clock = &s5p_set_clock;
94 if (host->bus_width == 8)
95 host->host_caps |= MMC_MODE_8BIT;
98 return add_sdhci(host, 52000000, 400000);
104 int s5p_sdhci_init(u32 regbase, int index, int bus_width)
106 struct sdhci_host *host = calloc(1, sizeof(struct sdhci_host));
108 printf("sdhci__host allocation fail!\n");
111 host->ioaddr = (void *)regbase;
113 host->bus_width = bus_width;
115 return s5p_sdhci_core_init(host);
118 #if CONFIG_IS_ENABLED(OF_CONTROL)
119 struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS];
121 static int do_sdhci_init(struct sdhci_host *host)
123 int dev_id, flag, ret;
125 flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
126 dev_id = host->index + PERIPH_ID_SDMMC0;
128 ret = exynos_pinmux_config(dev_id, flag);
130 printf("external SD not configured\n");
134 if (dm_gpio_is_valid(&host->pwr_gpio)) {
135 dm_gpio_set_value(&host->pwr_gpio, 1);
136 ret = exynos_pinmux_config(dev_id, flag);
138 debug("MMC not configured\n");
143 if (dm_gpio_is_valid(&host->cd_gpio)) {
144 ret = dm_gpio_get_value(&host->cd_gpio);
146 debug("no SD card detected (%d)\n", ret);
151 return s5p_sdhci_core_init(host);
154 static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host)
156 int bus_width, dev_id;
160 dev_id = pinmux_decode_periph_id(blob, node);
161 if (dev_id < PERIPH_ID_SDMMC0 || dev_id > PERIPH_ID_SDMMC3) {
162 debug("MMC: Can't get device id\n");
165 host->index = dev_id - PERIPH_ID_SDMMC0;
168 bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
169 if (bus_width <= 0) {
170 debug("MMC: Can't get bus-width\n");
173 host->bus_width = bus_width;
175 /* Get the base address from the device node */
176 base = fdtdec_get_addr(blob, node, "reg");
178 debug("MMC: Can't get base address\n");
181 host->ioaddr = (void *)base;
183 gpio_request_by_name_nodev(blob, node, "pwr-gpios", 0, &host->pwr_gpio,
185 gpio_request_by_name_nodev(blob, node, "cd-gpios", 0, &host->cd_gpio,
191 static int process_nodes(const void *blob, int node_list[], int count)
193 struct sdhci_host *host;
197 debug("%s: count = %d\n", __func__, count);
199 /* build sdhci_host[] for each controller */
200 for (i = 0; i < count; i++) {
205 host = &sdhci_host[i];
207 ret = sdhci_get_config(blob, node, host);
209 printf("%s: failed to decode dev %d (%d)\n", __func__, i, ret);
214 ret = do_sdhci_init(host);
215 if (ret && ret != -ENODEV) {
216 printf("%s: failed to initialize dev %d (%d)\n", __func__, i, ret);
221 /* we only consider it an error when all nodes fail */
222 return (failed == count ? -1 : 0);
225 int exynos_mmc_init(const void *blob)
228 int node_list[SDHCI_MAX_HOSTS];
230 count = fdtdec_find_aliases_for_id(blob, "mmc",
231 COMPAT_SAMSUNG_EXYNOS_MMC, node_list,
234 return process_nodes(blob, node_list, count);
239 static int s5p_sdhci_probe(struct udevice *dev)
241 struct s5p_sdhci_plat *plat = dev_get_platdata(dev);
242 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
243 struct sdhci_host *host = dev_get_priv(dev);
246 ret = sdhci_get_config(gd->fdt_blob, dev->of_offset, host);
250 ret = do_sdhci_init(host);
254 ret = sdhci_setup_cfg(&plat->cfg, host, 52000000, 400000);
258 host->mmc = &plat->mmc;
259 host->mmc->priv = host;
260 host->mmc->dev = dev;
261 upriv->mmc = host->mmc;
263 return sdhci_probe(dev);
266 static int s5p_sdhci_bind(struct udevice *dev)
268 struct s5p_sdhci_plat *plat = dev_get_platdata(dev);
271 ret = sdhci_bind(dev, &plat->mmc, &plat->cfg);
278 static const struct udevice_id s5p_sdhci_ids[] = {
279 { .compatible = "samsung,exynos4412-sdhci"},
283 U_BOOT_DRIVER(s5p_sdhci_drv) = {
286 .of_match = s5p_sdhci_ids,
287 .bind = s5p_sdhci_bind,
289 .probe = s5p_sdhci_probe,
290 .priv_auto_alloc_size = sizeof(struct sdhci_host),
291 .platdata_auto_alloc_size = sizeof(struct s5p_sdhci_plat),
293 #endif /* CONFIG_DM_MMC */