2 * Copyright 2011, Marvell Semiconductor Inc.
3 * Lei Wen <leiwen@marvell.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * Back ported to the 8xx platform (from the 8260 platform) by
24 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
34 static void sdhci_reset(struct sdhci_host *host, u8 mask)
36 unsigned long timeout;
40 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
41 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
43 printf("Reset 0x%x never completed.\n", (int)mask);
51 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
54 if (cmd->resp_type & MMC_RSP_136) {
55 /* CRC is stripped so we need to do some shifting. */
56 for (i = 0; i < 4; i++) {
57 cmd->response[i] = sdhci_readl(host,
58 SDHCI_RESPONSE + (3-i)*4) << 8;
60 cmd->response[i] |= sdhci_readb(host,
61 SDHCI_RESPONSE + (3-i)*4-1);
64 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
68 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
72 for (i = 0; i < data->blocksize; i += 4) {
73 offs = data->dest + i;
74 if (data->flags == MMC_DATA_READ)
75 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
77 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
81 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
82 unsigned int start_addr)
84 unsigned int stat, rdy, mask, timeout, block = 0;
85 #ifdef CONFIG_MMC_SDMA
87 ctrl = sdhci_readl(host, SDHCI_HOST_CONTROL);
88 ctrl &= ~SDHCI_CTRL_DMA_MASK;
89 ctrl |= SDHCI_CTRL_SDMA;
90 sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL);
94 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
95 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
97 stat = sdhci_readl(host, SDHCI_INT_STATUS);
98 if (stat & SDHCI_INT_ERROR) {
99 printf("Error detected in status(0x%X)!\n", stat);
103 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
105 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
106 sdhci_transfer_pio(host, data);
107 data->dest += data->blocksize;
108 if (++block >= data->blocks)
111 #ifdef CONFIG_MMC_SDMA
112 if (stat & SDHCI_INT_DMA_END) {
113 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
114 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
115 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
116 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
122 printf("Transfer data timeout\n");
125 } while (!(stat & SDHCI_INT_DATA_END));
129 int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
130 struct mmc_data *data)
132 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
133 unsigned int stat = 0;
135 int trans_bytes = 0, is_aligned = 1;
136 u32 mask, flags, mode;
137 unsigned int timeout, start_addr = 0;
138 unsigned int retry = 10000;
143 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
144 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
146 /* We shouldn't wait for data inihibit for stop commands, even
147 though they might use busy signaling */
148 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
149 mask &= ~SDHCI_DATA_INHIBIT;
151 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
153 printf("Controller never released inhibit bit(s).\n");
160 mask = SDHCI_INT_RESPONSE;
161 if (!(cmd->resp_type & MMC_RSP_PRESENT))
162 flags = SDHCI_CMD_RESP_NONE;
163 else if (cmd->resp_type & MMC_RSP_136)
164 flags = SDHCI_CMD_RESP_LONG;
165 else if (cmd->resp_type & MMC_RSP_BUSY) {
166 flags = SDHCI_CMD_RESP_SHORT_BUSY;
167 mask |= SDHCI_INT_DATA_END;
169 flags = SDHCI_CMD_RESP_SHORT;
171 if (cmd->resp_type & MMC_RSP_CRC)
172 flags |= SDHCI_CMD_CRC;
173 if (cmd->resp_type & MMC_RSP_OPCODE)
174 flags |= SDHCI_CMD_INDEX;
176 flags |= SDHCI_CMD_DATA;
178 /*Set Transfer mode regarding to data flag*/
180 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
181 mode = SDHCI_TRNS_BLK_CNT_EN;
182 trans_bytes = data->blocks * data->blocksize;
183 if (data->blocks > 1)
184 mode |= SDHCI_TRNS_MULTI;
186 if (data->flags == MMC_DATA_READ)
187 mode |= SDHCI_TRNS_READ;
189 #ifdef CONFIG_MMC_SDMA
190 if (data->flags == MMC_DATA_READ)
191 start_addr = (unsigned int)data->dest;
193 start_addr = (unsigned int)data->src;
194 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
195 (start_addr & 0x7) != 0x0) {
197 start_addr = (unsigned int)aligned_buffer;
198 if (data->flags != MMC_DATA_READ)
199 memcpy(aligned_buffer, data->src, trans_bytes);
202 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
203 mode |= SDHCI_TRNS_DMA;
205 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
208 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
209 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
212 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
213 #ifdef CONFIG_MMC_SDMA
214 flush_cache(start_addr, trans_bytes);
216 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
218 stat = sdhci_readl(host, SDHCI_INT_STATUS);
219 if (stat & SDHCI_INT_ERROR)
223 } while ((stat & mask) != mask);
226 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
229 printf("Timeout for status update!\n");
234 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
235 sdhci_cmd_done(host, cmd);
236 sdhci_writel(host, mask, SDHCI_INT_STATUS);
241 ret = sdhci_transfer_data(host, data, start_addr);
243 stat = sdhci_readl(host, SDHCI_INT_STATUS);
244 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
246 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
247 !is_aligned && (data->flags == MMC_DATA_READ))
248 memcpy(data->dest, aligned_buffer, trans_bytes);
252 sdhci_reset(host, SDHCI_RESET_CMD);
253 sdhci_reset(host, SDHCI_RESET_DATA);
254 if (stat & SDHCI_INT_TIMEOUT)
260 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
262 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
263 unsigned int div, clk, timeout;
265 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
270 if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300) {
271 /* Version 3.00 divisors must be a multiple of 2. */
272 if (mmc->f_max <= clock)
275 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
276 if ((mmc->f_max / div) <= clock)
281 /* Version 2.00 divisors must be a power of 2. */
282 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
283 if ((mmc->f_max / div) <= clock)
290 host->set_clock(host->index, div);
292 clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
293 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
294 << SDHCI_DIVIDER_HI_SHIFT;
295 clk |= SDHCI_CLOCK_INT_EN;
296 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
300 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
301 & SDHCI_CLOCK_INT_STABLE)) {
303 printf("Internal clock never stabilised.\n");
310 clk |= SDHCI_CLOCK_CARD_EN;
311 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
315 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
319 if (power != (unsigned short)-1) {
320 switch (1 << power) {
321 case MMC_VDD_165_195:
322 pwr = SDHCI_POWER_180;
326 pwr = SDHCI_POWER_300;
330 pwr = SDHCI_POWER_330;
336 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
340 pwr |= SDHCI_POWER_ON;
342 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
345 void sdhci_set_ios(struct mmc *mmc)
348 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
350 if (host->set_control_reg)
351 host->set_control_reg(host);
353 if (mmc->clock != host->clock)
354 sdhci_set_clock(mmc, mmc->clock);
357 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
358 if (mmc->bus_width == 8) {
359 ctrl &= ~SDHCI_CTRL_4BITBUS;
360 if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
361 ctrl |= SDHCI_CTRL_8BITBUS;
363 if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
364 ctrl &= ~SDHCI_CTRL_8BITBUS;
365 if (mmc->bus_width == 4)
366 ctrl |= SDHCI_CTRL_4BITBUS;
368 ctrl &= ~SDHCI_CTRL_4BITBUS;
371 if (mmc->clock > 26000000)
372 ctrl |= SDHCI_CTRL_HISPD;
374 ctrl &= ~SDHCI_CTRL_HISPD;
376 if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
377 ctrl &= ~SDHCI_CTRL_HISPD;
379 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
382 int sdhci_init(struct mmc *mmc)
384 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
386 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
387 aligned_buffer = memalign(8, 512*1024);
388 if (!aligned_buffer) {
389 printf("Aligned buffer alloc failed!!!");
394 sdhci_set_power(host, fls(mmc->voltages) - 1);
396 if (host->quirks & SDHCI_QUIRK_NO_CD) {
399 sdhci_writel(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
402 status = sdhci_readl(host, SDHCI_PRESENT_STATE);
403 while ((!(status & SDHCI_CARD_PRESENT)) ||
404 (!(status & SDHCI_CARD_STATE_STABLE)) ||
405 (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
406 status = sdhci_readl(host, SDHCI_PRESENT_STATE);
409 /* Eable all state */
410 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_ENABLE);
411 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_SIGNAL_ENABLE);
416 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
421 mmc = malloc(sizeof(struct mmc));
423 printf("mmc malloc fail!\n");
430 sprintf(mmc->name, "%s", host->name);
431 mmc->send_cmd = sdhci_send_command;
432 mmc->set_ios = sdhci_set_ios;
433 mmc->init = sdhci_init;
436 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
437 #ifdef CONFIG_MMC_SDMA
438 if (!(caps & SDHCI_CAN_DO_SDMA)) {
439 printf("Your controller don't support sdma!!\n");
445 mmc->f_max = max_clk;
447 if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
448 mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
449 >> SDHCI_CLOCK_BASE_SHIFT;
451 mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK)
452 >> SDHCI_CLOCK_BASE_SHIFT;
453 mmc->f_max *= 1000000;
455 if (mmc->f_max == 0) {
456 printf("Hardware doesn't specify base clock frequency\n");
460 mmc->f_min = min_clk;
462 if ((host->version & SDHCI_SPEC_VER_MASK) >= SDHCI_SPEC_300)
463 mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300;
465 mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200;
469 if (caps & SDHCI_CAN_VDD_330)
470 mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
471 if (caps & SDHCI_CAN_VDD_300)
472 mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
473 if (caps & SDHCI_CAN_VDD_180)
474 mmc->voltages |= MMC_VDD_165_195;
476 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
477 mmc->voltages |= host->voltages;
479 mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
480 if (caps & SDHCI_CAN_DO_8BIT)
481 mmc->host_caps |= MMC_MODE_8BIT;
483 mmc->host_caps |= host->host_caps;
485 sdhci_reset(host, SDHCI_RESET_ALL);