2 * (C) Copyright 2007-2011
3 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
4 * Aaron <leafy.myeh@allwinnertech.com>
6 * MMC driver for allwinner sunxi platform.
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/clock.h>
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/mmc.h>
19 struct sunxi_mmc_host {
24 struct sunxi_mmc *reg;
25 struct mmc_config cfg;
28 /* support 4 mmc hosts */
29 struct sunxi_mmc_host mmc_host[4];
31 static int mmc_resource_init(int sdc_no)
33 struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
34 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
36 debug("init mmc %d resource\n", sdc_no);
40 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
41 mmchost->mclkreg = &ccm->sd0_clk_cfg;
44 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
45 mmchost->mclkreg = &ccm->sd1_clk_cfg;
48 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
49 mmchost->mclkreg = &ccm->sd2_clk_cfg;
52 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
53 mmchost->mclkreg = &ccm->sd3_clk_cfg;
56 printf("Wrong mmc number %d\n", sdc_no);
59 mmchost->mmc_no = sdc_no;
64 static int mmc_clk_io_on(int sdc_no)
68 struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
69 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
71 debug("init mmc %d clock and io\n", sdc_no);
73 /* config ahb clock */
74 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
76 #if defined(CONFIG_SUN6I)
78 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
81 /* config mod clock */
82 pll_clk = clock_get_pll6();
83 /* should be close to 100 MHz but no more, so round up */
84 divider = ((pll_clk + 99999999) / 100000000) - 1;
85 writel(CCM_MMC_CTRL_ENABLE | CCM_MMC_CTRL_PLL6 | divider,
87 mmchost->mod_clk = pll_clk / (divider + 1);
92 static int mmc_update_clk(struct mmc *mmc)
94 struct sunxi_mmc_host *mmchost = mmc->priv;
96 unsigned timeout_msecs = 2000;
98 cmd = SUNXI_MMC_CMD_START |
99 SUNXI_MMC_CMD_UPCLK_ONLY |
100 SUNXI_MMC_CMD_WAIT_PRE_OVER;
101 writel(cmd, &mmchost->reg->cmd);
102 while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) {
103 if (!timeout_msecs--)
108 /* clock update sets various irq status bits, clear these */
109 writel(readl(&mmchost->reg->rint), &mmchost->reg->rint);
114 static int mmc_config_clock(struct mmc *mmc, unsigned div)
116 struct sunxi_mmc_host *mmchost = mmc->priv;
117 unsigned rval = readl(&mmchost->reg->clkcr);
120 rval &= ~SUNXI_MMC_CLK_ENABLE;
121 writel(rval, &mmchost->reg->clkcr);
122 if (mmc_update_clk(mmc))
125 /* Change Divider Factor */
126 rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
128 writel(rval, &mmchost->reg->clkcr);
129 if (mmc_update_clk(mmc))
131 /* Re-enable Clock */
132 rval |= SUNXI_MMC_CLK_ENABLE;
133 writel(rval, &mmchost->reg->clkcr);
135 if (mmc_update_clk(mmc))
141 static void mmc_set_ios(struct mmc *mmc)
143 struct sunxi_mmc_host *mmchost = mmc->priv;
144 unsigned int clkdiv = 0;
146 debug("set ios: bus_width: %x, clock: %d, mod_clk: %d\n",
147 mmc->bus_width, mmc->clock, mmchost->mod_clk);
149 /* Change clock first */
150 clkdiv = (mmchost->mod_clk + (mmc->clock >> 1)) / mmc->clock / 2;
152 if (mmc_config_clock(mmc, clkdiv)) {
153 mmchost->fatal_err = 1;
158 /* Change bus width */
159 if (mmc->bus_width == 8)
160 writel(0x2, &mmchost->reg->width);
161 else if (mmc->bus_width == 4)
162 writel(0x1, &mmchost->reg->width);
164 writel(0x0, &mmchost->reg->width);
167 static int mmc_core_init(struct mmc *mmc)
169 struct sunxi_mmc_host *mmchost = mmc->priv;
171 /* Reset controller */
172 writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
178 static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
180 struct sunxi_mmc_host *mmchost = mmc->priv;
181 const int reading = !!(data->flags & MMC_DATA_READ);
182 const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
183 SUNXI_MMC_STATUS_FIFO_FULL;
185 unsigned byte_cnt = data->blocksize * data->blocks;
186 unsigned timeout_msecs = 2000;
187 unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
189 /* Always read / write data through the CPU */
190 setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
192 for (i = 0; i < (byte_cnt >> 2); i++) {
193 while (readl(&mmchost->reg->status) & status_bit) {
194 if (!timeout_msecs--)
200 buff[i] = readl(&mmchost->reg->fifo);
202 writel(buff[i], &mmchost->reg->fifo);
208 static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs,
209 unsigned int done_bit, const char *what)
211 struct sunxi_mmc_host *mmchost = mmc->priv;
215 status = readl(&mmchost->reg->rint);
216 if (!timeout_msecs-- ||
217 (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
218 debug("%s timeout %x\n", what,
219 status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
223 } while (!(status & done_bit));
228 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
229 struct mmc_data *data)
231 struct sunxi_mmc_host *mmchost = mmc->priv;
232 unsigned int cmdval = SUNXI_MMC_CMD_START;
233 unsigned int timeout_msecs;
235 unsigned int status = 0;
236 unsigned int bytecnt = 0;
238 if (mmchost->fatal_err)
240 if (cmd->resp_type & MMC_RSP_BUSY)
241 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
242 if (cmd->cmdidx == 12)
246 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
247 if (cmd->resp_type & MMC_RSP_PRESENT)
248 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
249 if (cmd->resp_type & MMC_RSP_136)
250 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
251 if (cmd->resp_type & MMC_RSP_CRC)
252 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
255 if ((u32) data->dest & 0x3) {
260 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
261 if (data->flags & MMC_DATA_WRITE)
262 cmdval |= SUNXI_MMC_CMD_WRITE;
263 if (data->blocks > 1)
264 cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
265 writel(data->blocksize, &mmchost->reg->blksz);
266 writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt);
269 debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no,
270 cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
271 writel(cmd->cmdarg, &mmchost->reg->arg);
274 writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
277 * transfer data and check status
278 * STATREG[2] : FIFO empty
279 * STATREG[3] : FIFO full
284 bytecnt = data->blocksize * data->blocks;
285 debug("trans data %d bytes\n", bytecnt);
286 writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
287 ret = mmc_trans_data_by_cpu(mmc, data);
289 error = readl(&mmchost->reg->rint) & \
290 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
296 error = mmc_rint_wait(mmc, 0xfffff, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
302 debug("cacl timeout %x msec\n", timeout_msecs);
303 error = mmc_rint_wait(mmc, timeout_msecs,
305 SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
306 SUNXI_MMC_RINT_DATA_OVER,
312 if (cmd->resp_type & MMC_RSP_BUSY) {
313 timeout_msecs = 2000;
315 status = readl(&mmchost->reg->status);
316 if (!timeout_msecs--) {
317 debug("busy timeout\n");
322 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
325 if (cmd->resp_type & MMC_RSP_136) {
326 cmd->response[0] = readl(&mmchost->reg->resp3);
327 cmd->response[1] = readl(&mmchost->reg->resp2);
328 cmd->response[2] = readl(&mmchost->reg->resp1);
329 cmd->response[3] = readl(&mmchost->reg->resp0);
330 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
331 cmd->response[3], cmd->response[2],
332 cmd->response[1], cmd->response[0]);
334 cmd->response[0] = readl(&mmchost->reg->resp0);
335 debug("mmc resp 0x%08x\n", cmd->response[0]);
339 writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
342 writel(0xffffffff, &mmchost->reg->rint);
343 writel(readl(&mmchost->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
344 &mmchost->reg->gctrl);
349 static const struct mmc_ops sunxi_mmc_ops = {
350 .send_cmd = mmc_send_cmd,
351 .set_ios = mmc_set_ios,
352 .init = mmc_core_init,
355 int sunxi_mmc_init(int sdc_no)
357 struct mmc_config *cfg = &mmc_host[sdc_no].cfg;
359 memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host));
361 cfg->name = "SUNXI SD/MMC";
362 cfg->ops = &sunxi_mmc_ops;
364 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
365 cfg->host_caps = MMC_MODE_4BIT;
366 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
367 #if defined(CONFIG_SUN6I) || defined(CONFIG_SUN7I) || defined(CONFIG_SUN8I)
368 cfg->host_caps |= MMC_MODE_HC;
370 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
373 cfg->f_max = 52000000;
375 mmc_resource_init(sdc_no);
376 mmc_clk_io_on(sdc_no);
378 if (mmc_create(cfg, &mmc_host[sdc_no]) == NULL)