2 * Arasan NAND Flash Controller Driver
4 * Copyright (C) 2014 - 2015 Xilinx, Inc.
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/errno.h>
13 #include <linux/mtd/mtd.h>
14 #include <linux/mtd/rawnand.h>
15 #include <linux/mtd/partitions.h>
16 #include <linux/mtd/nand_ecc.h>
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/sys_proto.h>
21 struct arasan_nand_info {
22 void __iomem *nand_base;
24 bool on_die_ecc_enabled;
58 #define arasan_nand_base ((struct nand_regs __iomem *)ARASAN_NAND_BASEADDR)
60 struct arasan_nand_command_format {
67 #define ONDIE_ECC_FEATURE_ADDR 0x90
68 #define ENABLE_ONDIE_ECC 0x08
70 #define ARASAN_PROG_RD_MASK 0x00000001
71 #define ARASAN_PROG_BLK_ERS_MASK 0x00000004
72 #define ARASAN_PROG_RD_ID_MASK 0x00000040
73 #define ARASAN_PROG_RD_STS_MASK 0x00000008
74 #define ARASAN_PROG_PG_PROG_MASK 0x00000010
75 #define ARASAN_PROG_RD_PARAM_PG_MASK 0x00000080
76 #define ARASAN_PROG_RST_MASK 0x00000100
77 #define ARASAN_PROG_GET_FTRS_MASK 0x00000200
78 #define ARASAN_PROG_SET_FTRS_MASK 0x00000400
79 #define ARASAN_PROG_CHNG_ROWADR_END_MASK 0x00400000
81 #define ARASAN_NAND_CMD_ECC_ON_MASK 0x80000000
82 #define ARASAN_NAND_CMD_CMD12_MASK 0xFFFF
83 #define ARASAN_NAND_CMD_PG_SIZE_MASK 0x3800000
84 #define ARASAN_NAND_CMD_PG_SIZE_SHIFT 23
85 #define ARASAN_NAND_CMD_CMD2_SHIFT 8
86 #define ARASAN_NAND_CMD_ADDR_CYCL_MASK 0x70000000
87 #define ARASAN_NAND_CMD_ADDR_CYCL_SHIFT 28
89 #define ARASAN_NAND_MEM_ADDR1_PAGE_MASK 0xFFFF0000
90 #define ARASAN_NAND_MEM_ADDR1_COL_MASK 0xFFFF
91 #define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT 16
92 #define ARASAN_NAND_MEM_ADDR2_PAGE_MASK 0xFF
93 #define ARASAN_NAND_MEM_ADDR2_CS_MASK 0xC0000000
94 #define ARASAN_NAND_MEM_ADDR2_BCH_MASK 0xE000000
95 #define ARASAN_NAND_MEM_ADDR2_BCH_SHIFT 25
97 #define ARASAN_NAND_INT_STS_ERR_EN_MASK 0x10
98 #define ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK 0x08
99 #define ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK 0x02
100 #define ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK 0x01
101 #define ARASAN_NAND_INT_STS_XFR_CMPLT_MASK 0x04
103 #define ARASAN_NAND_PKT_REG_PKT_CNT_MASK 0xFFF000
104 #define ARASAN_NAND_PKT_REG_PKT_SIZE_MASK 0x7FF
105 #define ARASAN_NAND_PKT_REG_PKT_CNT_SHFT 12
107 #define ARASAN_NAND_ROW_ADDR_CYCL_MASK 0x0F
108 #define ARASAN_NAND_COL_ADDR_CYCL_MASK 0xF0
109 #define ARASAN_NAND_COL_ADDR_CYCL_SHIFT 4
111 #define ARASAN_NAND_ECC_SIZE_SHIFT 16
112 #define ARASAN_NAND_ECC_BCH_SHIFT 27
114 #define ARASAN_NAND_PKTSIZE_1K 1024
115 #define ARASAN_NAND_PKTSIZE_512 512
117 #define ARASAN_NAND_POLL_TIMEOUT 1000000
118 #define ARASAN_NAND_INVALID_ADDR_CYCL 0xFF
120 #define ERR_ADDR_CYCLE -1
121 #define READ_BUFF_SIZE 0x4000
123 static struct arasan_nand_command_format *curr_cmd;
133 static struct arasan_nand_command_format arasan_nand_commands[] = {
134 {NAND_CMD_READ0, NAND_CMD_READSTART, NAND_ADDR_CYCL_BOTH,
135 ARASAN_PROG_RD_MASK},
136 {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, NAND_ADDR_CYCL_COL,
137 ARASAN_PROG_RD_MASK},
138 {NAND_CMD_READID, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
139 ARASAN_PROG_RD_ID_MASK},
140 {NAND_CMD_STATUS, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE,
141 ARASAN_PROG_RD_STS_MASK},
142 {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, NAND_ADDR_CYCL_BOTH,
143 ARASAN_PROG_PG_PROG_MASK},
144 {NAND_CMD_RNDIN, NAND_CMD_NONE, NAND_ADDR_CYCL_COL,
145 ARASAN_PROG_CHNG_ROWADR_END_MASK},
146 {NAND_CMD_ERASE1, NAND_CMD_ERASE2, NAND_ADDR_CYCL_ROW,
147 ARASAN_PROG_BLK_ERS_MASK},
148 {NAND_CMD_RESET, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE,
149 ARASAN_PROG_RST_MASK},
150 {NAND_CMD_PARAM, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
151 ARASAN_PROG_RD_PARAM_PG_MASK},
152 {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
153 ARASAN_PROG_GET_FTRS_MASK},
154 {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
155 ARASAN_PROG_SET_FTRS_MASK},
156 {NAND_CMD_NONE, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE, 0},
159 struct arasan_ecc_matrix {
161 u32 ecc_codeword_size;
169 static const struct arasan_ecc_matrix ecc_matrix[] = {
170 {512, 512, 1, 0, 0, 0x20D, 0x3},
171 {512, 512, 4, 1, 3, 0x209, 0x7},
172 {512, 512, 8, 1, 2, 0x203, 0xD},
176 {2048, 512, 1, 0, 0, 0x834, 0xC},
177 {2048, 512, 4, 1, 3, 0x826, 0x1A},
178 {2048, 512, 8, 1, 2, 0x80c, 0x34},
179 {2048, 512, 12, 1, 1, 0x822, 0x4E},
180 {2048, 512, 16, 1, 0, 0x808, 0x68},
181 {2048, 1024, 24, 1, 4, 0x81c, 0x54},
185 {4096, 512, 1, 0, 0, 0x1068, 0x18},
186 {4096, 512, 4, 1, 3, 0x104c, 0x34},
187 {4096, 512, 8, 1, 2, 0x1018, 0x68},
188 {4096, 512, 12, 1, 1, 0x1044, 0x9C},
189 {4096, 512, 16, 1, 0, 0x1010, 0xD0},
190 {4096, 1024, 24, 1, 4, 0x1038, 0xA8},
194 {8192, 512, 1, 0, 0, 0x20d0, 0x30},
195 {8192, 512, 4, 1, 3, 0x2098, 0x68},
196 {8192, 512, 8, 1, 2, 0x2030, 0xD0},
197 {8192, 512, 12, 1, 1, 0x2088, 0x138},
198 {8192, 512, 16, 1, 0, 0x2020, 0x1A0},
199 {8192, 1024, 24, 1, 4, 0x2070, 0x150},
203 {16384, 512, 1, 0, 0, 0x4460, 0x60},
204 {16384, 512, 4, 1, 3, 0x43f0, 0xD0},
205 {16384, 512, 8, 1, 2, 0x4320, 0x1A0},
206 {16384, 512, 12, 1, 1, 0x4250, 0x270},
207 {16384, 512, 16, 1, 0, 0x4180, 0x340},
208 {16384, 1024, 24, 1, 4, 0x4220, 0x2A0}
211 static struct nand_ecclayout ondie_nand_oob_64 = {
215 8, 9, 10, 11, 12, 13, 14, 15,
216 24, 25, 26, 27, 28, 29, 30, 31,
217 40, 41, 42, 43, 44, 45, 46, 47,
218 56, 57, 58, 59, 60, 61, 62, 63
222 { .offset = 4, .length = 4 },
223 { .offset = 20, .length = 4 },
224 { .offset = 36, .length = 4 },
225 { .offset = 52, .length = 4 }
230 * bbt decriptors for chips with on-die ECC and
231 * chips with 64-byte OOB
233 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
234 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
236 static struct nand_bbt_descr bbt_main_descr = {
237 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
238 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
243 .pattern = bbt_pattern
246 static struct nand_bbt_descr bbt_mirror_descr = {
247 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
248 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
253 .pattern = mirror_pattern
256 static u8 buf_data[READ_BUFF_SIZE];
257 static u32 buf_index;
259 static struct nand_ecclayout nand_oob;
261 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
263 static void arasan_nand_select_chip(struct mtd_info *mtd, int chip)
267 static void arasan_nand_enable_ecc(void)
271 reg_val = readl(&arasan_nand_base->cmd_reg);
272 reg_val |= ARASAN_NAND_CMD_ECC_ON_MASK;
274 writel(reg_val, &arasan_nand_base->cmd_reg);
277 static u8 arasan_nand_get_addrcycle(struct mtd_info *mtd)
280 struct nand_chip *chip = mtd_to_nand(mtd);
282 switch (curr_cmd->addr_cycles) {
283 case NAND_ADDR_CYCL_NONE:
286 case NAND_ADDR_CYCL_ONE:
289 case NAND_ADDR_CYCL_ROW:
290 addrcycles = chip->onfi_params.addr_cycles &
291 ARASAN_NAND_ROW_ADDR_CYCL_MASK;
293 case NAND_ADDR_CYCL_COL:
294 addrcycles = (chip->onfi_params.addr_cycles &
295 ARASAN_NAND_COL_ADDR_CYCL_MASK) >>
296 ARASAN_NAND_COL_ADDR_CYCL_SHIFT;
298 case NAND_ADDR_CYCL_BOTH:
299 addrcycles = chip->onfi_params.addr_cycles &
300 ARASAN_NAND_ROW_ADDR_CYCL_MASK;
301 addrcycles += (chip->onfi_params.addr_cycles &
302 ARASAN_NAND_COL_ADDR_CYCL_MASK) >>
303 ARASAN_NAND_COL_ADDR_CYCL_SHIFT;
306 addrcycles = ARASAN_NAND_INVALID_ADDR_CYCL;
312 static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size)
314 struct nand_chip *chip = mtd_to_nand(mtd);
315 struct arasan_nand_info *nand = nand_get_controller_data(chip);
316 u32 reg_val, i, pktsize, pktnum;
317 u32 *bufptr = (u32 *)buf;
322 if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K)
323 pktsize = ARASAN_NAND_PKTSIZE_1K;
325 pktsize = ARASAN_NAND_PKTSIZE_512;
328 pktnum = size/pktsize + 1;
330 pktnum = size/pktsize;
332 reg_val = readl(&arasan_nand_base->intsts_enr);
333 reg_val |= ARASAN_NAND_INT_STS_ERR_EN_MASK |
334 ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK;
335 writel(reg_val, &arasan_nand_base->intsts_enr);
337 reg_val = readl(&arasan_nand_base->pkt_reg);
338 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
339 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
340 reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) |
342 writel(reg_val, &arasan_nand_base->pkt_reg);
344 if (!nand->on_die_ecc_enabled) {
345 arasan_nand_enable_ecc();
346 addr_cycles = arasan_nand_get_addrcycle(mtd);
347 if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
348 return ERR_ADDR_CYCLE;
350 writel((NAND_CMD_RNDOUTSTART << ARASAN_NAND_CMD_CMD2_SHIFT) |
351 NAND_CMD_RNDOUT | (addr_cycles <<
352 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT),
353 &arasan_nand_base->ecc_sprcmd_reg);
355 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
357 while (rdcount < pktnum) {
358 timeout = ARASAN_NAND_POLL_TIMEOUT;
359 while (!(readl(&arasan_nand_base->intsts_reg) &
360 ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) {
365 puts("arasan_read_page: timedout:Buff RDY\n");
371 if (pktnum == rdcount) {
372 reg_val = readl(&arasan_nand_base->intsts_enr);
373 reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
374 writel(reg_val, &arasan_nand_base->intsts_enr);
376 reg_val = readl(&arasan_nand_base->intsts_enr);
377 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
378 &arasan_nand_base->intsts_enr);
380 reg_val = readl(&arasan_nand_base->intsts_reg);
381 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
382 &arasan_nand_base->intsts_reg);
384 for (i = 0; i < pktsize/4; i++)
385 bufptr[i] = readl(&arasan_nand_base->buf_dataport);
390 if (rdcount >= pktnum)
393 writel(ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
394 &arasan_nand_base->intsts_enr);
397 timeout = ARASAN_NAND_POLL_TIMEOUT;
399 while (!(readl(&arasan_nand_base->intsts_reg) &
400 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
405 puts("arasan rd_page timedout:Xfer CMPLT\n");
409 reg_val = readl(&arasan_nand_base->intsts_enr);
410 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
411 &arasan_nand_base->intsts_enr);
412 reg_val = readl(&arasan_nand_base->intsts_reg);
413 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
414 &arasan_nand_base->intsts_reg);
416 if (!nand->on_die_ecc_enabled) {
417 if (readl(&arasan_nand_base->intsts_reg) &
418 ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK) {
419 printf("arasan rd_page:sbiterror\n");
423 if (readl(&arasan_nand_base->intsts_reg) &
424 ARASAN_NAND_INT_STS_ERR_EN_MASK) {
425 mtd->ecc_stats.failed++;
426 printf("arasan rd_page:multibiterror\n");
434 static int arasan_nand_read_page_hwecc(struct mtd_info *mtd,
435 struct nand_chip *chip, u8 *buf, int oob_required, int page)
439 status = arasan_nand_read_page(mtd, buf, (mtd->writesize));
442 chip->ecc.read_oob(mtd, chip, page);
447 static void arasan_nand_fill_tx(const u8 *buf, int len)
449 u32 __iomem *nand = &arasan_nand_base->buf_dataport;
451 if (((unsigned long)buf & 0x3) != 0) {
452 if (((unsigned long)buf & 0x1) != 0) {
460 if (((unsigned long)buf & 0x3) != 0) {
462 writew(*(u16 *)buf, nand);
470 writel(*(u32 *)buf, nand);
477 writew(*(u16 *)buf, nand);
487 static int arasan_nand_write_page_hwecc(struct mtd_info *mtd,
488 struct nand_chip *chip, const u8 *buf, int oob_required,
491 u32 reg_val, i, pktsize, pktnum;
492 const u32 *bufptr = (const u32 *)buf;
493 u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
494 u32 size = mtd->writesize;
496 u8 column_addr_cycles;
497 struct arasan_nand_info *nand = nand_get_controller_data(chip);
499 if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K)
500 pktsize = ARASAN_NAND_PKTSIZE_1K;
502 pktsize = ARASAN_NAND_PKTSIZE_512;
505 pktnum = size/pktsize + 1;
507 pktnum = size/pktsize;
509 reg_val = readl(&arasan_nand_base->pkt_reg);
510 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
511 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
512 reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | pktsize;
513 writel(reg_val, &arasan_nand_base->pkt_reg);
515 if (!nand->on_die_ecc_enabled) {
516 arasan_nand_enable_ecc();
517 column_addr_cycles = (chip->onfi_params.addr_cycles &
518 ARASAN_NAND_COL_ADDR_CYCL_MASK) >>
519 ARASAN_NAND_COL_ADDR_CYCL_SHIFT;
520 writel((NAND_CMD_RNDIN | (column_addr_cycles << 28)),
521 &arasan_nand_base->ecc_sprcmd_reg);
523 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
525 while (rdcount < pktnum) {
526 timeout = ARASAN_NAND_POLL_TIMEOUT;
527 while (!(readl(&arasan_nand_base->intsts_reg) &
528 ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) {
534 puts("arasan_write_page: timedout:Buff RDY\n");
540 if (pktnum == rdcount) {
541 reg_val = readl(&arasan_nand_base->intsts_enr);
542 reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
543 writel(reg_val, &arasan_nand_base->intsts_enr);
545 reg_val = readl(&arasan_nand_base->intsts_enr);
546 writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
547 &arasan_nand_base->intsts_enr);
550 reg_val = readl(&arasan_nand_base->intsts_reg);
551 writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
552 &arasan_nand_base->intsts_reg);
554 for (i = 0; i < pktsize/4; i++)
555 writel(bufptr[i], &arasan_nand_base->buf_dataport);
559 if (rdcount >= pktnum)
562 writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
563 &arasan_nand_base->intsts_enr);
566 timeout = ARASAN_NAND_POLL_TIMEOUT;
568 while (!(readl(&arasan_nand_base->intsts_reg) &
569 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
574 puts("arasan write_page timedout:Xfer CMPLT\n");
578 reg_val = readl(&arasan_nand_base->intsts_enr);
579 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
580 &arasan_nand_base->intsts_enr);
581 reg_val = readl(&arasan_nand_base->intsts_reg);
582 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
583 &arasan_nand_base->intsts_reg);
586 chip->ecc.write_oob(mtd, chip, nand->page);
591 static int arasan_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
594 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
595 chip->read_buf(mtd, chip->oob_poi, (mtd->oobsize));
600 static int arasan_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
604 const u8 *buf = chip->oob_poi;
606 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
607 chip->write_buf(mtd, buf, mtd->oobsize);
612 static int arasan_nand_reset(struct arasan_nand_command_format *curr_cmd)
614 u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
617 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
618 &arasan_nand_base->intsts_enr);
619 cmd_reg = readl(&arasan_nand_base->cmd_reg);
620 cmd_reg &= ~ARASAN_NAND_CMD_CMD12_MASK;
622 cmd_reg |= curr_cmd->cmd1 |
623 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
624 writel(cmd_reg, &arasan_nand_base->cmd_reg);
625 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
627 while (!(readl(&arasan_nand_base->intsts_reg) &
628 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
633 printf("ERROR:%s timedout\n", __func__);
637 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
638 &arasan_nand_base->intsts_enr);
640 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
641 &arasan_nand_base->intsts_reg);
646 static u8 arasan_nand_page(struct mtd_info *mtd)
650 switch (mtd->writesize) {
670 printf("%s:Pagesize>16K\n", __func__);
677 static int arasan_nand_send_wrcmd(struct arasan_nand_command_format *curr_cmd,
678 int column, int page_addr, struct mtd_info *mtd)
681 u8 page_val, addr_cycles;
683 writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
684 &arasan_nand_base->intsts_enr);
685 reg_val = readl(&arasan_nand_base->cmd_reg);
686 reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
687 reg_val |= curr_cmd->cmd1 |
688 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
689 if (curr_cmd->cmd1 == NAND_CMD_SEQIN) {
690 reg_val &= ~ARASAN_NAND_CMD_PG_SIZE_MASK;
691 page_val = arasan_nand_page(mtd);
692 reg_val |= (page_val << ARASAN_NAND_CMD_PG_SIZE_SHIFT);
695 reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
696 addr_cycles = arasan_nand_get_addrcycle(mtd);
698 if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
699 return ERR_ADDR_CYCLE;
701 reg_val |= (addr_cycles <<
702 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT);
703 writel(reg_val, &arasan_nand_base->cmd_reg);
708 page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
709 ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
710 column &= ARASAN_NAND_MEM_ADDR1_COL_MASK;
711 writel(page|column, &arasan_nand_base->memadr_reg1);
713 reg_val = readl(&arasan_nand_base->memadr_reg2);
714 reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
715 reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
716 writel(reg_val, &arasan_nand_base->memadr_reg2);
717 reg_val = readl(&arasan_nand_base->memadr_reg2);
718 reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK;
719 writel(reg_val, &arasan_nand_base->memadr_reg2);
724 static void arasan_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
727 u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
729 reg_val = readl(&arasan_nand_base->pkt_reg);
730 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
731 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
733 reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | len;
734 writel(reg_val, &arasan_nand_base->pkt_reg);
735 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
737 while (!(readl(&arasan_nand_base->intsts_reg) &
738 ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) {
744 puts("ERROR:arasan_nand_write_buf timedout:Buff RDY\n");
746 reg_val = readl(&arasan_nand_base->intsts_enr);
747 reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
748 writel(reg_val, &arasan_nand_base->intsts_enr);
749 writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
750 &arasan_nand_base->intsts_enr);
751 reg_val = readl(&arasan_nand_base->intsts_reg);
752 writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
753 &arasan_nand_base->intsts_reg);
755 arasan_nand_fill_tx(buf, len);
757 timeout = ARASAN_NAND_POLL_TIMEOUT;
758 while (!(readl(&arasan_nand_base->intsts_reg) &
759 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
764 puts("ERROR:arasan_nand_write_buf timedout:Xfer CMPLT\n");
766 writel(readl(&arasan_nand_base->intsts_enr) |
767 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
768 &arasan_nand_base->intsts_enr);
769 writel(readl(&arasan_nand_base->intsts_reg) |
770 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
771 &arasan_nand_base->intsts_reg);
774 static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd,
775 int column, int page_addr, struct mtd_info *mtd)
778 u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
781 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
782 &arasan_nand_base->intsts_enr);
783 reg_val = readl(&arasan_nand_base->cmd_reg);
784 reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
785 reg_val |= curr_cmd->cmd1 |
786 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
787 row_addr_cycles = arasan_nand_get_addrcycle(mtd);
789 if (row_addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
790 return ERR_ADDR_CYCLE;
792 reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
793 reg_val |= (row_addr_cycles <<
794 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT);
796 writel(reg_val, &arasan_nand_base->cmd_reg);
798 page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
799 ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
800 column = page_addr & ARASAN_NAND_MEM_ADDR1_COL_MASK;
801 writel(page | column, &arasan_nand_base->memadr_reg1);
803 reg_val = readl(&arasan_nand_base->memadr_reg2);
804 reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
805 reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
806 writel(reg_val, &arasan_nand_base->memadr_reg2);
807 reg_val = readl(&arasan_nand_base->memadr_reg2);
808 reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK;
809 writel(reg_val, &arasan_nand_base->memadr_reg2);
810 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
812 while (!(readl(&arasan_nand_base->intsts_reg) &
813 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
818 printf("ERROR:%s timedout:Xfer CMPLT\n", __func__);
822 reg_val = readl(&arasan_nand_base->intsts_enr);
823 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
824 &arasan_nand_base->intsts_enr);
825 reg_val = readl(&arasan_nand_base->intsts_reg);
826 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
827 &arasan_nand_base->intsts_reg);
832 static int arasan_nand_read_status(struct arasan_nand_command_format *curr_cmd,
833 int column, int page_addr, struct mtd_info *mtd)
836 u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
839 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
840 &arasan_nand_base->intsts_enr);
841 reg_val = readl(&arasan_nand_base->cmd_reg);
842 reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
843 reg_val |= curr_cmd->cmd1 |
844 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
845 addr_cycles = arasan_nand_get_addrcycle(mtd);
847 if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
848 return ERR_ADDR_CYCLE;
850 reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
851 reg_val |= (addr_cycles <<
852 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT);
854 writel(reg_val, &arasan_nand_base->cmd_reg);
856 reg_val = readl(&arasan_nand_base->pkt_reg);
857 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
858 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
859 reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | 1;
860 writel(reg_val, &arasan_nand_base->pkt_reg);
862 reg_val = readl(&arasan_nand_base->memadr_reg2);
863 reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK;
864 writel(reg_val, &arasan_nand_base->memadr_reg2);
866 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
867 while (!(readl(&arasan_nand_base->intsts_reg) &
868 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
874 printf("ERROR:%s: timedout:Xfer CMPLT\n", __func__);
878 reg_val = readl(&arasan_nand_base->intsts_enr);
879 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
880 &arasan_nand_base->intsts_enr);
881 reg_val = readl(&arasan_nand_base->intsts_reg);
882 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
883 &arasan_nand_base->intsts_reg);
888 static int arasan_nand_send_rdcmd(struct arasan_nand_command_format *curr_cmd,
889 int column, int page_addr, struct mtd_info *mtd)
891 u32 reg_val, addr_cycles, page;
894 reg_val = readl(&arasan_nand_base->intsts_enr);
895 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
896 &arasan_nand_base->intsts_enr);
898 reg_val = readl(&arasan_nand_base->cmd_reg);
899 reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
900 reg_val |= curr_cmd->cmd1 |
901 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
903 if (curr_cmd->cmd1 == NAND_CMD_RNDOUT ||
904 curr_cmd->cmd1 == NAND_CMD_READ0) {
905 reg_val &= ~ARASAN_NAND_CMD_PG_SIZE_MASK;
906 page_val = arasan_nand_page(mtd);
907 reg_val |= (page_val << ARASAN_NAND_CMD_PG_SIZE_SHIFT);
910 reg_val &= ~ARASAN_NAND_CMD_ECC_ON_MASK;
912 reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
914 addr_cycles = arasan_nand_get_addrcycle(mtd);
916 if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
917 return ERR_ADDR_CYCLE;
919 reg_val |= (addr_cycles << 28);
920 writel(reg_val, &arasan_nand_base->cmd_reg);
925 page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
926 ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
927 column &= ARASAN_NAND_MEM_ADDR1_COL_MASK;
928 writel(page | column, &arasan_nand_base->memadr_reg1);
930 reg_val = readl(&arasan_nand_base->memadr_reg2);
931 reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
932 reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
933 writel(reg_val, &arasan_nand_base->memadr_reg2);
935 reg_val = readl(&arasan_nand_base->memadr_reg2);
936 reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK;
937 writel(reg_val, &arasan_nand_base->memadr_reg2);
943 static void arasan_nand_read_buf(struct mtd_info *mtd, u8 *buf, int size)
946 u32 *bufptr = (u32 *)buf;
947 u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
949 reg_val = readl(&arasan_nand_base->pkt_reg);
950 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
951 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
952 reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | size;
953 writel(reg_val, &arasan_nand_base->pkt_reg);
955 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
957 while (!(readl(&arasan_nand_base->intsts_reg) &
958 ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) {
964 puts("ERROR:arasan_nand_read_buf timedout:Buff RDY\n");
966 reg_val = readl(&arasan_nand_base->intsts_enr);
967 reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
968 writel(reg_val, &arasan_nand_base->intsts_enr);
970 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
971 &arasan_nand_base->intsts_enr);
972 reg_val = readl(&arasan_nand_base->intsts_reg);
973 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
974 &arasan_nand_base->intsts_reg);
977 for (i = 0; i < size / 4; i++)
978 bufptr[i] = readl(&arasan_nand_base->buf_dataport);
981 bufptr[i] = readl(&arasan_nand_base->buf_dataport);
983 timeout = ARASAN_NAND_POLL_TIMEOUT;
985 while (!(readl(&arasan_nand_base->intsts_reg) &
986 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
992 puts("ERROR:arasan_nand_read_buf timedout:Xfer CMPLT\n");
994 reg_val = readl(&arasan_nand_base->intsts_enr);
995 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
996 &arasan_nand_base->intsts_enr);
997 reg_val = readl(&arasan_nand_base->intsts_reg);
998 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
999 &arasan_nand_base->intsts_reg);
1002 static u8 arasan_nand_read_byte(struct mtd_info *mtd)
1004 struct nand_chip *chip = mtd_to_nand(mtd);
1007 struct nand_onfi_params *p;
1009 if (buf_index == 0) {
1010 p = &chip->onfi_params;
1011 if (curr_cmd->cmd1 == NAND_CMD_READID)
1013 else if (curr_cmd->cmd1 == NAND_CMD_PARAM)
1014 size = sizeof(struct nand_onfi_params);
1015 else if (curr_cmd->cmd1 == NAND_CMD_RNDOUT)
1016 size = le16_to_cpu(p->ext_param_page_length) * 16;
1017 else if (curr_cmd->cmd1 == NAND_CMD_GET_FEATURES)
1019 else if (curr_cmd->cmd1 == NAND_CMD_STATUS)
1020 return readb(&arasan_nand_base->flash_sts_reg);
1023 chip->read_buf(mtd, &buf_data[0], size);
1026 val = *(&buf_data[0] + buf_index);
1032 static void arasan_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
1033 int column, int page_addr)
1036 struct nand_chip *chip = mtd_to_nand(mtd);
1037 struct arasan_nand_info *nand = nand_get_controller_data(chip);
1040 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
1041 &arasan_nand_base->intsts_enr);
1043 if ((command == NAND_CMD_READOOB) &&
1044 (mtd->writesize > 512)) {
1045 column += mtd->writesize;
1046 command = NAND_CMD_READ0;
1049 /* Get the command format */
1050 for (i = 0; (arasan_nand_commands[i].cmd1 != NAND_CMD_NONE ||
1051 arasan_nand_commands[i].cmd2 != NAND_CMD_NONE); i++) {
1052 if (command == arasan_nand_commands[i].cmd1) {
1053 curr_cmd = &arasan_nand_commands[i];
1058 if (curr_cmd == NULL) {
1059 printf("Unsupported Command; 0x%x\n", command);
1063 if (curr_cmd->cmd1 == NAND_CMD_RESET)
1064 ret = arasan_nand_reset(curr_cmd);
1066 if ((curr_cmd->cmd1 == NAND_CMD_READID) ||
1067 (curr_cmd->cmd1 == NAND_CMD_PARAM) ||
1068 (curr_cmd->cmd1 == NAND_CMD_RNDOUT) ||
1069 (curr_cmd->cmd1 == NAND_CMD_GET_FEATURES) ||
1070 (curr_cmd->cmd1 == NAND_CMD_READ0))
1071 ret = arasan_nand_send_rdcmd(curr_cmd, column, page_addr, mtd);
1073 if ((curr_cmd->cmd1 == NAND_CMD_SET_FEATURES) ||
1074 (curr_cmd->cmd1 == NAND_CMD_SEQIN)) {
1075 nand->page = page_addr;
1076 ret = arasan_nand_send_wrcmd(curr_cmd, column, page_addr, mtd);
1079 if (curr_cmd->cmd1 == NAND_CMD_ERASE1)
1080 ret = arasan_nand_erase(curr_cmd, column, page_addr, mtd);
1082 if (curr_cmd->cmd1 == NAND_CMD_STATUS)
1083 ret = arasan_nand_read_status(curr_cmd, column, page_addr, mtd);
1086 printf("ERROR:%s:command:0x%x\n", __func__, curr_cmd->cmd1);
1089 static void arasan_check_ondie(struct mtd_info *mtd)
1091 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1092 struct arasan_nand_info *nand = nand_get_controller_data(nand_chip);
1095 u8 set_feature[4] = {ENABLE_ONDIE_ECC, 0x00, 0x00, 0x00};
1098 /* Send the command for reading device ID */
1099 nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1100 nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0, -1);
1102 /* Read manufacturer and device IDs */
1103 maf_id = nand_chip->read_byte(mtd);
1104 dev_id = nand_chip->read_byte(mtd);
1106 if ((maf_id == NAND_MFR_MICRON) &&
1107 ((dev_id == 0xf1) || (dev_id == 0xa1) || (dev_id == 0xb1) ||
1108 (dev_id == 0xaa) || (dev_id == 0xba) || (dev_id == 0xda) ||
1109 (dev_id == 0xca) || (dev_id == 0xac) || (dev_id == 0xbc) ||
1110 (dev_id == 0xdc) || (dev_id == 0xcc) || (dev_id == 0xa3) ||
1111 (dev_id == 0xb3) || (dev_id == 0xd3) || (dev_id == 0xc3))) {
1112 nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
1113 ONDIE_ECC_FEATURE_ADDR, -1);
1115 nand_chip->write_buf(mtd, &set_feature[0], 4);
1116 nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
1117 ONDIE_ECC_FEATURE_ADDR, -1);
1119 for (i = 0; i < 4; i++)
1120 get_feature[i] = nand_chip->read_byte(mtd);
1122 if (get_feature[0] & ENABLE_ONDIE_ECC)
1123 nand->on_die_ecc_enabled = true;
1125 printf("%s: Unable to enable OnDie ECC\n", __func__);
1127 /* Use the BBT pattern descriptors */
1128 nand_chip->bbt_td = &bbt_main_descr;
1129 nand_chip->bbt_md = &bbt_mirror_descr;
1133 static int arasan_nand_ecc_init(struct mtd_info *mtd)
1136 u32 regval, eccpos_start, i, eccaddr;
1137 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1139 for (i = 0; i < ARRAY_SIZE(ecc_matrix); i++) {
1140 if ((ecc_matrix[i].pagesize == mtd->writesize) &&
1141 (ecc_matrix[i].ecc_codeword_size >=
1142 nand_chip->ecc_step_ds)) {
1143 if (ecc_matrix[i].eccbits >=
1144 nand_chip->ecc_strength_ds) {
1155 eccaddr = mtd->writesize + mtd->oobsize -
1156 ecc_matrix[found].eccsize;
1159 (ecc_matrix[found].eccsize << ARASAN_NAND_ECC_SIZE_SHIFT) |
1160 (ecc_matrix[found].bch << ARASAN_NAND_ECC_BCH_SHIFT);
1161 writel(regval, &arasan_nand_base->ecc_reg);
1163 if (ecc_matrix[found].bch) {
1164 regval = readl(&arasan_nand_base->memadr_reg2);
1165 regval &= ~ARASAN_NAND_MEM_ADDR2_BCH_MASK;
1166 regval |= (ecc_matrix[found].bchval <<
1167 ARASAN_NAND_MEM_ADDR2_BCH_SHIFT);
1168 writel(regval, &arasan_nand_base->memadr_reg2);
1171 nand_oob.eccbytes = ecc_matrix[found].eccsize;
1172 eccpos_start = mtd->oobsize - nand_oob.eccbytes;
1174 for (i = 0; i < nand_oob.eccbytes; i++)
1175 nand_oob.eccpos[i] = eccpos_start + i;
1177 nand_oob.oobfree[0].offset = 2;
1178 nand_oob.oobfree[0].length = eccpos_start - 2;
1180 nand_chip->ecc.size = ecc_matrix[found].ecc_codeword_size;
1181 nand_chip->ecc.strength = ecc_matrix[found].eccbits;
1182 nand_chip->ecc.bytes = ecc_matrix[found].eccsize;
1183 nand_chip->ecc.layout = &nand_oob;
1188 static int arasan_nand_init(struct nand_chip *nand_chip, int devnum)
1190 struct arasan_nand_info *nand;
1191 struct mtd_info *mtd;
1194 nand = calloc(1, sizeof(struct arasan_nand_info));
1196 printf("%s: failed to allocate\n", __func__);
1200 nand->nand_base = arasan_nand_base;
1201 mtd = nand_to_mtd(nand_chip);
1202 nand_set_controller_data(nand_chip, nand);
1204 /* Set the driver entry points for MTD */
1205 nand_chip->cmdfunc = arasan_nand_cmd_function;
1206 nand_chip->select_chip = arasan_nand_select_chip;
1207 nand_chip->read_byte = arasan_nand_read_byte;
1209 /* Buffer read/write routines */
1210 nand_chip->read_buf = arasan_nand_read_buf;
1211 nand_chip->write_buf = arasan_nand_write_buf;
1212 nand_chip->bbt_options = NAND_BBT_USE_FLASH;
1214 writel(0x0, &arasan_nand_base->cmd_reg);
1215 writel(0x0, &arasan_nand_base->pgm_reg);
1217 /* first scan to find the device and get the page size */
1218 if (nand_scan_ident(mtd, 1, NULL)) {
1219 printf("%s: nand_scan_ident failed\n", __func__);
1223 nand_chip->ecc.mode = NAND_ECC_HW;
1224 nand_chip->ecc.hwctl = NULL;
1225 nand_chip->ecc.read_page = arasan_nand_read_page_hwecc;
1226 nand_chip->ecc.write_page = arasan_nand_write_page_hwecc;
1227 nand_chip->ecc.read_oob = arasan_nand_read_oob;
1228 nand_chip->ecc.write_oob = arasan_nand_write_oob;
1230 arasan_check_ondie(mtd);
1233 * If on die supported, then give priority to on-die ecc and use
1234 * it instead of controller ecc.
1236 if (nand->on_die_ecc_enabled) {
1237 nand_chip->ecc.strength = 1;
1238 nand_chip->ecc.size = mtd->writesize;
1239 nand_chip->ecc.bytes = 0;
1240 nand_chip->ecc.layout = &ondie_nand_oob_64;
1242 if (arasan_nand_ecc_init(mtd)) {
1243 printf("%s: nand_ecc_init failed\n", __func__);
1248 if (nand_scan_tail(mtd)) {
1249 printf("%s: nand_scan_tail failed\n", __func__);
1253 if (nand_register(devnum, mtd)) {
1254 printf("Nand Register Fail\n");
1264 void board_nand_init(void)
1266 struct nand_chip *nand = &nand_chip[0];
1268 if (arasan_nand_init(nand, 0))
1269 puts("NAND init failed\n");