2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
8 * Add Programmable Multibit ECC support for various AT91 SoC
9 * (C) Copyright 2012 ATMEL, Hong Xu
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/gpio.h>
21 #include <linux/mtd/nand_ecc.h>
23 #ifdef CONFIG_ATMEL_NAND_HWECC
25 /* Register access macros */
26 #define ecc_readl(add, reg) \
27 readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
28 #define ecc_writel(add, reg, value) \
29 writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
31 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
33 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
35 #ifdef CONFIG_SPL_BUILD
36 #undef CONFIG_SYS_NAND_ONFI_DETECTION
39 struct atmel_nand_host {
40 struct pmecc_regs __iomem *pmecc;
41 struct pmecc_errloc_regs __iomem *pmerrloc;
42 void __iomem *pmecc_rom_base;
45 u16 pmecc_sector_size;
46 u32 pmecc_index_table_offset;
49 int pmecc_bytes_per_sector;
50 int pmecc_sector_number;
51 int pmecc_degree; /* Degree of remainders */
52 int pmecc_cw_len; /* Length of codeword */
54 /* lookup table for alpha_to and index_of */
55 void __iomem *pmecc_alpha_to;
56 void __iomem *pmecc_index_of;
58 /* data for pmecc computation */
60 int16_t *pmecc_partial_syn;
62 int16_t *pmecc_lmu; /* polynomal order */
68 static struct atmel_nand_host pmecc_host;
69 static struct nand_ecclayout atmel_pmecc_oobinfo;
72 * Return number of ecc bytes per sector according to sector size and
73 * correction capability
75 * Following table shows what at91 PMECC supported:
76 * Correction Capability Sector_512_bytes Sector_1024_bytes
77 * ===================== ================ =================
78 * 2-bits 4-bytes 4-bytes
79 * 4-bits 7-bytes 7-bytes
80 * 8-bits 13-bytes 14-bytes
81 * 12-bits 20-bytes 21-bytes
82 * 24-bits 39-bytes 42-bytes
84 static int pmecc_get_ecc_bytes(int cap, int sector_size)
86 int m = 12 + sector_size / 512;
87 return (m * cap + 7) / 8;
90 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
91 int oobsize, int ecc_len)
95 layout->eccbytes = ecc_len;
97 /* ECC will occupy the last ecc_len bytes continuously */
98 for (i = 0; i < ecc_len; i++)
99 layout->eccpos[i] = oobsize - ecc_len + i;
101 layout->oobfree[0].offset = 2;
102 layout->oobfree[0].length =
103 oobsize - ecc_len - layout->oobfree[0].offset;
106 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
110 table_size = host->pmecc_sector_size == 512 ?
111 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
113 /* the ALPHA lookup table is right behind the INDEX lookup table. */
114 return host->pmecc_rom_base + host->pmecc_index_table_offset +
115 table_size * sizeof(int16_t);
118 static void pmecc_data_free(struct atmel_nand_host *host)
120 free(host->pmecc_partial_syn);
121 free(host->pmecc_si);
122 free(host->pmecc_lmu);
123 free(host->pmecc_smu);
124 free(host->pmecc_mu);
125 free(host->pmecc_dmu);
126 free(host->pmecc_delta);
129 static int pmecc_data_alloc(struct atmel_nand_host *host)
131 const int cap = host->pmecc_corr_cap;
134 size = (2 * cap + 1) * sizeof(int16_t);
135 host->pmecc_partial_syn = malloc(size);
136 host->pmecc_si = malloc(size);
137 host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
138 host->pmecc_smu = malloc((cap + 2) * size);
140 size = (cap + 1) * sizeof(int);
141 host->pmecc_mu = malloc(size);
142 host->pmecc_dmu = malloc(size);
143 host->pmecc_delta = malloc(size);
145 if (host->pmecc_partial_syn &&
155 pmecc_data_free(host);
160 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
162 struct nand_chip *nand_chip = mtd->priv;
163 struct atmel_nand_host *host = nand_chip->priv;
167 /* Fill odd syndromes */
168 for (i = 0; i < host->pmecc_corr_cap; i++) {
169 value = pmecc_readl(host->pmecc, rem_port[sector].rem[i / 2]);
173 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
177 static void pmecc_substitute(struct mtd_info *mtd)
179 struct nand_chip *nand_chip = mtd->priv;
180 struct atmel_nand_host *host = nand_chip->priv;
181 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
182 int16_t __iomem *index_of = host->pmecc_index_of;
183 int16_t *partial_syn = host->pmecc_partial_syn;
184 const int cap = host->pmecc_corr_cap;
188 /* si[] is a table that holds the current syndrome value,
189 * an element of that table belongs to the field
193 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
195 /* Computation 2t syndromes based on S(x) */
197 for (i = 1; i < 2 * cap; i += 2) {
198 for (j = 0; j < host->pmecc_degree; j++) {
199 if (partial_syn[i] & (0x1 << j))
200 si[i] = readw(alpha_to + i * j) ^ si[i];
203 /* Even syndrome = (Odd syndrome) ** 2 */
204 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
210 tmp = readw(index_of + si[j]);
211 tmp = (tmp * 2) % host->pmecc_cw_len;
212 si[i] = readw(alpha_to + tmp);
218 * This function defines a Berlekamp iterative procedure for
219 * finding the value of the error location polynomial.
220 * The input is si[], initialize by pmecc_substitute().
221 * The output is smu[][].
223 * This function is written according to chip datasheet Chapter:
224 * Find the Error Location Polynomial Sigma(x) of Section:
225 * Programmable Multibit ECC Control (PMECC).
227 static void pmecc_get_sigma(struct mtd_info *mtd)
229 struct nand_chip *nand_chip = mtd->priv;
230 struct atmel_nand_host *host = nand_chip->priv;
232 int16_t *lmu = host->pmecc_lmu;
233 int16_t *si = host->pmecc_si;
234 int *mu = host->pmecc_mu;
235 int *dmu = host->pmecc_dmu; /* Discrepancy */
236 int *delta = host->pmecc_delta; /* Delta order */
237 int cw_len = host->pmecc_cw_len;
238 const int16_t cap = host->pmecc_corr_cap;
239 const int num = 2 * cap + 1;
240 int16_t __iomem *index_of = host->pmecc_index_of;
241 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
243 uint32_t dmu_0_count, tmp;
244 int16_t *smu = host->pmecc_smu;
246 /* index of largest delta */
251 /* Init the Sigma(x) */
252 memset(smu, 0, sizeof(int16_t) * ARRAY_SIZE(smu));
263 /* discrepancy set to 1 */
265 /* polynom order set to 0 */
267 /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
274 /* Sigma(x) set to 1 */
277 /* discrepancy set to S1 */
280 /* polynom order set to 0 */
283 /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
286 for (i = 1; i <= cap; i++) {
288 /* Begin Computing Sigma (Mu+1) and L(mu) */
289 /* check if discrepancy is set to 0 */
293 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
294 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
299 if (dmu_0_count == tmp) {
300 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
301 smu[(cap + 1) * num + j] =
304 lmu[cap + 1] = lmu[i];
309 for (j = 0; j <= lmu[i] >> 1; j++)
310 smu[(i + 1) * num + j] = smu[i * num + j];
312 /* copy previous polynom order to the next */
317 /* find largest delta with dmu != 0 */
318 for (j = 0; j < i; j++) {
319 if ((dmu[j]) && (delta[j] > largest)) {
325 /* compute difference */
326 diff = (mu[i] - mu[ro]);
328 /* Compute degree of the new smu polynomial */
329 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
332 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
334 /* Init smu[i+1] with 0 */
335 for (k = 0; k < num; k++)
336 smu[(i + 1) * num + k] = 0;
338 /* Compute smu[i+1] */
339 for (k = 0; k <= lmu[ro] >> 1; k++) {
342 if (!(smu[ro * num + k] && dmu[i]))
344 a = readw(index_of + dmu[i]);
345 b = readw(index_of + dmu[ro]);
346 c = readw(index_of + smu[ro * num + k]);
347 tmp = a + (cw_len - b) + c;
348 a = readw(alpha_to + tmp % cw_len);
349 smu[(i + 1) * num + (k + diff)] = a;
352 for (k = 0; k <= lmu[i] >> 1; k++)
353 smu[(i + 1) * num + k] ^= smu[i * num + k];
356 /* End Computing Sigma (Mu+1) and L(mu) */
357 /* In either case compute delta */
358 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
360 /* Do not compute discrepancy for the last iteration */
364 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
367 dmu[i + 1] = si[tmp + 3];
368 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
371 smu[(i + 1) * num + k]);
372 b = si[2 * (i - 1) + 3 - k];
373 c = readw(index_of + b);
376 dmu[i + 1] = readw(alpha_to + tmp) ^
383 static int pmecc_err_location(struct mtd_info *mtd)
385 struct nand_chip *nand_chip = mtd->priv;
386 struct atmel_nand_host *host = nand_chip->priv;
387 const int cap = host->pmecc_corr_cap;
388 const int num = 2 * cap + 1;
389 int sector_size = host->pmecc_sector_size;
390 int err_nbr = 0; /* number of error */
391 int roots_nbr; /* number of roots */
394 int16_t *smu = host->pmecc_smu;
395 int timeout = PMECC_MAX_TIMEOUT_US;
397 pmecc_writel(host->pmerrloc, eldis, PMERRLOC_DISABLE);
399 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
400 pmecc_writel(host->pmerrloc, sigma[i],
401 smu[(cap + 1) * num + i]);
405 val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
406 if (sector_size == 1024)
407 val |= PMERRLOC_ELCFG_SECTOR_1024;
409 pmecc_writel(host->pmerrloc, elcfg, val);
410 pmecc_writel(host->pmerrloc, elen,
411 sector_size * 8 + host->pmecc_degree * cap);
414 if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE)
421 dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n");
425 roots_nbr = (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_ERR_NUM_MASK)
427 /* Number of roots == degree of smu hence <= cap */
428 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
431 /* Number of roots does not match the degree of smu
432 * unable to correct error */
436 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
437 int sector_num, int extra_bytes, int err_nbr)
439 struct nand_chip *nand_chip = mtd->priv;
440 struct atmel_nand_host *host = nand_chip->priv;
442 int byte_pos, bit_pos, sector_size, pos;
446 sector_size = host->pmecc_sector_size;
449 tmp = pmecc_readl(host->pmerrloc, el[i]) - 1;
453 if (byte_pos >= (sector_size + extra_bytes))
454 BUG(); /* should never happen */
456 if (byte_pos < sector_size) {
457 err_byte = *(buf + byte_pos);
458 *(buf + byte_pos) ^= (1 << bit_pos);
460 pos = sector_num * host->pmecc_sector_size + byte_pos;
461 dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
462 pos, bit_pos, err_byte, *(buf + byte_pos));
464 /* Bit flip in OOB area */
465 tmp = sector_num * host->pmecc_bytes_per_sector
466 + (byte_pos - sector_size);
468 ecc[tmp] ^= (1 << bit_pos);
470 pos = tmp + nand_chip->ecc.layout->eccpos[0];
471 dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
472 pos, bit_pos, err_byte, ecc[tmp]);
482 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
485 struct nand_chip *nand_chip = mtd->priv;
486 struct atmel_nand_host *host = nand_chip->priv;
487 int i, err_nbr, eccbytes;
490 /* SAMA5D4 PMECC IP can correct errors for all 0xff page */
491 if (host->pmecc_version >= PMECC_VERSION_SAMA5D4)
494 eccbytes = nand_chip->ecc.bytes;
495 for (i = 0; i < eccbytes; i++)
498 /* Erased page, return OK */
502 for (i = 0; i < host->pmecc_sector_number; i++) {
504 if (pmecc_stat & 0x1) {
505 buf_pos = buf + i * host->pmecc_sector_size;
507 pmecc_gen_syndrome(mtd, i);
508 pmecc_substitute(mtd);
509 pmecc_get_sigma(mtd);
511 err_nbr = pmecc_err_location(mtd);
513 dev_err(host->dev, "PMECC: Too many errors\n");
514 mtd->ecc_stats.failed++;
517 pmecc_correct_data(mtd, buf_pos, ecc, i,
518 host->pmecc_bytes_per_sector, err_nbr);
519 mtd->ecc_stats.corrected += err_nbr;
528 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
529 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
531 struct atmel_nand_host *host = chip->priv;
532 int eccsize = chip->ecc.size;
533 uint8_t *oob = chip->oob_poi;
534 uint32_t *eccpos = chip->ecc.layout->eccpos;
536 int timeout = PMECC_MAX_TIMEOUT_US;
538 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
539 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
540 pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
541 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
543 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
544 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
546 chip->read_buf(mtd, buf, eccsize);
547 chip->read_buf(mtd, oob, mtd->oobsize);
550 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
557 dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n");
561 stat = pmecc_readl(host->pmecc, isr);
563 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
569 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
570 struct nand_chip *chip, const uint8_t *buf,
573 struct atmel_nand_host *host = chip->priv;
574 uint32_t *eccpos = chip->ecc.layout->eccpos;
576 int timeout = PMECC_MAX_TIMEOUT_US;
578 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
579 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
581 pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
582 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
584 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
585 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
587 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
590 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
597 dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
601 for (i = 0; i < host->pmecc_sector_number; i++) {
602 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
605 pos = i * host->pmecc_bytes_per_sector + j;
606 chip->oob_poi[eccpos[pos]] =
607 pmecc_readb(host->pmecc, ecc_port[i].ecc[j]);
610 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
615 static void atmel_pmecc_core_init(struct mtd_info *mtd)
617 struct nand_chip *nand_chip = mtd->priv;
618 struct atmel_nand_host *host = nand_chip->priv;
620 struct nand_ecclayout *ecc_layout;
622 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
623 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
625 switch (host->pmecc_corr_cap) {
627 val = PMECC_CFG_BCH_ERR2;
630 val = PMECC_CFG_BCH_ERR4;
633 val = PMECC_CFG_BCH_ERR8;
636 val = PMECC_CFG_BCH_ERR12;
639 val = PMECC_CFG_BCH_ERR24;
643 if (host->pmecc_sector_size == 512)
644 val |= PMECC_CFG_SECTOR512;
645 else if (host->pmecc_sector_size == 1024)
646 val |= PMECC_CFG_SECTOR1024;
648 switch (host->pmecc_sector_number) {
650 val |= PMECC_CFG_PAGE_1SECTOR;
653 val |= PMECC_CFG_PAGE_2SECTORS;
656 val |= PMECC_CFG_PAGE_4SECTORS;
659 val |= PMECC_CFG_PAGE_8SECTORS;
663 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
664 | PMECC_CFG_AUTO_DISABLE);
665 pmecc_writel(host->pmecc, cfg, val);
667 ecc_layout = nand_chip->ecc.layout;
668 pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
669 pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
670 pmecc_writel(host->pmecc, eaddr,
671 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
672 /* See datasheet about PMECC Clock Control Register */
673 pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
674 pmecc_writel(host->pmecc, idr, 0xff);
675 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
678 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
680 * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
681 * pmecc_corr_cap or pmecc_sector_size is 0, then set it as
682 * ONFI ECC parameters.
683 * @host: point to an atmel_nand_host structure.
684 * if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
685 * if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
686 * @chip: point to an nand_chip structure.
687 * @cap: store the ONFI ECC correct bits capbility
688 * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
690 * Return 0 if success. otherwise return the error code.
692 static int pmecc_choose_ecc(struct atmel_nand_host *host,
693 struct nand_chip *chip,
694 int *cap, int *sector_size)
696 /* Get ECC requirement from ONFI parameters */
697 *cap = *sector_size = 0;
698 if (chip->onfi_version) {
699 *cap = chip->ecc_strength_ds;
700 *sector_size = chip->ecc_step_ds;
701 MTDDEBUG(MTD_DEBUG_LEVEL1, "ONFI params, minimum required ECC: %d bits in %d bytes\n",
705 if (*cap == 0 && *sector_size == 0) {
706 /* Non-ONFI compliant */
707 dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes\n");
712 /* If head file doesn't specify then use the one in ONFI parameters */
713 if (host->pmecc_corr_cap == 0) {
714 /* use the most fitable ecc bits (the near bigger one ) */
716 host->pmecc_corr_cap = 2;
718 host->pmecc_corr_cap = 4;
720 host->pmecc_corr_cap = 8;
722 host->pmecc_corr_cap = 12;
724 host->pmecc_corr_cap = 24;
728 if (host->pmecc_sector_size == 0) {
729 /* use the most fitable sector size (the near smaller one ) */
730 if (*sector_size >= 1024)
731 host->pmecc_sector_size = 1024;
732 else if (*sector_size >= 512)
733 host->pmecc_sector_size = 512;
741 #if defined(NO_GALOIS_TABLE_IN_ROM)
742 static uint16_t *pmecc_galois_table;
743 static inline int deg(unsigned int poly)
745 /* polynomial degree is the most-significant bit index */
746 return fls(poly) - 1;
749 static int build_gf_tables(int mm, unsigned int poly,
750 int16_t *index_of, int16_t *alpha_to)
752 unsigned int i, x = 1;
753 const unsigned int k = 1 << deg(poly);
754 unsigned int nn = (1 << mm) - 1;
756 /* primitive polynomial must be of degree m */
760 for (i = 0; i < nn; i++) {
764 /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
777 static uint16_t *create_lookup_table(int sector_size)
779 int degree = (sector_size == 512) ?
780 PMECC_GF_DIMENSION_13 :
781 PMECC_GF_DIMENSION_14;
782 unsigned int poly = (sector_size == 512) ?
783 PMECC_GF_13_PRIMITIVE_POLY :
784 PMECC_GF_14_PRIMITIVE_POLY;
785 int table_size = (sector_size == 512) ?
786 PMECC_INDEX_TABLE_SIZE_512 :
787 PMECC_INDEX_TABLE_SIZE_1024;
789 int16_t *addr = kzalloc(2 * table_size * sizeof(uint16_t), GFP_KERNEL);
790 if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
793 return (uint16_t *)addr;
797 static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
798 struct mtd_info *mtd)
800 struct atmel_nand_host *host;
801 int cap, sector_size;
803 host = nand->priv = &pmecc_host;
805 nand->ecc.mode = NAND_ECC_HW;
806 nand->ecc.calculate = NULL;
807 nand->ecc.correct = NULL;
808 nand->ecc.hwctl = NULL;
810 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
811 host->pmecc_corr_cap = host->pmecc_sector_size = 0;
813 #ifdef CONFIG_PMECC_CAP
814 host->pmecc_corr_cap = CONFIG_PMECC_CAP;
816 #ifdef CONFIG_PMECC_SECTOR_SIZE
817 host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
819 /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
820 * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
823 if (pmecc_choose_ecc(host, nand, &cap, §or_size)) {
824 dev_err(host->dev, "The NAND flash's ECC requirement(ecc_bits: %d, sector_size: %d) are not support!",
829 if (cap > host->pmecc_corr_cap)
830 dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
831 host->pmecc_corr_cap, cap);
832 if (sector_size < host->pmecc_sector_size)
833 dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
834 host->pmecc_sector_size, sector_size);
835 #else /* CONFIG_SYS_NAND_ONFI_DETECTION */
836 host->pmecc_corr_cap = CONFIG_PMECC_CAP;
837 host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
840 cap = host->pmecc_corr_cap;
841 sector_size = host->pmecc_sector_size;
843 /* TODO: need check whether cap & sector_size is validate */
844 #if defined(NO_GALOIS_TABLE_IN_ROM)
846 * As pmecc_rom_base is the begin of the gallois field table, So the
847 * index offset just set as 0.
849 host->pmecc_index_table_offset = 0;
851 if (host->pmecc_sector_size == 512)
852 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
854 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
857 MTDDEBUG(MTD_DEBUG_LEVEL1,
858 "Initialize PMECC params, cap: %d, sector: %d\n",
861 host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
862 host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
864 #if defined(NO_GALOIS_TABLE_IN_ROM)
865 pmecc_galois_table = create_lookup_table(host->pmecc_sector_size);
866 if (!pmecc_galois_table) {
867 dev_err(host->dev, "out of memory\n");
871 host->pmecc_rom_base = (void __iomem *)pmecc_galois_table;
873 host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
876 /* ECC is calculated for the whole page (1 step) */
877 nand->ecc.size = mtd->writesize;
879 /* set ECC page size and oob layout */
880 switch (mtd->writesize) {
884 host->pmecc_degree = (sector_size == 512) ?
885 PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
886 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
887 host->pmecc_sector_number = mtd->writesize / sector_size;
888 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
890 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
891 host->pmecc_index_of = host->pmecc_rom_base +
892 host->pmecc_index_table_offset;
895 nand->ecc.bytes = host->pmecc_bytes_per_sector *
896 host->pmecc_sector_number;
898 if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
899 dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n",
900 MTD_MAX_ECCPOS_ENTRIES_LARGE);
904 if (nand->ecc.bytes > mtd->oobsize - 2) {
905 dev_err(host->dev, "No room for ECC bytes\n");
908 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
911 nand->ecc.layout = &atmel_pmecc_oobinfo;
916 dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n");
918 /* page size not handled by HW ECC */
919 /* switching back to soft ECC */
920 nand->ecc.mode = NAND_ECC_SOFT;
921 nand->ecc.read_page = NULL;
922 nand->ecc.postpad = 0;
923 nand->ecc.prepad = 0;
928 /* Allocate data for PMECC computation */
929 if (pmecc_data_alloc(host)) {
930 dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
934 nand->options |= NAND_NO_SUBPAGE_WRITE;
935 nand->ecc.read_page = atmel_nand_pmecc_read_page;
936 nand->ecc.write_page = atmel_nand_pmecc_write_page;
937 nand->ecc.strength = cap;
939 /* Check the PMECC ip version */
940 host->pmecc_version = pmecc_readl(host->pmerrloc, version);
941 dev_dbg(host->dev, "PMECC IP version is: %x\n", host->pmecc_version);
943 atmel_pmecc_core_init(mtd);
950 /* oob layout for large page size
951 * bad block info is on bytes 0 and 1
952 * the bytes have to be consecutives to avoid
953 * several NAND_CMD_RNDOUT during read
955 static struct nand_ecclayout atmel_oobinfo_large = {
957 .eccpos = {60, 61, 62, 63},
963 /* oob layout for small page size
964 * bad block info is on bytes 4 and 5
965 * the bytes have to be consecutives to avoid
966 * several NAND_CMD_RNDOUT during read
968 static struct nand_ecclayout atmel_oobinfo_small = {
970 .eccpos = {0, 1, 2, 3},
979 * function called after a write
981 * mtd: MTD block structure
982 * dat: raw data (unused)
983 * ecc_code: buffer for ECC
985 static int atmel_nand_calculate(struct mtd_info *mtd,
986 const u_char *dat, unsigned char *ecc_code)
988 unsigned int ecc_value;
990 /* get the first 2 ECC bytes */
991 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
993 ecc_code[0] = ecc_value & 0xFF;
994 ecc_code[1] = (ecc_value >> 8) & 0xFF;
996 /* get the last 2 ECC bytes */
997 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
999 ecc_code[2] = ecc_value & 0xFF;
1000 ecc_code[3] = (ecc_value >> 8) & 0xFF;
1006 * HW ECC read page function
1008 * mtd: mtd info structure
1009 * chip: nand chip info structure
1010 * buf: buffer to store read data
1011 * oob_required: caller expects OOB data read to chip->oob_poi
1013 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1014 uint8_t *buf, int oob_required, int page)
1016 int eccsize = chip->ecc.size;
1017 int eccbytes = chip->ecc.bytes;
1018 uint32_t *eccpos = chip->ecc.layout->eccpos;
1020 uint8_t *oob = chip->oob_poi;
1025 chip->read_buf(mtd, p, eccsize);
1027 /* move to ECC position if needed */
1028 if (eccpos[0] != 0) {
1029 /* This only works on large pages
1030 * because the ECC controller waits for
1031 * NAND_CMD_RNDOUTSTART after the
1033 * anyway, for small pages, the eccpos[0] == 0
1035 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1036 mtd->writesize + eccpos[0], -1);
1039 /* the ECC controller needs to read the ECC just after the data */
1040 ecc_pos = oob + eccpos[0];
1041 chip->read_buf(mtd, ecc_pos, eccbytes);
1043 /* check if there's an error */
1044 stat = chip->ecc.correct(mtd, p, oob, NULL);
1047 mtd->ecc_stats.failed++;
1049 mtd->ecc_stats.corrected += stat;
1051 /* get back to oob start (end of page) */
1052 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1055 chip->read_buf(mtd, oob, mtd->oobsize);
1063 * function called after a read
1065 * mtd: MTD block structure
1066 * dat: raw data read from the chip
1067 * read_ecc: ECC from the chip (unused)
1070 * Detect and correct a 1 bit error for a page
1072 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1073 u_char *read_ecc, u_char *isnull)
1075 struct nand_chip *nand_chip = mtd->priv;
1076 unsigned int ecc_status;
1077 unsigned int ecc_word, ecc_bit;
1079 /* get the status from the Status Register */
1080 ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
1082 /* if there's no error */
1083 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1086 /* get error bit offset (4 bits) */
1087 ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
1088 /* get word address (12 bits) */
1089 ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
1092 /* if there are multiple errors */
1093 if (ecc_status & ATMEL_ECC_MULERR) {
1094 /* check if it is a freshly erased block
1095 * (filled with 0xff) */
1096 if ((ecc_bit == ATMEL_ECC_BITADDR)
1097 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1098 /* the block has just been erased, return OK */
1101 /* it doesn't seems to be a freshly
1103 * We can't correct so many errors */
1104 dev_warn(host->dev, "atmel_nand : multiple errors detected."
1105 " Unable to correct.\n");
1109 /* if there's a single bit error : we can correct it */
1110 if (ecc_status & ATMEL_ECC_ECCERR) {
1111 /* there's nothing much to do here.
1112 * the bit error is on the ECC itself.
1114 dev_warn(host->dev, "atmel_nand : one bit error on ECC code."
1115 " Nothing to correct\n");
1119 dev_warn(host->dev, "atmel_nand : one bit error on data."
1120 " (word offset in the page :"
1121 " 0x%x bit offset : 0x%x)\n",
1123 /* correct the error */
1124 if (nand_chip->options & NAND_BUSWIDTH_16) {
1126 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1129 dat[ecc_word] ^= (1 << ecc_bit);
1131 dev_warn(host->dev, "atmel_nand : error corrected\n");
1136 * Enable HW ECC : unused on most chips
1138 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1142 int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
1144 nand->ecc.mode = NAND_ECC_HW;
1145 nand->ecc.calculate = atmel_nand_calculate;
1146 nand->ecc.correct = atmel_nand_correct;
1147 nand->ecc.hwctl = atmel_nand_hwctl;
1148 nand->ecc.read_page = atmel_nand_read_page;
1149 nand->ecc.bytes = 4;
1151 if (nand->ecc.mode == NAND_ECC_HW) {
1152 /* ECC is calculated for the whole page (1 step) */
1153 nand->ecc.size = mtd->writesize;
1155 /* set ECC page size and oob layout */
1156 switch (mtd->writesize) {
1158 nand->ecc.layout = &atmel_oobinfo_small;
1159 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1160 ATMEL_ECC_PAGESIZE_528);
1163 nand->ecc.layout = &atmel_oobinfo_large;
1164 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1165 ATMEL_ECC_PAGESIZE_1056);
1168 nand->ecc.layout = &atmel_oobinfo_large;
1169 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1170 ATMEL_ECC_PAGESIZE_2112);
1173 nand->ecc.layout = &atmel_oobinfo_large;
1174 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1175 ATMEL_ECC_PAGESIZE_4224);
1178 /* page size not handled by HW ECC */
1179 /* switching back to soft ECC */
1180 nand->ecc.mode = NAND_ECC_SOFT;
1181 nand->ecc.calculate = NULL;
1182 nand->ecc.correct = NULL;
1183 nand->ecc.hwctl = NULL;
1184 nand->ecc.read_page = NULL;
1185 nand->ecc.postpad = 0;
1186 nand->ecc.prepad = 0;
1187 nand->ecc.bytes = 0;
1195 #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1197 #endif /* CONFIG_ATMEL_NAND_HWECC */
1199 static void at91_nand_hwcontrol(struct mtd_info *mtd,
1200 int cmd, unsigned int ctrl)
1202 struct nand_chip *this = mtd->priv;
1204 if (ctrl & NAND_CTRL_CHANGE) {
1205 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
1206 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
1207 | CONFIG_SYS_NAND_MASK_CLE);
1209 if (ctrl & NAND_CLE)
1210 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
1211 if (ctrl & NAND_ALE)
1212 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
1214 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
1215 gpio_set_value(CONFIG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE));
1217 this->IO_ADDR_W = (void *) IO_ADDR_W;
1220 if (cmd != NAND_CMD_NONE)
1221 writeb(cmd, this->IO_ADDR_W);
1224 #ifdef CONFIG_SYS_NAND_READY_PIN
1225 static int at91_nand_ready(struct mtd_info *mtd)
1227 return gpio_get_value(CONFIG_SYS_NAND_READY_PIN);
1231 #ifdef CONFIG_SPL_BUILD
1232 /* The following code is for SPL */
1233 static nand_info_t mtd;
1234 static struct nand_chip nand_chip;
1236 static int nand_command(int block, int page, uint32_t offs, u8 cmd)
1238 struct nand_chip *this = mtd.priv;
1239 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1240 void (*hwctrl)(struct mtd_info *mtd, int cmd,
1241 unsigned int ctrl) = this->cmd_ctrl;
1243 while (!this->dev_ready(&mtd))
1246 if (cmd == NAND_CMD_READOOB) {
1247 offs += CONFIG_SYS_NAND_PAGE_SIZE;
1248 cmd = NAND_CMD_READ0;
1251 hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1253 if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
1256 hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1257 hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
1258 hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE);
1259 hwctrl(&mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
1260 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1261 hwctrl(&mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
1263 hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1265 hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1266 hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1268 while (!this->dev_ready(&mtd))
1274 static int nand_is_bad_block(int block)
1276 struct nand_chip *this = mtd.priv;
1278 nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
1280 if (this->options & NAND_BUSWIDTH_16) {
1281 if (readw(this->IO_ADDR_R) != 0xffff)
1284 if (readb(this->IO_ADDR_R) != 0xff)
1291 #ifdef CONFIG_SPL_NAND_ECC
1292 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
1293 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
1294 CONFIG_SYS_NAND_ECCSIZE)
1295 #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
1297 static int nand_read_page(int block, int page, void *dst)
1299 struct nand_chip *this = mtd.priv;
1300 u_char ecc_calc[ECCTOTAL];
1301 u_char ecc_code[ECCTOTAL];
1302 u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
1303 int eccsize = CONFIG_SYS_NAND_ECCSIZE;
1304 int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
1305 int eccsteps = ECCSTEPS;
1308 nand_command(block, page, 0, NAND_CMD_READ0);
1310 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1311 if (this->ecc.mode != NAND_ECC_SOFT)
1312 this->ecc.hwctl(&mtd, NAND_ECC_READ);
1313 this->read_buf(&mtd, p, eccsize);
1314 this->ecc.calculate(&mtd, p, &ecc_calc[i]);
1316 this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
1318 for (i = 0; i < ECCTOTAL; i++)
1319 ecc_code[i] = oob_data[nand_ecc_pos[i]];
1321 eccsteps = ECCSTEPS;
1324 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1325 this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
1330 int spl_nand_erase_one(int block, int page)
1332 struct nand_chip *this = mtd.priv;
1333 void (*hwctrl)(struct mtd_info *mtd, int cmd,
1334 unsigned int ctrl) = this->cmd_ctrl;
1337 if (nand_chip.select_chip)
1338 nand_chip.select_chip(&mtd, 0);
1340 page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1341 hwctrl(&mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1343 hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1344 hwctrl(&mtd, ((page_addr >> 8) & 0xff),
1345 NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1346 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1347 /* One more address cycle for devices > 128MiB */
1348 hwctrl(&mtd, (page_addr >> 16) & 0x0f,
1349 NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1351 hwctrl(&mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1353 while (!this->dev_ready(&mtd))
1361 static int nand_read_page(int block, int page, void *dst)
1363 struct nand_chip *this = mtd.priv;
1365 nand_command(block, page, 0, NAND_CMD_READ0);
1366 atmel_nand_pmecc_read_page(&mtd, this, dst, 0, page);
1370 #endif /* CONFIG_SPL_NAND_ECC */
1372 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
1374 unsigned int block, lastblock;
1377 block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
1378 lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
1379 page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
1381 while (block <= lastblock) {
1382 if (!nand_is_bad_block(block)) {
1383 while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
1384 nand_read_page(block, page, dst);
1385 dst += CONFIG_SYS_NAND_PAGE_SIZE;
1400 int at91_nand_wait_ready(struct mtd_info *mtd)
1402 struct nand_chip *this = mtd->priv;
1404 udelay(this->chip_delay);
1409 int board_nand_init(struct nand_chip *nand)
1413 nand->ecc.mode = NAND_ECC_SOFT;
1414 #ifdef CONFIG_SYS_NAND_DBW_16
1415 nand->options = NAND_BUSWIDTH_16;
1416 nand->read_buf = nand_read_buf16;
1418 nand->read_buf = nand_read_buf;
1420 nand->cmd_ctrl = at91_nand_hwcontrol;
1421 #ifdef CONFIG_SYS_NAND_READY_PIN
1422 nand->dev_ready = at91_nand_ready;
1424 nand->dev_ready = at91_nand_wait_ready;
1426 nand->chip_delay = 20;
1427 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1428 nand->bbt_options |= NAND_BBT_USE_FLASH;
1431 #ifdef CONFIG_ATMEL_NAND_HWECC
1432 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1433 ret = atmel_pmecc_nand_init_params(nand, &mtd);
1440 void nand_init(void)
1442 mtd.writesize = CONFIG_SYS_NAND_PAGE_SIZE;
1443 mtd.oobsize = CONFIG_SYS_NAND_OOBSIZE;
1444 mtd.priv = &nand_chip;
1445 nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
1446 nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
1447 board_nand_init(&nand_chip);
1449 #ifdef CONFIG_SPL_NAND_ECC
1450 if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
1451 nand_chip.ecc.calculate = nand_calculate_ecc;
1452 nand_chip.ecc.correct = nand_correct_data;
1456 if (nand_chip.select_chip)
1457 nand_chip.select_chip(&mtd, 0);
1460 void nand_deselect(void)
1462 if (nand_chip.select_chip)
1463 nand_chip.select_chip(&mtd, -1);
1468 #ifndef CONFIG_SYS_NAND_BASE_LIST
1469 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1471 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1472 static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
1474 int atmel_nand_chip_init(int devnum, ulong base_addr)
1477 struct mtd_info *mtd = &nand_info[devnum];
1478 struct nand_chip *nand = &nand_chip[devnum];
1481 nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
1483 #ifdef CONFIG_NAND_ECC_BCH
1484 nand->ecc.mode = NAND_ECC_SOFT_BCH;
1486 nand->ecc.mode = NAND_ECC_SOFT;
1488 #ifdef CONFIG_SYS_NAND_DBW_16
1489 nand->options = NAND_BUSWIDTH_16;
1491 nand->cmd_ctrl = at91_nand_hwcontrol;
1492 #ifdef CONFIG_SYS_NAND_READY_PIN
1493 nand->dev_ready = at91_nand_ready;
1495 nand->chip_delay = 75;
1496 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1497 nand->bbt_options |= NAND_BBT_USE_FLASH;
1500 ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1504 #ifdef CONFIG_ATMEL_NAND_HWECC
1505 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1506 ret = atmel_pmecc_nand_init_params(nand, mtd);
1508 ret = atmel_hwecc_nand_init_param(nand, mtd);
1514 ret = nand_scan_tail(mtd);
1516 nand_register(devnum);
1521 void board_nand_init(void)
1524 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1525 if (atmel_nand_chip_init(i, base_addr[i]))
1526 dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
1529 #endif /* CONFIG_SPL_BUILD */