2 * NAND driver for TI DaVinci based boards.
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
11 * linux/drivers/mtd/nand/nand_davinci.c
15 * Copyright (C) 2006 Texas Instruments.
17 * ----------------------------------------------------------------------------
19 * SPDX-License-Identifier: GPL-2.0+
21 * ----------------------------------------------------------------------------
24 * This is a device driver for the NAND flash device found on the
25 * DaVinci board which utilizes the Samsung k9k2g08 part.
28 ver. 1.0: Feb 2005, Vinod/Sudhakar
35 #include <asm/ti-common/davinci_nand.h>
37 /* Definitions for 4-bit hardware ECC */
38 #define NAND_TIMEOUT 10240
39 #define NAND_ECC_BUSY 0xC
40 #define NAND_4BITECC_MASK 0x03FF03FF
41 #define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
42 #define ECC_STATE_NO_ERR 0x0
43 #define ECC_STATE_TOO_MANY_ERRS 0x1
44 #define ECC_STATE_ERR_CORR_COMP_P 0x2
45 #define ECC_STATE_ERR_CORR_COMP_N 0x3
48 * Exploit the little endianness of the ARM to do multi-byte transfers
49 * per device read. This can perform over twice as quickly as individual
50 * byte transfers when buffer alignment is conducive.
52 * NOTE: This only works if the NAND is not connected to the 2 LSBs of
53 * the address bus. On Davinci EVM platforms this has always been true.
55 static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
57 struct nand_chip *chip = mtd_to_nand(mtd);
58 const u32 *nand = chip->IO_ADDR_R;
60 /* Make sure that buf is 32 bit aligned */
61 if (((int)buf & 0x3) != 0) {
62 if (((int)buf & 0x1) != 0) {
70 if (((int)buf & 0x3) != 0) {
72 *(u16 *)buf = readw(nand);
79 /* copy aligned data */
81 *(u32 *)buf = __raw_readl(nand);
86 /* mop up any remaining bytes */
89 *(u16 *)buf = readw(nand);
99 static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
102 struct nand_chip *chip = mtd_to_nand(mtd);
103 const u32 *nand = chip->IO_ADDR_W;
105 /* Make sure that buf is 32 bit aligned */
106 if (((int)buf & 0x3) != 0) {
107 if (((int)buf & 0x1) != 0) {
115 if (((int)buf & 0x3) != 0) {
117 writew(*(u16 *)buf, nand);
124 /* copy aligned data */
126 __raw_writel(*(u32 *)buf, nand);
131 /* mop up any remaining bytes */
134 writew(*(u16 *)buf, nand);
144 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
147 struct nand_chip *this = mtd_to_nand(mtd);
148 u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
150 if (ctrl & NAND_CTRL_CHANGE) {
151 IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
154 IO_ADDR_W |= MASK_CLE;
156 IO_ADDR_W |= MASK_ALE;
157 this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
160 if (cmd != NAND_CMD_NONE)
161 writeb(cmd, IO_ADDR_W);
164 #ifdef CONFIG_SYS_NAND_HW_ECC
166 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
170 ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
171 CONFIG_SYS_NAND_CS - 2]));
176 static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
180 /* reading the ECC result register resets the ECC calculation */
181 nand_davinci_readecc(mtd);
183 val = __raw_readl(&davinci_emif_regs->nandfcr);
184 val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
185 val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
186 __raw_writel(val, &davinci_emif_regs->nandfcr);
189 static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
194 tmp = nand_davinci_readecc(mtd);
196 /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
197 * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
198 tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
200 /* Invert so that erased block ECC is correct */
204 *ecc_code++ = tmp >> 8;
205 *ecc_code++ = tmp >> 16;
207 /* NOTE: the above code matches mainline Linux:
208 * .PQR.stu ==> ~PQRstu
210 * MontaVista/TI kernels encode those bytes differently, use
211 * complicated (and allegedly sometimes-wrong) correction code,
212 * and usually shipped with U-Boot that uses software ECC:
213 * .PQR.stu ==> PsQRtu
215 * If you need MV/TI compatible NAND I/O in U-Boot, it should
216 * be possible to (a) change the mangling above, (b) reverse
217 * that mangling in nand_davinci_correct_data() below.
223 static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
224 u_char *read_ecc, u_char *calc_ecc)
226 struct nand_chip *this = mtd_to_nand(mtd);
227 u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
229 u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
231 u_int32_t diff = ecc_calc ^ ecc_nand;
234 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
235 /* Correctable error */
236 if ((diff >> (12 + 3)) < this->ecc.size) {
237 uint8_t find_bit = 1 << ((diff >> 12) & 7);
238 uint32_t find_byte = diff >> (12 + 3);
240 dat[find_byte] ^= find_bit;
241 pr_debug("Correcting single "
242 "bit ECC error at offset: %d, bit: "
243 "%d\n", find_byte, find_bit);
248 } else if (!(diff & (diff - 1))) {
249 /* Single bit ECC error in the ECC itself,
251 pr_debug("Single bit ECC error in " "ECC.\n");
254 /* Uncorrectable error */
255 pr_debug("ECC UNCORRECTED_ERROR 1\n");
261 #endif /* CONFIG_SYS_NAND_HW_ECC */
263 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
264 static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
265 #if defined(CONFIG_SYS_NAND_PAGE_2K)
267 #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
269 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
270 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
271 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
272 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
275 {2, 4}, {16, 6}, {32, 6}, {48, 6},
280 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
281 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
282 49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
286 {.offset = 2, .length = 22, },
288 #endif /* #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC */
289 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
292 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
293 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
294 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
295 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
296 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
297 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
298 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
299 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
302 {.offset = 2, .length = 46, },
307 #if defined CONFIG_KEYSTONE_RBL_NAND
308 static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = {
309 #if defined(CONFIG_SYS_NAND_PAGE_2K)
312 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
313 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
314 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
315 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
318 {.offset = 2, .length = 4, },
319 {.offset = 16, .length = 6, },
320 {.offset = 32, .length = 6, },
321 {.offset = 48, .length = 6, },
323 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
326 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
327 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
328 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
329 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
330 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
331 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
332 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,
333 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
336 {.offset = 2, .length = 4, },
337 {.offset = 16, .length = 6, },
338 {.offset = 32, .length = 6, },
339 {.offset = 48, .length = 6, },
340 {.offset = 64, .length = 6, },
341 {.offset = 80, .length = 6, },
342 {.offset = 96, .length = 6, },
343 {.offset = 112, .length = 6, },
348 #ifdef CONFIG_SYS_NAND_PAGE_2K
349 #define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 11
350 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
351 #define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 12
355 * nand_davinci_write_page - write one page
356 * @mtd: MTD device structure
357 * @chip: NAND chip descriptor
358 * @buf: the data to write
359 * @oob_required: must write chip->oob_poi to OOB
360 * @page: page number to write
361 * @cached: cached programming
362 * @raw: use _raw version of write_page
364 static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
365 uint32_t offset, int data_len,
366 const uint8_t *buf, int oob_required,
367 int page, int cached, int raw)
371 struct nand_ecclayout *saved_ecc_layout;
373 /* save current ECC layout and assign Keystone RBL ECC layout */
374 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
375 saved_ecc_layout = chip->ecc.layout;
376 chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
377 mtd->oobavail = chip->ecc.layout->oobavail;
380 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
383 status = chip->ecc.write_page_raw(mtd, chip, buf,
386 status = chip->ecc.write_page(mtd, chip, buf,
395 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
396 status = chip->waitfunc(mtd, chip);
399 * See if operation failed and additional status checks are
402 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
403 status = chip->errstat(mtd, chip, FL_WRITING, status, page);
405 if (status & NAND_STATUS_FAIL) {
411 /* restore ECC layout */
412 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
413 chip->ecc.layout = saved_ecc_layout;
414 mtd->oobavail = saved_ecc_layout->oobavail;
421 * nand_davinci_read_page_hwecc - hardware ECC based page read function
422 * @mtd: mtd info structure
423 * @chip: nand chip info structure
424 * @buf: buffer to store read data
425 * @oob_required: caller requires OOB data read to chip->oob_poi
426 * @page: page number to read
428 * Not for syndrome calculating ECC controllers which need a special oob layout.
430 static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
431 uint8_t *buf, int oob_required, int page)
433 int i, eccsize = chip->ecc.size;
434 int eccbytes = chip->ecc.bytes;
435 int eccsteps = chip->ecc.steps;
438 uint8_t *ecc_code = chip->buffers->ecccode;
439 uint8_t *ecc_calc = chip->buffers->ecccalc;
440 struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout;
442 /* save current ECC layout and assign Keystone RBL ECC layout */
443 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
444 chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
445 mtd->oobavail = chip->ecc.layout->oobavail;
448 eccpos = chip->ecc.layout->eccpos;
450 /* Read the OOB area first */
451 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
452 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
453 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
455 for (i = 0; i < chip->ecc.total; i++)
456 ecc_code[i] = chip->oob_poi[eccpos[i]];
458 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
461 chip->ecc.hwctl(mtd, NAND_ECC_READ);
462 chip->read_buf(mtd, p, eccsize);
463 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
465 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
467 mtd->ecc_stats.failed++;
469 mtd->ecc_stats.corrected += stat;
472 /* restore ECC layout */
473 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
474 chip->ecc.layout = saved_ecc_layout;
475 mtd->oobavail = saved_ecc_layout->oobavail;
480 #endif /* CONFIG_KEYSTONE_RBL_NAND */
482 static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
490 * Start a new ECC calculation for reading or writing 512 bytes
493 val = __raw_readl(&davinci_emif_regs->nandfcr);
494 val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
495 val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
496 val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
497 val |= DAVINCI_NANDFCR_4BIT_ECC_START;
498 __raw_writel(val, &davinci_emif_regs->nandfcr);
500 case NAND_ECC_READSYN:
501 val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
508 static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
512 for (i = 0; i < 4; i++) {
513 ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
520 static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
524 unsigned int hw_4ecc[4];
527 nand_davinci_4bit_readecc(mtd, hw_4ecc);
529 /*Convert 10 bit ecc value to 8 bit */
530 for (i = 0; i < 2; i++) {
531 unsigned int hw_ecc_low = hw_4ecc[i * 2];
532 unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];
534 /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
535 *ecc_code++ = hw_ecc_low & 0xFF;
538 * Take 2 bits as LSB bits from val1 (count1=0) or val5
539 * (count1=1) and 6 bits from val2 (count1=0) or
543 ((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC);
546 * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
547 * 4 bits from val3 (count1=0) or val6 (count1=1)
550 ((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0);
553 * Take 6 bits from val3(count1=0) or val6 (count1=1) and
554 * 2 bits from val4 (count1=0) or val7 (count1=1)
557 ((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0);
559 /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
560 *ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
566 static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
567 uint8_t *read_ecc, uint8_t *calc_ecc)
570 unsigned int hw_4ecc[4];
571 unsigned int iserror;
572 unsigned short *ecc16;
573 unsigned int numerrors, erroraddress, errorvalue;
577 * Check for an ECC where all bytes are 0xFF. If this is the case, we
578 * will assume we are looking at an erased page and we should ignore
581 for (i = 0; i < 10; i++) {
582 if (read_ecc[i] != 0xFF)
588 /* Convert 8 bit in to 10 bit */
589 ecc16 = (unsigned short *)&read_ecc[0];
592 * Write the parity values in the NAND Flash 4-bit ECC Load register.
593 * Write each parity value one at a time starting from 4bit_ecc_val8
597 /*Take 2 bits from 8th byte and 8 bits from 9th byte */
598 __raw_writel(((ecc16[4]) >> 6) & 0x3FF,
599 &davinci_emif_regs->nand4biteccload);
601 /* Take 4 bits from 7th byte and 6 bits from 8th byte */
602 __raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
603 &davinci_emif_regs->nand4biteccload);
605 /* Take 6 bits from 6th byte and 4 bits from 7th byte */
606 __raw_writel((ecc16[3] >> 2) & 0x3FF,
607 &davinci_emif_regs->nand4biteccload);
609 /* Take 8 bits from 5th byte and 2 bits from 6th byte */
610 __raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
611 &davinci_emif_regs->nand4biteccload);
613 /*Take 2 bits from 3rd byte and 8 bits from 4th byte */
614 __raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
615 &davinci_emif_regs->nand4biteccload);
617 /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
618 __raw_writel(((ecc16[1]) >> 4) & 0x3FF,
619 &davinci_emif_regs->nand4biteccload);
621 /* Take 6 bits from 1st byte and 4 bits from 2nd byte */
622 __raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
623 &davinci_emif_regs->nand4biteccload);
625 /* Take 10 bits from 0th and 1st bytes */
626 __raw_writel((ecc16[0]) & 0x3FF,
627 &davinci_emif_regs->nand4biteccload);
630 * Perform a dummy read to the EMIF Revision Code and Status register.
631 * This is required to ensure time for syndrome calculation after
632 * writing the ECC values in previous step.
635 val = __raw_readl(&davinci_emif_regs->nandfsr);
638 * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
639 * A syndrome value of 0 means no bit errors. If the syndrome is
640 * non-zero then go further otherwise return.
642 nand_davinci_4bit_readecc(mtd, hw_4ecc);
644 if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3]))
648 * Clear any previous address calculation by doing a dummy read of an
649 * error address register.
651 val = __raw_readl(&davinci_emif_regs->nanderradd1);
654 * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
657 __raw_writel(DAVINCI_NANDFCR_4BIT_CALC_START,
658 &davinci_emif_regs->nandfcr);
661 * Wait for the corr_state field (bits 8 to 11) in the
662 * NAND Flash Status register to be not equal to 0x0, 0x1, 0x2, or 0x3.
663 * Otherwise ECC calculation has not even begun and the next loop might
664 * fail because of a false positive!
668 val = __raw_readl(&davinci_emif_regs->nandfsr);
671 } while ((i > 0) && !val);
674 * Wait for the corr_state field (bits 8 to 11) in the
675 * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
679 val = __raw_readl(&davinci_emif_regs->nandfsr);
682 } while ((i > 0) && val);
684 iserror = __raw_readl(&davinci_emif_regs->nandfsr);
685 iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
686 iserror = iserror >> 8;
689 * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
690 * corrected (five or more errors). The number of errors
691 * calculated (err_num field) differs from the number of errors
692 * searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error
693 * correction complete (errors on bit 8 or 9).
694 * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
695 * complete (error exists).
698 if (iserror == ECC_STATE_NO_ERR) {
699 val = __raw_readl(&davinci_emif_regs->nanderrval1);
701 } else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
702 val = __raw_readl(&davinci_emif_regs->nanderrval1);
706 numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
709 /* Read the error address, error value and correct */
710 for (i = 0; i < numerrors; i++) {
713 ((__raw_readl(&davinci_emif_regs->nanderradd2) >>
714 (16 * (i & 1))) & 0x3FF);
715 erroraddress = ((512 + 7) - erroraddress);
717 ((__raw_readl(&davinci_emif_regs->nanderrval2) >>
718 (16 * (i & 1))) & 0xFF);
721 ((__raw_readl(&davinci_emif_regs->nanderradd1) >>
722 (16 * (i & 1))) & 0x3FF);
723 erroraddress = ((512 + 7) - erroraddress);
725 ((__raw_readl(&davinci_emif_regs->nanderrval1) >>
726 (16 * (i & 1))) & 0xFF);
728 /* xor the corrupt data with error value */
729 if (erroraddress < 512)
730 dat[erroraddress] ^= errorvalue;
735 #endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
737 static int nand_davinci_dev_ready(struct mtd_info *mtd)
739 return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
742 static void nand_flash_init(void)
744 /* This is for DM6446 EVM and *very* similar. DO NOT GROW THIS!
745 * Instead, have your board_init() set EMIF timings, based on its
746 * knowledge of the clocks and what devices are hooked up ... and
747 * don't even do that unless no UBL handled it.
749 #ifdef CONFIG_SOC_DM644X
750 u_int32_t acfg1 = 0x3ffffffc;
752 /*------------------------------------------------------------------*
753 * NAND FLASH CHIP TIMEOUT @ 459 MHz *
755 * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
756 * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
758 *------------------------------------------------------------------*/
760 | (0 << 31) /* selectStrobe */
761 | (0 << 30) /* extWait */
762 | (1 << 26) /* writeSetup 10 ns */
763 | (3 << 20) /* writeStrobe 40 ns */
764 | (1 << 17) /* writeHold 10 ns */
765 | (1 << 13) /* readSetup 10 ns */
766 | (5 << 7) /* readStrobe 60 ns */
767 | (1 << 4) /* readHold 10 ns */
768 | (3 << 2) /* turnAround ?? ns */
769 | (0 << 0) /* asyncSize 8-bit bus */
772 __raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */
774 /* NAND flash on CS2 */
775 __raw_writel(0x00000101, &davinci_emif_regs->nandfcr);
779 void davinci_nand_init(struct nand_chip *nand)
781 #if defined CONFIG_KEYSTONE_RBL_NAND
783 struct nand_ecclayout *layout;
785 layout = &nand_keystone_rbl_4bit_layout_oobfirst;
786 layout->oobavail = 0;
787 for (i = 0; layout->oobfree[i].length &&
788 i < ARRAY_SIZE(layout->oobfree); i++)
789 layout->oobavail += layout->oobfree[i].length;
791 nand->write_page = nand_davinci_write_page;
792 nand->ecc.read_page = nand_davinci_read_page_hwecc;
794 nand->chip_delay = 0;
795 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
796 nand->bbt_options |= NAND_BBT_USE_FLASH;
798 #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
799 nand->options |= NAND_NO_SUBPAGE_WRITE;
801 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
802 nand->options |= NAND_BUSWIDTH_16;
804 #ifdef CONFIG_SYS_NAND_HW_ECC
805 nand->ecc.mode = NAND_ECC_HW;
806 nand->ecc.size = 512;
808 nand->ecc.strength = 1;
809 nand->ecc.calculate = nand_davinci_calculate_ecc;
810 nand->ecc.correct = nand_davinci_correct_data;
811 nand->ecc.hwctl = nand_davinci_enable_hwecc;
813 nand->ecc.mode = NAND_ECC_SOFT;
814 #endif /* CONFIG_SYS_NAND_HW_ECC */
815 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
816 nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
817 nand->ecc.size = 512;
818 nand->ecc.bytes = 10;
819 nand->ecc.strength = 4;
820 nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
821 nand->ecc.correct = nand_davinci_4bit_correct_data;
822 nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
823 nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
825 /* Set address of hardware control function */
826 nand->cmd_ctrl = nand_davinci_hwcontrol;
828 nand->read_buf = nand_davinci_read_buf;
829 nand->write_buf = nand_davinci_write_buf;
831 nand->dev_ready = nand_davinci_dev_ready;
836 int board_nand_init(struct nand_chip *chip) __attribute__((weak));
838 int board_nand_init(struct nand_chip *chip)
840 davinci_nand_init(chip);