2 * NAND driver for TI DaVinci based boards.
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
11 * linux/drivers/mtd/nand/nand_davinci.c
15 * Copyright (C) 2006 Texas Instruments.
17 * ----------------------------------------------------------------------------
19 * SPDX-License-Identifier: GPL-2.0+
21 * ----------------------------------------------------------------------------
24 * This is a device driver for the NAND flash device found on the
25 * DaVinci board which utilizes the Samsung k9k2g08 part.
28 ver. 1.0: Feb 2005, Vinod/Sudhakar
35 #include <asm/ti-common/davinci_nand.h>
37 /* Definitions for 4-bit hardware ECC */
38 #define NAND_TIMEOUT 10240
39 #define NAND_ECC_BUSY 0xC
40 #define NAND_4BITECC_MASK 0x03FF03FF
41 #define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
42 #define ECC_STATE_NO_ERR 0x0
43 #define ECC_STATE_TOO_MANY_ERRS 0x1
44 #define ECC_STATE_ERR_CORR_COMP_P 0x2
45 #define ECC_STATE_ERR_CORR_COMP_N 0x3
48 * Exploit the little endianness of the ARM to do multi-byte transfers
49 * per device read. This can perform over twice as quickly as individual
50 * byte transfers when buffer alignment is conducive.
52 * NOTE: This only works if the NAND is not connected to the 2 LSBs of
53 * the address bus. On Davinci EVM platforms this has always been true.
55 static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
57 struct nand_chip *chip = mtd_to_nand(mtd);
58 const u32 *nand = chip->IO_ADDR_R;
60 /* Make sure that buf is 32 bit aligned */
61 if (((int)buf & 0x3) != 0) {
62 if (((int)buf & 0x1) != 0) {
70 if (((int)buf & 0x3) != 0) {
72 *(u16 *)buf = readw(nand);
79 /* copy aligned data */
81 *(u32 *)buf = __raw_readl(nand);
86 /* mop up any remaining bytes */
89 *(u16 *)buf = readw(nand);
99 static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
102 struct nand_chip *chip = mtd_to_nand(mtd);
103 const u32 *nand = chip->IO_ADDR_W;
105 /* Make sure that buf is 32 bit aligned */
106 if (((int)buf & 0x3) != 0) {
107 if (((int)buf & 0x1) != 0) {
115 if (((int)buf & 0x3) != 0) {
117 writew(*(u16 *)buf, nand);
124 /* copy aligned data */
126 __raw_writel(*(u32 *)buf, nand);
131 /* mop up any remaining bytes */
134 writew(*(u16 *)buf, nand);
144 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
147 struct nand_chip *this = mtd_to_nand(mtd);
148 u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
150 if (ctrl & NAND_CTRL_CHANGE) {
151 IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
154 IO_ADDR_W |= MASK_CLE;
156 IO_ADDR_W |= MASK_ALE;
157 this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
160 if (cmd != NAND_CMD_NONE)
161 writeb(cmd, IO_ADDR_W);
164 #ifdef CONFIG_SYS_NAND_HW_ECC
166 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
170 ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
171 CONFIG_SYS_NAND_CS - 2]));
176 static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
180 /* reading the ECC result register resets the ECC calculation */
181 nand_davinci_readecc(mtd);
183 val = __raw_readl(&davinci_emif_regs->nandfcr);
184 val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
185 val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
186 __raw_writel(val, &davinci_emif_regs->nandfcr);
189 static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
194 tmp = nand_davinci_readecc(mtd);
196 /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
197 * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
198 tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
200 /* Invert so that erased block ECC is correct */
204 *ecc_code++ = tmp >> 8;
205 *ecc_code++ = tmp >> 16;
207 /* NOTE: the above code matches mainline Linux:
208 * .PQR.stu ==> ~PQRstu
210 * MontaVista/TI kernels encode those bytes differently, use
211 * complicated (and allegedly sometimes-wrong) correction code,
212 * and usually shipped with U-Boot that uses software ECC:
213 * .PQR.stu ==> PsQRtu
215 * If you need MV/TI compatible NAND I/O in U-Boot, it should
216 * be possible to (a) change the mangling above, (b) reverse
217 * that mangling in nand_davinci_correct_data() below.
223 static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
224 u_char *read_ecc, u_char *calc_ecc)
226 struct nand_chip *this = mtd_to_nand(mtd);
227 u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
229 u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
231 u_int32_t diff = ecc_calc ^ ecc_nand;
234 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
235 /* Correctable error */
236 if ((diff >> (12 + 3)) < this->ecc.size) {
237 uint8_t find_bit = 1 << ((diff >> 12) & 7);
238 uint32_t find_byte = diff >> (12 + 3);
240 dat[find_byte] ^= find_bit;
241 pr_debug("Correcting single "
242 "bit ECC error at offset: %d, bit: "
243 "%d\n", find_byte, find_bit);
248 } else if (!(diff & (diff - 1))) {
249 /* Single bit ECC error in the ECC itself,
251 pr_debug("Single bit ECC error in " "ECC.\n");
254 /* Uncorrectable error */
255 pr_debug("ECC UNCORRECTED_ERROR 1\n");
261 #endif /* CONFIG_SYS_NAND_HW_ECC */
263 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
264 static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
265 #if defined(CONFIG_SYS_NAND_PAGE_2K)
267 #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
269 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
270 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
271 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
272 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
275 {2, 4}, {16, 6}, {32, 6}, {48, 6},
280 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
281 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
282 49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
286 {.offset = 2, .length = 22, },
288 #endif /* #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC */
289 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
292 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
293 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
294 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
295 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
296 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
297 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
298 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
299 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
302 {.offset = 2, .length = 46, },
307 #if defined CONFIG_KEYSTONE_RBL_NAND
308 static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = {
309 #if defined(CONFIG_SYS_NAND_PAGE_2K)
312 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
313 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
314 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
315 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
318 {.offset = 2, .length = 4, },
319 {.offset = 16, .length = 6, },
320 {.offset = 32, .length = 6, },
321 {.offset = 48, .length = 6, },
323 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
326 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
327 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
328 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
329 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
330 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
331 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
332 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,
333 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
336 {.offset = 2, .length = 4, },
337 {.offset = 16, .length = 6, },
338 {.offset = 32, .length = 6, },
339 {.offset = 48, .length = 6, },
340 {.offset = 64, .length = 6, },
341 {.offset = 80, .length = 6, },
342 {.offset = 96, .length = 6, },
343 {.offset = 112, .length = 6, },
348 #ifdef CONFIG_SYS_NAND_PAGE_2K
349 #define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 11
350 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
351 #define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 12
355 * nand_davinci_write_page - write one page
356 * @mtd: MTD device structure
357 * @chip: NAND chip descriptor
358 * @buf: the data to write
359 * @oob_required: must write chip->oob_poi to OOB
360 * @page: page number to write
361 * @raw: use _raw version of write_page
363 static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
364 uint32_t offset, int data_len,
365 const uint8_t *buf, int oob_required,
370 struct nand_ecclayout *saved_ecc_layout;
372 /* save current ECC layout and assign Keystone RBL ECC layout */
373 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
374 saved_ecc_layout = chip->ecc.layout;
375 chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
376 mtd->oobavail = chip->ecc.layout->oobavail;
379 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
382 status = chip->ecc.write_page_raw(mtd, chip, buf,
385 status = chip->ecc.write_page(mtd, chip, buf,
394 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
395 status = chip->waitfunc(mtd, chip);
398 * See if operation failed and additional status checks are
401 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
402 status = chip->errstat(mtd, chip, FL_WRITING, status, page);
404 if (status & NAND_STATUS_FAIL) {
410 /* restore ECC layout */
411 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
412 chip->ecc.layout = saved_ecc_layout;
413 mtd->oobavail = saved_ecc_layout->oobavail;
420 * nand_davinci_read_page_hwecc - hardware ECC based page read function
421 * @mtd: mtd info structure
422 * @chip: nand chip info structure
423 * @buf: buffer to store read data
424 * @oob_required: caller requires OOB data read to chip->oob_poi
425 * @page: page number to read
427 * Not for syndrome calculating ECC controllers which need a special oob layout.
429 static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
430 uint8_t *buf, int oob_required, int page)
432 int i, eccsize = chip->ecc.size;
433 int eccbytes = chip->ecc.bytes;
434 int eccsteps = chip->ecc.steps;
437 uint8_t *ecc_code = chip->buffers->ecccode;
438 uint8_t *ecc_calc = chip->buffers->ecccalc;
439 struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout;
441 /* save current ECC layout and assign Keystone RBL ECC layout */
442 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
443 chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
444 mtd->oobavail = chip->ecc.layout->oobavail;
447 eccpos = chip->ecc.layout->eccpos;
449 /* Read the OOB area first */
450 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
451 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
452 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
454 for (i = 0; i < chip->ecc.total; i++)
455 ecc_code[i] = chip->oob_poi[eccpos[i]];
457 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
460 chip->ecc.hwctl(mtd, NAND_ECC_READ);
461 chip->read_buf(mtd, p, eccsize);
462 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
464 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
466 mtd->ecc_stats.failed++;
468 mtd->ecc_stats.corrected += stat;
471 /* restore ECC layout */
472 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
473 chip->ecc.layout = saved_ecc_layout;
474 mtd->oobavail = saved_ecc_layout->oobavail;
479 #endif /* CONFIG_KEYSTONE_RBL_NAND */
481 static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
489 * Start a new ECC calculation for reading or writing 512 bytes
492 val = __raw_readl(&davinci_emif_regs->nandfcr);
493 val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
494 val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
495 val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
496 val |= DAVINCI_NANDFCR_4BIT_ECC_START;
497 __raw_writel(val, &davinci_emif_regs->nandfcr);
499 case NAND_ECC_READSYN:
500 val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
507 static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
511 for (i = 0; i < 4; i++) {
512 ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
519 static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
523 unsigned int hw_4ecc[4];
526 nand_davinci_4bit_readecc(mtd, hw_4ecc);
528 /*Convert 10 bit ecc value to 8 bit */
529 for (i = 0; i < 2; i++) {
530 unsigned int hw_ecc_low = hw_4ecc[i * 2];
531 unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];
533 /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
534 *ecc_code++ = hw_ecc_low & 0xFF;
537 * Take 2 bits as LSB bits from val1 (count1=0) or val5
538 * (count1=1) and 6 bits from val2 (count1=0) or
542 ((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC);
545 * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
546 * 4 bits from val3 (count1=0) or val6 (count1=1)
549 ((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0);
552 * Take 6 bits from val3(count1=0) or val6 (count1=1) and
553 * 2 bits from val4 (count1=0) or val7 (count1=1)
556 ((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0);
558 /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
559 *ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
565 static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
566 uint8_t *read_ecc, uint8_t *calc_ecc)
569 unsigned int hw_4ecc[4];
570 unsigned int iserror;
571 unsigned short *ecc16;
572 unsigned int numerrors, erroraddress, errorvalue;
576 * Check for an ECC where all bytes are 0xFF. If this is the case, we
577 * will assume we are looking at an erased page and we should ignore
580 for (i = 0; i < 10; i++) {
581 if (read_ecc[i] != 0xFF)
587 /* Convert 8 bit in to 10 bit */
588 ecc16 = (unsigned short *)&read_ecc[0];
591 * Write the parity values in the NAND Flash 4-bit ECC Load register.
592 * Write each parity value one at a time starting from 4bit_ecc_val8
596 /*Take 2 bits from 8th byte and 8 bits from 9th byte */
597 __raw_writel(((ecc16[4]) >> 6) & 0x3FF,
598 &davinci_emif_regs->nand4biteccload);
600 /* Take 4 bits from 7th byte and 6 bits from 8th byte */
601 __raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
602 &davinci_emif_regs->nand4biteccload);
604 /* Take 6 bits from 6th byte and 4 bits from 7th byte */
605 __raw_writel((ecc16[3] >> 2) & 0x3FF,
606 &davinci_emif_regs->nand4biteccload);
608 /* Take 8 bits from 5th byte and 2 bits from 6th byte */
609 __raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
610 &davinci_emif_regs->nand4biteccload);
612 /*Take 2 bits from 3rd byte and 8 bits from 4th byte */
613 __raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
614 &davinci_emif_regs->nand4biteccload);
616 /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
617 __raw_writel(((ecc16[1]) >> 4) & 0x3FF,
618 &davinci_emif_regs->nand4biteccload);
620 /* Take 6 bits from 1st byte and 4 bits from 2nd byte */
621 __raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
622 &davinci_emif_regs->nand4biteccload);
624 /* Take 10 bits from 0th and 1st bytes */
625 __raw_writel((ecc16[0]) & 0x3FF,
626 &davinci_emif_regs->nand4biteccload);
629 * Perform a dummy read to the EMIF Revision Code and Status register.
630 * This is required to ensure time for syndrome calculation after
631 * writing the ECC values in previous step.
634 val = __raw_readl(&davinci_emif_regs->nandfsr);
637 * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
638 * A syndrome value of 0 means no bit errors. If the syndrome is
639 * non-zero then go further otherwise return.
641 nand_davinci_4bit_readecc(mtd, hw_4ecc);
643 if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3]))
647 * Clear any previous address calculation by doing a dummy read of an
648 * error address register.
650 val = __raw_readl(&davinci_emif_regs->nanderradd1);
653 * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
656 __raw_writel(DAVINCI_NANDFCR_4BIT_CALC_START,
657 &davinci_emif_regs->nandfcr);
660 * Wait for the corr_state field (bits 8 to 11) in the
661 * NAND Flash Status register to be not equal to 0x0, 0x1, 0x2, or 0x3.
662 * Otherwise ECC calculation has not even begun and the next loop might
663 * fail because of a false positive!
667 val = __raw_readl(&davinci_emif_regs->nandfsr);
670 } while ((i > 0) && !val);
673 * Wait for the corr_state field (bits 8 to 11) in the
674 * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
678 val = __raw_readl(&davinci_emif_regs->nandfsr);
681 } while ((i > 0) && val);
683 iserror = __raw_readl(&davinci_emif_regs->nandfsr);
684 iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
685 iserror = iserror >> 8;
688 * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
689 * corrected (five or more errors). The number of errors
690 * calculated (err_num field) differs from the number of errors
691 * searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error
692 * correction complete (errors on bit 8 or 9).
693 * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
694 * complete (error exists).
697 if (iserror == ECC_STATE_NO_ERR) {
698 val = __raw_readl(&davinci_emif_regs->nanderrval1);
700 } else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
701 val = __raw_readl(&davinci_emif_regs->nanderrval1);
705 numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
708 /* Read the error address, error value and correct */
709 for (i = 0; i < numerrors; i++) {
712 ((__raw_readl(&davinci_emif_regs->nanderradd2) >>
713 (16 * (i & 1))) & 0x3FF);
714 erroraddress = ((512 + 7) - erroraddress);
716 ((__raw_readl(&davinci_emif_regs->nanderrval2) >>
717 (16 * (i & 1))) & 0xFF);
720 ((__raw_readl(&davinci_emif_regs->nanderradd1) >>
721 (16 * (i & 1))) & 0x3FF);
722 erroraddress = ((512 + 7) - erroraddress);
724 ((__raw_readl(&davinci_emif_regs->nanderrval1) >>
725 (16 * (i & 1))) & 0xFF);
727 /* xor the corrupt data with error value */
728 if (erroraddress < 512)
729 dat[erroraddress] ^= errorvalue;
734 #endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
736 static int nand_davinci_dev_ready(struct mtd_info *mtd)
738 return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
741 static void nand_flash_init(void)
743 /* This is for DM6446 EVM and *very* similar. DO NOT GROW THIS!
744 * Instead, have your board_init() set EMIF timings, based on its
745 * knowledge of the clocks and what devices are hooked up ... and
746 * don't even do that unless no UBL handled it.
748 #ifdef CONFIG_SOC_DM644X
749 u_int32_t acfg1 = 0x3ffffffc;
751 /*------------------------------------------------------------------*
752 * NAND FLASH CHIP TIMEOUT @ 459 MHz *
754 * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
755 * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
757 *------------------------------------------------------------------*/
759 | (0 << 31) /* selectStrobe */
760 | (0 << 30) /* extWait */
761 | (1 << 26) /* writeSetup 10 ns */
762 | (3 << 20) /* writeStrobe 40 ns */
763 | (1 << 17) /* writeHold 10 ns */
764 | (1 << 13) /* readSetup 10 ns */
765 | (5 << 7) /* readStrobe 60 ns */
766 | (1 << 4) /* readHold 10 ns */
767 | (3 << 2) /* turnAround ?? ns */
768 | (0 << 0) /* asyncSize 8-bit bus */
771 __raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */
773 /* NAND flash on CS2 */
774 __raw_writel(0x00000101, &davinci_emif_regs->nandfcr);
778 void davinci_nand_init(struct nand_chip *nand)
780 #if defined CONFIG_KEYSTONE_RBL_NAND
782 struct nand_ecclayout *layout;
784 layout = &nand_keystone_rbl_4bit_layout_oobfirst;
785 layout->oobavail = 0;
786 for (i = 0; layout->oobfree[i].length &&
787 i < ARRAY_SIZE(layout->oobfree); i++)
788 layout->oobavail += layout->oobfree[i].length;
790 nand->write_page = nand_davinci_write_page;
791 nand->ecc.read_page = nand_davinci_read_page_hwecc;
793 nand->chip_delay = 0;
794 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
795 nand->bbt_options |= NAND_BBT_USE_FLASH;
797 #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
798 nand->options |= NAND_NO_SUBPAGE_WRITE;
800 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
801 nand->options |= NAND_BUSWIDTH_16;
803 #ifdef CONFIG_SYS_NAND_HW_ECC
804 nand->ecc.mode = NAND_ECC_HW;
805 nand->ecc.size = 512;
807 nand->ecc.strength = 1;
808 nand->ecc.calculate = nand_davinci_calculate_ecc;
809 nand->ecc.correct = nand_davinci_correct_data;
810 nand->ecc.hwctl = nand_davinci_enable_hwecc;
812 nand->ecc.mode = NAND_ECC_SOFT;
813 #endif /* CONFIG_SYS_NAND_HW_ECC */
814 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
815 nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
816 nand->ecc.size = 512;
817 nand->ecc.bytes = 10;
818 nand->ecc.strength = 4;
819 nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
820 nand->ecc.correct = nand_davinci_4bit_correct_data;
821 nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
822 nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
824 /* Set address of hardware control function */
825 nand->cmd_ctrl = nand_davinci_hwcontrol;
827 nand->read_buf = nand_davinci_read_buf;
828 nand->write_buf = nand_davinci_write_buf;
830 nand->dev_ready = nand_davinci_dev_ready;
835 int board_nand_init(struct nand_chip *chip) __attribute__((weak));
837 int board_nand_init(struct nand_chip *chip)
839 davinci_nand_init(chip);