2 * Copyright (C) 2014 Panasonic Corporation
3 * Copyright (C) 2013-2014, Altera Corporation <www.altera.com>
4 * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/errno.h>
17 #define NAND_DEFAULT_TIMINGS -1
19 static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
22 * We define a macro here that combines all interrupts this driver uses into
23 * a single constant value, for convenience.
25 #define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
26 INTR_STATUS__ECC_TRANSACTION_DONE | \
27 INTR_STATUS__ECC_ERR | \
28 INTR_STATUS__PROGRAM_FAIL | \
29 INTR_STATUS__LOAD_COMP | \
30 INTR_STATUS__PROGRAM_COMP | \
31 INTR_STATUS__TIME_OUT | \
32 INTR_STATUS__ERASE_FAIL | \
33 INTR_STATUS__RST_COMP | \
34 INTR_STATUS__ERASE_COMP | \
35 INTR_STATUS__ECC_UNCOR_ERR | \
36 INTR_STATUS__INT_ACT | \
37 INTR_STATUS__LOCKED_BLK)
40 * indicates whether or not the internal value for the flash bank is
43 #define CHIP_SELECT_INVALID -1
45 #define SUPPORT_8BITECC 1
48 * this macro allows us to convert from an MTD structure to our own
49 * device context (denali) structure.
51 static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
53 return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
57 * These constants are defined by the driver to enable common driver
58 * configuration options.
60 #define SPARE_ACCESS 0x41
61 #define MAIN_ACCESS 0x42
62 #define MAIN_SPARE_ACCESS 0x43
63 #define PIPELINE_ACCESS 0x2000
65 #define DENALI_UNLOCK_START 0x10
66 #define DENALI_UNLOCK_END 0x11
67 #define DENALI_LOCK 0x21
68 #define DENALI_LOCK_TIGHT 0x31
69 #define DENALI_BUFFER_LOAD 0x60
70 #define DENALI_BUFFER_WRITE 0x62
73 #define DENALI_WRITE 0x100
75 /* types of device accesses. We can issue commands and get status */
76 #define COMMAND_CYCLE 0
78 #define STATUS_CYCLE 2
81 * this is a helper macro that allows us to
82 * format the bank into the proper bits for the controller
84 #define BANK(x) ((x) << 24)
86 /* Interrupts are cleared by writing a 1 to the appropriate status bit */
87 static inline void clear_interrupt(struct denali_nand_info *denali,
90 uint32_t intr_status_reg;
92 intr_status_reg = INTR_STATUS(denali->flash_bank);
94 writel(irq_mask, denali->flash_reg + intr_status_reg);
97 static uint32_t read_interrupt_status(struct denali_nand_info *denali)
99 uint32_t intr_status_reg;
101 intr_status_reg = INTR_STATUS(denali->flash_bank);
103 return readl(denali->flash_reg + intr_status_reg);
106 static void clear_interrupts(struct denali_nand_info *denali)
110 status = read_interrupt_status(denali);
111 clear_interrupt(denali, status);
113 denali->irq_status = 0;
116 static void denali_irq_enable(struct denali_nand_info *denali,
121 for (i = 0; i < denali->max_banks; ++i)
122 writel(int_mask, denali->flash_reg + INTR_EN(i));
125 static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
127 unsigned long timeout = 1000000;
128 uint32_t intr_status;
131 intr_status = read_interrupt_status(denali) & DENALI_IRQ_ALL;
132 if (intr_status & irq_mask) {
133 denali->irq_status &= ~irq_mask;
134 /* our interrupt was detected */
139 } while (timeout != 0);
143 printf("Denali timeout with interrupt status %08x\n",
144 read_interrupt_status(denali));
151 * Certain operations for the denali NAND controller use an indexed mode to
152 * read/write data. The operation is performed by writing the address value
153 * of the command to the device memory followed by the data. This function
154 * abstracts this common operation.
156 static void index_addr(struct denali_nand_info *denali,
157 uint32_t address, uint32_t data)
159 writel(address, denali->flash_mem + INDEX_CTRL_REG);
160 writel(data, denali->flash_mem + INDEX_DATA_REG);
163 /* Perform an indexed read of the device */
164 static void index_addr_read_data(struct denali_nand_info *denali,
165 uint32_t address, uint32_t *pdata)
167 writel(address, denali->flash_mem + INDEX_CTRL_REG);
168 *pdata = readl(denali->flash_mem + INDEX_DATA_REG);
172 * We need to buffer some data for some of the NAND core routines.
173 * The operations manage buffering that data.
175 static void reset_buf(struct denali_nand_info *denali)
177 denali->buf.head = 0;
178 denali->buf.tail = 0;
181 static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
183 denali->buf.buf[denali->buf.tail++] = byte;
186 /* resets a specific device connected to the core */
187 static void reset_bank(struct denali_nand_info *denali)
190 uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT;
192 clear_interrupts(denali);
194 writel(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
196 irq_status = wait_for_irq(denali, irq_mask);
197 if (irq_status & INTR_STATUS__TIME_OUT)
198 debug("reset bank failed.\n");
201 /* Reset the flash controller */
202 static uint32_t denali_nand_reset(struct denali_nand_info *denali)
206 for (i = 0; i < denali->max_banks; i++)
207 writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
208 denali->flash_reg + INTR_STATUS(i));
210 for (i = 0; i < denali->max_banks; i++) {
211 writel(1 << i, denali->flash_reg + DEVICE_RESET);
212 while (!(readl(denali->flash_reg + INTR_STATUS(i)) &
213 (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))
214 if (readl(denali->flash_reg + INTR_STATUS(i)) &
215 INTR_STATUS__TIME_OUT)
216 debug("NAND Reset operation timed out on bank"
220 for (i = 0; i < denali->max_banks; i++)
221 writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
222 denali->flash_reg + INTR_STATUS(i));
228 * this routine calculates the ONFI timing values for a given mode and
229 * programs the clocking register accordingly. The mode is determined by
230 * the get_onfi_nand_para routine.
232 static void nand_onfi_timing_set(struct denali_nand_info *denali,
235 uint32_t trea[6] = {40, 30, 25, 20, 20, 16};
236 uint32_t trp[6] = {50, 25, 17, 15, 12, 10};
237 uint32_t treh[6] = {30, 15, 15, 10, 10, 7};
238 uint32_t trc[6] = {100, 50, 35, 30, 25, 20};
239 uint32_t trhoh[6] = {0, 15, 15, 15, 15, 15};
240 uint32_t trloh[6] = {0, 0, 0, 0, 5, 5};
241 uint32_t tcea[6] = {100, 45, 30, 25, 25, 25};
242 uint32_t tadl[6] = {200, 100, 100, 100, 70, 70};
243 uint32_t trhw[6] = {200, 100, 100, 100, 100, 100};
244 uint32_t trhz[6] = {200, 100, 100, 100, 100, 100};
245 uint32_t twhr[6] = {120, 80, 80, 60, 60, 60};
246 uint32_t tcs[6] = {70, 35, 25, 25, 20, 15};
248 uint32_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
249 uint32_t dv_window = 0;
250 uint32_t en_lo, en_hi;
252 uint32_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
254 en_lo = DIV_ROUND_UP(trp[mode], CLK_X);
255 en_hi = DIV_ROUND_UP(treh[mode], CLK_X);
256 if ((en_hi * CLK_X) < (treh[mode] + 2))
259 if ((en_lo + en_hi) * CLK_X < trc[mode])
260 en_lo += DIV_ROUND_UP((trc[mode] - (en_lo + en_hi) * CLK_X),
263 if ((en_lo + en_hi) < CLK_MULTI)
264 en_lo += CLK_MULTI - en_lo - en_hi;
266 while (dv_window < 8) {
267 data_invalid_rhoh = en_lo * CLK_X + trhoh[mode];
269 data_invalid_rloh = (en_lo + en_hi) * CLK_X + trloh[mode];
271 data_invalid = data_invalid_rhoh < data_invalid_rloh ?
272 data_invalid_rhoh : data_invalid_rloh;
274 dv_window = data_invalid - trea[mode];
280 acc_clks = DIV_ROUND_UP(trea[mode], CLK_X);
282 while (acc_clks * CLK_X - trea[mode] < 3)
285 if (data_invalid - acc_clks * CLK_X < 2)
286 debug("%s, Line %d: Warning!\n", __FILE__, __LINE__);
288 addr_2_data = DIV_ROUND_UP(tadl[mode], CLK_X);
289 re_2_we = DIV_ROUND_UP(trhw[mode], CLK_X);
290 re_2_re = DIV_ROUND_UP(trhz[mode], CLK_X);
291 we_2_re = DIV_ROUND_UP(twhr[mode], CLK_X);
292 cs_cnt = DIV_ROUND_UP((tcs[mode] - trp[mode]), CLK_X);
297 while (cs_cnt * CLK_X + trea[mode] < tcea[mode])
301 /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
302 if (readl(denali->flash_reg + MANUFACTURER_ID) == 0 &&
303 readl(denali->flash_reg + DEVICE_ID) == 0x88)
306 writel(acc_clks, denali->flash_reg + ACC_CLKS);
307 writel(re_2_we, denali->flash_reg + RE_2_WE);
308 writel(re_2_re, denali->flash_reg + RE_2_RE);
309 writel(we_2_re, denali->flash_reg + WE_2_RE);
310 writel(addr_2_data, denali->flash_reg + ADDR_2_DATA);
311 writel(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
312 writel(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
313 writel(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
316 /* queries the NAND device to see what ONFI modes it supports. */
317 static uint32_t get_onfi_nand_para(struct denali_nand_info *denali)
322 * we needn't to do a reset here because driver has already
323 * reset all the banks before
325 if (!(readl(denali->flash_reg + ONFI_TIMING_MODE) &
326 ONFI_TIMING_MODE__VALUE))
329 for (i = 5; i > 0; i--) {
330 if (readl(denali->flash_reg + ONFI_TIMING_MODE) &
335 nand_onfi_timing_set(denali, i);
338 * By now, all the ONFI devices we know support the page cache
339 * rw feature. So here we enable the pipeline_rw_ahead feature
345 static void get_samsung_nand_para(struct denali_nand_info *denali,
348 if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
349 /* Set timing register values according to datasheet */
350 writel(5, denali->flash_reg + ACC_CLKS);
351 writel(20, denali->flash_reg + RE_2_WE);
352 writel(12, denali->flash_reg + WE_2_RE);
353 writel(14, denali->flash_reg + ADDR_2_DATA);
354 writel(3, denali->flash_reg + RDWR_EN_LO_CNT);
355 writel(2, denali->flash_reg + RDWR_EN_HI_CNT);
356 writel(2, denali->flash_reg + CS_SETUP_CNT);
360 static void get_toshiba_nand_para(struct denali_nand_info *denali)
365 * Workaround to fix a controller bug which reports a wrong
366 * spare area size for some kind of Toshiba NAND device
368 if ((readl(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
369 (readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
370 writel(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
371 tmp = readl(denali->flash_reg + DEVICES_CONNECTED) *
372 readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
373 writel(tmp, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
377 static void get_hynix_nand_para(struct denali_nand_info *denali,
380 uint32_t main_size, spare_size;
383 case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
384 case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
385 writel(128, denali->flash_reg + PAGES_PER_BLOCK);
386 writel(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
387 writel(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
389 readl(denali->flash_reg + DEVICES_CONNECTED);
391 readl(denali->flash_reg + DEVICES_CONNECTED);
392 writel(main_size, denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
393 writel(spare_size, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
394 writel(0, denali->flash_reg + DEVICE_WIDTH);
397 debug("Spectra: Unknown Hynix NAND (Device ID: 0x%x).\n"
398 "Will use default parameter values instead.\n",
404 * determines how many NAND chips are connected to the controller. Note for
405 * Intel CE4100 devices we don't support more than one device.
407 static void find_valid_banks(struct denali_nand_info *denali)
409 uint32_t id[denali->max_banks];
412 denali->total_used_banks = 1;
413 for (i = 0; i < denali->max_banks; i++) {
414 index_addr(denali, MODE_11 | (i << 24) | 0, 0x90);
415 index_addr(denali, MODE_11 | (i << 24) | 1, 0);
416 index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]);
419 if (!(id[i] & 0x0ff))
422 if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
423 denali->total_used_banks++;
431 * Use the configuration feature register to determine the maximum number of
432 * banks that the hardware supports.
434 static void detect_max_banks(struct denali_nand_info *denali)
436 uint32_t features = readl(denali->flash_reg + FEATURES);
438 * Read the revision register, so we can calculate the max_banks
439 * properly: the encoding changed from rev 5.0 to 5.1
441 u32 revision = MAKE_COMPARABLE_REVISION(
442 readl(denali->flash_reg + REVISION));
443 if (revision < REVISION_5_1)
444 denali->max_banks = 2 << (features & FEATURES__N_BANKS);
446 denali->max_banks = 1 << (features & FEATURES__N_BANKS);
449 static void detect_partition_feature(struct denali_nand_info *denali)
452 * For MRST platform, denali->fwblks represent the
453 * number of blocks firmware is taken,
454 * FW is in protect partition and MTD driver has no
455 * permission to access it. So let driver know how many
456 * blocks it can't touch.
458 if (readl(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
459 if ((readl(denali->flash_reg + PERM_SRC_ID(1)) &
460 PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) {
462 ((readl(denali->flash_reg + MIN_MAX_BANK(1)) &
463 MIN_MAX_BANK__MIN_VALUE) *
466 (readl(denali->flash_reg + MIN_BLK_ADDR(1)) &
467 MIN_BLK_ADDR__VALUE);
469 denali->fwblks = SPECTRA_START_BLOCK;
472 denali->fwblks = SPECTRA_START_BLOCK;
476 static uint32_t denali_nand_timing_set(struct denali_nand_info *denali)
478 uint32_t id_bytes[8], addr;
479 uint8_t maf_id, device_id;
483 * Use read id method to get device ID and other params.
484 * For some NAND chips, controller can't report the correct
485 * device ID by reading from DEVICE_ID register
487 addr = MODE_11 | BANK(denali->flash_bank);
488 index_addr(denali, addr | 0, 0x90);
489 index_addr(denali, addr | 1, 0);
490 for (i = 0; i < 8; i++)
491 index_addr_read_data(denali, addr | 2, &id_bytes[i]);
492 maf_id = id_bytes[0];
493 device_id = id_bytes[1];
495 if (readl(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
496 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
497 if (get_onfi_nand_para(denali))
499 } else if (maf_id == 0xEC) { /* Samsung NAND */
500 get_samsung_nand_para(denali, device_id);
501 } else if (maf_id == 0x98) { /* Toshiba NAND */
502 get_toshiba_nand_para(denali);
503 } else if (maf_id == 0xAD) { /* Hynix NAND */
504 get_hynix_nand_para(denali, device_id);
507 find_valid_banks(denali);
509 detect_partition_feature(denali);
512 * If the user specified to override the default timings
513 * with a specific ONFI mode, we apply those changes here.
515 if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
516 nand_onfi_timing_set(denali, onfi_timing_mode);
522 * validation function to verify that the controlling software is making
525 static inline bool is_flash_bank_valid(int flash_bank)
527 return flash_bank >= 0 && flash_bank < 4;
530 static void denali_irq_init(struct denali_nand_info *denali)
535 /* Disable global interrupts */
536 writel(0, denali->flash_reg + GLOBAL_INT_ENABLE);
538 int_mask = DENALI_IRQ_ALL;
540 /* Clear all status bits */
541 for (i = 0; i < denali->max_banks; ++i)
542 writel(0xFFFF, denali->flash_reg + INTR_STATUS(i));
544 denali_irq_enable(denali, int_mask);
548 * This helper function setups the registers for ECC and whether or not
549 * the spare area will be transferred.
551 static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
554 int ecc_en_flag, transfer_spare_flag;
556 /* set ECC, transfer spare bits if needed */
557 ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
558 transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
560 /* Enable spare area/ECC per user's request. */
561 writel(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
562 /* applicable for MAP01 only */
563 writel(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG);
567 * sends a pipeline command operation to the controller. See the Denali NAND
568 * controller's user guide for more information (section 4.2.3.6).
570 static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
571 bool ecc_en, bool transfer_spare,
572 int access_type, int op)
574 uint32_t addr, cmd, irq_status;
575 static uint32_t page_count = 1;
577 setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
579 clear_interrupts(denali);
581 addr = BANK(denali->flash_bank) | denali->page;
583 /* setup the acccess type */
584 cmd = MODE_10 | addr;
585 index_addr(denali, cmd, access_type);
587 /* setup the pipeline command */
588 index_addr(denali, cmd, 0x2000 | op | page_count);
590 cmd = MODE_01 | addr;
591 writel(cmd, denali->flash_mem + INDEX_CTRL_REG);
593 if (op == DENALI_READ) {
594 /* wait for command to be accepted */
595 irq_status = wait_for_irq(denali, INTR_STATUS__LOAD_COMP);
604 /* helper function that simply writes a buffer to the flash */
605 static int write_data_to_flash_mem(struct denali_nand_info *denali,
606 const uint8_t *buf, int len)
612 * verify that the len is a multiple of 4.
613 * see comment in read_data_from_flash_mem()
615 BUG_ON((len % 4) != 0);
617 /* write the data to the flash memory */
618 buf32 = (uint32_t *)buf;
619 for (i = 0; i < len / 4; i++)
620 writel(*buf32++, denali->flash_mem + INDEX_DATA_REG);
621 return i * 4; /* intent is to return the number of bytes read */
624 /* helper function that simply reads a buffer from the flash */
625 static int read_data_from_flash_mem(struct denali_nand_info *denali,
626 uint8_t *buf, int len)
632 * we assume that len will be a multiple of 4, if not it would be nice
633 * to know about it ASAP rather than have random failures...
634 * This assumption is based on the fact that this function is designed
635 * to be used to read flash pages, which are typically multiples of 4.
637 BUG_ON((len % 4) != 0);
639 /* transfer the data from the flash */
640 buf32 = (uint32_t *)buf;
641 for (i = 0; i < len / 4; i++)
642 *buf32++ = readl(denali->flash_mem + INDEX_DATA_REG);
644 return i * 4; /* intent is to return the number of bytes read */
647 static void denali_mode_main_access(struct denali_nand_info *denali)
651 addr = BANK(denali->flash_bank) | denali->page;
652 cmd = MODE_10 | addr;
653 index_addr(denali, cmd, MAIN_ACCESS);
656 static void denali_mode_main_spare_access(struct denali_nand_info *denali)
660 addr = BANK(denali->flash_bank) | denali->page;
661 cmd = MODE_10 | addr;
662 index_addr(denali, cmd, MAIN_SPARE_ACCESS);
665 /* writes OOB data to the device */
666 static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
668 struct denali_nand_info *denali = mtd_to_denali(mtd);
670 uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |
671 INTR_STATUS__PROGRAM_FAIL;
676 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
677 DENALI_WRITE) == 0) {
678 write_data_to_flash_mem(denali, buf, mtd->oobsize);
680 /* wait for operation to complete */
681 irq_status = wait_for_irq(denali, irq_mask);
683 if (irq_status == 0) {
684 dev_err(denali->dev, "OOB write failed\n");
688 printf("unable to send pipeline command\n");
694 /* reads OOB data from the device */
695 static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
697 struct denali_nand_info *denali = mtd_to_denali(mtd);
698 uint32_t irq_mask = INTR_STATUS__LOAD_COMP;
699 uint32_t irq_status, addr, cmd;
703 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
705 read_data_from_flash_mem(denali, buf, mtd->oobsize);
708 * wait for command to be accepted
709 * can always use status0 bit as the
710 * mask is identical for each bank.
712 irq_status = wait_for_irq(denali, irq_mask);
715 printf("page on OOB timeout %d\n", denali->page);
718 * We set the device back to MAIN_ACCESS here as I observed
719 * instability with the controller if you do a block erase
720 * and the last transaction was a SPARE_ACCESS. Block erase
721 * is reliable (according to the MTD test infrastructure)
722 * if you are in MAIN_ACCESS.
724 addr = BANK(denali->flash_bank) | denali->page;
725 cmd = MODE_10 | addr;
726 index_addr(denali, cmd, MAIN_ACCESS);
731 * this function examines buffers to see if they contain data that
732 * indicate that the buffer is part of an erased region of flash.
734 static bool is_erased(uint8_t *buf, int len)
738 for (i = 0; i < len; i++)
744 /* programs the controller to either enable/disable DMA transfers */
745 static void denali_enable_dma(struct denali_nand_info *denali, bool en)
747 writel(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE);
748 readl(denali->flash_reg + DMA_ENABLE);
751 /* setups the HW to perform the data DMA */
752 static void denali_setup_dma(struct denali_nand_info *denali, int op)
755 const int page_count = 1;
756 uint64_t addr = (unsigned long)denali->buf.dma_buf;
758 flush_dcache_range(addr, addr + sizeof(denali->buf.dma_buf));
760 /* For Denali controller that is 64 bit bus IP core */
761 #ifdef CONFIG_SYS_NAND_DENALI_64BIT
762 mode = MODE_10 | BANK(denali->flash_bank) | denali->page;
764 /* DMA is a three step process */
766 /* 1. setup transfer type, interrupt when complete,
767 burst len = 64 bytes, the number of pages */
768 index_addr(denali, mode, 0x01002000 | (64 << 16) | op | page_count);
770 /* 2. set memory low address bits 31:0 */
771 index_addr(denali, mode, addr);
773 /* 3. set memory high address bits 64:32 */
774 index_addr(denali, mode, addr >> 32);
776 mode = MODE_10 | BANK(denali->flash_bank);
778 /* DMA is a four step process */
780 /* 1. setup transfer type and # of pages */
781 index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
783 /* 2. set memory high address bits 23:8 */
784 index_addr(denali, mode | (((addr >> 16) & 0xffff) << 8), 0x2200);
786 /* 3. set memory low address bits 23:8 */
787 index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300);
789 /* 4. interrupt when complete, burst len = 64 bytes */
790 index_addr(denali, mode | 0x14000, 0x2400);
794 /* Common DMA function */
795 static uint32_t denali_dma_configuration(struct denali_nand_info *denali,
796 uint32_t ops, bool raw_xfer,
797 uint32_t irq_mask, int oob_required)
799 uint32_t irq_status = 0;
800 /* setup_ecc_for_xfer(bool ecc_en, bool transfer_spare) */
801 setup_ecc_for_xfer(denali, !raw_xfer, oob_required);
803 /* clear any previous interrupt flags */
804 clear_interrupts(denali);
807 denali_enable_dma(denali, true);
810 denali_setup_dma(denali, ops);
812 /* wait for operation to complete */
813 irq_status = wait_for_irq(denali, irq_mask);
815 /* if ECC fault happen, seems we need delay before turning off DMA.
816 * If not, the controller will go into non responsive condition */
817 if (irq_status & INTR_STATUS__ECC_UNCOR_ERR)
820 /* disable the DMA */
821 denali_enable_dma(denali, false);
826 static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
827 const uint8_t *buf, bool raw_xfer, int oob_required)
829 struct denali_nand_info *denali = mtd_to_denali(mtd);
831 uint32_t irq_status = 0;
832 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;
836 /* copy buffer into DMA buffer */
837 memcpy(denali->buf.dma_buf, buf, mtd->writesize);
839 /* need extra memcpy for raw transfer */
841 memcpy(denali->buf.dma_buf + mtd->writesize,
842 chip->oob_poi, mtd->oobsize);
845 irq_status = denali_dma_configuration(denali, DENALI_WRITE, raw_xfer,
846 irq_mask, oob_required);
848 /* if timeout happen, error out */
849 if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) {
850 debug("DMA timeout for denali write_page\n");
851 denali->status = NAND_STATUS_FAIL;
855 if (irq_status & INTR_STATUS__LOCKED_BLK) {
856 debug("Failed as write to locked block\n");
857 denali->status = NAND_STATUS_FAIL;
863 /* NAND core entry points */
866 * this is the callback that the NAND core calls to write a page. Since
867 * writing a page with ECC or without is similar, all the work is done
868 * by write_page above.
870 static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
871 const uint8_t *buf, int oob_required, int page)
873 struct denali_nand_info *denali = mtd_to_denali(mtd);
876 * for regular page writes, we let HW handle all the ECC
877 * data written to the device.
880 /* switch to main + spare access */
881 denali_mode_main_spare_access(denali);
883 /* switch to main access only */
884 denali_mode_main_access(denali);
886 return write_page(mtd, chip, buf, false, oob_required);
890 * This is the callback that the NAND core calls to write a page without ECC.
891 * raw access is similar to ECC page writes, so all the work is done in the
892 * write_page() function above.
894 static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
895 const uint8_t *buf, int oob_required,
898 struct denali_nand_info *denali = mtd_to_denali(mtd);
901 * for raw page writes, we want to disable ECC and simply write
902 * whatever data is in the buffer.
906 /* switch to main + spare access */
907 denali_mode_main_spare_access(denali);
909 /* switch to main access only */
910 denali_mode_main_access(denali);
912 return write_page(mtd, chip, buf, true, oob_required);
915 static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
918 return write_oob_data(mtd, chip->oob_poi, page);
921 /* raw include ECC value and all the spare area */
922 static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
923 uint8_t *buf, int oob_required, int page)
925 struct denali_nand_info *denali = mtd_to_denali(mtd);
927 uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP;
929 if (denali->page != page) {
930 debug("Missing NAND_CMD_READ0 command\n");
935 /* switch to main + spare access */
936 denali_mode_main_spare_access(denali);
938 /* switch to main access only */
939 denali_mode_main_access(denali);
941 /* setting up the DMA where ecc_enable is false */
942 irq_status = denali_dma_configuration(denali, DENALI_READ, true,
943 irq_mask, oob_required);
945 /* if timeout happen, error out */
946 if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) {
947 debug("DMA timeout for denali_read_page_raw\n");
951 /* splitting the content to destination buffer holder */
952 memcpy(chip->oob_poi, (denali->buf.dma_buf + mtd->writesize),
954 memcpy(buf, denali->buf.dma_buf, mtd->writesize);
959 static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
960 uint8_t *buf, int oob_required, int page)
962 struct denali_nand_info *denali = mtd_to_denali(mtd);
963 uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP;
965 if (denali->page != page) {
966 debug("Missing NAND_CMD_READ0 command\n");
971 /* switch to main + spare access */
972 denali_mode_main_spare_access(denali);
974 /* switch to main access only */
975 denali_mode_main_access(denali);
977 /* setting up the DMA where ecc_enable is true */
978 irq_status = denali_dma_configuration(denali, DENALI_READ, false,
979 irq_mask, oob_required);
981 memcpy(buf, denali->buf.dma_buf, mtd->writesize);
983 /* check whether any ECC error */
984 if (irq_status & INTR_STATUS__ECC_UNCOR_ERR) {
985 /* is the ECC cause by erase page, check using read_page_raw */
986 debug(" Uncorrected ECC detected\n");
987 denali_read_page_raw(mtd, chip, buf, oob_required,
990 if (is_erased(buf, mtd->writesize) == true &&
991 is_erased(chip->oob_poi, mtd->oobsize) == true) {
992 debug(" ECC error cause by erased block\n");
993 /* false alarm, return the 0xFF */
998 memcpy(buf, denali->buf.dma_buf, mtd->writesize);
1002 static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1005 read_oob_data(mtd, chip->oob_poi, page);
1010 static uint8_t denali_read_byte(struct mtd_info *mtd)
1012 struct denali_nand_info *denali = mtd_to_denali(mtd);
1013 uint32_t addr, result;
1015 addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
1016 index_addr_read_data(denali, addr | 2, &result);
1017 return (uint8_t)result & 0xFF;
1020 static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1022 struct denali_nand_info *denali = mtd_to_denali(mtd);
1023 uint32_t i, addr, result;
1025 /* delay for tR (data transfer from Flash array to data register) */
1028 /* ensure device completed else additional delay and polling */
1029 wait_for_irq(denali, INTR_STATUS__INT_ACT);
1031 addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
1032 for (i = 0; i < len; i++) {
1033 index_addr_read_data(denali, (uint32_t)addr | 2, &result);
1034 write_byte_to_buf(denali, result);
1036 memcpy(buf, denali->buf.buf, len);
1039 static void denali_select_chip(struct mtd_info *mtd, int chip)
1041 struct denali_nand_info *denali = mtd_to_denali(mtd);
1043 denali->flash_bank = chip;
1046 static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
1048 struct denali_nand_info *denali = mtd_to_denali(mtd);
1049 int status = denali->status;
1056 static int denali_erase(struct mtd_info *mtd, int page)
1058 struct denali_nand_info *denali = mtd_to_denali(mtd);
1060 uint32_t cmd, irq_status;
1062 clear_interrupts(denali);
1064 /* setup page read request for access type */
1065 cmd = MODE_10 | BANK(denali->flash_bank) | page;
1066 index_addr(denali, cmd, 0x1);
1068 /* wait for erase to complete or failure to occur */
1069 irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP |
1070 INTR_STATUS__ERASE_FAIL);
1072 if (irq_status & INTR_STATUS__ERASE_FAIL ||
1073 irq_status & INTR_STATUS__LOCKED_BLK)
1074 return NAND_STATUS_FAIL;
1079 static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
1082 struct denali_nand_info *denali = mtd_to_denali(mtd);
1086 case NAND_CMD_PAGEPROG:
1088 case NAND_CMD_STATUS:
1089 addr = MODE_11 | BANK(denali->flash_bank);
1090 index_addr(denali, addr | 0, cmd);
1092 case NAND_CMD_READID:
1093 case NAND_CMD_PARAM:
1096 * sometimes ManufactureId read from register is not right
1097 * e.g. some of Micron MT29F32G08QAA MLC NAND chips
1098 * So here we send READID cmd to NAND insteand
1100 addr = MODE_11 | BANK(denali->flash_bank);
1101 index_addr(denali, addr | 0, cmd);
1102 index_addr(denali, addr | 1, col & 0xFF);
1103 if (cmd == NAND_CMD_PARAM)
1106 case NAND_CMD_RNDOUT:
1107 addr = MODE_11 | BANK(denali->flash_bank);
1108 index_addr(denali, addr | 0, cmd);
1109 index_addr(denali, addr | 1, col & 0xFF);
1110 index_addr(denali, addr | 1, col >> 8);
1111 index_addr(denali, addr | 0, NAND_CMD_RNDOUTSTART);
1113 case NAND_CMD_READ0:
1114 case NAND_CMD_SEQIN:
1115 denali->page = page;
1117 case NAND_CMD_RESET:
1120 case NAND_CMD_READOOB:
1121 /* TODO: Read OOB data */
1123 case NAND_CMD_ERASE1:
1125 * supporting block erase only, not multiblock erase as
1126 * it will cross plane and software need complex calculation
1127 * to identify the block count for the cross plane
1129 denali_erase(mtd, page);
1131 case NAND_CMD_ERASE2:
1132 /* nothing to do here as it was done during NAND_CMD_ERASE1 */
1134 case NAND_CMD_UNLOCK1:
1135 addr = MODE_10 | BANK(denali->flash_bank) | page;
1136 index_addr(denali, addr | 0, DENALI_UNLOCK_START);
1138 case NAND_CMD_UNLOCK2:
1139 addr = MODE_10 | BANK(denali->flash_bank) | page;
1140 index_addr(denali, addr | 0, DENALI_UNLOCK_END);
1143 addr = MODE_10 | BANK(denali->flash_bank);
1144 index_addr(denali, addr | 0, DENALI_LOCK);
1147 printf(": unsupported command received 0x%x\n", cmd);
1151 /* end NAND core entry points */
1153 /* Initialization code to bring the device up to a known good state */
1154 static void denali_hw_init(struct denali_nand_info *denali)
1157 * tell driver how many bit controller will skip before writing
1158 * ECC code in OOB. This is normally used for bad block marker
1160 writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES,
1161 denali->flash_reg + SPARE_AREA_SKIP_BYTES);
1162 detect_max_banks(denali);
1163 denali_nand_reset(denali);
1164 writel(0x0F, denali->flash_reg + RB_PIN_ENABLED);
1165 writel(CHIP_EN_DONT_CARE__FLAG,
1166 denali->flash_reg + CHIP_ENABLE_DONT_CARE);
1167 writel(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
1169 /* Should set value for these registers when init */
1170 writel(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
1171 writel(1, denali->flash_reg + ECC_ENABLE);
1172 denali_nand_timing_set(denali);
1173 denali_irq_init(denali);
1176 static struct nand_ecclayout nand_oob;
1178 static int denali_init(struct denali_nand_info *denali)
1180 struct mtd_info *mtd = nand_to_mtd(&denali->nand);
1183 denali_hw_init(denali);
1185 mtd->name = "denali-nand";
1186 mtd->owner = THIS_MODULE;
1188 /* register the driver with the NAND core subsystem */
1189 denali->nand.select_chip = denali_select_chip;
1190 denali->nand.cmdfunc = denali_cmdfunc;
1191 denali->nand.read_byte = denali_read_byte;
1192 denali->nand.read_buf = denali_read_buf;
1193 denali->nand.waitfunc = denali_waitfunc;
1196 * scan for NAND devices attached to the controller
1197 * this is the first stage in a two step process to register
1198 * with the nand subsystem
1200 if (nand_scan_ident(mtd, denali->max_banks, NULL)) {
1205 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1206 /* check whether flash got BBT table (located at end of flash). As we
1207 * use NAND_BBT_NO_OOB, the BBT page will start with
1208 * bbt_pattern. We will have mirror pattern too */
1209 denali->nand.bbt_options |= NAND_BBT_USE_FLASH;
1211 * We are using main + spare with ECC support. As BBT need ECC support,
1212 * we need to ensure BBT code don't write to OOB for the BBT pattern.
1213 * All BBT info will be stored into data area with ECC support.
1215 denali->nand.bbt_options |= NAND_BBT_NO_OOB;
1218 denali->nand.ecc.mode = NAND_ECC_HW;
1219 denali->nand.ecc.size = CONFIG_NAND_DENALI_ECC_SIZE;
1221 /* no subpage writes on denali */
1222 denali->nand.options |= NAND_NO_SUBPAGE_WRITE;
1225 * Tell driver the ecc strength. This register may be already set
1226 * correctly. So we read this value out.
1228 denali->nand.ecc.strength = readl(denali->flash_reg + ECC_CORRECTION);
1229 switch (denali->nand.ecc.size) {
1231 denali->nand.ecc.bytes =
1232 (denali->nand.ecc.strength * 13 + 15) / 16 * 2;
1235 denali->nand.ecc.bytes =
1236 (denali->nand.ecc.strength * 14 + 15) / 16 * 2;
1239 pr_err("Unsupported ECC size\n");
1243 nand_oob.eccbytes = denali->nand.ecc.bytes;
1244 denali->nand.ecc.layout = &nand_oob;
1246 writel(mtd->erasesize / mtd->writesize,
1247 denali->flash_reg + PAGES_PER_BLOCK);
1248 writel(denali->nand.options & NAND_BUSWIDTH_16 ? 1 : 0,
1249 denali->flash_reg + DEVICE_WIDTH);
1250 writel(mtd->writesize,
1251 denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
1252 writel(mtd->oobsize,
1253 denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
1254 if (readl(denali->flash_reg + DEVICES_CONNECTED) == 0)
1255 writel(1, denali->flash_reg + DEVICES_CONNECTED);
1257 /* override the default operations */
1258 denali->nand.ecc.read_page = denali_read_page;
1259 denali->nand.ecc.read_page_raw = denali_read_page_raw;
1260 denali->nand.ecc.write_page = denali_write_page;
1261 denali->nand.ecc.write_page_raw = denali_write_page_raw;
1262 denali->nand.ecc.read_oob = denali_read_oob;
1263 denali->nand.ecc.write_oob = denali_write_oob;
1265 if (nand_scan_tail(mtd)) {
1270 ret = nand_register(0, mtd);
1276 static int __board_nand_init(void)
1278 struct denali_nand_info *denali;
1280 denali = kzalloc(sizeof(*denali), GFP_KERNEL);
1285 * In the future, these base addresses should be taken from
1286 * Device Tree or platform data.
1288 denali->flash_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
1289 denali->flash_mem = (void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
1291 return denali_init(denali);
1294 void board_nand_init(void)
1296 if (__board_nand_init() < 0)
1297 pr_warn("Failed to initialize Denali NAND controller.\n");