2 * Copyright (C) 2014 Panasonic Corporation
3 * Copyright (C) 2013-2014, Altera Corporation <www.altera.com>
4 * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/errno.h>
17 #define NAND_DEFAULT_TIMINGS -1
19 static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
22 * We define a macro here that combines all interrupts this driver uses into
23 * a single constant value, for convenience.
25 #define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
26 INTR_STATUS__ECC_TRANSACTION_DONE | \
27 INTR_STATUS__ECC_ERR | \
28 INTR_STATUS__PROGRAM_FAIL | \
29 INTR_STATUS__LOAD_COMP | \
30 INTR_STATUS__PROGRAM_COMP | \
31 INTR_STATUS__TIME_OUT | \
32 INTR_STATUS__ERASE_FAIL | \
33 INTR_STATUS__RST_COMP | \
34 INTR_STATUS__ERASE_COMP | \
35 INTR_STATUS__ECC_UNCOR_ERR | \
36 INTR_STATUS__INT_ACT | \
37 INTR_STATUS__LOCKED_BLK)
40 * indicates whether or not the internal value for the flash bank is
43 #define CHIP_SELECT_INVALID -1
45 #define SUPPORT_8BITECC 1
48 * this macro allows us to convert from an MTD structure to our own
49 * device context (denali) structure.
51 static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
53 return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
57 * These constants are defined by the driver to enable common driver
58 * configuration options.
60 #define SPARE_ACCESS 0x41
61 #define MAIN_ACCESS 0x42
62 #define MAIN_SPARE_ACCESS 0x43
63 #define PIPELINE_ACCESS 0x2000
65 #define DENALI_UNLOCK_START 0x10
66 #define DENALI_UNLOCK_END 0x11
67 #define DENALI_LOCK 0x21
68 #define DENALI_LOCK_TIGHT 0x31
69 #define DENALI_BUFFER_LOAD 0x60
70 #define DENALI_BUFFER_WRITE 0x62
73 #define DENALI_WRITE 0x100
75 /* types of device accesses. We can issue commands and get status */
76 #define COMMAND_CYCLE 0
78 #define STATUS_CYCLE 2
81 * this is a helper macro that allows us to
82 * format the bank into the proper bits for the controller
84 #define BANK(x) ((x) << 24)
86 /* Interrupts are cleared by writing a 1 to the appropriate status bit */
87 static inline void clear_interrupt(struct denali_nand_info *denali,
90 uint32_t intr_status_reg;
92 intr_status_reg = INTR_STATUS(denali->flash_bank);
94 writel(irq_mask, denali->flash_reg + intr_status_reg);
97 static uint32_t read_interrupt_status(struct denali_nand_info *denali)
99 uint32_t intr_status_reg;
101 intr_status_reg = INTR_STATUS(denali->flash_bank);
103 return readl(denali->flash_reg + intr_status_reg);
106 static void clear_interrupts(struct denali_nand_info *denali)
110 status = read_interrupt_status(denali);
111 clear_interrupt(denali, status);
113 denali->irq_status = 0;
116 static void denali_irq_enable(struct denali_nand_info *denali,
121 for (i = 0; i < denali->max_banks; ++i)
122 writel(int_mask, denali->flash_reg + INTR_EN(i));
125 static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
127 unsigned long timeout = 1000000;
128 uint32_t intr_status;
131 intr_status = read_interrupt_status(denali) & DENALI_IRQ_ALL;
132 if (intr_status & irq_mask) {
133 denali->irq_status &= ~irq_mask;
134 /* our interrupt was detected */
139 } while (timeout != 0);
143 printf("Denali timeout with interrupt status %08x\n",
144 read_interrupt_status(denali));
151 * Certain operations for the denali NAND controller use an indexed mode to
152 * read/write data. The operation is performed by writing the address value
153 * of the command to the device memory followed by the data. This function
154 * abstracts this common operation.
156 static void index_addr(struct denali_nand_info *denali,
157 uint32_t address, uint32_t data)
159 writel(address, denali->flash_mem + INDEX_CTRL_REG);
160 writel(data, denali->flash_mem + INDEX_DATA_REG);
163 /* Perform an indexed read of the device */
164 static void index_addr_read_data(struct denali_nand_info *denali,
165 uint32_t address, uint32_t *pdata)
167 writel(address, denali->flash_mem + INDEX_CTRL_REG);
168 *pdata = readl(denali->flash_mem + INDEX_DATA_REG);
172 * We need to buffer some data for some of the NAND core routines.
173 * The operations manage buffering that data.
175 static void reset_buf(struct denali_nand_info *denali)
177 denali->buf.head = 0;
178 denali->buf.tail = 0;
181 static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
183 denali->buf.buf[denali->buf.tail++] = byte;
186 /* resets a specific device connected to the core */
187 static void reset_bank(struct denali_nand_info *denali)
190 uint32_t irq_mask = INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT;
192 clear_interrupts(denali);
194 writel(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
196 irq_status = wait_for_irq(denali, irq_mask);
197 if (irq_status & INTR_STATUS__TIME_OUT)
198 debug("reset bank failed.\n");
201 /* Reset the flash controller */
202 static uint32_t denali_nand_reset(struct denali_nand_info *denali)
206 for (i = 0; i < denali->max_banks; i++)
207 writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
208 denali->flash_reg + INTR_STATUS(i));
210 for (i = 0; i < denali->max_banks; i++) {
211 writel(1 << i, denali->flash_reg + DEVICE_RESET);
212 while (!(readl(denali->flash_reg + INTR_STATUS(i)) &
213 (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))
214 if (readl(denali->flash_reg + INTR_STATUS(i)) &
215 INTR_STATUS__TIME_OUT)
216 debug("NAND Reset operation timed out on bank"
220 for (i = 0; i < denali->max_banks; i++)
221 writel(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
222 denali->flash_reg + INTR_STATUS(i));
228 * this routine calculates the ONFI timing values for a given mode and
229 * programs the clocking register accordingly. The mode is determined by
230 * the get_onfi_nand_para routine.
232 static void nand_onfi_timing_set(struct denali_nand_info *denali,
235 uint32_t trea[6] = {40, 30, 25, 20, 20, 16};
236 uint32_t trp[6] = {50, 25, 17, 15, 12, 10};
237 uint32_t treh[6] = {30, 15, 15, 10, 10, 7};
238 uint32_t trc[6] = {100, 50, 35, 30, 25, 20};
239 uint32_t trhoh[6] = {0, 15, 15, 15, 15, 15};
240 uint32_t trloh[6] = {0, 0, 0, 0, 5, 5};
241 uint32_t tcea[6] = {100, 45, 30, 25, 25, 25};
242 uint32_t tadl[6] = {200, 100, 100, 100, 70, 70};
243 uint32_t trhw[6] = {200, 100, 100, 100, 100, 100};
244 uint32_t trhz[6] = {200, 100, 100, 100, 100, 100};
245 uint32_t twhr[6] = {120, 80, 80, 60, 60, 60};
246 uint32_t tcs[6] = {70, 35, 25, 25, 20, 15};
248 uint32_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
249 uint32_t dv_window = 0;
250 uint32_t en_lo, en_hi;
252 uint32_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
254 en_lo = DIV_ROUND_UP(trp[mode], CLK_X);
255 en_hi = DIV_ROUND_UP(treh[mode], CLK_X);
256 if ((en_hi * CLK_X) < (treh[mode] + 2))
259 if ((en_lo + en_hi) * CLK_X < trc[mode])
260 en_lo += DIV_ROUND_UP((trc[mode] - (en_lo + en_hi) * CLK_X),
263 if ((en_lo + en_hi) < CLK_MULTI)
264 en_lo += CLK_MULTI - en_lo - en_hi;
266 while (dv_window < 8) {
267 data_invalid_rhoh = en_lo * CLK_X + trhoh[mode];
269 data_invalid_rloh = (en_lo + en_hi) * CLK_X + trloh[mode];
271 data_invalid = data_invalid_rhoh < data_invalid_rloh ?
272 data_invalid_rhoh : data_invalid_rloh;
274 dv_window = data_invalid - trea[mode];
280 acc_clks = DIV_ROUND_UP(trea[mode], CLK_X);
282 while (acc_clks * CLK_X - trea[mode] < 3)
285 if (data_invalid - acc_clks * CLK_X < 2)
286 debug("%s, Line %d: Warning!\n", __FILE__, __LINE__);
288 addr_2_data = DIV_ROUND_UP(tadl[mode], CLK_X);
289 re_2_we = DIV_ROUND_UP(trhw[mode], CLK_X);
290 re_2_re = DIV_ROUND_UP(trhz[mode], CLK_X);
291 we_2_re = DIV_ROUND_UP(twhr[mode], CLK_X);
292 cs_cnt = DIV_ROUND_UP((tcs[mode] - trp[mode]), CLK_X);
297 while (cs_cnt * CLK_X + trea[mode] < tcea[mode])
301 /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
302 if (readl(denali->flash_reg + MANUFACTURER_ID) == 0 &&
303 readl(denali->flash_reg + DEVICE_ID) == 0x88)
306 writel(acc_clks, denali->flash_reg + ACC_CLKS);
307 writel(re_2_we, denali->flash_reg + RE_2_WE);
308 writel(re_2_re, denali->flash_reg + RE_2_RE);
309 writel(we_2_re, denali->flash_reg + WE_2_RE);
310 writel(addr_2_data, denali->flash_reg + ADDR_2_DATA);
311 writel(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
312 writel(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
313 writel(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
316 /* queries the NAND device to see what ONFI modes it supports. */
317 static uint32_t get_onfi_nand_para(struct denali_nand_info *denali)
322 * we needn't to do a reset here because driver has already
323 * reset all the banks before
325 if (!(readl(denali->flash_reg + ONFI_TIMING_MODE) &
326 ONFI_TIMING_MODE__VALUE))
329 for (i = 5; i > 0; i--) {
330 if (readl(denali->flash_reg + ONFI_TIMING_MODE) &
335 nand_onfi_timing_set(denali, i);
338 * By now, all the ONFI devices we know support the page cache
339 * rw feature. So here we enable the pipeline_rw_ahead feature
345 static void get_samsung_nand_para(struct denali_nand_info *denali,
348 if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
349 /* Set timing register values according to datasheet */
350 writel(5, denali->flash_reg + ACC_CLKS);
351 writel(20, denali->flash_reg + RE_2_WE);
352 writel(12, denali->flash_reg + WE_2_RE);
353 writel(14, denali->flash_reg + ADDR_2_DATA);
354 writel(3, denali->flash_reg + RDWR_EN_LO_CNT);
355 writel(2, denali->flash_reg + RDWR_EN_HI_CNT);
356 writel(2, denali->flash_reg + CS_SETUP_CNT);
360 static void get_toshiba_nand_para(struct denali_nand_info *denali)
365 * Workaround to fix a controller bug which reports a wrong
366 * spare area size for some kind of Toshiba NAND device
368 if ((readl(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
369 (readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
370 writel(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
371 tmp = readl(denali->flash_reg + DEVICES_CONNECTED) *
372 readl(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
373 writel(tmp, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
377 static void get_hynix_nand_para(struct denali_nand_info *denali,
380 uint32_t main_size, spare_size;
383 case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
384 case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
385 writel(128, denali->flash_reg + PAGES_PER_BLOCK);
386 writel(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
387 writel(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
389 readl(denali->flash_reg + DEVICES_CONNECTED);
391 readl(denali->flash_reg + DEVICES_CONNECTED);
392 writel(main_size, denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
393 writel(spare_size, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
394 writel(0, denali->flash_reg + DEVICE_WIDTH);
397 debug("Spectra: Unknown Hynix NAND (Device ID: 0x%x).\n"
398 "Will use default parameter values instead.\n",
404 * determines how many NAND chips are connected to the controller. Note for
405 * Intel CE4100 devices we don't support more than one device.
407 static void find_valid_banks(struct denali_nand_info *denali)
409 uint32_t id[denali->max_banks];
412 denali->total_used_banks = 1;
413 for (i = 0; i < denali->max_banks; i++) {
414 index_addr(denali, MODE_11 | (i << 24) | 0, 0x90);
415 index_addr(denali, MODE_11 | (i << 24) | 1, 0);
416 index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]);
419 if (!(id[i] & 0x0ff))
422 if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
423 denali->total_used_banks++;
431 * Use the configuration feature register to determine the maximum number of
432 * banks that the hardware supports.
434 static void detect_max_banks(struct denali_nand_info *denali)
436 uint32_t features = ioread32(denali->flash_reg + FEATURES);
438 denali->max_banks = 1 << (features & FEATURES__N_BANKS);
440 /* the encoding changed from rev 5.0 to 5.1 */
441 if (denali->revision < 0x0501)
442 denali->max_banks <<= 1;
445 static void detect_partition_feature(struct denali_nand_info *denali)
448 * For MRST platform, denali->fwblks represent the
449 * number of blocks firmware is taken,
450 * FW is in protect partition and MTD driver has no
451 * permission to access it. So let driver know how many
452 * blocks it can't touch.
454 if (readl(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
455 if ((readl(denali->flash_reg + PERM_SRC_ID(1)) &
456 PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) {
458 ((readl(denali->flash_reg + MIN_MAX_BANK(1)) &
459 MIN_MAX_BANK__MIN_VALUE) *
462 (readl(denali->flash_reg + MIN_BLK_ADDR(1)) &
463 MIN_BLK_ADDR__VALUE);
465 denali->fwblks = SPECTRA_START_BLOCK;
468 denali->fwblks = SPECTRA_START_BLOCK;
472 static uint32_t denali_nand_timing_set(struct denali_nand_info *denali)
474 uint32_t id_bytes[8], addr;
475 uint8_t maf_id, device_id;
479 * Use read id method to get device ID and other params.
480 * For some NAND chips, controller can't report the correct
481 * device ID by reading from DEVICE_ID register
483 addr = MODE_11 | BANK(denali->flash_bank);
484 index_addr(denali, addr | 0, 0x90);
485 index_addr(denali, addr | 1, 0);
486 for (i = 0; i < 8; i++)
487 index_addr_read_data(denali, addr | 2, &id_bytes[i]);
488 maf_id = id_bytes[0];
489 device_id = id_bytes[1];
491 if (readl(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
492 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
493 if (get_onfi_nand_para(denali))
495 } else if (maf_id == 0xEC) { /* Samsung NAND */
496 get_samsung_nand_para(denali, device_id);
497 } else if (maf_id == 0x98) { /* Toshiba NAND */
498 get_toshiba_nand_para(denali);
499 } else if (maf_id == 0xAD) { /* Hynix NAND */
500 get_hynix_nand_para(denali, device_id);
503 find_valid_banks(denali);
505 detect_partition_feature(denali);
508 * If the user specified to override the default timings
509 * with a specific ONFI mode, we apply those changes here.
511 if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
512 nand_onfi_timing_set(denali, onfi_timing_mode);
518 * validation function to verify that the controlling software is making
521 static inline bool is_flash_bank_valid(int flash_bank)
523 return flash_bank >= 0 && flash_bank < 4;
526 static void denali_irq_init(struct denali_nand_info *denali)
531 /* Disable global interrupts */
532 writel(0, denali->flash_reg + GLOBAL_INT_ENABLE);
534 int_mask = DENALI_IRQ_ALL;
536 /* Clear all status bits */
537 for (i = 0; i < denali->max_banks; ++i)
538 writel(0xFFFF, denali->flash_reg + INTR_STATUS(i));
540 denali_irq_enable(denali, int_mask);
544 * This helper function setups the registers for ECC and whether or not
545 * the spare area will be transferred.
547 static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
550 int ecc_en_flag, transfer_spare_flag;
552 /* set ECC, transfer spare bits if needed */
553 ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
554 transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
556 /* Enable spare area/ECC per user's request. */
557 writel(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
558 /* applicable for MAP01 only */
559 writel(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG);
563 * sends a pipeline command operation to the controller. See the Denali NAND
564 * controller's user guide for more information (section 4.2.3.6).
566 static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
567 bool ecc_en, bool transfer_spare,
568 int access_type, int op)
570 uint32_t addr, cmd, irq_status;
571 static uint32_t page_count = 1;
573 setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
575 clear_interrupts(denali);
577 addr = BANK(denali->flash_bank) | denali->page;
579 /* setup the acccess type */
580 cmd = MODE_10 | addr;
581 index_addr(denali, cmd, access_type);
583 /* setup the pipeline command */
584 index_addr(denali, cmd, 0x2000 | op | page_count);
586 cmd = MODE_01 | addr;
587 writel(cmd, denali->flash_mem + INDEX_CTRL_REG);
589 if (op == DENALI_READ) {
590 /* wait for command to be accepted */
591 irq_status = wait_for_irq(denali, INTR_STATUS__LOAD_COMP);
600 /* helper function that simply writes a buffer to the flash */
601 static int write_data_to_flash_mem(struct denali_nand_info *denali,
602 const uint8_t *buf, int len)
608 * verify that the len is a multiple of 4.
609 * see comment in read_data_from_flash_mem()
611 BUG_ON((len % 4) != 0);
613 /* write the data to the flash memory */
614 buf32 = (uint32_t *)buf;
615 for (i = 0; i < len / 4; i++)
616 writel(*buf32++, denali->flash_mem + INDEX_DATA_REG);
617 return i * 4; /* intent is to return the number of bytes read */
620 /* helper function that simply reads a buffer from the flash */
621 static int read_data_from_flash_mem(struct denali_nand_info *denali,
622 uint8_t *buf, int len)
628 * we assume that len will be a multiple of 4, if not it would be nice
629 * to know about it ASAP rather than have random failures...
630 * This assumption is based on the fact that this function is designed
631 * to be used to read flash pages, which are typically multiples of 4.
633 BUG_ON((len % 4) != 0);
635 /* transfer the data from the flash */
636 buf32 = (uint32_t *)buf;
637 for (i = 0; i < len / 4; i++)
638 *buf32++ = readl(denali->flash_mem + INDEX_DATA_REG);
640 return i * 4; /* intent is to return the number of bytes read */
643 static void denali_mode_main_access(struct denali_nand_info *denali)
647 addr = BANK(denali->flash_bank) | denali->page;
648 cmd = MODE_10 | addr;
649 index_addr(denali, cmd, MAIN_ACCESS);
652 static void denali_mode_main_spare_access(struct denali_nand_info *denali)
656 addr = BANK(denali->flash_bank) | denali->page;
657 cmd = MODE_10 | addr;
658 index_addr(denali, cmd, MAIN_SPARE_ACCESS);
661 /* writes OOB data to the device */
662 static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
664 struct denali_nand_info *denali = mtd_to_denali(mtd);
666 uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |
667 INTR_STATUS__PROGRAM_FAIL;
672 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
673 DENALI_WRITE) == 0) {
674 write_data_to_flash_mem(denali, buf, mtd->oobsize);
676 /* wait for operation to complete */
677 irq_status = wait_for_irq(denali, irq_mask);
679 if (irq_status == 0) {
680 dev_err(denali->dev, "OOB write failed\n");
684 printf("unable to send pipeline command\n");
690 /* reads OOB data from the device */
691 static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
693 struct denali_nand_info *denali = mtd_to_denali(mtd);
694 uint32_t irq_mask = INTR_STATUS__LOAD_COMP;
695 uint32_t irq_status, addr, cmd;
699 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
701 read_data_from_flash_mem(denali, buf, mtd->oobsize);
704 * wait for command to be accepted
705 * can always use status0 bit as the
706 * mask is identical for each bank.
708 irq_status = wait_for_irq(denali, irq_mask);
711 printf("page on OOB timeout %d\n", denali->page);
714 * We set the device back to MAIN_ACCESS here as I observed
715 * instability with the controller if you do a block erase
716 * and the last transaction was a SPARE_ACCESS. Block erase
717 * is reliable (according to the MTD test infrastructure)
718 * if you are in MAIN_ACCESS.
720 addr = BANK(denali->flash_bank) | denali->page;
721 cmd = MODE_10 | addr;
722 index_addr(denali, cmd, MAIN_ACCESS);
727 * this function examines buffers to see if they contain data that
728 * indicate that the buffer is part of an erased region of flash.
730 static bool is_erased(uint8_t *buf, int len)
734 for (i = 0; i < len; i++)
740 /* programs the controller to either enable/disable DMA transfers */
741 static void denali_enable_dma(struct denali_nand_info *denali, bool en)
743 writel(en ? DMA_ENABLE__FLAG : 0, denali->flash_reg + DMA_ENABLE);
744 readl(denali->flash_reg + DMA_ENABLE);
747 /* setups the HW to perform the data DMA */
748 static void denali_setup_dma(struct denali_nand_info *denali, int op)
751 const int page_count = 1;
752 uint64_t addr = (unsigned long)denali->buf.dma_buf;
754 flush_dcache_range(addr, addr + sizeof(denali->buf.dma_buf));
756 /* For Denali controller that is 64 bit bus IP core */
757 #ifdef CONFIG_SYS_NAND_DENALI_64BIT
758 mode = MODE_10 | BANK(denali->flash_bank) | denali->page;
760 /* DMA is a three step process */
762 /* 1. setup transfer type, interrupt when complete,
763 burst len = 64 bytes, the number of pages */
764 index_addr(denali, mode, 0x01002000 | (64 << 16) | op | page_count);
766 /* 2. set memory low address bits 31:0 */
767 index_addr(denali, mode, addr);
769 /* 3. set memory high address bits 64:32 */
770 index_addr(denali, mode, addr >> 32);
772 mode = MODE_10 | BANK(denali->flash_bank);
774 /* DMA is a four step process */
776 /* 1. setup transfer type and # of pages */
777 index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
779 /* 2. set memory high address bits 23:8 */
780 index_addr(denali, mode | (((addr >> 16) & 0xffff) << 8), 0x2200);
782 /* 3. set memory low address bits 23:8 */
783 index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300);
785 /* 4. interrupt when complete, burst len = 64 bytes */
786 index_addr(denali, mode | 0x14000, 0x2400);
790 /* Common DMA function */
791 static uint32_t denali_dma_configuration(struct denali_nand_info *denali,
792 uint32_t ops, bool raw_xfer,
793 uint32_t irq_mask, int oob_required)
795 uint32_t irq_status = 0;
796 /* setup_ecc_for_xfer(bool ecc_en, bool transfer_spare) */
797 setup_ecc_for_xfer(denali, !raw_xfer, oob_required);
799 /* clear any previous interrupt flags */
800 clear_interrupts(denali);
803 denali_enable_dma(denali, true);
806 denali_setup_dma(denali, ops);
808 /* wait for operation to complete */
809 irq_status = wait_for_irq(denali, irq_mask);
811 /* if ECC fault happen, seems we need delay before turning off DMA.
812 * If not, the controller will go into non responsive condition */
813 if (irq_status & INTR_STATUS__ECC_UNCOR_ERR)
816 /* disable the DMA */
817 denali_enable_dma(denali, false);
822 static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
823 const uint8_t *buf, bool raw_xfer, int oob_required)
825 struct denali_nand_info *denali = mtd_to_denali(mtd);
827 uint32_t irq_status = 0;
828 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;
832 /* copy buffer into DMA buffer */
833 memcpy(denali->buf.dma_buf, buf, mtd->writesize);
835 /* need extra memcpy for raw transfer */
837 memcpy(denali->buf.dma_buf + mtd->writesize,
838 chip->oob_poi, mtd->oobsize);
841 irq_status = denali_dma_configuration(denali, DENALI_WRITE, raw_xfer,
842 irq_mask, oob_required);
844 /* if timeout happen, error out */
845 if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) {
846 debug("DMA timeout for denali write_page\n");
847 denali->status = NAND_STATUS_FAIL;
851 if (irq_status & INTR_STATUS__LOCKED_BLK) {
852 debug("Failed as write to locked block\n");
853 denali->status = NAND_STATUS_FAIL;
859 /* NAND core entry points */
862 * this is the callback that the NAND core calls to write a page. Since
863 * writing a page with ECC or without is similar, all the work is done
864 * by write_page above.
866 static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
867 const uint8_t *buf, int oob_required, int page)
869 struct denali_nand_info *denali = mtd_to_denali(mtd);
872 * for regular page writes, we let HW handle all the ECC
873 * data written to the device.
876 /* switch to main + spare access */
877 denali_mode_main_spare_access(denali);
879 /* switch to main access only */
880 denali_mode_main_access(denali);
882 return write_page(mtd, chip, buf, false, oob_required);
886 * This is the callback that the NAND core calls to write a page without ECC.
887 * raw access is similar to ECC page writes, so all the work is done in the
888 * write_page() function above.
890 static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
891 const uint8_t *buf, int oob_required,
894 struct denali_nand_info *denali = mtd_to_denali(mtd);
897 * for raw page writes, we want to disable ECC and simply write
898 * whatever data is in the buffer.
902 /* switch to main + spare access */
903 denali_mode_main_spare_access(denali);
905 /* switch to main access only */
906 denali_mode_main_access(denali);
908 return write_page(mtd, chip, buf, true, oob_required);
911 static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
914 return write_oob_data(mtd, chip->oob_poi, page);
917 /* raw include ECC value and all the spare area */
918 static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
919 uint8_t *buf, int oob_required, int page)
921 struct denali_nand_info *denali = mtd_to_denali(mtd);
923 uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP;
925 if (denali->page != page) {
926 debug("Missing NAND_CMD_READ0 command\n");
931 /* switch to main + spare access */
932 denali_mode_main_spare_access(denali);
934 /* switch to main access only */
935 denali_mode_main_access(denali);
937 /* setting up the DMA where ecc_enable is false */
938 irq_status = denali_dma_configuration(denali, DENALI_READ, true,
939 irq_mask, oob_required);
941 /* if timeout happen, error out */
942 if (!(irq_status & INTR_STATUS__DMA_CMD_COMP)) {
943 debug("DMA timeout for denali_read_page_raw\n");
947 /* splitting the content to destination buffer holder */
948 memcpy(chip->oob_poi, (denali->buf.dma_buf + mtd->writesize),
950 memcpy(buf, denali->buf.dma_buf, mtd->writesize);
955 static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
956 uint8_t *buf, int oob_required, int page)
958 struct denali_nand_info *denali = mtd_to_denali(mtd);
959 uint32_t irq_status, irq_mask = INTR_STATUS__DMA_CMD_COMP;
961 if (denali->page != page) {
962 debug("Missing NAND_CMD_READ0 command\n");
967 /* switch to main + spare access */
968 denali_mode_main_spare_access(denali);
970 /* switch to main access only */
971 denali_mode_main_access(denali);
973 /* setting up the DMA where ecc_enable is true */
974 irq_status = denali_dma_configuration(denali, DENALI_READ, false,
975 irq_mask, oob_required);
977 memcpy(buf, denali->buf.dma_buf, mtd->writesize);
979 /* check whether any ECC error */
980 if (irq_status & INTR_STATUS__ECC_UNCOR_ERR) {
981 /* is the ECC cause by erase page, check using read_page_raw */
982 debug(" Uncorrected ECC detected\n");
983 denali_read_page_raw(mtd, chip, buf, oob_required,
986 if (is_erased(buf, mtd->writesize) == true &&
987 is_erased(chip->oob_poi, mtd->oobsize) == true) {
988 debug(" ECC error cause by erased block\n");
989 /* false alarm, return the 0xFF */
994 memcpy(buf, denali->buf.dma_buf, mtd->writesize);
998 static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1001 read_oob_data(mtd, chip->oob_poi, page);
1006 static uint8_t denali_read_byte(struct mtd_info *mtd)
1008 struct denali_nand_info *denali = mtd_to_denali(mtd);
1009 uint32_t addr, result;
1011 addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
1012 index_addr_read_data(denali, addr | 2, &result);
1013 return (uint8_t)result & 0xFF;
1016 static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1018 struct denali_nand_info *denali = mtd_to_denali(mtd);
1019 uint32_t i, addr, result;
1021 /* delay for tR (data transfer from Flash array to data register) */
1024 /* ensure device completed else additional delay and polling */
1025 wait_for_irq(denali, INTR_STATUS__INT_ACT);
1027 addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
1028 for (i = 0; i < len; i++) {
1029 index_addr_read_data(denali, (uint32_t)addr | 2, &result);
1030 write_byte_to_buf(denali, result);
1032 memcpy(buf, denali->buf.buf, len);
1035 static void denali_select_chip(struct mtd_info *mtd, int chip)
1037 struct denali_nand_info *denali = mtd_to_denali(mtd);
1039 denali->flash_bank = chip;
1042 static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
1044 struct denali_nand_info *denali = mtd_to_denali(mtd);
1045 int status = denali->status;
1052 static int denali_erase(struct mtd_info *mtd, int page)
1054 struct denali_nand_info *denali = mtd_to_denali(mtd);
1056 uint32_t cmd, irq_status;
1058 clear_interrupts(denali);
1060 /* setup page read request for access type */
1061 cmd = MODE_10 | BANK(denali->flash_bank) | page;
1062 index_addr(denali, cmd, 0x1);
1064 /* wait for erase to complete or failure to occur */
1065 irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP |
1066 INTR_STATUS__ERASE_FAIL);
1068 if (irq_status & INTR_STATUS__ERASE_FAIL ||
1069 irq_status & INTR_STATUS__LOCKED_BLK)
1070 return NAND_STATUS_FAIL;
1075 static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
1078 struct denali_nand_info *denali = mtd_to_denali(mtd);
1082 case NAND_CMD_PAGEPROG:
1084 case NAND_CMD_STATUS:
1085 addr = MODE_11 | BANK(denali->flash_bank);
1086 index_addr(denali, addr | 0, cmd);
1088 case NAND_CMD_READID:
1089 case NAND_CMD_PARAM:
1092 * sometimes ManufactureId read from register is not right
1093 * e.g. some of Micron MT29F32G08QAA MLC NAND chips
1094 * So here we send READID cmd to NAND insteand
1096 addr = MODE_11 | BANK(denali->flash_bank);
1097 index_addr(denali, addr | 0, cmd);
1098 index_addr(denali, addr | 1, col & 0xFF);
1099 if (cmd == NAND_CMD_PARAM)
1102 case NAND_CMD_RNDOUT:
1103 addr = MODE_11 | BANK(denali->flash_bank);
1104 index_addr(denali, addr | 0, cmd);
1105 index_addr(denali, addr | 1, col & 0xFF);
1106 index_addr(denali, addr | 1, col >> 8);
1107 index_addr(denali, addr | 0, NAND_CMD_RNDOUTSTART);
1109 case NAND_CMD_READ0:
1110 case NAND_CMD_SEQIN:
1111 denali->page = page;
1113 case NAND_CMD_RESET:
1116 case NAND_CMD_READOOB:
1117 /* TODO: Read OOB data */
1119 case NAND_CMD_ERASE1:
1121 * supporting block erase only, not multiblock erase as
1122 * it will cross plane and software need complex calculation
1123 * to identify the block count for the cross plane
1125 denali_erase(mtd, page);
1127 case NAND_CMD_ERASE2:
1128 /* nothing to do here as it was done during NAND_CMD_ERASE1 */
1130 case NAND_CMD_UNLOCK1:
1131 addr = MODE_10 | BANK(denali->flash_bank) | page;
1132 index_addr(denali, addr | 0, DENALI_UNLOCK_START);
1134 case NAND_CMD_UNLOCK2:
1135 addr = MODE_10 | BANK(denali->flash_bank) | page;
1136 index_addr(denali, addr | 0, DENALI_UNLOCK_END);
1139 addr = MODE_10 | BANK(denali->flash_bank);
1140 index_addr(denali, addr | 0, DENALI_LOCK);
1143 printf(": unsupported command received 0x%x\n", cmd);
1147 /* end NAND core entry points */
1149 /* Initialization code to bring the device up to a known good state */
1150 static void denali_hw_init(struct denali_nand_info *denali)
1153 * The REVISION register may not be reliable. Platforms are allowed to
1156 if (!denali->revision)
1157 denali->revision = swab16(ioread32(denali->flash_reg + REVISION));
1160 * tell driver how many bit controller will skip before writing
1161 * ECC code in OOB. This is normally used for bad block marker
1163 writel(CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES,
1164 denali->flash_reg + SPARE_AREA_SKIP_BYTES);
1165 detect_max_banks(denali);
1166 denali_nand_reset(denali);
1167 writel(0x0F, denali->flash_reg + RB_PIN_ENABLED);
1168 writel(CHIP_EN_DONT_CARE__FLAG,
1169 denali->flash_reg + CHIP_ENABLE_DONT_CARE);
1170 writel(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
1172 /* Should set value for these registers when init */
1173 writel(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
1174 writel(1, denali->flash_reg + ECC_ENABLE);
1175 denali_nand_timing_set(denali);
1176 denali_irq_init(denali);
1179 static struct nand_ecclayout nand_oob;
1181 int denali_init(struct denali_nand_info *denali)
1183 struct mtd_info *mtd = nand_to_mtd(&denali->nand);
1186 denali_hw_init(denali);
1188 mtd->name = "denali-nand";
1189 mtd->owner = THIS_MODULE;
1191 /* register the driver with the NAND core subsystem */
1192 denali->nand.select_chip = denali_select_chip;
1193 denali->nand.cmdfunc = denali_cmdfunc;
1194 denali->nand.read_byte = denali_read_byte;
1195 denali->nand.read_buf = denali_read_buf;
1196 denali->nand.waitfunc = denali_waitfunc;
1199 * scan for NAND devices attached to the controller
1200 * this is the first stage in a two step process to register
1201 * with the nand subsystem
1203 if (nand_scan_ident(mtd, denali->max_banks, NULL)) {
1208 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1209 /* check whether flash got BBT table (located at end of flash). As we
1210 * use NAND_BBT_NO_OOB, the BBT page will start with
1211 * bbt_pattern. We will have mirror pattern too */
1212 denali->nand.bbt_options |= NAND_BBT_USE_FLASH;
1214 * We are using main + spare with ECC support. As BBT need ECC support,
1215 * we need to ensure BBT code don't write to OOB for the BBT pattern.
1216 * All BBT info will be stored into data area with ECC support.
1218 denali->nand.bbt_options |= NAND_BBT_NO_OOB;
1221 denali->nand.ecc.mode = NAND_ECC_HW;
1222 denali->nand.ecc.size = CONFIG_NAND_DENALI_ECC_SIZE;
1224 /* no subpage writes on denali */
1225 denali->nand.options |= NAND_NO_SUBPAGE_WRITE;
1228 * Tell driver the ecc strength. This register may be already set
1229 * correctly. So we read this value out.
1231 denali->nand.ecc.strength = readl(denali->flash_reg + ECC_CORRECTION);
1232 switch (denali->nand.ecc.size) {
1234 denali->nand.ecc.bytes =
1235 (denali->nand.ecc.strength * 13 + 15) / 16 * 2;
1238 denali->nand.ecc.bytes =
1239 (denali->nand.ecc.strength * 14 + 15) / 16 * 2;
1242 pr_err("Unsupported ECC size\n");
1246 nand_oob.eccbytes = denali->nand.ecc.bytes;
1247 denali->nand.ecc.layout = &nand_oob;
1249 writel(mtd->erasesize / mtd->writesize,
1250 denali->flash_reg + PAGES_PER_BLOCK);
1251 writel(denali->nand.options & NAND_BUSWIDTH_16 ? 1 : 0,
1252 denali->flash_reg + DEVICE_WIDTH);
1253 writel(mtd->writesize,
1254 denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
1255 writel(mtd->oobsize,
1256 denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
1257 if (readl(denali->flash_reg + DEVICES_CONNECTED) == 0)
1258 writel(1, denali->flash_reg + DEVICES_CONNECTED);
1260 /* override the default operations */
1261 denali->nand.ecc.read_page = denali_read_page;
1262 denali->nand.ecc.read_page_raw = denali_read_page_raw;
1263 denali->nand.ecc.write_page = denali_write_page;
1264 denali->nand.ecc.write_page_raw = denali_write_page_raw;
1265 denali->nand.ecc.read_oob = denali_read_oob;
1266 denali->nand.ecc.write_oob = denali_write_oob;
1268 if (nand_scan_tail(mtd)) {
1273 ret = nand_register(0, mtd);
1279 #ifndef CONFIG_NAND_DENALI_DT
1280 static int __board_nand_init(void)
1282 struct denali_nand_info *denali;
1284 denali = kzalloc(sizeof(*denali), GFP_KERNEL);
1289 * In the future, these base addresses should be taken from
1290 * Device Tree or platform data.
1292 denali->flash_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
1293 denali->flash_mem = (void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
1295 return denali_init(denali);
1298 void board_nand_init(void)
1300 if (__board_nand_init() < 0)
1301 pr_warn("Failed to initialize Denali NAND controller.\n");