1 // SPDX-License-Identifier: GPL-2.0+
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10 #include <asm/arch/soc.h>
11 #include <asm/arch/mpp.h>
14 /* NAND Flash Soc registers */
15 struct kwnandf_registers {
16 u32 rd_params; /* 0x10418 */
17 u32 wr_param; /* 0x1041c */
18 u8 pad[0x10470 - 0x1041c - 4];
19 u32 ctrl; /* 0x10470 */
22 static struct kwnandf_registers *nf_reg =
23 (struct kwnandf_registers *)KW_NANDF_BASE;
25 static u32 nand_mpp_backup[9] = { 0 };
28 * hardware specific access to control-lines/bits
30 #define NAND_ACTCEBOOT_BIT 0x02
32 static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd,
35 struct nand_chip *nc = mtd_to_nand(mtd);
38 if (cmd == NAND_CMD_NONE)
42 offs = (1 << 0); /* Commands with A[1:0] == 01 */
43 else if (ctrl & NAND_ALE)
44 offs = (1 << 1); /* Addresses with A[1:0] == 10 */
48 writeb(cmd, nc->IO_ADDR_W + offs);
51 void kw_nand_select_chip(struct mtd_info *mtd, int chip)
54 static const u32 nand_config[] = {
67 kirkwood_mpp_conf(nand_config, nand_mpp_backup);
69 kirkwood_mpp_conf(nand_mpp_backup, NULL);
71 data = readl(&nf_reg->ctrl);
72 data |= NAND_ACTCEBOOT_BIT;
73 writel(data, &nf_reg->ctrl);
76 int board_nand_init(struct nand_chip *nand)
78 nand->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING;
79 #if defined(CONFIG_SYS_NAND_NO_SUBPAGE_WRITE)
80 nand->options |= NAND_NO_SUBPAGE_WRITE;
82 #if defined(CONFIG_NAND_ECC_BCH)
83 nand->ecc.mode = NAND_ECC_SOFT_BCH;
85 nand->ecc.mode = NAND_ECC_SOFT;
87 nand->cmd_ctrl = kw_nand_hwcontrol;
88 nand->chip_delay = 40;
89 nand->select_chip = kw_nand_select_chip;