git.sur5r.net Git - u-boot/blob - drivers/mtd/nand/mxc_nand.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc.
   3  * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
   4  * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <nand.h>
  11 #include <linux/err.h>
  12 #include <asm/io.h>
  13 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
  14         defined(CONFIG_MX51) || defined(CONFIG_MX53)
  15 #include <asm/arch/imx-regs.h>
  16 #endif
  17 #include "mxc_nand.h"
  18
  19 #define DRIVER_NAME "mxc_nand"
  20
  21 struct mxc_nand_host {
  22         struct nand_chip                *nand;
  23
  24         struct mxc_nand_regs __iomem    *regs;
  25 #ifdef MXC_NFC_V3_2
  26         struct mxc_nand_ip_regs __iomem *ip_regs;
  27 #endif
  28         int                             spare_only;
  29         int                             status_request;
  30         int                             pagesize_2k;
  31         int                             clk_act;
  32         uint16_t                        col_addr;
  33         unsigned int                    page_addr;
  34 };
  35
  36 static struct mxc_nand_host mxc_host;
  37 static struct mxc_nand_host *host = &mxc_host;
  38
  39 /* Define delays in microsec for NAND device operations */
  40 #define TROP_US_DELAY   2000
  41 /* Macros to get byte and bit positions of ECC */
  42 #define COLPOS(x)  ((x) >> 3)
  43 #define BITPOS(x) ((x) & 0xf)
  44
  45 /* Define single bit Error positions in Main & Spare area */
  46 #define MAIN_SINGLEBIT_ERROR 0x4
  47 #define SPARE_SINGLEBIT_ERROR 0x1
  48
  49 /* OOB placement block for use with hardware ecc generation */
  50 #if defined(MXC_NFC_V1)
  51 #ifndef CONFIG_SYS_NAND_LARGEPAGE
  52 static struct nand_ecclayout nand_hw_eccoob = {
  53         .eccbytes = 5,
  54         .eccpos = {6, 7, 8, 9, 10},
  55         .oobfree = { {0, 5}, {11, 5}, }
  56 };
  57 #else
  58 static struct nand_ecclayout nand_hw_eccoob2k = {
  59         .eccbytes = 20,
  60         .eccpos = {
  61                 6, 7, 8, 9, 10,
  62                 22, 23, 24, 25, 26,
  63                 38, 39, 40, 41, 42,
  64                 54, 55, 56, 57, 58,
  65         },
  66         .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
  67 };
  68 #endif
  69 #elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
  70 #ifndef CONFIG_SYS_NAND_LARGEPAGE
  71 static struct nand_ecclayout nand_hw_eccoob = {
  72         .eccbytes = 9,
  73         .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
  74         .oobfree = { {2, 5} }
  75 };
  76 #else
  77 static struct nand_ecclayout nand_hw_eccoob2k = {
  78         .eccbytes = 36,
  79         .eccpos = {
  80                 7, 8, 9, 10, 11, 12, 13, 14, 15,
  81                 23, 24, 25, 26, 27, 28, 29, 30, 31,
  82                 39, 40, 41, 42, 43, 44, 45, 46, 47,
  83                 55, 56, 57, 58, 59, 60, 61, 62, 63,
  84         },
  85         .oobfree = { {2, 5}, {16, 7}, {32, 7}, {48, 7} },
  86 };
  87 #endif
  88 #endif
  89
  90 static int is_16bit_nand(void)
  91 {
  92 #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
  93         return 1;
  94 #else
  95         return 0;
  96 #endif
  97 }
  98
  99 static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
 100 {
 101         uint32_t *d = dest;
 102
 103         size >>= 2;
 104         while (size--)
 105                 __raw_writel(__raw_readl(source++), d++);
 106         return dest;
 107 }
 108
 109 /*
 110  * This function polls the NANDFC to wait for the basic operation to
 111  * complete by checking the INT bit.
 112  */
 113 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
 114                                 uint16_t param)
 115 {
 116         uint32_t tmp;
 117
 118         while (max_retries-- > 0) {
 119 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 120                 tmp = readnfc(&host->regs->config2);
 121                 if (tmp & NFC_V1_V2_CONFIG2_INT) {
 122                         tmp &= ~NFC_V1_V2_CONFIG2_INT;
 123                         writenfc(tmp, &host->regs->config2);
 124 #elif defined(MXC_NFC_V3_2)
 125                 tmp = readnfc(&host->ip_regs->ipc);
 126                 if (tmp & NFC_V3_IPC_INT) {
 127                         tmp &= ~NFC_V3_IPC_INT;
 128                         writenfc(tmp, &host->ip_regs->ipc);
 129 #endif
 130                         break;
 131                 }
 132                 udelay(1);
 133         }
 134         if (max_retries < 0) {
 135                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
 136                                 __func__, param);
 137         }
 138 }
 139
 140 /*
 141  * This function issues the specified command to the NAND device and
 142  * waits for completion.
 143  */
 144 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
 145 {
 146         MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
 147
 148         writenfc(cmd, &host->regs->flash_cmd);
 149         writenfc(NFC_CMD, &host->regs->operation);
 150
 151         /* Wait for operation to complete */
 152         wait_op_done(host, TROP_US_DELAY, cmd);
 153 }
 154
 155 /*
 156  * This function sends an address (or partial address) to the
 157  * NAND device. The address is used to select the source/destination for
 158  * a NAND command.
 159  */
 160 static void send_addr(struct mxc_nand_host *host, uint16_t addr)
 161 {
 162         MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
 163
 164         writenfc(addr, &host->regs->flash_addr);
 165         writenfc(NFC_ADDR, &host->regs->operation);
 166
 167         /* Wait for operation to complete */
 168         wait_op_done(host, TROP_US_DELAY, addr);
 169 }
 170
 171 /*
 172  * This function requests the NANDFC to initiate the transfer
 173  * of data currently in the NANDFC RAM buffer to the NAND device.
 174  */
 175 static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
 176                         int spare_only)
 177 {
 178         if (spare_only)
 179                 MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only);
 180
 181         if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
 182                 int i;
 183                 /*
 184                  *  The controller copies the 64 bytes of spare data from
 185                  *  the first 16 bytes of each of the 4 64 byte spare buffers.
 186                  *  Copy the contiguous data starting in spare_area[0] to
 187                  *  the four spare area buffers.
 188                  */
 189                 for (i = 1; i < 4; i++) {
 190                         void __iomem *src = &host->regs->spare_area[0][i * 16];
 191                         void __iomem *dst = &host->regs->spare_area[i][0];
 192
 193                         mxc_nand_memcpy32(dst, src, 16);
 194                 }
 195         }
 196
 197 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 198         writenfc(buf_id, &host->regs->buf_addr);
 199 #elif defined(MXC_NFC_V3_2)
 200         uint32_t tmp = readnfc(&host->regs->config1);
 201         tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
 202         tmp |= NFC_V3_CONFIG1_RBA(buf_id);
 203         writenfc(tmp, &host->regs->config1);
 204 #endif
 205
 206         /* Configure spare or page+spare access */
 207         if (!host->pagesize_2k) {
 208                 uint32_t config1 = readnfc(&host->regs->config1);
 209                 if (spare_only)
 210                         config1 |= NFC_CONFIG1_SP_EN;
 211                 else
 212                         config1 &= ~NFC_CONFIG1_SP_EN;
 213                 writenfc(config1, &host->regs->config1);
 214         }
 215
 216         writenfc(NFC_INPUT, &host->regs->operation);
 217
 218         /* Wait for operation to complete */
 219         wait_op_done(host, TROP_US_DELAY, spare_only);
 220 }
 221
 222 /*
 223  * Requests NANDFC to initiate the transfer of data from the
 224  * NAND device into in the NANDFC ram buffer.
 225  */
 226 static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
 227                 int spare_only)
 228 {
 229         MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
 230
 231 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 232         writenfc(buf_id, &host->regs->buf_addr);
 233 #elif defined(MXC_NFC_V3_2)
 234         uint32_t tmp = readnfc(&host->regs->config1);
 235         tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
 236         tmp |= NFC_V3_CONFIG1_RBA(buf_id);
 237         writenfc(tmp, &host->regs->config1);
 238 #endif
 239
 240         /* Configure spare or page+spare access */
 241         if (!host->pagesize_2k) {
 242                 uint32_t config1 = readnfc(&host->regs->config1);
 243                 if (spare_only)
 244                         config1 |= NFC_CONFIG1_SP_EN;
 245                 else
 246                         config1 &= ~NFC_CONFIG1_SP_EN;
 247                 writenfc(config1, &host->regs->config1);
 248         }
 249
 250         writenfc(NFC_OUTPUT, &host->regs->operation);
 251
 252         /* Wait for operation to complete */
 253         wait_op_done(host, TROP_US_DELAY, spare_only);
 254
 255         if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
 256                 int i;
 257
 258                 /*
 259                  *  The controller copies the 64 bytes of spare data to
 260                  *  the first 16 bytes of each of the 4 spare buffers.
 261                  *  Make the data contiguous starting in spare_area[0].
 262                  */
 263                 for (i = 1; i < 4; i++) {
 264                         void __iomem *src = &host->regs->spare_area[i][0];
 265                         void __iomem *dst = &host->regs->spare_area[0][i * 16];
 266
 267                         mxc_nand_memcpy32(dst, src, 16);
 268                 }
 269         }
 270 }
 271
 272 /* Request the NANDFC to perform a read of the NAND device ID. */
 273 static void send_read_id(struct mxc_nand_host *host)
 274 {
 275         uint32_t tmp;
 276
 277 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 278         /* NANDFC buffer 0 is used for device ID output */
 279         writenfc(0x0, &host->regs->buf_addr);
 280 #elif defined(MXC_NFC_V3_2)
 281         tmp = readnfc(&host->regs->config1);
 282         tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
 283         writenfc(tmp, &host->regs->config1);
 284 #endif
 285
 286         /* Read ID into main buffer */
 287         tmp = readnfc(&host->regs->config1);
 288         tmp &= ~NFC_CONFIG1_SP_EN;
 289         writenfc(tmp, &host->regs->config1);
 290
 291         writenfc(NFC_ID, &host->regs->operation);
 292
 293         /* Wait for operation to complete */
 294         wait_op_done(host, TROP_US_DELAY, 0);
 295 }
 296
 297 /*
 298  * This function requests the NANDFC to perform a read of the
 299  * NAND device status and returns the current status.
 300  */
 301 static uint16_t get_dev_status(struct mxc_nand_host *host)
 302 {
 303 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 304         void __iomem *main_buf = host->regs->main_area[1];
 305         uint32_t store;
 306 #endif
 307         uint32_t ret, tmp;
 308         /* Issue status request to NAND device */
 309
 310 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 311         /* store the main area1 first word, later do recovery */
 312         store = readl(main_buf);
 313         /* NANDFC buffer 1 is used for device status */
 314         writenfc(1, &host->regs->buf_addr);
 315 #endif
 316
 317         /* Read status into main buffer */
 318         tmp = readnfc(&host->regs->config1);
 319         tmp &= ~NFC_CONFIG1_SP_EN;
 320         writenfc(tmp, &host->regs->config1);
 321
 322         writenfc(NFC_STATUS, &host->regs->operation);
 323
 324         /* Wait for operation to complete */
 325         wait_op_done(host, TROP_US_DELAY, 0);
 326
 327 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 328         /*
 329          *  Status is placed in first word of main buffer
 330          * get status, then recovery area 1 data
 331          */
 332         ret = readw(main_buf);
 333         writel(store, main_buf);
 334 #elif defined(MXC_NFC_V3_2)
 335         ret = readnfc(&host->regs->config1) >> 16;
 336 #endif
 337
 338         return ret;
 339 }
 340
 341 /* This function is used by upper layer to checks if device is ready */
 342 static int mxc_nand_dev_ready(struct mtd_info *mtd)
 343 {
 344         /*
 345          * NFC handles R/B internally. Therefore, this function
 346          * always returns status as ready.
 347          */
 348         return 1;
 349 }
 350
 351 static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
 352 {
 353         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 354         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 355 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 356         uint16_t tmp = readnfc(&host->regs->config1);
 357
 358         if (on)
 359                 tmp |= NFC_V1_V2_CONFIG1_ECC_EN;
 360         else
 361                 tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN;
 362         writenfc(tmp, &host->regs->config1);
 363 #elif defined(MXC_NFC_V3_2)
 364         uint32_t tmp = readnfc(&host->ip_regs->config2);
 365
 366         if (on)
 367                 tmp |= NFC_V3_CONFIG2_ECC_EN;
 368         else
 369                 tmp &= ~NFC_V3_CONFIG2_ECC_EN;
 370         writenfc(tmp, &host->ip_regs->config2);
 371 #endif
 372 }
 373
 374 #ifdef CONFIG_MXC_NAND_HWECC
 375 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 376 {
 377         /*
 378          * If HW ECC is enabled, we turn it on during init. There is
 379          * no need to enable again here.
 380          */
 381 }
 382
 383 #if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
 384 static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
 385                                       struct nand_chip *chip,
 386                                       int page)
 387 {
 388         struct mxc_nand_host *host = nand_get_controller_data(chip);
 389         uint8_t *buf = chip->oob_poi;
 390         int length = mtd->oobsize;
 391         int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
 392         uint8_t *bufpoi = buf;
 393         int i, toread;
 394
 395         MTDDEBUG(MTD_DEBUG_LEVEL0,
 396                         "%s: Reading OOB area of page %u to oob %p\n",
 397                          __func__, page, buf);
 398
 399         chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
 400         for (i = 0; i < chip->ecc.steps; i++) {
 401                 toread = min_t(int, length, chip->ecc.prepad);
 402                 if (toread) {
 403                         chip->read_buf(mtd, bufpoi, toread);
 404                         bufpoi += toread;
 405                         length -= toread;
 406                 }
 407                 bufpoi += chip->ecc.bytes;
 408                 host->col_addr += chip->ecc.bytes;
 409                 length -= chip->ecc.bytes;
 410
 411                 toread = min_t(int, length, chip->ecc.postpad);
 412                 if (toread) {
 413                         chip->read_buf(mtd, bufpoi, toread);
 414                         bufpoi += toread;
 415                         length -= toread;
 416                 }
 417         }
 418         if (length > 0)
 419                 chip->read_buf(mtd, bufpoi, length);
 420
 421         _mxc_nand_enable_hwecc(mtd, 0);
 422         chip->cmdfunc(mtd, NAND_CMD_READOOB,
 423                         mtd->writesize + chip->ecc.prepad, page);
 424         bufpoi = buf + chip->ecc.prepad;
 425         length = mtd->oobsize - chip->ecc.prepad;
 426         for (i = 0; i < chip->ecc.steps; i++) {
 427                 toread = min_t(int, length, chip->ecc.bytes);
 428                 chip->read_buf(mtd, bufpoi, toread);
 429                 bufpoi += eccpitch;
 430                 length -= eccpitch;
 431                 host->col_addr += chip->ecc.postpad + chip->ecc.prepad;
 432         }
 433         _mxc_nand_enable_hwecc(mtd, 1);
 434         return 1;
 435 }
 436
 437 static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
 438                                            struct nand_chip *chip,
 439                                            uint8_t *buf,
 440                                            int oob_required,
 441                                            int page)
 442 {
 443         struct mxc_nand_host *host = nand_get_controller_data(chip);
 444         int eccsize = chip->ecc.size;
 445         int eccbytes = chip->ecc.bytes;
 446         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 447         uint8_t *oob = chip->oob_poi;
 448         int steps, size;
 449         int n;
 450
 451         _mxc_nand_enable_hwecc(mtd, 0);
 452         chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
 453
 454         for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
 455                 host->col_addr = n * eccsize;
 456                 chip->read_buf(mtd, buf, eccsize);
 457                 buf += eccsize;
 458
 459                 host->col_addr = mtd->writesize + n * eccpitch;
 460                 if (chip->ecc.prepad) {
 461                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 462                         oob += chip->ecc.prepad;
 463                 }
 464
 465                 chip->read_buf(mtd, oob, eccbytes);
 466                 oob += eccbytes;
 467
 468                 if (chip->ecc.postpad) {
 469                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 470                         oob += chip->ecc.postpad;
 471                 }
 472         }
 473
 474         size = mtd->oobsize - (oob - chip->oob_poi);
 475         if (size)
 476                 chip->read_buf(mtd, oob, size);
 477         _mxc_nand_enable_hwecc(mtd, 1);
 478
 479         return 0;
 480 }
 481
 482 static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
 483                                        struct nand_chip *chip,
 484                                        uint8_t *buf,
 485                                        int oob_required,
 486                                        int page)
 487 {
 488         struct mxc_nand_host *host = nand_get_controller_data(chip);
 489         int n, eccsize = chip->ecc.size;
 490         int eccbytes = chip->ecc.bytes;
 491         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 492         int eccsteps = chip->ecc.steps;
 493         uint8_t *p = buf;
 494         uint8_t *oob = chip->oob_poi;
 495
 496         MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n",
 497               page, buf, oob);
 498
 499         /* first read the data area and the available portion of OOB */
 500         for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
 501                 int stat;
 502
 503                 host->col_addr = n * eccsize;
 504
 505                 chip->read_buf(mtd, p, eccsize);
 506
 507                 host->col_addr = mtd->writesize + n * eccpitch;
 508
 509                 if (chip->ecc.prepad) {
 510                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 511                         oob += chip->ecc.prepad;
 512                 }
 513
 514                 stat = chip->ecc.correct(mtd, p, oob, NULL);
 515
 516                 if (stat < 0)
 517                         mtd->ecc_stats.failed++;
 518                 else
 519                         mtd->ecc_stats.corrected += stat;
 520                 oob += eccbytes;
 521
 522                 if (chip->ecc.postpad) {
 523                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 524                         oob += chip->ecc.postpad;
 525                 }
 526         }
 527
 528         /* Calculate remaining oob bytes */
 529         n = mtd->oobsize - (oob - chip->oob_poi);
 530         if (n)
 531                 chip->read_buf(mtd, oob, n);
 532
 533         /* Then switch ECC off and read the OOB area to get the ECC code */
 534         _mxc_nand_enable_hwecc(mtd, 0);
 535         chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
 536         eccsteps = chip->ecc.steps;
 537         oob = chip->oob_poi + chip->ecc.prepad;
 538         for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
 539                 host->col_addr = mtd->writesize +
 540                                  n * eccpitch +
 541                                  chip->ecc.prepad;
 542                 chip->read_buf(mtd, oob, eccbytes);
 543                 oob += eccbytes + chip->ecc.postpad;
 544         }
 545         _mxc_nand_enable_hwecc(mtd, 1);
 546         return 0;
 547 }
 548
 549 static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
 550                                        struct nand_chip *chip, int page)
 551 {
 552         struct mxc_nand_host *host = nand_get_controller_data(chip);
 553         int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
 554         int length = mtd->oobsize;
 555         int i, len, status, steps = chip->ecc.steps;
 556         const uint8_t *bufpoi = chip->oob_poi;
 557
 558         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 559         for (i = 0; i < steps; i++) {
 560                 len = min_t(int, length, eccpitch);
 561
 562                 chip->write_buf(mtd, bufpoi, len);
 563                 bufpoi += len;
 564                 length -= len;
 565                 host->col_addr += chip->ecc.prepad + chip->ecc.postpad;
 566         }
 567         if (length > 0)
 568                 chip->write_buf(mtd, bufpoi, length);
 569
 570         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 571         status = chip->waitfunc(mtd, chip);
 572         return status & NAND_STATUS_FAIL ? -EIO : 0;
 573 }
 574
 575 static int mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
 576                                              struct nand_chip *chip,
 577                                              const uint8_t *buf,
 578                                              int oob_required, int page)
 579 {
 580         struct mxc_nand_host *host = nand_get_controller_data(chip);
 581         int eccsize = chip->ecc.size;
 582         int eccbytes = chip->ecc.bytes;
 583         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 584         uint8_t *oob = chip->oob_poi;
 585         int steps, size;
 586         int n;
 587
 588         for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
 589                 host->col_addr = n * eccsize;
 590                 chip->write_buf(mtd, buf, eccsize);
 591                 buf += eccsize;
 592
 593                 host->col_addr = mtd->writesize + n * eccpitch;
 594
 595                 if (chip->ecc.prepad) {
 596                         chip->write_buf(mtd, oob, chip->ecc.prepad);
 597                         oob += chip->ecc.prepad;
 598                 }
 599
 600                 host->col_addr += eccbytes;
 601                 oob += eccbytes;
 602
 603                 if (chip->ecc.postpad) {
 604                         chip->write_buf(mtd, oob, chip->ecc.postpad);
 605                         oob += chip->ecc.postpad;
 606                 }
 607         }
 608
 609         size = mtd->oobsize - (oob - chip->oob_poi);
 610         if (size)
 611                 chip->write_buf(mtd, oob, size);
 612         return 0;
 613 }
 614
 615 static int mxc_nand_write_page_syndrome(struct mtd_info *mtd,
 616                                          struct nand_chip *chip,
 617                                          const uint8_t *buf,
 618                                          int oob_required, int page)
 619 {
 620         struct mxc_nand_host *host = nand_get_controller_data(chip);
 621         int i, n, eccsize = chip->ecc.size;
 622         int eccbytes = chip->ecc.bytes;
 623         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 624         int eccsteps = chip->ecc.steps;
 625         const uint8_t *p = buf;
 626         uint8_t *oob = chip->oob_poi;
 627
 628         chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
 629
 630         for (i = n = 0;
 631              eccsteps;
 632              n++, eccsteps--, i += eccbytes, p += eccsize) {
 633                 host->col_addr = n * eccsize;
 634
 635                 chip->write_buf(mtd, p, eccsize);
 636
 637                 host->col_addr = mtd->writesize + n * eccpitch;
 638
 639                 if (chip->ecc.prepad) {
 640                         chip->write_buf(mtd, oob, chip->ecc.prepad);
 641                         oob += chip->ecc.prepad;
 642                 }
 643
 644                 chip->write_buf(mtd, oob, eccbytes);
 645                 oob += eccbytes;
 646
 647                 if (chip->ecc.postpad) {
 648                         chip->write_buf(mtd, oob, chip->ecc.postpad);
 649                         oob += chip->ecc.postpad;
 650                 }
 651         }
 652
 653         /* Calculate remaining oob bytes */
 654         i = mtd->oobsize - (oob - chip->oob_poi);
 655         if (i)
 656                 chip->write_buf(mtd, oob, i);
 657         return 0;
 658 }
 659
 660 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 661                                  u_char *read_ecc, u_char *calc_ecc)
 662 {
 663         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 664         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 665         uint32_t ecc_status = readl(&host->regs->ecc_status_result);
 666         int subpages = mtd->writesize / nand_chip->subpagesize;
 667         int pg2blk_shift = nand_chip->phys_erase_shift -
 668                            nand_chip->page_shift;
 669
 670         do {
 671                 if ((ecc_status & 0xf) > 4) {
 672                         static int last_bad = -1;
 673
 674                         if (last_bad != host->page_addr >> pg2blk_shift) {
 675                                 last_bad = host->page_addr >> pg2blk_shift;
 676                                 printk(KERN_DEBUG
 677                                        "MXC_NAND: HWECC uncorrectable ECC error"
 678                                        " in block %u page %u subpage %d\n",
 679                                        last_bad, host->page_addr,
 680                                        mtd->writesize / nand_chip->subpagesize
 681                                             - subpages);
 682                         }
 683                         return -EBADMSG;
 684                 }
 685                 ecc_status >>= 4;
 686                 subpages--;
 687         } while (subpages > 0);
 688
 689         return 0;
 690 }
 691 #else
 692 #define mxc_nand_read_page_syndrome NULL
 693 #define mxc_nand_read_page_raw_syndrome NULL
 694 #define mxc_nand_read_oob_syndrome NULL
 695 #define mxc_nand_write_page_syndrome NULL
 696 #define mxc_nand_write_page_raw_syndrome NULL
 697 #define mxc_nand_write_oob_syndrome NULL
 698
 699 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 700                                  u_char *read_ecc, u_char *calc_ecc)
 701 {
 702         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 703         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 704
 705         /*
 706          * 1-Bit errors are automatically corrected in HW.  No need for
 707          * additional correction.  2-Bit errors cannot be corrected by
 708          * HW ECC, so we need to return failure
 709          */
 710         uint16_t ecc_status = readnfc(&host->regs->ecc_status_result);
 711
 712         if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
 713                 MTDDEBUG(MTD_DEBUG_LEVEL0,
 714                       "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
 715                 return -EBADMSG;
 716         }
 717
 718         return 0;
 719 }
 720 #endif
 721
 722 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 723                                   u_char *ecc_code)
 724 {
 725         return 0;
 726 }
 727 #endif
 728
 729 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 730 {
 731         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 732         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 733         uint8_t ret = 0;
 734         uint16_t col;
 735         uint16_t __iomem *main_buf =
 736                 (uint16_t __iomem *)host->regs->main_area[0];
 737         uint16_t __iomem *spare_buf =
 738                 (uint16_t __iomem *)host->regs->spare_area[0];
 739         union {
 740                 uint16_t word;
 741                 uint8_t bytes[2];
 742         } nfc_word;
 743
 744         /* Check for status request */
 745         if (host->status_request)
 746                 return get_dev_status(host) & 0xFF;
 747
 748         /* Get column for 16-bit access */
 749         col = host->col_addr >> 1;
 750
 751         /* If we are accessing the spare region */
 752         if (host->spare_only)
 753                 nfc_word.word = readw(&spare_buf[col]);
 754         else
 755                 nfc_word.word = readw(&main_buf[col]);
 756
 757         /* Pick upper/lower byte of word from RAM buffer */
 758         ret = nfc_word.bytes[host->col_addr & 0x1];
 759
 760         /* Update saved column address */
 761         if (nand_chip->options & NAND_BUSWIDTH_16)
 762                 host->col_addr += 2;
 763         else
 764                 host->col_addr++;
 765
 766         return ret;
 767 }
 768
 769 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
 770 {
 771         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 772         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 773         uint16_t col, ret;
 774         uint16_t __iomem *p;
 775
 776         MTDDEBUG(MTD_DEBUG_LEVEL3,
 777               "mxc_nand_read_word(col = %d)\n", host->col_addr);
 778
 779         col = host->col_addr;
 780         /* Adjust saved column address */
 781         if (col < mtd->writesize && host->spare_only)
 782                 col += mtd->writesize;
 783
 784         if (col < mtd->writesize) {
 785                 p = (uint16_t __iomem *)(host->regs->main_area[0] +
 786                                 (col >> 1));
 787         } else {
 788                 p = (uint16_t __iomem *)(host->regs->spare_area[0] +
 789                                 ((col - mtd->writesize) >> 1));
 790         }
 791
 792         if (col & 1) {
 793                 union {
 794                         uint16_t word;
 795                         uint8_t bytes[2];
 796                 } nfc_word[3];
 797
 798                 nfc_word[0].word = readw(p);
 799                 nfc_word[1].word = readw(p + 1);
 800
 801                 nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
 802                 nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
 803
 804                 ret = nfc_word[2].word;
 805         } else {
 806                 ret = readw(p);
 807         }
 808
 809         /* Update saved column address */
 810         host->col_addr = col + 2;
 811
 812         return ret;
 813 }
 814
 815 /*
 816  * Write data of length len to buffer buf. The data to be
 817  * written on NAND Flash is first copied to RAMbuffer. After the Data Input
 818  * Operation by the NFC, the data is written to NAND Flash
 819  */
 820 static void mxc_nand_write_buf(struct mtd_info *mtd,
 821                                 const u_char *buf, int len)
 822 {
 823         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 824         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 825         int n, col, i = 0;
 826
 827         MTDDEBUG(MTD_DEBUG_LEVEL3,
 828               "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
 829               len);
 830
 831         col = host->col_addr;
 832
 833         /* Adjust saved column address */
 834         if (col < mtd->writesize && host->spare_only)
 835                 col += mtd->writesize;
 836
 837         n = mtd->writesize + mtd->oobsize - col;
 838         n = min(len, n);
 839
 840         MTDDEBUG(MTD_DEBUG_LEVEL3,
 841               "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
 842
 843         while (n > 0) {
 844                 void __iomem *p;
 845
 846                 if (col < mtd->writesize) {
 847                         p = host->regs->main_area[0] + (col & ~3);
 848                 } else {
 849                         p = host->regs->spare_area[0] -
 850                                                 mtd->writesize + (col & ~3);
 851                 }
 852
 853                 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
 854                       __LINE__, p);
 855
 856                 if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
 857                         union {
 858                                 uint32_t word;
 859                                 uint8_t bytes[4];
 860                         } nfc_word;
 861
 862                         nfc_word.word = readl(p);
 863                         nfc_word.bytes[col & 3] = buf[i++];
 864                         n--;
 865                         col++;
 866
 867                         writel(nfc_word.word, p);
 868                 } else {
 869                         int m = mtd->writesize - col;
 870
 871                         if (col >= mtd->writesize)
 872                                 m += mtd->oobsize;
 873
 874                         m = min(n, m) & ~3;
 875
 876                         MTDDEBUG(MTD_DEBUG_LEVEL3,
 877                               "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
 878                               __func__,  __LINE__, n, m, i, col);
 879
 880                         mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
 881                         col += m;
 882                         i += m;
 883                         n -= m;
 884                 }
 885         }
 886         /* Update saved column address */
 887         host->col_addr = col;
 888 }
 889
 890 /*
 891  * Read the data buffer from the NAND Flash. To read the data from NAND
 892  * Flash first the data output cycle is initiated by the NFC, which copies
 893  * the data to RAMbuffer. This data of length len is then copied to buffer buf.
 894  */
 895 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 896 {
 897         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 898         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 899         int n, col, i = 0;
 900
 901         MTDDEBUG(MTD_DEBUG_LEVEL3,
 902               "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
 903
 904         col = host->col_addr;
 905
 906         /* Adjust saved column address */
 907         if (col < mtd->writesize && host->spare_only)
 908                 col += mtd->writesize;
 909
 910         n = mtd->writesize + mtd->oobsize - col;
 911         n = min(len, n);
 912
 913         while (n > 0) {
 914                 void __iomem *p;
 915
 916                 if (col < mtd->writesize) {
 917                         p = host->regs->main_area[0] + (col & ~3);
 918                 } else {
 919                         p = host->regs->spare_area[0] -
 920                                         mtd->writesize + (col & ~3);
 921                 }
 922
 923                 if (((col | (int)&buf[i]) & 3) || n < 4) {
 924                         union {
 925                                 uint32_t word;
 926                                 uint8_t bytes[4];
 927                         } nfc_word;
 928
 929                         nfc_word.word = readl(p);
 930                         buf[i++] = nfc_word.bytes[col & 3];
 931                         n--;
 932                         col++;
 933                 } else {
 934                         int m = mtd->writesize - col;
 935
 936                         if (col >= mtd->writesize)
 937                                 m += mtd->oobsize;
 938
 939                         m = min(n, m) & ~3;
 940                         mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
 941
 942                         col += m;
 943                         i += m;
 944                         n -= m;
 945                 }
 946         }
 947         /* Update saved column address */
 948         host->col_addr = col;
 949 }
 950
 951 /*
 952  * This function is used by upper layer for select and
 953  * deselect of the NAND chip
 954  */
 955 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
 956 {
 957         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 958         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 959
 960         switch (chip) {
 961         case -1:
 962                 /* TODO: Disable the NFC clock */
 963                 if (host->clk_act)
 964                         host->clk_act = 0;
 965                 break;
 966         case 0:
 967                 /* TODO: Enable the NFC clock */
 968                 if (!host->clk_act)
 969                         host->clk_act = 1;
 970                 break;
 971
 972         default:
 973                 break;
 974         }
 975 }
 976
 977 /*
 978  * Used by the upper layer to write command to NAND Flash for
 979  * different operations to be carried out on NAND Flash
 980  */
 981 void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 982                                 int column, int page_addr)
 983 {
 984         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 985         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 986
 987         MTDDEBUG(MTD_DEBUG_LEVEL3,
 988               "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
 989               command, column, page_addr);
 990
 991         /* Reset command state information */
 992         host->status_request = false;
 993
 994         /* Command pre-processing step */
 995         switch (command) {
 996
 997         case NAND_CMD_STATUS:
 998                 host->col_addr = 0;
 999                 host->status_request = true;
1000                 break;
1001
1002         case NAND_CMD_READ0:
1003                 host->page_addr = page_addr;
1004                 host->col_addr = column;
1005                 host->spare_only = false;
1006                 break;
1007
1008         case NAND_CMD_READOOB:
1009                 host->col_addr = column;
1010                 host->spare_only = true;
1011                 if (host->pagesize_2k)
1012                         command = NAND_CMD_READ0; /* only READ0 is valid */
1013                 break;
1014
1015         case NAND_CMD_SEQIN:
1016                 if (column >= mtd->writesize) {
1017                         /*
1018                          * before sending SEQIN command for partial write,
1019                          * we need read one page out. FSL NFC does not support
1020                          * partial write. It always sends out 512+ecc+512+ecc
1021                          * for large page nand flash. But for small page nand
1022                          * flash, it does support SPARE ONLY operation.
1023                          */
1024                         if (host->pagesize_2k) {
1025                                 /* call ourself to read a page */
1026                                 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
1027                                                 page_addr);
1028                         }
1029
1030                         host->col_addr = column - mtd->writesize;
1031                         host->spare_only = true;
1032
1033                         /* Set program pointer to spare region */
1034                         if (!host->pagesize_2k)
1035                                 send_cmd(host, NAND_CMD_READOOB);
1036                 } else {
1037                         host->spare_only = false;
1038                         host->col_addr = column;
1039
1040                         /* Set program pointer to page start */
1041                         if (!host->pagesize_2k)
1042                                 send_cmd(host, NAND_CMD_READ0);
1043                 }
1044                 break;
1045
1046         case NAND_CMD_PAGEPROG:
1047                 send_prog_page(host, 0, host->spare_only);
1048
1049                 if (host->pagesize_2k && is_mxc_nfc_1()) {
1050                         /* data in 4 areas */
1051                         send_prog_page(host, 1, host->spare_only);
1052                         send_prog_page(host, 2, host->spare_only);
1053                         send_prog_page(host, 3, host->spare_only);
1054                 }
1055
1056                 break;
1057         }
1058
1059         /* Write out the command to the device. */
1060         send_cmd(host, command);
1061
1062         /* Write out column address, if necessary */
1063         if (column != -1) {
1064                 /*
1065                  * MXC NANDFC can only perform full page+spare or
1066                  * spare-only read/write. When the upper layers perform
1067                  * a read/write buffer operation, we will use the saved
1068                  * column address to index into the full page.
1069                  */
1070                 send_addr(host, 0);
1071                 if (host->pagesize_2k)
1072                         /* another col addr cycle for 2k page */
1073                         send_addr(host, 0);
1074         }
1075
1076         /* Write out page address, if necessary */
1077         if (page_addr != -1) {
1078                 u32 page_mask = nand_chip->pagemask;
1079                 do {
1080                         send_addr(host, page_addr & 0xFF);
1081                         page_addr >>= 8;
1082                         page_mask >>= 8;
1083                 } while (page_mask);
1084         }
1085
1086         /* Command post-processing step */
1087         switch (command) {
1088
1089         case NAND_CMD_RESET:
1090                 break;
1091
1092         case NAND_CMD_READOOB:
1093         case NAND_CMD_READ0:
1094                 if (host->pagesize_2k) {
1095                         /* send read confirm command */
1096                         send_cmd(host, NAND_CMD_READSTART);
1097                         /* read for each AREA */
1098                         send_read_page(host, 0, host->spare_only);
1099                         if (is_mxc_nfc_1()) {
1100                                 send_read_page(host, 1, host->spare_only);
1101                                 send_read_page(host, 2, host->spare_only);
1102                                 send_read_page(host, 3, host->spare_only);
1103                         }
1104                 } else {
1105                         send_read_page(host, 0, host->spare_only);
1106                 }
1107                 break;
1108
1109         case NAND_CMD_READID:
1110                 host->col_addr = 0;
1111                 send_read_id(host);
1112                 break;
1113
1114         case NAND_CMD_PAGEPROG:
1115                 break;
1116
1117         case NAND_CMD_STATUS:
1118                 break;
1119
1120         case NAND_CMD_ERASE2:
1121                 break;
1122         }
1123 }
1124
1125 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1126
1127 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
1128 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
1129
1130 static struct nand_bbt_descr bbt_main_descr = {
1131         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1132                    NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1133         .offs = 0,
1134         .len = 4,
1135         .veroffs = 4,
1136         .maxblocks = 4,
1137         .pattern = bbt_pattern,
1138 };
1139
1140 static struct nand_bbt_descr bbt_mirror_descr = {
1141         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1142                    NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1143         .offs = 0,
1144         .len = 4,
1145         .veroffs = 4,
1146         .maxblocks = 4,
1147         .pattern = mirror_pattern,
1148 };
1149
1150 #endif
1151
1152 int board_nand_init(struct nand_chip *this)
1153 {
1154         struct mtd_info *mtd;
1155 #if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
1156         uint32_t tmp;
1157 #endif
1158
1159 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1160         this->bbt_options |= NAND_BBT_USE_FLASH;
1161         this->bbt_td = &bbt_main_descr;
1162         this->bbt_md = &bbt_mirror_descr;
1163 #endif
1164
1165         /* structures must be linked */
1166         mtd = &this->mtd;
1167         host->nand = this;
1168
1169         /* 5 us command delay time */
1170         this->chip_delay = 5;
1171
1172         nand_set_controller_data(this, host);
1173         this->dev_ready = mxc_nand_dev_ready;
1174         this->cmdfunc = mxc_nand_command;
1175         this->select_chip = mxc_nand_select_chip;
1176         this->read_byte = mxc_nand_read_byte;
1177         this->read_word = mxc_nand_read_word;
1178         this->write_buf = mxc_nand_write_buf;
1179         this->read_buf = mxc_nand_read_buf;
1180
1181         host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
1182 #ifdef MXC_NFC_V3_2
1183         host->ip_regs =
1184                 (struct mxc_nand_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE;
1185 #endif
1186         host->clk_act = 1;
1187
1188 #ifdef CONFIG_MXC_NAND_HWECC
1189         this->ecc.calculate = mxc_nand_calculate_ecc;
1190         this->ecc.hwctl = mxc_nand_enable_hwecc;
1191         this->ecc.correct = mxc_nand_correct_data;
1192         if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
1193                 this->ecc.mode = NAND_ECC_HW_SYNDROME;
1194                 this->ecc.read_page = mxc_nand_read_page_syndrome;
1195                 this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
1196                 this->ecc.read_oob = mxc_nand_read_oob_syndrome;
1197                 this->ecc.write_page = mxc_nand_write_page_syndrome;
1198                 this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome;
1199                 this->ecc.write_oob = mxc_nand_write_oob_syndrome;
1200                 this->ecc.bytes = 9;
1201                 this->ecc.prepad = 7;
1202         } else {
1203                 this->ecc.mode = NAND_ECC_HW;
1204         }
1205
1206         if (is_mxc_nfc_1())
1207                 this->ecc.strength = 1;
1208         else
1209                 this->ecc.strength = 4;
1210
1211         host->pagesize_2k = 0;
1212
1213         this->ecc.size = 512;
1214         _mxc_nand_enable_hwecc(mtd, 1);
1215 #else
1216         this->ecc.layout = &nand_soft_eccoob;
1217         this->ecc.mode = NAND_ECC_SOFT;
1218         _mxc_nand_enable_hwecc(mtd, 0);
1219 #endif
1220         /* Reset NAND */
1221         this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1222
1223         /* NAND bus width determines access functions used by upper layer */
1224         if (is_16bit_nand())
1225                 this->options |= NAND_BUSWIDTH_16;
1226
1227 #ifdef CONFIG_SYS_NAND_LARGEPAGE
1228         host->pagesize_2k = 1;
1229         this->ecc.layout = &nand_hw_eccoob2k;
1230 #else
1231         host->pagesize_2k = 0;
1232         this->ecc.layout = &nand_hw_eccoob;
1233 #endif
1234
1235 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
1236 #ifdef MXC_NFC_V2_1
1237         tmp = readnfc(&host->regs->config1);
1238         tmp |= NFC_V2_CONFIG1_ONE_CYCLE;
1239         tmp |= NFC_V2_CONFIG1_ECC_MODE_4;
1240         writenfc(tmp, &host->regs->config1);
1241         if (host->pagesize_2k)
1242                 writenfc(64/2, &host->regs->spare_area_size);
1243         else
1244                 writenfc(16/2, &host->regs->spare_area_size);
1245 #endif
1246
1247         /*
1248          * preset operation
1249          * Unlock the internal RAM Buffer
1250          */
1251         writenfc(0x2, &host->regs->config);
1252
1253         /* Blocks to be unlocked */
1254         writenfc(0x0, &host->regs->unlockstart_blkaddr);
1255         /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
1256          * unlockend_blkaddr, but the magic 0x4000 does not always work
1257          * when writing more than some 32 megabytes (on 2k page nands)
1258          * However 0xFFFF doesn't seem to have this kind
1259          * of limitation (tried it back and forth several times).
1260          * The linux kernel driver sets this to 0xFFFF for the v2 controller
1261          * only, but probably this was not tested there for v1.
1262          * The very same limitation seems to apply to this kernel driver.
1263          * This might be NAND chip specific and the i.MX31 datasheet is
1264          * extremely vague about the semantics of this register.
1265          */
1266         writenfc(0xFFFF, &host->regs->unlockend_blkaddr);
1267
1268         /* Unlock Block Command for given address range */
1269         writenfc(0x4, &host->regs->wrprot);
1270 #elif defined(MXC_NFC_V3_2)
1271         writenfc(NFC_V3_CONFIG1_RBA(0), &host->regs->config1);
1272         writenfc(NFC_V3_IPC_CREQ, &host->ip_regs->ipc);
1273
1274         /* Unlock the internal RAM Buffer */
1275         writenfc(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1276                         &host->ip_regs->wrprot);
1277
1278         /* Blocks to be unlocked */
1279         for (tmp = 0; tmp < CONFIG_SYS_NAND_MAX_CHIPS; tmp++)
1280                 writenfc(0x0 | 0xFFFF << 16,
1281                                 &host->ip_regs->wrprot_unlock_blkaddr[tmp]);
1282
1283         writenfc(0, &host->ip_regs->ipc);
1284
1285         tmp = readnfc(&host->ip_regs->config2);
1286         tmp &= ~(NFC_V3_CONFIG2_SPAS_MASK | NFC_V3_CONFIG2_EDC_MASK |
1287                         NFC_V3_CONFIG2_ECC_MODE_8 | NFC_V3_CONFIG2_PS_MASK);
1288         tmp |= NFC_V3_CONFIG2_ONE_CYCLE;
1289
1290         if (host->pagesize_2k) {
1291                 tmp |= NFC_V3_CONFIG2_SPAS(64/2);
1292                 tmp |= NFC_V3_CONFIG2_PS_2048;
1293         } else {
1294                 tmp |= NFC_V3_CONFIG2_SPAS(16/2);
1295                 tmp |= NFC_V3_CONFIG2_PS_512;
1296         }
1297
1298         writenfc(tmp, &host->ip_regs->config2);
1299
1300         tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) |
1301                         NFC_V3_CONFIG3_NO_SDMA |
1302                         NFC_V3_CONFIG3_RBB_MODE |
1303                         NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1304                         NFC_V3_CONFIG3_ADD_OP(0);
1305
1306         if (!(this->options & NAND_BUSWIDTH_16))
1307                 tmp |= NFC_V3_CONFIG3_FW8;
1308
1309         writenfc(tmp, &host->ip_regs->config3);
1310
1311         writenfc(0, &host->ip_regs->delay_line);
1312 #endif
1313
1314         return 0;
1315 }