2 * Copyright 2004-2007 Freescale Semiconductor, Inc.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
23 #include <linux/err.h>
25 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35)
26 #include <asm/arch/imx-regs.h>
30 #define DRIVER_NAME "mxc_nand"
32 typedef enum {false, true} bool;
34 struct mxc_nand_host {
36 struct nand_chip *nand;
38 struct fsl_nfc_regs __iomem *regs;
44 unsigned int page_addr;
47 static struct mxc_nand_host mxc_host;
48 static struct mxc_nand_host *host = &mxc_host;
50 /* Define delays in microsec for NAND device operations */
51 #define TROP_US_DELAY 2000
52 /* Macros to get byte and bit positions of ECC */
53 #define COLPOS(x) ((x) >> 3)
54 #define BITPOS(x) ((x) & 0xf)
56 /* Define single bit Error positions in Main & Spare area */
57 #define MAIN_SINGLEBIT_ERROR 0x4
58 #define SPARE_SINGLEBIT_ERROR 0x1
60 /* OOB placement block for use with hardware ecc generation */
61 #if defined(MXC_NFC_V1)
62 #ifndef CONFIG_SYS_NAND_LARGEPAGE
63 static struct nand_ecclayout nand_hw_eccoob = {
65 .eccpos = {6, 7, 8, 9, 10},
66 .oobfree = { {0, 5}, {11, 5}, }
69 static struct nand_ecclayout nand_hw_eccoob2k = {
77 .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
80 #elif defined(MXC_NFC_V1_1)
81 #ifndef CONFIG_SYS_NAND_LARGEPAGE
82 static struct nand_ecclayout nand_hw_eccoob = {
84 .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
88 static struct nand_ecclayout nand_hw_eccoob2k = {
91 7, 8, 9, 10, 11, 12, 13, 14, 15,
92 23, 24, 25, 26, 27, 28, 29, 30, 31,
93 39, 40, 41, 42, 43, 44, 45, 46, 47,
94 55, 56, 57, 58, 59, 60, 61, 62, 63,
96 .oobfree = { {2, 5}, {16, 7}, {32, 7}, {48, 7} },
102 static int is_16bit_nand(void)
104 struct system_control_regs *sc_regs =
105 (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
107 if (readl(&sc_regs->fmcr) & NF_16BIT_SEL)
112 #elif defined(CONFIG_MX31)
113 static int is_16bit_nand(void)
115 struct clock_control_regs *sc_regs =
116 (struct clock_control_regs *)CCM_BASE;
118 if (readl(&sc_regs->rcsr) & CCM_RCSR_NF16B)
123 #elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
124 static int is_16bit_nand(void)
126 struct ccm_regs *ccm =
127 (struct ccm_regs *)IMX_CCM_BASE;
129 if (readl(&ccm->rcsr) & CCM_RCSR_NF_16BIT_SEL)
135 #warning "8/16 bit NAND autodetection not supported"
136 static int is_16bit_nand(void)
142 static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
148 __raw_writel(__raw_readl(source++), d++);
153 * This function polls the NANDFC to wait for the basic operation to
154 * complete by checking the INT bit of config2 register.
156 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
161 while (max_retries-- > 0) {
162 if (readw(&host->regs->config2) & NFC_INT) {
163 tmp = readw(&host->regs->config2);
165 writew(tmp, &host->regs->config2);
170 if (max_retries < 0) {
171 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
177 * This function issues the specified command to the NAND device and
178 * waits for completion.
180 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
182 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
184 writew(cmd, &host->regs->flash_cmd);
185 writew(NFC_CMD, &host->regs->config2);
187 /* Wait for operation to complete */
188 wait_op_done(host, TROP_US_DELAY, cmd);
192 * This function sends an address (or partial address) to the
193 * NAND device. The address is used to select the source/destination for
196 static void send_addr(struct mxc_nand_host *host, uint16_t addr)
198 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
200 writew(addr, &host->regs->flash_addr);
201 writew(NFC_ADDR, &host->regs->config2);
203 /* Wait for operation to complete */
204 wait_op_done(host, TROP_US_DELAY, addr);
208 * This function requests the NANDFC to initiate the transfer
209 * of data currently in the NANDFC RAM buffer to the NAND device.
211 static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
215 MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only);
217 if (is_mxc_nfc_11()) {
220 * The controller copies the 64 bytes of spare data from
221 * the first 16 bytes of each of the 4 64 byte spare buffers.
222 * Copy the contiguous data starting in spare_area[0] to
223 * the four spare area buffers.
225 for (i = 1; i < 4; i++) {
226 void __iomem *src = &host->regs->spare_area[0][i * 16];
227 void __iomem *dst = &host->regs->spare_area[i][0];
229 mxc_nand_memcpy32(dst, src, 16);
233 writew(buf_id, &host->regs->buf_addr);
235 /* Configure spare or page+spare access */
236 if (!host->pagesize_2k) {
237 uint16_t config1 = readw(&host->regs->config1);
239 config1 |= NFC_SP_EN;
241 config1 &= ~(NFC_SP_EN);
242 writew(config1, &host->regs->config1);
245 writew(NFC_INPUT, &host->regs->config2);
247 /* Wait for operation to complete */
248 wait_op_done(host, TROP_US_DELAY, spare_only);
252 * Requests NANDFC to initiate the transfer of data from the
253 * NAND device into in the NANDFC ram buffer.
255 static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
258 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
260 writew(buf_id, &host->regs->buf_addr);
262 /* Configure spare or page+spare access */
263 if (!host->pagesize_2k) {
264 uint32_t config1 = readw(&host->regs->config1);
266 config1 |= NFC_SP_EN;
268 config1 &= ~NFC_SP_EN;
269 writew(config1, &host->regs->config1);
272 writew(NFC_OUTPUT, &host->regs->config2);
274 /* Wait for operation to complete */
275 wait_op_done(host, TROP_US_DELAY, spare_only);
277 if (is_mxc_nfc_11()) {
281 * The controller copies the 64 bytes of spare data to
282 * the first 16 bytes of each of the 4 spare buffers.
283 * Make the data contiguous starting in spare_area[0].
285 for (i = 1; i < 4; i++) {
286 void __iomem *src = &host->regs->spare_area[i][0];
287 void __iomem *dst = &host->regs->spare_area[0][i * 16];
289 mxc_nand_memcpy32(dst, src, 16);
294 /* Request the NANDFC to perform a read of the NAND device ID. */
295 static void send_read_id(struct mxc_nand_host *host)
299 /* NANDFC buffer 0 is used for device ID output */
300 writew(0x0, &host->regs->buf_addr);
302 /* Read ID into main buffer */
303 tmp = readw(&host->regs->config1);
305 writew(tmp, &host->regs->config1);
307 writew(NFC_ID, &host->regs->config2);
309 /* Wait for operation to complete */
310 wait_op_done(host, TROP_US_DELAY, 0);
314 * This function requests the NANDFC to perform a read of the
315 * NAND device status and returns the current status.
317 static uint16_t get_dev_status(struct mxc_nand_host *host)
319 void __iomem *main_buf = host->regs->main_area[1];
322 /* Issue status request to NAND device */
324 /* store the main area1 first word, later do recovery */
325 store = readl(main_buf);
326 /* NANDFC buffer 1 is used for device status */
327 writew(1, &host->regs->buf_addr);
329 /* Read status into main buffer */
330 tmp = readw(&host->regs->config1);
332 writew(tmp, &host->regs->config1);
334 writew(NFC_STATUS, &host->regs->config2);
336 /* Wait for operation to complete */
337 wait_op_done(host, TROP_US_DELAY, 0);
340 * Status is placed in first word of main buffer
341 * get status, then recovery area 1 data
343 ret = readw(main_buf);
344 writel(store, main_buf);
349 /* This function is used by upper layer to checks if device is ready */
350 static int mxc_nand_dev_ready(struct mtd_info *mtd)
353 * NFC handles R/B internally. Therefore, this function
354 * always returns status as ready.
359 #ifdef CONFIG_MXC_NAND_HWECC
360 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
363 * If HW ECC is enabled, we turn it on during init. There is
364 * no need to enable again here.
369 static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
371 struct nand_chip *nand_chip = mtd->priv;
372 struct mxc_nand_host *host = nand_chip->priv;
373 uint16_t tmp = readw(&host->regs->config1);
379 writew(tmp, &host->regs->config1);
382 static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
383 struct nand_chip *chip,
384 int page, int sndcmd)
386 struct mxc_nand_host *host = chip->priv;
387 uint8_t *buf = chip->oob_poi;
388 int length = mtd->oobsize;
389 int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
390 uint8_t *bufpoi = buf;
393 MTDDEBUG(MTD_DEBUG_LEVEL0,
394 "%s: Reading OOB area of page %u to oob %p\n",
395 __FUNCTION__, host->page_addr, buf);
397 chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
398 for (i = 0; i < chip->ecc.steps; i++) {
399 toread = min_t(int, length, chip->ecc.prepad);
401 chip->read_buf(mtd, bufpoi, toread);
405 bufpoi += chip->ecc.bytes;
406 host->col_addr += chip->ecc.bytes;
407 length -= chip->ecc.bytes;
409 toread = min_t(int, length, chip->ecc.postpad);
411 chip->read_buf(mtd, bufpoi, toread);
417 chip->read_buf(mtd, bufpoi, length);
419 _mxc_nand_enable_hwecc(mtd, 0);
420 chip->cmdfunc(mtd, NAND_CMD_READOOB,
421 mtd->writesize + chip->ecc.prepad, page);
422 bufpoi = buf + chip->ecc.prepad;
423 length = mtd->oobsize - chip->ecc.prepad;
424 for (i = 0; i < chip->ecc.steps; i++) {
425 toread = min_t(int, length, chip->ecc.bytes);
426 chip->read_buf(mtd, bufpoi, toread);
429 host->col_addr += chip->ecc.postpad + chip->ecc.prepad;
431 _mxc_nand_enable_hwecc(mtd, 1);
435 static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
436 struct nand_chip *chip,
440 struct mxc_nand_host *host = chip->priv;
441 int eccsize = chip->ecc.size;
442 int eccbytes = chip->ecc.bytes;
443 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
444 uint8_t *oob = chip->oob_poi;
448 _mxc_nand_enable_hwecc(mtd, 0);
449 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, host->page_addr);
451 for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
452 host->col_addr = n * eccsize;
453 chip->read_buf(mtd, buf, eccsize);
456 host->col_addr = mtd->writesize + n * eccpitch;
457 if (chip->ecc.prepad) {
458 chip->read_buf(mtd, oob, chip->ecc.prepad);
459 oob += chip->ecc.prepad;
462 chip->read_buf(mtd, oob, eccbytes);
465 if (chip->ecc.postpad) {
466 chip->read_buf(mtd, oob, chip->ecc.postpad);
467 oob += chip->ecc.postpad;
471 size = mtd->oobsize - (oob - chip->oob_poi);
473 chip->read_buf(mtd, oob, size);
474 _mxc_nand_enable_hwecc(mtd, 0);
479 static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
480 struct nand_chip *chip,
484 struct mxc_nand_host *host = chip->priv;
485 int n, eccsize = chip->ecc.size;
486 int eccbytes = chip->ecc.bytes;
487 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
488 int eccsteps = chip->ecc.steps;
490 uint8_t *oob = chip->oob_poi;
492 MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n",
493 host->page_addr, buf, oob);
495 /* first read the data area and the available portion of OOB */
496 for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
499 host->col_addr = n * eccsize;
501 chip->read_buf(mtd, p, eccsize);
503 host->col_addr = mtd->writesize + n * eccpitch;
505 if (chip->ecc.prepad) {
506 chip->read_buf(mtd, oob, chip->ecc.prepad);
507 oob += chip->ecc.prepad;
510 stat = chip->ecc.correct(mtd, p, oob, NULL);
513 mtd->ecc_stats.failed++;
515 mtd->ecc_stats.corrected += stat;
518 if (chip->ecc.postpad) {
519 chip->read_buf(mtd, oob, chip->ecc.postpad);
520 oob += chip->ecc.postpad;
524 /* Calculate remaining oob bytes */
525 n = mtd->oobsize - (oob - chip->oob_poi);
527 chip->read_buf(mtd, oob, n);
529 /* Then switch ECC off and read the OOB area to get the ECC code */
530 _mxc_nand_enable_hwecc(mtd, 0);
531 chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, host->page_addr);
532 eccsteps = chip->ecc.steps;
533 oob = chip->oob_poi + chip->ecc.prepad;
534 for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
535 host->col_addr = mtd->writesize +
538 chip->read_buf(mtd, oob, eccbytes);
539 oob += eccbytes + chip->ecc.postpad;
541 _mxc_nand_enable_hwecc(mtd, 1);
545 static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
546 struct nand_chip *chip, int page)
548 struct mxc_nand_host *host = chip->priv;
549 int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
550 int length = mtd->oobsize;
551 int i, len, status, steps = chip->ecc.steps;
552 const uint8_t *bufpoi = chip->oob_poi;
554 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
555 for (i = 0; i < steps; i++) {
556 len = min_t(int, length, eccpitch);
558 chip->write_buf(mtd, bufpoi, len);
561 host->col_addr += chip->ecc.prepad + chip->ecc.postpad;
564 chip->write_buf(mtd, bufpoi, length);
566 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
567 status = chip->waitfunc(mtd, chip);
568 return status & NAND_STATUS_FAIL ? -EIO : 0;
571 static void mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
572 struct nand_chip *chip,
575 struct mxc_nand_host *host = chip->priv;
576 int eccsize = chip->ecc.size;
577 int eccbytes = chip->ecc.bytes;
578 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
579 uint8_t *oob = chip->oob_poi;
583 for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
584 host->col_addr = n * eccsize;
585 chip->write_buf(mtd, buf, eccsize);
588 host->col_addr = mtd->writesize + n * eccpitch;
590 if (chip->ecc.prepad) {
591 chip->write_buf(mtd, oob, chip->ecc.prepad);
592 oob += chip->ecc.prepad;
595 host->col_addr += eccbytes;
598 if (chip->ecc.postpad) {
599 chip->write_buf(mtd, oob, chip->ecc.postpad);
600 oob += chip->ecc.postpad;
604 size = mtd->oobsize - (oob - chip->oob_poi);
606 chip->write_buf(mtd, oob, size);
609 static void mxc_nand_write_page_syndrome(struct mtd_info *mtd,
610 struct nand_chip *chip,
613 struct mxc_nand_host *host = chip->priv;
614 int i, n, eccsize = chip->ecc.size;
615 int eccbytes = chip->ecc.bytes;
616 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
617 int eccsteps = chip->ecc.steps;
618 const uint8_t *p = buf;
619 uint8_t *oob = chip->oob_poi;
621 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
625 n++, eccsteps--, i += eccbytes, p += eccsize) {
626 host->col_addr = n * eccsize;
628 chip->write_buf(mtd, p, eccsize);
630 host->col_addr = mtd->writesize + n * eccpitch;
632 if (chip->ecc.prepad) {
633 chip->write_buf(mtd, oob, chip->ecc.prepad);
634 oob += chip->ecc.prepad;
637 chip->write_buf(mtd, oob, eccbytes);
640 if (chip->ecc.postpad) {
641 chip->write_buf(mtd, oob, chip->ecc.postpad);
642 oob += chip->ecc.postpad;
646 /* Calculate remaining oob bytes */
647 i = mtd->oobsize - (oob - chip->oob_poi);
649 chip->write_buf(mtd, oob, i);
652 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
653 u_char *read_ecc, u_char *calc_ecc)
655 struct nand_chip *nand_chip = mtd->priv;
656 struct mxc_nand_host *host = nand_chip->priv;
657 uint16_t ecc_status = readw(&host->regs->ecc_status_result);
658 int subpages = mtd->writesize / nand_chip->subpagesize;
659 int pg2blk_shift = nand_chip->phys_erase_shift -
660 nand_chip->page_shift;
663 if ((ecc_status & 0xf) > 4) {
664 static int last_bad = -1;
666 if (last_bad != host->page_addr >> pg2blk_shift) {
667 last_bad = host->page_addr >> pg2blk_shift;
669 "MXC_NAND: HWECC uncorrectable ECC error"
670 " in block %u page %u subpage %d\n",
671 last_bad, host->page_addr,
672 mtd->writesize / nand_chip->subpagesize
679 } while (subpages > 0);
684 #define mxc_nand_read_page_syndrome NULL
685 #define mxc_nand_read_page_raw_syndrome NULL
686 #define mxc_nand_read_oob_syndrome NULL
687 #define mxc_nand_write_page_syndrome NULL
688 #define mxc_nand_write_page_raw_syndrome NULL
689 #define mxc_nand_write_oob_syndrome NULL
690 #define mxc_nfc_11_nand_correct_data NULL
692 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
693 u_char *read_ecc, u_char *calc_ecc)
695 struct nand_chip *nand_chip = mtd->priv;
696 struct mxc_nand_host *host = nand_chip->priv;
699 * 1-Bit errors are automatically corrected in HW. No need for
700 * additional correction. 2-Bit errors cannot be corrected by
701 * HW ECC, so we need to return failure
703 uint16_t ecc_status = readw(&host->regs->ecc_status_result);
705 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
706 MTDDEBUG(MTD_DEBUG_LEVEL0,
707 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
715 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
722 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
724 struct nand_chip *nand_chip = mtd->priv;
725 struct mxc_nand_host *host = nand_chip->priv;
728 uint16_t __iomem *main_buf =
729 (uint16_t __iomem *)host->regs->main_area[0];
730 uint16_t __iomem *spare_buf =
731 (uint16_t __iomem *)host->regs->spare_area[0];
737 /* Check for status request */
738 if (host->status_request)
739 return get_dev_status(host) & 0xFF;
741 /* Get column for 16-bit access */
742 col = host->col_addr >> 1;
744 /* If we are accessing the spare region */
745 if (host->spare_only)
746 nfc_word.word = readw(&spare_buf[col]);
748 nfc_word.word = readw(&main_buf[col]);
750 /* Pick upper/lower byte of word from RAM buffer */
751 ret = nfc_word.bytes[host->col_addr & 0x1];
753 /* Update saved column address */
754 if (nand_chip->options & NAND_BUSWIDTH_16)
762 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
764 struct nand_chip *nand_chip = mtd->priv;
765 struct mxc_nand_host *host = nand_chip->priv;
769 MTDDEBUG(MTD_DEBUG_LEVEL3,
770 "mxc_nand_read_word(col = %d)\n", host->col_addr);
772 col = host->col_addr;
773 /* Adjust saved column address */
774 if (col < mtd->writesize && host->spare_only)
775 col += mtd->writesize;
777 if (col < mtd->writesize) {
778 p = (uint16_t __iomem *)(host->regs->main_area[0] +
781 p = (uint16_t __iomem *)(host->regs->spare_area[0] +
782 ((col - mtd->writesize) >> 1));
791 nfc_word[0].word = readw(p);
792 nfc_word[1].word = readw(p + 1);
794 nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
795 nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
797 ret = nfc_word[2].word;
802 /* Update saved column address */
803 host->col_addr = col + 2;
809 * Write data of length len to buffer buf. The data to be
810 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
811 * Operation by the NFC, the data is written to NAND Flash
813 static void mxc_nand_write_buf(struct mtd_info *mtd,
814 const u_char *buf, int len)
816 struct nand_chip *nand_chip = mtd->priv;
817 struct mxc_nand_host *host = nand_chip->priv;
820 MTDDEBUG(MTD_DEBUG_LEVEL3,
821 "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
824 col = host->col_addr;
826 /* Adjust saved column address */
827 if (col < mtd->writesize && host->spare_only)
828 col += mtd->writesize;
830 n = mtd->writesize + mtd->oobsize - col;
833 MTDDEBUG(MTD_DEBUG_LEVEL3,
834 "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
839 if (col < mtd->writesize) {
840 p = host->regs->main_area[0] + (col & ~3);
842 p = host->regs->spare_area[0] -
843 mtd->writesize + (col & ~3);
846 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
849 if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
855 nfc_word.word = readl(p);
856 nfc_word.bytes[col & 3] = buf[i++];
860 writel(nfc_word.word, p);
862 int m = mtd->writesize - col;
864 if (col >= mtd->writesize)
869 MTDDEBUG(MTD_DEBUG_LEVEL3,
870 "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
871 __func__, __LINE__, n, m, i, col);
873 mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
879 /* Update saved column address */
880 host->col_addr = col;
884 * Read the data buffer from the NAND Flash. To read the data from NAND
885 * Flash first the data output cycle is initiated by the NFC, which copies
886 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
888 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
890 struct nand_chip *nand_chip = mtd->priv;
891 struct mxc_nand_host *host = nand_chip->priv;
894 MTDDEBUG(MTD_DEBUG_LEVEL3,
895 "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
897 col = host->col_addr;
899 /* Adjust saved column address */
900 if (col < mtd->writesize && host->spare_only)
901 col += mtd->writesize;
903 n = mtd->writesize + mtd->oobsize - col;
909 if (col < mtd->writesize) {
910 p = host->regs->main_area[0] + (col & ~3);
912 p = host->regs->spare_area[0] -
913 mtd->writesize + (col & ~3);
916 if (((col | (int)&buf[i]) & 3) || n < 4) {
922 nfc_word.word = readl(p);
923 buf[i++] = nfc_word.bytes[col & 3];
927 int m = mtd->writesize - col;
929 if (col >= mtd->writesize)
933 mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
940 /* Update saved column address */
941 host->col_addr = col;
945 * Used by the upper layer to verify the data in NAND Flash
946 * with the data in the buf.
948 static int mxc_nand_verify_buf(struct mtd_info *mtd,
949 const u_char *buf, int len)
955 bsize = min(len, 256);
956 mxc_nand_read_buf(mtd, tmp, bsize);
958 if (memcmp(buf, tmp, bsize))
969 * This function is used by upper layer for select and
970 * deselect of the NAND chip
972 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
974 struct nand_chip *nand_chip = mtd->priv;
975 struct mxc_nand_host *host = nand_chip->priv;
979 /* TODO: Disable the NFC clock */
984 /* TODO: Enable the NFC clock */
995 * Used by the upper layer to write command to NAND Flash for
996 * different operations to be carried out on NAND Flash
998 void mxc_nand_command(struct mtd_info *mtd, unsigned command,
999 int column, int page_addr)
1001 struct nand_chip *nand_chip = mtd->priv;
1002 struct mxc_nand_host *host = nand_chip->priv;
1004 MTDDEBUG(MTD_DEBUG_LEVEL3,
1005 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1006 command, column, page_addr);
1008 /* Reset command state information */
1009 host->status_request = false;
1011 /* Command pre-processing step */
1014 case NAND_CMD_STATUS:
1016 host->status_request = true;
1019 case NAND_CMD_READ0:
1020 host->page_addr = page_addr;
1021 host->col_addr = column;
1022 host->spare_only = false;
1025 case NAND_CMD_READOOB:
1026 host->col_addr = column;
1027 host->spare_only = true;
1028 if (host->pagesize_2k)
1029 command = NAND_CMD_READ0; /* only READ0 is valid */
1032 case NAND_CMD_SEQIN:
1033 if (column >= mtd->writesize) {
1035 * before sending SEQIN command for partial write,
1036 * we need read one page out. FSL NFC does not support
1037 * partial write. It always sends out 512+ecc+512+ecc
1038 * for large page nand flash. But for small page nand
1039 * flash, it does support SPARE ONLY operation.
1041 if (host->pagesize_2k) {
1042 /* call ourself to read a page */
1043 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
1047 host->col_addr = column - mtd->writesize;
1048 host->spare_only = true;
1050 /* Set program pointer to spare region */
1051 if (!host->pagesize_2k)
1052 send_cmd(host, NAND_CMD_READOOB);
1054 host->spare_only = false;
1055 host->col_addr = column;
1057 /* Set program pointer to page start */
1058 if (!host->pagesize_2k)
1059 send_cmd(host, NAND_CMD_READ0);
1063 case NAND_CMD_PAGEPROG:
1064 send_prog_page(host, 0, host->spare_only);
1066 if (host->pagesize_2k && !is_mxc_nfc_11()) {
1067 /* data in 4 areas */
1068 send_prog_page(host, 1, host->spare_only);
1069 send_prog_page(host, 2, host->spare_only);
1070 send_prog_page(host, 3, host->spare_only);
1076 /* Write out the command to the device. */
1077 send_cmd(host, command);
1079 /* Write out column address, if necessary */
1082 * MXC NANDFC can only perform full page+spare or
1083 * spare-only read/write. When the upper layers perform
1084 * a read/write buffer operation, we will use the saved
1085 * column address to index into the full page.
1088 if (host->pagesize_2k)
1089 /* another col addr cycle for 2k page */
1093 /* Write out page address, if necessary */
1094 if (page_addr != -1) {
1095 u32 page_mask = nand_chip->pagemask;
1097 send_addr(host, page_addr & 0xFF);
1100 } while (page_mask);
1103 /* Command post-processing step */
1106 case NAND_CMD_RESET:
1109 case NAND_CMD_READOOB:
1110 case NAND_CMD_READ0:
1111 if (host->pagesize_2k) {
1112 /* send read confirm command */
1113 send_cmd(host, NAND_CMD_READSTART);
1114 /* read for each AREA */
1115 send_read_page(host, 0, host->spare_only);
1116 if (!is_mxc_nfc_11()) {
1117 send_read_page(host, 1, host->spare_only);
1118 send_read_page(host, 2, host->spare_only);
1119 send_read_page(host, 3, host->spare_only);
1122 send_read_page(host, 0, host->spare_only);
1126 case NAND_CMD_READID:
1131 case NAND_CMD_PAGEPROG:
1134 case NAND_CMD_STATUS:
1137 case NAND_CMD_ERASE2:
1143 static void mxc_setup_config1(void)
1147 tmp = readw(&host->regs->config1);
1148 tmp |= NFC_ONE_CYCLE;
1149 tmp |= NFC_4_8N_ECC;
1150 writew(tmp, &host->regs->config1);
1151 if (host->pagesize_2k)
1152 writew(64/2, &host->regs->spare_area_size);
1154 writew(16/2, &host->regs->spare_area_size);
1157 #define mxc_setup_config1()
1160 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1162 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
1163 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
1165 static struct nand_bbt_descr bbt_main_descr = {
1166 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1167 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1172 .pattern = bbt_pattern,
1175 static struct nand_bbt_descr bbt_mirror_descr = {
1176 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1177 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1182 .pattern = mirror_pattern,
1187 int board_nand_init(struct nand_chip *this)
1189 struct mtd_info *mtd;
1193 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1194 this->options |= NAND_USE_FLASH_BBT;
1195 this->bbt_td = &bbt_main_descr;
1196 this->bbt_md = &bbt_mirror_descr;
1199 /* structures must be linked */
1204 /* 5 us command delay time */
1205 this->chip_delay = 5;
1208 this->dev_ready = mxc_nand_dev_ready;
1209 this->cmdfunc = mxc_nand_command;
1210 this->select_chip = mxc_nand_select_chip;
1211 this->read_byte = mxc_nand_read_byte;
1212 this->read_word = mxc_nand_read_word;
1213 this->write_buf = mxc_nand_write_buf;
1214 this->read_buf = mxc_nand_read_buf;
1215 this->verify_buf = mxc_nand_verify_buf;
1217 host->regs = (struct fsl_nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
1220 #ifdef CONFIG_MXC_NAND_HWECC
1221 this->ecc.calculate = mxc_nand_calculate_ecc;
1222 this->ecc.hwctl = mxc_nand_enable_hwecc;
1223 this->ecc.correct = mxc_nand_correct_data;
1224 if (is_mxc_nfc_11()) {
1225 this->ecc.mode = NAND_ECC_HW_SYNDROME;
1226 this->ecc.read_page = mxc_nand_read_page_syndrome;
1227 this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
1228 this->ecc.read_oob = mxc_nand_read_oob_syndrome;
1229 this->ecc.write_page = mxc_nand_write_page_syndrome;
1230 this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome;
1231 this->ecc.write_oob = mxc_nand_write_oob_syndrome;
1232 this->ecc.bytes = 9;
1233 this->ecc.prepad = 7;
1235 this->ecc.mode = NAND_ECC_HW;
1238 host->pagesize_2k = 0;
1240 this->ecc.size = 512;
1241 tmp = readw(&host->regs->config1);
1243 writew(tmp, &host->regs->config1);
1245 this->ecc.layout = &nand_soft_eccoob;
1246 this->ecc.mode = NAND_ECC_SOFT;
1247 tmp = readw(&host->regs->config1);
1249 writew(tmp, &host->regs->config1);
1252 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1256 * Unlock the internal RAM Buffer
1258 writew(0x2, &host->regs->config);
1260 /* Blocks to be unlocked */
1261 writew(0x0, &host->regs->unlockstart_blkaddr);
1262 /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
1263 * unlockend_blkaddr, but the magic 0x4000 does not always work
1264 * when writing more than some 32 megabytes (on 2k page nands)
1265 * However 0xFFFF doesn't seem to have this kind
1266 * of limitation (tried it back and forth several times).
1267 * The linux kernel driver sets this to 0xFFFF for the v2 controller
1268 * only, but probably this was not tested there for v1.
1269 * The very same limitation seems to apply to this kernel driver.
1270 * This might be NAND chip specific and the i.MX31 datasheet is
1271 * extremely vague about the semantics of this register.
1273 writew(0xFFFF, &host->regs->unlockend_blkaddr);
1275 /* Unlock Block Command for given address range */
1276 writew(0x4, &host->regs->wrprot);
1278 /* NAND bus width determines access functions used by upper layer */
1279 if (is_16bit_nand())
1280 this->options |= NAND_BUSWIDTH_16;
1282 #ifdef CONFIG_SYS_NAND_LARGEPAGE
1283 host->pagesize_2k = 1;
1284 this->ecc.layout = &nand_hw_eccoob2k;
1286 host->pagesize_2k = 0;
1287 this->ecc.layout = &nand_hw_eccoob;
1289 mxc_setup_config1();