2 * Copyright 2004-2007 Freescale Semiconductor, Inc.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
23 #include <linux/err.h>
26 #include <asm/arch/imx-regs.h>
29 #define DRIVER_NAME "mxc_nand"
32 /* NFC RAM BUFFER Main area 0 */
33 uint8_t main_area0[0x200];
34 uint8_t main_area1[0x200];
35 uint8_t main_area2[0x200];
36 uint8_t main_area3[0x200];
37 /* SPARE BUFFER Spare area 0 */
38 uint8_t spare_area0[0x10];
39 uint8_t spare_area1[0x10];
40 uint8_t spare_area2[0x10];
41 uint8_t spare_area3[0x10];
44 uint16_t nfc_buf_size;
46 uint16_t nfc_buf_addr;
47 uint16_t nfc_flash_addr;
48 uint16_t nfc_flash_cmd;
50 uint16_t nfc_ecc_status_result;
51 uint16_t nfc_rsltmain_area;
52 uint16_t nfc_rsltspare_area;
54 uint16_t nfc_unlockstart_blkaddr;
55 uint16_t nfc_unlockend_blkaddr;
56 uint16_t nfc_nf_wrprst;
62 * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
63 * for Command operation
68 * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
69 * for Address operation
74 * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
80 * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
81 * for Data Output operation
83 #define NFC_OUTPUT 0x8
86 * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
87 * for Read ID operation
92 * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
93 * for Read Status operation
95 #define NFC_STATUS 0x20
98 * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
101 #define NFC_INT 0x8000
103 #define NFC_SP_EN (1 << 2)
104 #define NFC_ECC_EN (1 << 3)
105 #define NFC_BIG (1 << 5)
106 #define NFC_RST (1 << 6)
107 #define NFC_CE (1 << 7)
108 #define NFC_ONE_CYCLE (1 << 8)
110 typedef enum {false, true} bool;
112 struct mxc_nand_host {
114 struct nand_chip *nand;
116 struct nfc_regs __iomem *regs;
124 static struct mxc_nand_host mxc_host;
125 static struct mxc_nand_host *host = &mxc_host;
127 /* Define delays in microsec for NAND device operations */
128 #define TROP_US_DELAY 2000
129 /* Macros to get byte and bit positions of ECC */
130 #define COLPOS(x) ((x) >> 3)
131 #define BITPOS(x) ((x) & 0xf)
133 /* Define single bit Error positions in Main & Spare area */
134 #define MAIN_SINGLEBIT_ERROR 0x4
135 #define SPARE_SINGLEBIT_ERROR 0x1
137 /* OOB placement block for use with hardware ecc generation */
138 #ifdef CONFIG_MXC_NAND_HWECC
139 static struct nand_ecclayout nand_hw_eccoob = {
141 .eccpos = {6, 7, 8, 9, 10},
142 .oobfree = {{0, 5}, {11, 5}, }
145 static struct nand_ecclayout nand_soft_eccoob = {
147 .eccpos = {6, 7, 8, 9, 10, 11},
148 .oobfree = {{0, 5}, {12, 4}, }
152 static struct nand_ecclayout nand_hw_eccoob_largepage = {
154 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
155 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
156 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
160 static int is_16bit_nand(void)
162 struct system_control_regs *sc_regs =
163 (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
165 if (readl(&sc_regs->fmcr) & NF_16BIT_SEL)
170 #elif defined(CONFIG_MX31)
171 static int is_16bit_nand(void)
173 struct clock_control_regs *sc_regs =
174 (struct clock_control_regs *)CCM_BASE;
176 if (readl(&sc_regs->rcsr) & CCM_RCSR_NF16B)
182 #warning "8/16 bit NAND autodetection not supported"
183 static int is_16bit_nand(void)
189 static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
195 __raw_writel(__raw_readl(source++), d++);
200 * This function polls the NANDFC to wait for the basic operation to
201 * complete by checking the INT bit of config2 register.
203 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
208 while (max_retries-- > 0) {
209 if (readw(&host->regs->nfc_config2) & NFC_INT) {
210 tmp = readw(&host->regs->nfc_config2);
212 writew(tmp, &host->regs->nfc_config2);
217 if (max_retries < 0) {
218 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
224 * This function issues the specified command to the NAND device and
225 * waits for completion.
227 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
229 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
231 writew(cmd, &host->regs->nfc_flash_cmd);
232 writew(NFC_CMD, &host->regs->nfc_config2);
234 /* Wait for operation to complete */
235 wait_op_done(host, TROP_US_DELAY, cmd);
239 * This function sends an address (or partial address) to the
240 * NAND device. The address is used to select the source/destination for
243 static void send_addr(struct mxc_nand_host *host, uint16_t addr)
245 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
247 writew(addr, &host->regs->nfc_flash_addr);
248 writew(NFC_ADDR, &host->regs->nfc_config2);
250 /* Wait for operation to complete */
251 wait_op_done(host, TROP_US_DELAY, addr);
255 * This function requests the NANDFC to initate the transfer
256 * of data currently in the NANDFC RAM buffer to the NAND device.
258 static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
261 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", spare_only);
263 writew(buf_id, &host->regs->nfc_buf_addr);
265 /* Configure spare or page+spare access */
266 if (!host->pagesize_2k) {
267 uint16_t config1 = readw(&host->regs->nfc_config1);
269 config1 |= NFC_SP_EN;
271 config1 &= ~(NFC_SP_EN);
272 writew(config1, &host->regs->nfc_config1);
275 writew(NFC_INPUT, &host->regs->nfc_config2);
277 /* Wait for operation to complete */
278 wait_op_done(host, TROP_US_DELAY, spare_only);
282 * Requests NANDFC to initated the transfer of data from the
283 * NAND device into in the NANDFC ram buffer.
285 static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
288 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
290 writew(buf_id, &host->regs->nfc_buf_addr);
292 /* Configure spare or page+spare access */
293 if (!host->pagesize_2k) {
294 uint32_t config1 = readw(&host->regs->nfc_config1);
296 config1 |= NFC_SP_EN;
298 config1 &= ~NFC_SP_EN;
299 writew(config1, &host->regs->nfc_config1);
302 writew(NFC_OUTPUT, &host->regs->nfc_config2);
304 /* Wait for operation to complete */
305 wait_op_done(host, TROP_US_DELAY, spare_only);
308 /* Request the NANDFC to perform a read of the NAND device ID. */
309 static void send_read_id(struct mxc_nand_host *host)
313 /* NANDFC buffer 0 is used for device ID output */
314 writew(0x0, &host->regs->nfc_buf_addr);
316 /* Read ID into main buffer */
317 tmp = readw(&host->regs->nfc_config1);
319 writew(tmp, &host->regs->nfc_config1);
321 writew(NFC_ID, &host->regs->nfc_config2);
323 /* Wait for operation to complete */
324 wait_op_done(host, TROP_US_DELAY, 0);
328 * This function requests the NANDFC to perform a read of the
329 * NAND device status and returns the current status.
331 static uint16_t get_dev_status(struct mxc_nand_host *host)
333 void __iomem *main_buf = host->regs->main_area1;
336 /* Issue status request to NAND device */
338 /* store the main area1 first word, later do recovery */
339 store = readl(main_buf);
340 /* NANDFC buffer 1 is used for device status */
341 writew(1, &host->regs->nfc_buf_addr);
343 /* Read status into main buffer */
344 tmp = readw(&host->regs->nfc_config1);
346 writew(tmp, &host->regs->nfc_config1);
348 writew(NFC_STATUS, &host->regs->nfc_config2);
350 /* Wait for operation to complete */
351 wait_op_done(host, TROP_US_DELAY, 0);
354 * Status is placed in first word of main buffer
355 * get status, then recovery area 1 data
357 ret = readw(main_buf);
358 writel(store, main_buf);
363 /* This function is used by upper layer to checks if device is ready */
364 static int mxc_nand_dev_ready(struct mtd_info *mtd)
367 * NFC handles R/B internally. Therefore, this function
368 * always returns status as ready.
373 #ifdef CONFIG_MXC_NAND_HWECC
374 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
377 * If HW ECC is enabled, we turn it on during init. There is
378 * no need to enable again here.
382 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
383 u_char *read_ecc, u_char *calc_ecc)
385 struct nand_chip *nand_chip = mtd->priv;
386 struct mxc_nand_host *host = nand_chip->priv;
389 * 1-Bit errors are automatically corrected in HW. No need for
390 * additional correction. 2-Bit errors cannot be corrected by
391 * HW ECC, so we need to return failure
393 uint16_t ecc_status = readw(&host->regs->nfc_ecc_status_result);
395 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
396 MTDDEBUG(MTD_DEBUG_LEVEL0,
397 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
404 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
411 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
413 struct nand_chip *nand_chip = mtd->priv;
414 struct mxc_nand_host *host = nand_chip->priv;
417 uint16_t __iomem *main_buf =
418 (uint16_t __iomem *)host->regs->main_area0;
419 uint16_t __iomem *spare_buf =
420 (uint16_t __iomem *)host->regs->spare_area0;
426 /* Check for status request */
427 if (host->status_request)
428 return get_dev_status(host) & 0xFF;
430 /* Get column for 16-bit access */
431 col = host->col_addr >> 1;
433 /* If we are accessing the spare region */
434 if (host->spare_only)
435 nfc_word.word = readw(&spare_buf[col]);
437 nfc_word.word = readw(&main_buf[col]);
439 /* Pick upper/lower byte of word from RAM buffer */
440 ret = nfc_word.bytes[host->col_addr & 0x1];
442 /* Update saved column address */
443 if (nand_chip->options & NAND_BUSWIDTH_16)
451 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
453 struct nand_chip *nand_chip = mtd->priv;
454 struct mxc_nand_host *host = nand_chip->priv;
458 MTDDEBUG(MTD_DEBUG_LEVEL3,
459 "mxc_nand_read_word(col = %d)\n", host->col_addr);
461 col = host->col_addr;
462 /* Adjust saved column address */
463 if (col < mtd->writesize && host->spare_only)
464 col += mtd->writesize;
466 if (col < mtd->writesize) {
467 p = (uint16_t __iomem *)(host->regs->main_area0 + (col >> 1));
469 p = (uint16_t __iomem *)(host->regs->spare_area0 +
470 ((col - mtd->writesize) >> 1));
479 nfc_word[0].word = readw(p);
480 nfc_word[1].word = readw(p + 1);
482 nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
483 nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
485 ret = nfc_word[2].word;
490 /* Update saved column address */
491 host->col_addr = col + 2;
497 * Write data of length len to buffer buf. The data to be
498 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
499 * Operation by the NFC, the data is written to NAND Flash
501 static void mxc_nand_write_buf(struct mtd_info *mtd,
502 const u_char *buf, int len)
504 struct nand_chip *nand_chip = mtd->priv;
505 struct mxc_nand_host *host = nand_chip->priv;
508 MTDDEBUG(MTD_DEBUG_LEVEL3,
509 "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
512 col = host->col_addr;
514 /* Adjust saved column address */
515 if (col < mtd->writesize && host->spare_only)
516 col += mtd->writesize;
518 n = mtd->writesize + mtd->oobsize - col;
521 MTDDEBUG(MTD_DEBUG_LEVEL3,
522 "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
527 if (col < mtd->writesize) {
528 p = host->regs->main_area0 + (col & ~3);
530 p = host->regs->spare_area0 -
531 mtd->writesize + (col & ~3);
534 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
537 if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
543 nfc_word.word = readl(p);
544 nfc_word.bytes[col & 3] = buf[i++];
548 writel(nfc_word.word, p);
550 int m = mtd->writesize - col;
552 if (col >= mtd->writesize)
557 MTDDEBUG(MTD_DEBUG_LEVEL3,
558 "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
559 __func__, __LINE__, n, m, i, col);
561 mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
567 /* Update saved column address */
568 host->col_addr = col;
572 * Read the data buffer from the NAND Flash. To read the data from NAND
573 * Flash first the data output cycle is initiated by the NFC, which copies
574 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
576 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
578 struct nand_chip *nand_chip = mtd->priv;
579 struct mxc_nand_host *host = nand_chip->priv;
582 MTDDEBUG(MTD_DEBUG_LEVEL3,
583 "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
585 col = host->col_addr;
587 /* Adjust saved column address */
588 if (col < mtd->writesize && host->spare_only)
589 col += mtd->writesize;
591 n = mtd->writesize + mtd->oobsize - col;
597 if (col < mtd->writesize) {
598 p = host->regs->main_area0 + (col & ~3);
600 p = host->regs->spare_area0 -
601 mtd->writesize + (col & ~3);
604 if (((col | (int)&buf[i]) & 3) || n < 4) {
610 nfc_word.word = readl(p);
611 buf[i++] = nfc_word.bytes[col & 3];
615 int m = mtd->writesize - col;
617 if (col >= mtd->writesize)
621 mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
628 /* Update saved column address */
629 host->col_addr = col;
633 * Used by the upper layer to verify the data in NAND Flash
634 * with the data in the buf.
636 static int mxc_nand_verify_buf(struct mtd_info *mtd,
637 const u_char *buf, int len)
643 bsize = min(len, 256);
644 mxc_nand_read_buf(mtd, tmp, bsize);
646 if (memcmp(buf, tmp, bsize))
657 * This function is used by upper layer for select and
658 * deselect of the NAND chip
660 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
662 struct nand_chip *nand_chip = mtd->priv;
663 struct mxc_nand_host *host = nand_chip->priv;
667 /* TODO: Disable the NFC clock */
672 /* TODO: Enable the NFC clock */
683 * Used by the upper layer to write command to NAND Flash for
684 * different operations to be carried out on NAND Flash
686 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
687 int column, int page_addr)
689 struct nand_chip *nand_chip = mtd->priv;
690 struct mxc_nand_host *host = nand_chip->priv;
692 MTDDEBUG(MTD_DEBUG_LEVEL3,
693 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
694 command, column, page_addr);
696 /* Reset command state information */
697 host->status_request = false;
699 /* Command pre-processing step */
702 case NAND_CMD_STATUS:
704 host->status_request = true;
708 host->col_addr = column;
709 host->spare_only = false;
712 case NAND_CMD_READOOB:
713 host->col_addr = column;
714 host->spare_only = true;
715 if (host->pagesize_2k)
716 command = NAND_CMD_READ0; /* only READ0 is valid */
720 if (column >= mtd->writesize) {
722 * before sending SEQIN command for partial write,
723 * we need read one page out. FSL NFC does not support
724 * partial write. It alway send out 512+ecc+512+ecc ...
725 * for large page nand flash. But for small page nand
726 * flash, it does support SPARE ONLY operation.
728 if (host->pagesize_2k) {
729 /* call ourself to read a page */
730 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
734 host->col_addr = column - mtd->writesize;
735 host->spare_only = true;
737 /* Set program pointer to spare region */
738 if (!host->pagesize_2k)
739 send_cmd(host, NAND_CMD_READOOB);
741 host->spare_only = false;
742 host->col_addr = column;
744 /* Set program pointer to page start */
745 if (!host->pagesize_2k)
746 send_cmd(host, NAND_CMD_READ0);
750 case NAND_CMD_PAGEPROG:
751 send_prog_page(host, 0, host->spare_only);
753 if (host->pagesize_2k) {
754 /* data in 4 areas datas */
755 send_prog_page(host, 1, host->spare_only);
756 send_prog_page(host, 2, host->spare_only);
757 send_prog_page(host, 3, host->spare_only);
763 /* Write out the command to the device. */
764 send_cmd(host, command);
766 /* Write out column address, if necessary */
769 * MXC NANDFC can only perform full page+spare or
770 * spare-only read/write. When the upper layers
771 * layers perform a read/write buf operation,
772 * we will used the saved column adress to index into
776 if (host->pagesize_2k)
777 /* another col addr cycle for 2k page */
781 /* Write out page address, if necessary */
782 if (page_addr != -1) {
783 /* paddr_0 - p_addr_7 */
784 send_addr(host, (page_addr & 0xff));
786 if (host->pagesize_2k) {
787 send_addr(host, (page_addr >> 8) & 0xFF);
788 if (mtd->size >= 0x10000000) {
789 /* paddr_8 - paddr_15 */
790 send_addr(host, (page_addr >> 8) & 0xff);
791 send_addr(host, (page_addr >> 16) & 0xff);
793 /* paddr_8 - paddr_15 */
794 send_addr(host, (page_addr >> 8) & 0xff);
797 /* One more address cycle for higher density devices */
798 if (mtd->size >= 0x4000000) {
799 /* paddr_8 - paddr_15 */
800 send_addr(host, (page_addr >> 8) & 0xff);
801 send_addr(host, (page_addr >> 16) & 0xff);
803 /* paddr_8 - paddr_15 */
804 send_addr(host, (page_addr >> 8) & 0xff);
809 /* Command post-processing step */
815 case NAND_CMD_READOOB:
817 if (host->pagesize_2k) {
818 /* send read confirm command */
819 send_cmd(host, NAND_CMD_READSTART);
820 /* read for each AREA */
821 send_read_page(host, 0, host->spare_only);
822 send_read_page(host, 1, host->spare_only);
823 send_read_page(host, 2, host->spare_only);
824 send_read_page(host, 3, host->spare_only);
826 send_read_page(host, 0, host->spare_only);
830 case NAND_CMD_READID:
835 case NAND_CMD_PAGEPROG:
838 case NAND_CMD_STATUS:
841 case NAND_CMD_ERASE2:
846 int board_nand_init(struct nand_chip *this)
848 struct mtd_info *mtd;
852 /* structures must be linked */
857 /* 5 us command delay time */
858 this->chip_delay = 5;
861 this->dev_ready = mxc_nand_dev_ready;
862 this->cmdfunc = mxc_nand_command;
863 this->select_chip = mxc_nand_select_chip;
864 this->read_byte = mxc_nand_read_byte;
865 this->read_word = mxc_nand_read_word;
866 this->write_buf = mxc_nand_write_buf;
867 this->read_buf = mxc_nand_read_buf;
868 this->verify_buf = mxc_nand_verify_buf;
870 host->regs = (struct nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
873 #ifdef CONFIG_MXC_NAND_HWECC
874 this->ecc.calculate = mxc_nand_calculate_ecc;
875 this->ecc.hwctl = mxc_nand_enable_hwecc;
876 this->ecc.correct = mxc_nand_correct_data;
877 this->ecc.mode = NAND_ECC_HW;
878 this->ecc.size = 512;
880 this->ecc.layout = &nand_hw_eccoob;
881 tmp = readw(&host->regs->nfc_config1);
883 writew(tmp, &host->regs->nfc_config1);
885 this->ecc.layout = &nand_soft_eccoob;
886 this->ecc.mode = NAND_ECC_SOFT;
887 tmp = readw(&host->regs->nfc_config1);
889 writew(tmp, &host->regs->nfc_config1);
893 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
897 * Unlock the internal RAM Buffer
899 writew(0x2, &host->regs->nfc_config);
901 /* Blocks to be unlocked */
902 writew(0x0, &host->regs->nfc_unlockstart_blkaddr);
903 writew(0x4000, &host->regs->nfc_unlockend_blkaddr);
905 /* Unlock Block Command for given address range */
906 writew(0x4, &host->regs->nfc_wrprot);
908 /* NAND bus width determines access funtions used by upper layer */
910 this->options |= NAND_BUSWIDTH_16;
912 #ifdef CONFIG_SYS_NAND_LARGEPAGE
913 host->pagesize_2k = 1;
914 this->ecc.layout = &nand_hw_eccoob_largepage;
916 host->pagesize_2k = 0;