2 * Copyright 2004-2007 Freescale Semiconductor, Inc.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
23 #include <linux/err.h>
26 #include <asm/arch/imx-regs.h>
29 #define DRIVER_NAME "mxc_nand"
32 /* NFC RAM BUFFER Main area 0 */
33 uint8_t main_area0[0x200];
34 uint8_t main_area1[0x200];
35 uint8_t main_area2[0x200];
36 uint8_t main_area3[0x200];
37 /* SPARE BUFFER Spare area 0 */
38 uint8_t spare_area0[0x10];
39 uint8_t spare_area1[0x10];
40 uint8_t spare_area2[0x10];
41 uint8_t spare_area3[0x10];
44 uint16_t nfc_buf_size;
46 uint16_t nfc_buf_addr;
47 uint16_t nfc_flash_addr;
48 uint16_t nfc_flash_cmd;
50 uint16_t nfc_ecc_status_result;
51 uint16_t nfc_rsltmain_area;
52 uint16_t nfc_rsltspare_area;
54 uint16_t nfc_unlockstart_blkaddr;
55 uint16_t nfc_unlockend_blkaddr;
56 uint16_t nfc_nf_wrprst;
62 * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
63 * for Command operation
68 * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
69 * for Address operation
74 * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
80 * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
81 * for Data Output operation
83 #define NFC_OUTPUT 0x8
86 * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
87 * for Read ID operation
92 * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
93 * for Read Status operation
95 #define NFC_STATUS 0x20
98 * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
101 #define NFC_INT 0x8000
103 #define NFC_SP_EN (1 << 2)
104 #define NFC_ECC_EN (1 << 3)
105 #define NFC_BIG (1 << 5)
106 #define NFC_RST (1 << 6)
107 #define NFC_CE (1 << 7)
108 #define NFC_ONE_CYCLE (1 << 8)
110 typedef enum {false, true} bool;
112 struct mxc_nand_host {
114 struct nand_chip *nand;
116 struct nfc_regs __iomem *regs;
124 static struct mxc_nand_host mxc_host;
125 static struct mxc_nand_host *host = &mxc_host;
127 /* Define delays in microsec for NAND device operations */
128 #define TROP_US_DELAY 2000
129 /* Macros to get byte and bit positions of ECC */
130 #define COLPOS(x) ((x) >> 3)
131 #define BITPOS(x) ((x) & 0xf)
133 /* Define single bit Error positions in Main & Spare area */
134 #define MAIN_SINGLEBIT_ERROR 0x4
135 #define SPARE_SINGLEBIT_ERROR 0x1
137 /* OOB placement block for use with hardware ecc generation */
138 #ifdef CONFIG_MXC_NAND_HWECC
139 static struct nand_ecclayout nand_hw_eccoob = {
141 .eccpos = {6, 7, 8, 9, 10},
142 .oobfree = {{0, 5}, {11, 5}, }
145 static struct nand_ecclayout nand_soft_eccoob = {
147 .eccpos = {6, 7, 8, 9, 10, 11},
148 .oobfree = {{0, 5}, {12, 4}, }
153 static int is_16bit_nand(void)
155 struct system_control_regs *sc_regs =
156 (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
158 if (readl(&sc_regs->fmcr) & NF_16BIT_SEL)
163 #elif defined(CONFIG_MX31)
164 static int is_16bit_nand(void)
166 struct clock_control_regs *sc_regs =
167 (struct clock_control_regs *)CCM_BASE;
169 if (readl(&sc_regs->rcsr) & CCM_RCSR_NF16B)
175 #warning "8/16 bit NAND autodetection not supported"
176 static int is_16bit_nand(void)
182 static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
188 __raw_writel(__raw_readl(source++), d++);
193 * This function polls the NANDFC to wait for the basic operation to
194 * complete by checking the INT bit of config2 register.
196 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
201 while (max_retries-- > 0) {
202 if (readw(&host->regs->nfc_config2) & NFC_INT) {
203 tmp = readw(&host->regs->nfc_config2);
205 writew(tmp, &host->regs->nfc_config2);
210 if (max_retries < 0) {
211 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
217 * This function issues the specified command to the NAND device and
218 * waits for completion.
220 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
222 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
224 writew(cmd, &host->regs->nfc_flash_cmd);
225 writew(NFC_CMD, &host->regs->nfc_config2);
227 /* Wait for operation to complete */
228 wait_op_done(host, TROP_US_DELAY, cmd);
232 * This function sends an address (or partial address) to the
233 * NAND device. The address is used to select the source/destination for
236 static void send_addr(struct mxc_nand_host *host, uint16_t addr)
238 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
240 writew(addr, &host->regs->nfc_flash_addr);
241 writew(NFC_ADDR, &host->regs->nfc_config2);
243 /* Wait for operation to complete */
244 wait_op_done(host, TROP_US_DELAY, addr);
248 * This function requests the NANDFC to initate the transfer
249 * of data currently in the NANDFC RAM buffer to the NAND device.
251 static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
254 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", spare_only);
256 writew(buf_id, &host->regs->nfc_buf_addr);
258 /* Configure spare or page+spare access */
259 if (!host->pagesize_2k) {
260 uint16_t config1 = readw(&host->regs->nfc_config1);
262 config1 |= NFC_SP_EN;
264 config1 &= ~(NFC_SP_EN);
265 writew(config1, &host->regs->nfc_config1);
268 writew(NFC_INPUT, &host->regs->nfc_config2);
270 /* Wait for operation to complete */
271 wait_op_done(host, TROP_US_DELAY, spare_only);
275 * Requests NANDFC to initated the transfer of data from the
276 * NAND device into in the NANDFC ram buffer.
278 static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
281 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
283 writew(buf_id, &host->regs->nfc_buf_addr);
285 /* Configure spare or page+spare access */
286 if (!host->pagesize_2k) {
287 uint32_t config1 = readw(&host->regs->nfc_config1);
289 config1 |= NFC_SP_EN;
291 config1 &= ~NFC_SP_EN;
292 writew(config1, &host->regs->nfc_config1);
295 writew(NFC_OUTPUT, &host->regs->nfc_config2);
297 /* Wait for operation to complete */
298 wait_op_done(host, TROP_US_DELAY, spare_only);
301 /* Request the NANDFC to perform a read of the NAND device ID. */
302 static void send_read_id(struct mxc_nand_host *host)
306 /* NANDFC buffer 0 is used for device ID output */
307 writew(0x0, &host->regs->nfc_buf_addr);
309 /* Read ID into main buffer */
310 tmp = readw(&host->regs->nfc_config1);
312 writew(tmp, &host->regs->nfc_config1);
314 writew(NFC_ID, &host->regs->nfc_config2);
316 /* Wait for operation to complete */
317 wait_op_done(host, TROP_US_DELAY, 0);
321 * This function requests the NANDFC to perform a read of the
322 * NAND device status and returns the current status.
324 static uint16_t get_dev_status(struct mxc_nand_host *host)
326 void __iomem *main_buf = host->regs->main_area1;
329 /* Issue status request to NAND device */
331 /* store the main area1 first word, later do recovery */
332 store = readl(main_buf);
333 /* NANDFC buffer 1 is used for device status */
334 writew(1, &host->regs->nfc_buf_addr);
336 /* Read status into main buffer */
337 tmp = readw(&host->regs->nfc_config1);
339 writew(tmp, &host->regs->nfc_config1);
341 writew(NFC_STATUS, &host->regs->nfc_config2);
343 /* Wait for operation to complete */
344 wait_op_done(host, TROP_US_DELAY, 0);
347 * Status is placed in first word of main buffer
348 * get status, then recovery area 1 data
350 ret = readw(main_buf);
351 writel(store, main_buf);
356 /* This function is used by upper layer to checks if device is ready */
357 static int mxc_nand_dev_ready(struct mtd_info *mtd)
360 * NFC handles R/B internally. Therefore, this function
361 * always returns status as ready.
366 #ifdef CONFIG_MXC_NAND_HWECC
367 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
370 * If HW ECC is enabled, we turn it on during init. There is
371 * no need to enable again here.
375 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
376 u_char *read_ecc, u_char *calc_ecc)
378 struct nand_chip *nand_chip = mtd->priv;
379 struct mxc_nand_host *host = nand_chip->priv;
382 * 1-Bit errors are automatically corrected in HW. No need for
383 * additional correction. 2-Bit errors cannot be corrected by
384 * HW ECC, so we need to return failure
386 uint16_t ecc_status = readw(&host->regs->nfc_ecc_status_result);
388 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
389 MTDDEBUG(MTD_DEBUG_LEVEL0,
390 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
397 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
404 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
406 struct nand_chip *nand_chip = mtd->priv;
407 struct mxc_nand_host *host = nand_chip->priv;
410 uint16_t __iomem *main_buf =
411 (uint16_t __iomem *)host->regs->main_area0;
412 uint16_t __iomem *spare_buf =
413 (uint16_t __iomem *)host->regs->spare_area0;
419 /* Check for status request */
420 if (host->status_request)
421 return get_dev_status(host) & 0xFF;
423 /* Get column for 16-bit access */
424 col = host->col_addr >> 1;
426 /* If we are accessing the spare region */
427 if (host->spare_only)
428 nfc_word.word = readw(&spare_buf[col]);
430 nfc_word.word = readw(&main_buf[col]);
432 /* Pick upper/lower byte of word from RAM buffer */
433 ret = nfc_word.bytes[host->col_addr & 0x1];
435 /* Update saved column address */
436 if (nand_chip->options & NAND_BUSWIDTH_16)
444 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
446 struct nand_chip *nand_chip = mtd->priv;
447 struct mxc_nand_host *host = nand_chip->priv;
451 MTDDEBUG(MTD_DEBUG_LEVEL3,
452 "mxc_nand_read_word(col = %d)\n", host->col_addr);
454 col = host->col_addr;
455 /* Adjust saved column address */
456 if (col < mtd->writesize && host->spare_only)
457 col += mtd->writesize;
459 if (col < mtd->writesize) {
460 p = (uint16_t __iomem *)(host->regs->main_area0 + (col >> 1));
462 p = (uint16_t __iomem *)(host->regs->spare_area0 +
463 ((col - mtd->writesize) >> 1));
472 nfc_word[0].word = readw(p);
473 nfc_word[1].word = readw(p + 1);
475 nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
476 nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
478 ret = nfc_word[2].word;
483 /* Update saved column address */
484 host->col_addr = col + 2;
490 * Write data of length len to buffer buf. The data to be
491 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
492 * Operation by the NFC, the data is written to NAND Flash
494 static void mxc_nand_write_buf(struct mtd_info *mtd,
495 const u_char *buf, int len)
497 struct nand_chip *nand_chip = mtd->priv;
498 struct mxc_nand_host *host = nand_chip->priv;
501 MTDDEBUG(MTD_DEBUG_LEVEL3,
502 "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
505 col = host->col_addr;
507 /* Adjust saved column address */
508 if (col < mtd->writesize && host->spare_only)
509 col += mtd->writesize;
511 n = mtd->writesize + mtd->oobsize - col;
514 MTDDEBUG(MTD_DEBUG_LEVEL3,
515 "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
520 if (col < mtd->writesize) {
521 p = host->regs->main_area0 + (col & ~3);
523 p = host->regs->spare_area0 -
524 mtd->writesize + (col & ~3);
527 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
530 if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
536 nfc_word.word = readl(p);
537 nfc_word.bytes[col & 3] = buf[i++];
541 writel(nfc_word.word, p);
543 int m = mtd->writesize - col;
545 if (col >= mtd->writesize)
550 MTDDEBUG(MTD_DEBUG_LEVEL3,
551 "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
552 __func__, __LINE__, n, m, i, col);
554 mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
560 /* Update saved column address */
561 host->col_addr = col;
565 * Read the data buffer from the NAND Flash. To read the data from NAND
566 * Flash first the data output cycle is initiated by the NFC, which copies
567 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
569 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
571 struct nand_chip *nand_chip = mtd->priv;
572 struct mxc_nand_host *host = nand_chip->priv;
575 MTDDEBUG(MTD_DEBUG_LEVEL3,
576 "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
578 col = host->col_addr;
580 /* Adjust saved column address */
581 if (col < mtd->writesize && host->spare_only)
582 col += mtd->writesize;
584 n = mtd->writesize + mtd->oobsize - col;
590 if (col < mtd->writesize) {
591 p = host->regs->main_area0 + (col & ~3);
593 p = host->regs->spare_area0 -
594 mtd->writesize + (col & ~3);
597 if (((col | (int)&buf[i]) & 3) || n < 4) {
603 nfc_word.word = readl(p);
604 buf[i++] = nfc_word.bytes[col & 3];
608 int m = mtd->writesize - col;
610 if (col >= mtd->writesize)
614 mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
621 /* Update saved column address */
622 host->col_addr = col;
626 * Used by the upper layer to verify the data in NAND Flash
627 * with the data in the buf.
629 static int mxc_nand_verify_buf(struct mtd_info *mtd,
630 const u_char *buf, int len)
636 bsize = min(len, 256);
637 mxc_nand_read_buf(mtd, tmp, bsize);
639 if (memcmp(buf, tmp, bsize))
650 * This function is used by upper layer for select and
651 * deselect of the NAND chip
653 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
655 struct nand_chip *nand_chip = mtd->priv;
656 struct mxc_nand_host *host = nand_chip->priv;
660 /* TODO: Disable the NFC clock */
665 /* TODO: Enable the NFC clock */
676 * Used by the upper layer to write command to NAND Flash for
677 * different operations to be carried out on NAND Flash
679 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
680 int column, int page_addr)
682 struct nand_chip *nand_chip = mtd->priv;
683 struct mxc_nand_host *host = nand_chip->priv;
685 MTDDEBUG(MTD_DEBUG_LEVEL3,
686 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
687 command, column, page_addr);
689 /* Reset command state information */
690 host->status_request = false;
692 /* Command pre-processing step */
695 case NAND_CMD_STATUS:
697 host->status_request = true;
701 host->col_addr = column;
702 host->spare_only = false;
705 case NAND_CMD_READOOB:
706 host->col_addr = column;
707 host->spare_only = true;
708 if (host->pagesize_2k)
709 command = NAND_CMD_READ0; /* only READ0 is valid */
713 if (column >= mtd->writesize) {
715 * before sending SEQIN command for partial write,
716 * we need read one page out. FSL NFC does not support
717 * partial write. It alway send out 512+ecc+512+ecc ...
718 * for large page nand flash. But for small page nand
719 * flash, it does support SPARE ONLY operation.
721 if (host->pagesize_2k) {
722 /* call ourself to read a page */
723 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
727 host->col_addr = column - mtd->writesize;
728 host->spare_only = true;
730 /* Set program pointer to spare region */
731 if (!host->pagesize_2k)
732 send_cmd(host, NAND_CMD_READOOB);
734 host->spare_only = false;
735 host->col_addr = column;
737 /* Set program pointer to page start */
738 if (!host->pagesize_2k)
739 send_cmd(host, NAND_CMD_READ0);
743 case NAND_CMD_PAGEPROG:
744 send_prog_page(host, 0, host->spare_only);
746 if (host->pagesize_2k) {
747 /* data in 4 areas datas */
748 send_prog_page(host, 1, host->spare_only);
749 send_prog_page(host, 2, host->spare_only);
750 send_prog_page(host, 3, host->spare_only);
756 /* Write out the command to the device. */
757 send_cmd(host, command);
759 /* Write out column address, if necessary */
762 * MXC NANDFC can only perform full page+spare or
763 * spare-only read/write. When the upper layers
764 * layers perform a read/write buf operation,
765 * we will used the saved column adress to index into
769 if (host->pagesize_2k)
770 /* another col addr cycle for 2k page */
774 /* Write out page address, if necessary */
775 if (page_addr != -1) {
776 /* paddr_0 - p_addr_7 */
777 send_addr(host, (page_addr & 0xff));
779 if (host->pagesize_2k) {
780 send_addr(host, (page_addr >> 8) & 0xFF);
781 if (mtd->size >= 0x10000000) {
782 /* paddr_8 - paddr_15 */
783 send_addr(host, (page_addr >> 8) & 0xff);
784 send_addr(host, (page_addr >> 16) & 0xff);
786 /* paddr_8 - paddr_15 */
787 send_addr(host, (page_addr >> 8) & 0xff);
790 /* One more address cycle for higher density devices */
791 if (mtd->size >= 0x4000000) {
792 /* paddr_8 - paddr_15 */
793 send_addr(host, (page_addr >> 8) & 0xff);
794 send_addr(host, (page_addr >> 16) & 0xff);
796 /* paddr_8 - paddr_15 */
797 send_addr(host, (page_addr >> 8) & 0xff);
802 /* Command post-processing step */
808 case NAND_CMD_READOOB:
810 if (host->pagesize_2k) {
811 /* send read confirm command */
812 send_cmd(host, NAND_CMD_READSTART);
813 /* read for each AREA */
814 send_read_page(host, 0, host->spare_only);
815 send_read_page(host, 1, host->spare_only);
816 send_read_page(host, 2, host->spare_only);
817 send_read_page(host, 3, host->spare_only);
819 send_read_page(host, 0, host->spare_only);
823 case NAND_CMD_READID:
828 case NAND_CMD_PAGEPROG:
831 case NAND_CMD_STATUS:
834 case NAND_CMD_ERASE2:
839 int board_nand_init(struct nand_chip *this)
841 struct mtd_info *mtd;
845 /* structures must be linked */
850 /* 5 us command delay time */
851 this->chip_delay = 5;
854 this->dev_ready = mxc_nand_dev_ready;
855 this->cmdfunc = mxc_nand_command;
856 this->select_chip = mxc_nand_select_chip;
857 this->read_byte = mxc_nand_read_byte;
858 this->read_word = mxc_nand_read_word;
859 this->write_buf = mxc_nand_write_buf;
860 this->read_buf = mxc_nand_read_buf;
861 this->verify_buf = mxc_nand_verify_buf;
863 host->regs = (struct nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
866 #ifdef CONFIG_MXC_NAND_HWECC
867 this->ecc.calculate = mxc_nand_calculate_ecc;
868 this->ecc.hwctl = mxc_nand_enable_hwecc;
869 this->ecc.correct = mxc_nand_correct_data;
870 this->ecc.mode = NAND_ECC_HW;
871 this->ecc.size = 512;
873 this->ecc.layout = &nand_hw_eccoob;
874 tmp = readw(&host->regs->nfc_config1);
876 writew(tmp, &host->regs->nfc_config1);
878 this->ecc.layout = &nand_soft_eccoob;
879 this->ecc.mode = NAND_ECC_SOFT;
880 tmp = readw(&host->regs->nfc_config1);
882 writew(tmp, &host->regs->nfc_config1);
886 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
890 * Unlock the internal RAM Buffer
892 writew(0x2, &host->regs->nfc_config);
894 /* Blocks to be unlocked */
895 writew(0x0, &host->regs->nfc_unlockstart_blkaddr);
896 writew(0x4000, &host->regs->nfc_unlockend_blkaddr);
898 /* Unlock Block Command for given address range */
899 writew(0x4, &host->regs->nfc_wrprot);
901 /* NAND bus width determines access funtions used by upper layer */
903 this->options |= NAND_BUSWIDTH_16;
905 host->pagesize_2k = 0;