5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
8 * Additional technical information is available on
9 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
12 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
15 * David Woodhouse for adding multichip support
17 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
18 * rework for 2K page size chips
21 * Enable cached programming for 2k page size chips
22 * Check, if mtd->ecctype should be set to MTD_ECC_HW
23 * if we have HW ECC support.
24 * BBT table is not serialized, has to be fixed
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License version 2 as
28 * published by the Free Software Foundation.
33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
35 #include <linux/module.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/err.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/mtd/mtd.h>
43 #include <linux/mtd/nand.h>
44 #include <linux/mtd/nand_ecc.h>
45 #include <linux/mtd/nand_bch.h>
46 #include <linux/interrupt.h>
47 #include <linux/bitops.h>
48 #include <linux/leds.h>
50 #include <linux/mtd/partitions.h>
52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
56 #include <linux/err.h>
57 #include <linux/compat.h>
58 #include <linux/mtd/mtd.h>
59 #include <linux/mtd/nand.h>
60 #include <linux/mtd/nand_ecc.h>
61 #include <linux/mtd/nand_bch.h>
62 #ifdef CONFIG_MTD_PARTITIONS
63 #include <linux/mtd/partitions.h>
66 #include <asm/errno.h>
69 * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
70 * a flash. NAND flash is initialized prior to interrupts so standard timers
71 * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
72 * which is greater than (max NAND reset time / NAND status read time).
73 * A conservative default of 200000 (500 us / 25 ns) is used as a default.
75 #ifndef CONFIG_SYS_NAND_RESET_CNT
76 #define CONFIG_SYS_NAND_RESET_CNT 200000
79 static bool is_module_text_address(unsigned long addr) {return 0;}
82 /* Define default oob placement schemes for large and small page devices */
83 static struct nand_ecclayout nand_oob_8 = {
93 static struct nand_ecclayout nand_oob_16 = {
95 .eccpos = {0, 1, 2, 3, 6, 7},
101 static struct nand_ecclayout nand_oob_64 = {
104 40, 41, 42, 43, 44, 45, 46, 47,
105 48, 49, 50, 51, 52, 53, 54, 55,
106 56, 57, 58, 59, 60, 61, 62, 63},
112 static struct nand_ecclayout nand_oob_128 = {
115 80, 81, 82, 83, 84, 85, 86, 87,
116 88, 89, 90, 91, 92, 93, 94, 95,
117 96, 97, 98, 99, 100, 101, 102, 103,
118 104, 105, 106, 107, 108, 109, 110, 111,
119 112, 113, 114, 115, 116, 117, 118, 119,
120 120, 121, 122, 123, 124, 125, 126, 127},
126 static int nand_get_device(struct mtd_info *mtd, int new_state);
128 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
129 struct mtd_oob_ops *ops);
132 * For devices which display every fart in the system on a separate LED. Is
133 * compiled away when LED support is disabled.
135 DEFINE_LED_TRIGGER(nand_led_trigger);
137 static int check_offs_len(struct mtd_info *mtd,
138 loff_t ofs, uint64_t len)
140 struct nand_chip *chip = mtd->priv;
143 /* Start address must align on block boundary */
144 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
145 pr_debug("%s: unaligned address\n", __func__);
149 /* Length must align on block boundary */
150 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
151 pr_debug("%s: length not block aligned\n", __func__);
159 * nand_release_device - [GENERIC] release chip
160 * @mtd: MTD device structure
162 * Release chip lock and wake up anyone waiting on the device.
164 static void nand_release_device(struct mtd_info *mtd)
166 struct nand_chip *chip = mtd->priv;
169 /* Release the controller and the chip */
170 spin_lock(&chip->controller->lock);
171 chip->controller->active = NULL;
172 chip->state = FL_READY;
173 wake_up(&chip->controller->wq);
174 spin_unlock(&chip->controller->lock);
176 /* De-select the NAND device */
177 chip->select_chip(mtd, -1);
182 * nand_read_byte - [DEFAULT] read one byte from the chip
183 * @mtd: MTD device structure
185 * Default read function for 8bit buswidth
188 static uint8_t nand_read_byte(struct mtd_info *mtd)
190 uint8_t nand_read_byte(struct mtd_info *mtd)
193 struct nand_chip *chip = mtd->priv;
194 return readb(chip->IO_ADDR_R);
198 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
199 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
200 * @mtd: MTD device structure
202 * Default read function for 16bit buswidth with endianness conversion.
205 static uint8_t nand_read_byte16(struct mtd_info *mtd)
207 struct nand_chip *chip = mtd->priv;
208 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
212 * nand_read_word - [DEFAULT] read one word from the chip
213 * @mtd: MTD device structure
215 * Default read function for 16bit buswidth without endianness conversion.
217 static u16 nand_read_word(struct mtd_info *mtd)
219 struct nand_chip *chip = mtd->priv;
220 return readw(chip->IO_ADDR_R);
224 * nand_select_chip - [DEFAULT] control CE line
225 * @mtd: MTD device structure
226 * @chipnr: chipnumber to select, -1 for deselect
228 * Default select function for 1 chip devices.
230 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
232 struct nand_chip *chip = mtd->priv;
236 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
247 * nand_write_byte - [DEFAULT] write single byte to chip
248 * @mtd: MTD device structure
249 * @byte: value to write
251 * Default function to write a byte to I/O[7:0]
253 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
255 struct nand_chip *chip = mtd->priv;
257 chip->write_buf(mtd, &byte, 1);
261 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
262 * @mtd: MTD device structure
263 * @byte: value to write
265 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
267 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
269 struct nand_chip *chip = mtd->priv;
270 uint16_t word = byte;
273 * It's not entirely clear what should happen to I/O[15:8] when writing
274 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
276 * When the host supports a 16-bit bus width, only data is
277 * transferred at the 16-bit width. All address and command line
278 * transfers shall use only the lower 8-bits of the data bus. During
279 * command transfers, the host may place any value on the upper
280 * 8-bits of the data bus. During address transfers, the host shall
281 * set the upper 8-bits of the data bus to 00h.
283 * One user of the write_byte callback is nand_onfi_set_features. The
284 * four parameters are specified to be written to I/O[7:0], but this is
285 * neither an address nor a command transfer. Let's assume a 0 on the
286 * upper I/O lines is OK.
288 chip->write_buf(mtd, (uint8_t *)&word, 2);
291 #if defined(__UBOOT__) && !defined(CONFIG_BLACKFIN)
292 static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
296 for (i = 0; i < len; i++)
297 writeb(buf[i], addr);
299 static void ioread8_rep(void *addr, uint8_t *buf, int len)
303 for (i = 0; i < len; i++)
304 buf[i] = readb(addr);
307 static void ioread16_rep(void *addr, void *buf, int len)
310 u16 *p = (u16 *) buf;
312 for (i = 0; i < len; i++)
316 static void iowrite16_rep(void *addr, void *buf, int len)
319 u16 *p = (u16 *) buf;
321 for (i = 0; i < len; i++)
327 * nand_write_buf - [DEFAULT] write buffer to chip
328 * @mtd: MTD device structure
330 * @len: number of bytes to write
332 * Default write function for 8bit buswidth.
335 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
337 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
340 struct nand_chip *chip = mtd->priv;
342 iowrite8_rep(chip->IO_ADDR_W, buf, len);
346 * nand_read_buf - [DEFAULT] read chip data into buffer
347 * @mtd: MTD device structure
348 * @buf: buffer to store date
349 * @len: number of bytes to read
351 * Default read function for 8bit buswidth.
354 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
356 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
359 struct nand_chip *chip = mtd->priv;
361 ioread8_rep(chip->IO_ADDR_R, buf, len);
365 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
367 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
368 * @mtd: MTD device structure
369 * @buf: buffer containing the data to compare
370 * @len: number of bytes to compare
372 * Default verify function for 8bit buswidth.
374 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
377 struct nand_chip *chip = mtd->priv;
379 for (i = 0; i < len; i++)
380 if (buf[i] != readb(chip->IO_ADDR_R))
386 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
387 * @mtd: MTD device structure
388 * @buf: buffer containing the data to compare
389 * @len: number of bytes to compare
391 * Default verify function for 16bit buswidth.
393 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
396 struct nand_chip *chip = mtd->priv;
397 u16 *p = (u16 *) buf;
400 for (i = 0; i < len; i++)
401 if (p[i] != readw(chip->IO_ADDR_R))
410 * nand_write_buf16 - [DEFAULT] write buffer to chip
411 * @mtd: MTD device structure
413 * @len: number of bytes to write
415 * Default write function for 16bit buswidth.
418 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
420 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
423 struct nand_chip *chip = mtd->priv;
424 u16 *p = (u16 *) buf;
426 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
430 * nand_read_buf16 - [DEFAULT] read chip data into buffer
431 * @mtd: MTD device structure
432 * @buf: buffer to store date
433 * @len: number of bytes to read
435 * Default read function for 16bit buswidth.
438 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
440 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
443 struct nand_chip *chip = mtd->priv;
444 u16 *p = (u16 *) buf;
446 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
450 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
451 * @mtd: MTD device structure
452 * @ofs: offset from device start
453 * @getchip: 0, if the chip is already selected
455 * Check, if the block is bad.
457 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
459 int page, chipnr, res = 0, i = 0;
460 struct nand_chip *chip = mtd->priv;
463 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
464 ofs += mtd->erasesize - mtd->writesize;
466 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
469 chipnr = (int)(ofs >> chip->chip_shift);
471 nand_get_device(mtd, FL_READING);
473 /* Select the NAND device */
474 chip->select_chip(mtd, chipnr);
478 if (chip->options & NAND_BUSWIDTH_16) {
479 chip->cmdfunc(mtd, NAND_CMD_READOOB,
480 chip->badblockpos & 0xFE, page);
481 bad = cpu_to_le16(chip->read_word(mtd));
482 if (chip->badblockpos & 0x1)
487 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
489 bad = chip->read_byte(mtd);
492 if (likely(chip->badblockbits == 8))
495 res = hweight8(bad) < chip->badblockbits;
496 ofs += mtd->writesize;
497 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
499 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
502 chip->select_chip(mtd, -1);
503 nand_release_device(mtd);
510 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
511 * @mtd: MTD device structure
512 * @ofs: offset from device start
514 * This is the default implementation, which can be overridden by a hardware
515 * specific driver. It provides the details for writing a bad block marker to a
518 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
520 struct nand_chip *chip = mtd->priv;
521 struct mtd_oob_ops ops;
522 uint8_t buf[2] = { 0, 0 };
523 int ret = 0, res, i = 0;
527 ops.ooboffs = chip->badblockpos;
528 if (chip->options & NAND_BUSWIDTH_16) {
529 ops.ooboffs &= ~0x01;
530 ops.len = ops.ooblen = 2;
532 ops.len = ops.ooblen = 1;
534 ops.mode = MTD_OPS_PLACE_OOB;
536 /* Write to first/last page(s) if necessary */
537 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
538 ofs += mtd->erasesize - mtd->writesize;
540 res = nand_do_write_oob(mtd, ofs, &ops);
545 ofs += mtd->writesize;
546 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
552 * nand_block_markbad_lowlevel - mark a block bad
553 * @mtd: MTD device structure
554 * @ofs: offset from device start
556 * This function performs the generic NAND bad block marking steps (i.e., bad
557 * block table(s) and/or marker(s)). We only allow the hardware driver to
558 * specify how to write bad block markers to OOB (chip->block_markbad).
560 * We try operations in the following order:
561 * (1) erase the affected block, to allow OOB marker to be written cleanly
562 * (2) write bad block marker to OOB area of affected block (unless flag
563 * NAND_BBT_NO_OOB_BBM is present)
565 * Note that we retain the first error encountered in (2) or (3), finish the
566 * procedures, and dump the error in the end.
568 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
570 struct nand_chip *chip = mtd->priv;
573 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
574 struct erase_info einfo;
576 /* Attempt erase before marking OOB */
577 memset(&einfo, 0, sizeof(einfo));
580 einfo.len = 1ULL << chip->phys_erase_shift;
581 nand_erase_nand(mtd, &einfo, 0);
583 /* Write bad block marker to OOB */
584 nand_get_device(mtd, FL_WRITING);
585 ret = chip->block_markbad(mtd, ofs);
586 nand_release_device(mtd);
589 /* Mark block bad in BBT */
591 res = nand_markbad_bbt(mtd, ofs);
597 mtd->ecc_stats.badblocks++;
603 * nand_check_wp - [GENERIC] check if the chip is write protected
604 * @mtd: MTD device structure
606 * Check, if the device is write protected. The function expects, that the
607 * device is already selected.
609 static int nand_check_wp(struct mtd_info *mtd)
611 struct nand_chip *chip = mtd->priv;
613 /* Broken xD cards report WP despite being writable */
614 if (chip->options & NAND_BROKEN_XD)
617 /* Check the WP bit */
618 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
619 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
623 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
624 * @mtd: MTD device structure
625 * @ofs: offset from device start
626 * @getchip: 0, if the chip is already selected
627 * @allowbbt: 1, if its allowed to access the bbt area
629 * Check, if the block is bad. Either by reading the bad block table or
630 * calling of the scan function.
632 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
635 struct nand_chip *chip = mtd->priv;
637 if (!(chip->options & NAND_SKIP_BBTSCAN) &&
638 !(chip->options & NAND_BBT_SCANNED)) {
639 chip->options |= NAND_BBT_SCANNED;
644 return chip->block_bad(mtd, ofs, getchip);
646 /* Return info from the table */
647 return nand_isbad_bbt(mtd, ofs, allowbbt);
652 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
653 * @mtd: MTD device structure
656 * Helper function for nand_wait_ready used when needing to wait in interrupt
659 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
661 struct nand_chip *chip = mtd->priv;
664 /* Wait for the device to get ready */
665 for (i = 0; i < timeo; i++) {
666 if (chip->dev_ready(mtd))
668 touch_softlockup_watchdog();
674 /* Wait for the ready pin, after a command. The timeout is caught later. */
675 void nand_wait_ready(struct mtd_info *mtd)
677 struct nand_chip *chip = mtd->priv;
679 unsigned long timeo = jiffies + msecs_to_jiffies(20);
682 if (in_interrupt() || oops_in_progress)
683 return panic_nand_wait_ready(mtd, 400);
685 led_trigger_event(nand_led_trigger, LED_FULL);
686 /* Wait until command is processed or timeout occurs */
688 if (chip->dev_ready(mtd))
690 touch_softlockup_watchdog();
691 } while (time_before(jiffies, timeo));
692 led_trigger_event(nand_led_trigger, LED_OFF);
694 u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
697 time_start = get_timer(0);
698 /* Wait until command is processed or timeout occurs */
699 while (get_timer(time_start) < timeo) {
701 if (chip->dev_ready(mtd))
706 EXPORT_SYMBOL_GPL(nand_wait_ready);
709 * nand_command - [DEFAULT] Send command to NAND device
710 * @mtd: MTD device structure
711 * @command: the command to be sent
712 * @column: the column address for this command, -1 if none
713 * @page_addr: the page address for this command, -1 if none
715 * Send command to NAND device. This function is used for small page devices
716 * (512 Bytes per page).
718 static void nand_command(struct mtd_info *mtd, unsigned int command,
719 int column, int page_addr)
721 register struct nand_chip *chip = mtd->priv;
722 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
723 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
725 /* Write out the command to the device */
726 if (command == NAND_CMD_SEQIN) {
729 if (column >= mtd->writesize) {
731 column -= mtd->writesize;
732 readcmd = NAND_CMD_READOOB;
733 } else if (column < 256) {
734 /* First 256 bytes --> READ0 */
735 readcmd = NAND_CMD_READ0;
738 readcmd = NAND_CMD_READ1;
740 chip->cmd_ctrl(mtd, readcmd, ctrl);
741 ctrl &= ~NAND_CTRL_CHANGE;
743 chip->cmd_ctrl(mtd, command, ctrl);
745 /* Address cycle, when necessary */
746 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
747 /* Serially input address */
749 /* Adjust columns for 16 bit buswidth */
750 if (chip->options & NAND_BUSWIDTH_16 &&
751 !nand_opcode_8bits(command))
753 chip->cmd_ctrl(mtd, column, ctrl);
754 ctrl &= ~NAND_CTRL_CHANGE;
756 if (page_addr != -1) {
757 chip->cmd_ctrl(mtd, page_addr, ctrl);
758 ctrl &= ~NAND_CTRL_CHANGE;
759 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
760 /* One more address cycle for devices > 32MiB */
761 if (chip->chipsize > (32 << 20))
762 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
764 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
767 * Program and erase have their own busy handlers status and sequential
772 case NAND_CMD_PAGEPROG:
773 case NAND_CMD_ERASE1:
774 case NAND_CMD_ERASE2:
776 case NAND_CMD_STATUS:
782 udelay(chip->chip_delay);
783 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
784 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
786 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
787 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
791 /* This applies to read commands */
794 * If we don't have access to the busy pin, we apply the given
797 if (!chip->dev_ready) {
798 udelay(chip->chip_delay);
803 * Apply this short delay always to ensure that we do wait tWB in
804 * any case on any machine.
808 nand_wait_ready(mtd);
812 * nand_command_lp - [DEFAULT] Send command to NAND large page device
813 * @mtd: MTD device structure
814 * @command: the command to be sent
815 * @column: the column address for this command, -1 if none
816 * @page_addr: the page address for this command, -1 if none
818 * Send command to NAND device. This is the version for the new large page
819 * devices. We don't have the separate regions as we have in the small page
820 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
822 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
823 int column, int page_addr)
825 register struct nand_chip *chip = mtd->priv;
826 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
828 /* Emulate NAND_CMD_READOOB */
829 if (command == NAND_CMD_READOOB) {
830 column += mtd->writesize;
831 command = NAND_CMD_READ0;
834 /* Command latch cycle */
835 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
837 if (column != -1 || page_addr != -1) {
838 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
840 /* Serially input address */
842 /* Adjust columns for 16 bit buswidth */
843 if (chip->options & NAND_BUSWIDTH_16 &&
844 !nand_opcode_8bits(command))
846 chip->cmd_ctrl(mtd, column, ctrl);
847 ctrl &= ~NAND_CTRL_CHANGE;
848 chip->cmd_ctrl(mtd, column >> 8, ctrl);
850 if (page_addr != -1) {
851 chip->cmd_ctrl(mtd, page_addr, ctrl);
852 chip->cmd_ctrl(mtd, page_addr >> 8,
853 NAND_NCE | NAND_ALE);
854 /* One more address cycle for devices > 128MiB */
855 if (chip->chipsize > (128 << 20))
856 chip->cmd_ctrl(mtd, page_addr >> 16,
857 NAND_NCE | NAND_ALE);
860 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
863 * Program and erase have their own busy handlers status, sequential
864 * in, and deplete1 need no delay.
868 case NAND_CMD_CACHEDPROG:
869 case NAND_CMD_PAGEPROG:
870 case NAND_CMD_ERASE1:
871 case NAND_CMD_ERASE2:
874 case NAND_CMD_STATUS:
880 udelay(chip->chip_delay);
881 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
882 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
883 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
884 NAND_NCE | NAND_CTRL_CHANGE);
885 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
889 case NAND_CMD_RNDOUT:
890 /* No ready / busy check necessary */
891 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
892 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
893 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
894 NAND_NCE | NAND_CTRL_CHANGE);
898 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
899 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
900 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
901 NAND_NCE | NAND_CTRL_CHANGE);
903 /* This applies to read commands */
906 * If we don't have access to the busy pin, we apply the given
909 if (!chip->dev_ready) {
910 udelay(chip->chip_delay);
916 * Apply this short delay always to ensure that we do wait tWB in
917 * any case on any machine.
921 nand_wait_ready(mtd);
925 * panic_nand_get_device - [GENERIC] Get chip for selected access
926 * @chip: the nand chip descriptor
927 * @mtd: MTD device structure
928 * @new_state: the state which is requested
930 * Used when in panic, no locks are taken.
932 static void panic_nand_get_device(struct nand_chip *chip,
933 struct mtd_info *mtd, int new_state)
935 /* Hardware controller shared among independent devices */
936 chip->controller->active = chip;
937 chip->state = new_state;
941 * nand_get_device - [GENERIC] Get chip for selected access
942 * @mtd: MTD device structure
943 * @new_state: the state which is requested
945 * Get the device and lock it for exclusive access
948 nand_get_device(struct mtd_info *mtd, int new_state)
950 struct nand_chip *chip = mtd->priv;
952 spinlock_t *lock = &chip->controller->lock;
953 wait_queue_head_t *wq = &chip->controller->wq;
954 DECLARE_WAITQUEUE(wait, current);
958 /* Hardware controller shared among independent devices */
959 if (!chip->controller->active)
960 chip->controller->active = chip;
962 if (chip->controller->active == chip && chip->state == FL_READY) {
963 chip->state = new_state;
967 if (new_state == FL_PM_SUSPENDED) {
968 if (chip->controller->active->state == FL_PM_SUSPENDED) {
969 chip->state = FL_PM_SUSPENDED;
974 set_current_state(TASK_UNINTERRUPTIBLE);
975 add_wait_queue(wq, &wait);
978 remove_wait_queue(wq, &wait);
981 chip->state = new_state;
987 * panic_nand_wait - [GENERIC] wait until the command is done
988 * @mtd: MTD device structure
989 * @chip: NAND chip structure
992 * Wait for command done. This is a helper function for nand_wait used when
993 * we are in interrupt context. May happen when in panic and trying to write
994 * an oops through mtdoops.
996 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
1000 for (i = 0; i < timeo; i++) {
1001 if (chip->dev_ready) {
1002 if (chip->dev_ready(mtd))
1005 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1013 * nand_wait - [DEFAULT] wait until the command is done
1014 * @mtd: MTD device structure
1015 * @chip: NAND chip structure
1017 * Wait for command done. This applies to erase and program only. Erase can
1018 * take up to 400ms and program up to 20ms according to general NAND and
1021 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1024 int status, state = chip->state;
1025 unsigned long timeo = (state == FL_ERASING ? 400 : 20);
1027 led_trigger_event(nand_led_trigger, LED_FULL);
1030 * Apply this short delay always to ensure that we do wait tWB in any
1031 * case on any machine.
1035 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1038 if (in_interrupt() || oops_in_progress)
1039 panic_nand_wait(mtd, chip, timeo);
1041 timeo = jiffies + msecs_to_jiffies(timeo);
1042 while (time_before(jiffies, timeo)) {
1043 if (chip->dev_ready) {
1044 if (chip->dev_ready(mtd))
1047 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1054 u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
1057 time_start = get_timer(0);
1058 while (get_timer(time_start) < timer) {
1059 if (chip->dev_ready) {
1060 if (chip->dev_ready(mtd))
1063 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1068 led_trigger_event(nand_led_trigger, LED_OFF);
1070 status = (int)chip->read_byte(mtd);
1071 /* This can happen if in case of timeout or buggy dev_ready */
1072 WARN_ON(!(status & NAND_STATUS_READY));
1078 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1080 * @ofs: offset to start unlock from
1081 * @len: length to unlock
1082 * @invert: when = 0, unlock the range of blocks within the lower and
1083 * upper boundary address
1084 * when = 1, unlock the range of blocks outside the boundaries
1085 * of the lower and upper boundary address
1087 * Returs unlock status.
1089 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
1090 uint64_t len, int invert)
1094 struct nand_chip *chip = mtd->priv;
1096 /* Submit address of first page to unlock */
1097 page = ofs >> chip->page_shift;
1098 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
1100 /* Submit address of last page to unlock */
1101 page = (ofs + len) >> chip->page_shift;
1102 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
1103 (page | invert) & chip->pagemask);
1105 /* Call wait ready function */
1106 status = chip->waitfunc(mtd, chip);
1107 /* See if device thinks it succeeded */
1108 if (status & NAND_STATUS_FAIL) {
1109 pr_debug("%s: error status = 0x%08x\n",
1118 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1120 * @ofs: offset to start unlock from
1121 * @len: length to unlock
1123 * Returns unlock status.
1125 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1129 struct nand_chip *chip = mtd->priv;
1131 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1132 __func__, (unsigned long long)ofs, len);
1134 if (check_offs_len(mtd, ofs, len))
1137 /* Align to last block address if size addresses end of the device */
1138 if (ofs + len == mtd->size)
1139 len -= mtd->erasesize;
1141 nand_get_device(mtd, FL_UNLOCKING);
1143 /* Shift to get chip number */
1144 chipnr = ofs >> chip->chip_shift;
1146 chip->select_chip(mtd, chipnr);
1148 /* Check, if it is write protected */
1149 if (nand_check_wp(mtd)) {
1150 pr_debug("%s: device is write protected!\n",
1156 ret = __nand_unlock(mtd, ofs, len, 0);
1159 chip->select_chip(mtd, -1);
1160 nand_release_device(mtd);
1164 EXPORT_SYMBOL(nand_unlock);
1167 * nand_lock - [REPLACEABLE] locks all blocks present in the device
1169 * @ofs: offset to start unlock from
1170 * @len: length to unlock
1172 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1173 * have this feature, but it allows only to lock all blocks, not for specified
1174 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1177 * Returns lock status.
1179 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1182 int chipnr, status, page;
1183 struct nand_chip *chip = mtd->priv;
1185 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1186 __func__, (unsigned long long)ofs, len);
1188 if (check_offs_len(mtd, ofs, len))
1191 nand_get_device(mtd, FL_LOCKING);
1193 /* Shift to get chip number */
1194 chipnr = ofs >> chip->chip_shift;
1196 chip->select_chip(mtd, chipnr);
1198 /* Check, if it is write protected */
1199 if (nand_check_wp(mtd)) {
1200 pr_debug("%s: device is write protected!\n",
1202 status = MTD_ERASE_FAILED;
1207 /* Submit address of first page to lock */
1208 page = ofs >> chip->page_shift;
1209 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1211 /* Call wait ready function */
1212 status = chip->waitfunc(mtd, chip);
1213 /* See if device thinks it succeeded */
1214 if (status & NAND_STATUS_FAIL) {
1215 pr_debug("%s: error status = 0x%08x\n",
1221 ret = __nand_unlock(mtd, ofs, len, 0x1);
1224 chip->select_chip(mtd, -1);
1225 nand_release_device(mtd);
1229 EXPORT_SYMBOL(nand_lock);
1233 * nand_read_page_raw - [INTERN] read raw page data without ecc
1234 * @mtd: mtd info structure
1235 * @chip: nand chip info structure
1236 * @buf: buffer to store read data
1237 * @oob_required: caller requires OOB data read to chip->oob_poi
1238 * @page: page number to read
1240 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1242 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1243 uint8_t *buf, int oob_required, int page)
1245 chip->read_buf(mtd, buf, mtd->writesize);
1247 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1252 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1253 * @mtd: mtd info structure
1254 * @chip: nand chip info structure
1255 * @buf: buffer to store read data
1256 * @oob_required: caller requires OOB data read to chip->oob_poi
1257 * @page: page number to read
1259 * We need a special oob layout and handling even when OOB isn't used.
1261 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1262 struct nand_chip *chip, uint8_t *buf,
1263 int oob_required, int page)
1265 int eccsize = chip->ecc.size;
1266 int eccbytes = chip->ecc.bytes;
1267 uint8_t *oob = chip->oob_poi;
1270 for (steps = chip->ecc.steps; steps > 0; steps--) {
1271 chip->read_buf(mtd, buf, eccsize);
1274 if (chip->ecc.prepad) {
1275 chip->read_buf(mtd, oob, chip->ecc.prepad);
1276 oob += chip->ecc.prepad;
1279 chip->read_buf(mtd, oob, eccbytes);
1282 if (chip->ecc.postpad) {
1283 chip->read_buf(mtd, oob, chip->ecc.postpad);
1284 oob += chip->ecc.postpad;
1288 size = mtd->oobsize - (oob - chip->oob_poi);
1290 chip->read_buf(mtd, oob, size);
1296 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1297 * @mtd: mtd info structure
1298 * @chip: nand chip info structure
1299 * @buf: buffer to store read data
1300 * @oob_required: caller requires OOB data read to chip->oob_poi
1301 * @page: page number to read
1303 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1304 uint8_t *buf, int oob_required, int page)
1306 int i, eccsize = chip->ecc.size;
1307 int eccbytes = chip->ecc.bytes;
1308 int eccsteps = chip->ecc.steps;
1310 uint8_t *ecc_calc = chip->buffers->ecccalc;
1311 uint8_t *ecc_code = chip->buffers->ecccode;
1312 uint32_t *eccpos = chip->ecc.layout->eccpos;
1313 unsigned int max_bitflips = 0;
1315 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1317 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1318 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1320 for (i = 0; i < chip->ecc.total; i++)
1321 ecc_code[i] = chip->oob_poi[eccpos[i]];
1323 eccsteps = chip->ecc.steps;
1326 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1329 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1331 mtd->ecc_stats.failed++;
1333 mtd->ecc_stats.corrected += stat;
1334 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1337 return max_bitflips;
1341 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1342 * @mtd: mtd info structure
1343 * @chip: nand chip info structure
1344 * @data_offs: offset of requested data within the page
1345 * @readlen: data length
1346 * @bufpoi: buffer to store read data
1347 * @page: page number to read
1349 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1350 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1353 int start_step, end_step, num_steps;
1354 uint32_t *eccpos = chip->ecc.layout->eccpos;
1356 int data_col_addr, i, gaps = 0;
1357 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1358 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1360 unsigned int max_bitflips = 0;
1362 /* Column address within the page aligned to ECC size (256bytes) */
1363 start_step = data_offs / chip->ecc.size;
1364 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1365 num_steps = end_step - start_step + 1;
1366 index = start_step * chip->ecc.bytes;
1368 /* Data size aligned to ECC ecc.size */
1369 datafrag_len = num_steps * chip->ecc.size;
1370 eccfrag_len = num_steps * chip->ecc.bytes;
1372 data_col_addr = start_step * chip->ecc.size;
1373 /* If we read not a page aligned data */
1374 if (data_col_addr != 0)
1375 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1377 p = bufpoi + data_col_addr;
1378 chip->read_buf(mtd, p, datafrag_len);
1381 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1382 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1385 * The performance is faster if we position offsets according to
1386 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1388 for (i = 0; i < eccfrag_len - 1; i++) {
1389 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1390 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1396 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1397 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1400 * Send the command to read the particular ECC bytes take care
1401 * about buswidth alignment in read_buf.
1403 aligned_pos = eccpos[index] & ~(busw - 1);
1404 aligned_len = eccfrag_len;
1405 if (eccpos[index] & (busw - 1))
1407 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1410 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1411 mtd->writesize + aligned_pos, -1);
1412 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1415 for (i = 0; i < eccfrag_len; i++)
1416 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1418 p = bufpoi + data_col_addr;
1419 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1422 stat = chip->ecc.correct(mtd, p,
1423 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1425 mtd->ecc_stats.failed++;
1427 mtd->ecc_stats.corrected += stat;
1428 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1431 return max_bitflips;
1435 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1436 * @mtd: mtd info structure
1437 * @chip: nand chip info structure
1438 * @buf: buffer to store read data
1439 * @oob_required: caller requires OOB data read to chip->oob_poi
1440 * @page: page number to read
1442 * Not for syndrome calculating ECC controllers which need a special oob layout.
1444 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1445 uint8_t *buf, int oob_required, int page)
1447 int i, eccsize = chip->ecc.size;
1448 int eccbytes = chip->ecc.bytes;
1449 int eccsteps = chip->ecc.steps;
1451 uint8_t *ecc_calc = chip->buffers->ecccalc;
1452 uint8_t *ecc_code = chip->buffers->ecccode;
1453 uint32_t *eccpos = chip->ecc.layout->eccpos;
1454 unsigned int max_bitflips = 0;
1456 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1457 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1458 chip->read_buf(mtd, p, eccsize);
1459 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1461 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1463 for (i = 0; i < chip->ecc.total; i++)
1464 ecc_code[i] = chip->oob_poi[eccpos[i]];
1466 eccsteps = chip->ecc.steps;
1469 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1472 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1474 mtd->ecc_stats.failed++;
1476 mtd->ecc_stats.corrected += stat;
1477 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1480 return max_bitflips;
1484 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1485 * @mtd: mtd info structure
1486 * @chip: nand chip info structure
1487 * @buf: buffer to store read data
1488 * @oob_required: caller requires OOB data read to chip->oob_poi
1489 * @page: page number to read
1491 * Hardware ECC for large page chips, require OOB to be read first. For this
1492 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1493 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1494 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1495 * the data area, by overwriting the NAND manufacturer bad block markings.
1497 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1498 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1500 int i, eccsize = chip->ecc.size;
1501 int eccbytes = chip->ecc.bytes;
1502 int eccsteps = chip->ecc.steps;
1504 uint8_t *ecc_code = chip->buffers->ecccode;
1505 uint32_t *eccpos = chip->ecc.layout->eccpos;
1506 uint8_t *ecc_calc = chip->buffers->ecccalc;
1507 unsigned int max_bitflips = 0;
1509 /* Read the OOB area first */
1510 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1511 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1512 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1514 for (i = 0; i < chip->ecc.total; i++)
1515 ecc_code[i] = chip->oob_poi[eccpos[i]];
1517 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1520 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1521 chip->read_buf(mtd, p, eccsize);
1522 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1524 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1526 mtd->ecc_stats.failed++;
1528 mtd->ecc_stats.corrected += stat;
1529 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1532 return max_bitflips;
1536 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1537 * @mtd: mtd info structure
1538 * @chip: nand chip info structure
1539 * @buf: buffer to store read data
1540 * @oob_required: caller requires OOB data read to chip->oob_poi
1541 * @page: page number to read
1543 * The hw generator calculates the error syndrome automatically. Therefore we
1544 * need a special oob layout and handling.
1546 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1547 uint8_t *buf, int oob_required, int page)
1549 int i, eccsize = chip->ecc.size;
1550 int eccbytes = chip->ecc.bytes;
1551 int eccsteps = chip->ecc.steps;
1553 uint8_t *oob = chip->oob_poi;
1554 unsigned int max_bitflips = 0;
1556 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1559 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1560 chip->read_buf(mtd, p, eccsize);
1562 if (chip->ecc.prepad) {
1563 chip->read_buf(mtd, oob, chip->ecc.prepad);
1564 oob += chip->ecc.prepad;
1567 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1568 chip->read_buf(mtd, oob, eccbytes);
1569 stat = chip->ecc.correct(mtd, p, oob, NULL);
1572 mtd->ecc_stats.failed++;
1574 mtd->ecc_stats.corrected += stat;
1575 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1580 if (chip->ecc.postpad) {
1581 chip->read_buf(mtd, oob, chip->ecc.postpad);
1582 oob += chip->ecc.postpad;
1586 /* Calculate remaining oob bytes */
1587 i = mtd->oobsize - (oob - chip->oob_poi);
1589 chip->read_buf(mtd, oob, i);
1591 return max_bitflips;
1595 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1596 * @chip: nand chip structure
1597 * @oob: oob destination address
1598 * @ops: oob ops structure
1599 * @len: size of oob to transfer
1601 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1602 struct mtd_oob_ops *ops, size_t len)
1604 switch (ops->mode) {
1606 case MTD_OPS_PLACE_OOB:
1608 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1611 case MTD_OPS_AUTO_OOB: {
1612 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1613 uint32_t boffs = 0, roffs = ops->ooboffs;
1616 for (; free->length && len; free++, len -= bytes) {
1617 /* Read request not from offset 0? */
1618 if (unlikely(roffs)) {
1619 if (roffs >= free->length) {
1620 roffs -= free->length;
1623 boffs = free->offset + roffs;
1624 bytes = min_t(size_t, len,
1625 (free->length - roffs));
1628 bytes = min_t(size_t, len, free->length);
1629 boffs = free->offset;
1631 memcpy(oob, chip->oob_poi + boffs, bytes);
1643 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1644 * @mtd: MTD device structure
1645 * @retry_mode: the retry mode to use
1647 * Some vendors supply a special command to shift the Vt threshold, to be used
1648 * when there are too many bitflips in a page (i.e., ECC error). After setting
1649 * a new threshold, the host should retry reading the page.
1651 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1653 struct nand_chip *chip = mtd->priv;
1655 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1657 if (retry_mode >= chip->read_retries)
1660 if (!chip->setup_read_retry)
1663 return chip->setup_read_retry(mtd, retry_mode);
1667 * nand_do_read_ops - [INTERN] Read data with ECC
1668 * @mtd: MTD device structure
1669 * @from: offset to read from
1670 * @ops: oob ops structure
1672 * Internal function. Called with chip held.
1674 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1675 struct mtd_oob_ops *ops)
1677 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1678 struct nand_chip *chip = mtd->priv;
1680 uint32_t readlen = ops->len;
1681 uint32_t oobreadlen = ops->ooblen;
1682 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1683 mtd->oobavail : mtd->oobsize;
1685 uint8_t *bufpoi, *oob, *buf;
1686 unsigned int max_bitflips = 0;
1688 bool ecc_fail = false;
1690 chipnr = (int)(from >> chip->chip_shift);
1691 chip->select_chip(mtd, chipnr);
1693 realpage = (int)(from >> chip->page_shift);
1694 page = realpage & chip->pagemask;
1696 col = (int)(from & (mtd->writesize - 1));
1700 oob_required = oob ? 1 : 0;
1703 unsigned int ecc_failures = mtd->ecc_stats.failed;
1706 bytes = min(mtd->writesize - col, readlen);
1707 aligned = (bytes == mtd->writesize);
1709 /* Is the current page in the buffer? */
1710 if (realpage != chip->pagebuf || oob) {
1711 bufpoi = aligned ? buf : chip->buffers->databuf;
1714 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1717 * Now read the page into the buffer. Absent an error,
1718 * the read methods return max bitflips per ecc step.
1720 if (unlikely(ops->mode == MTD_OPS_RAW))
1721 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1724 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1726 ret = chip->ecc.read_subpage(mtd, chip,
1730 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1731 oob_required, page);
1734 /* Invalidate page cache */
1739 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1741 /* Transfer not aligned data */
1743 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1744 !(mtd->ecc_stats.failed - ecc_failures) &&
1745 (ops->mode != MTD_OPS_RAW)) {
1746 chip->pagebuf = realpage;
1747 chip->pagebuf_bitflips = ret;
1749 /* Invalidate page cache */
1752 memcpy(buf, chip->buffers->databuf + col, bytes);
1755 if (unlikely(oob)) {
1756 int toread = min(oobreadlen, max_oobsize);
1759 oob = nand_transfer_oob(chip,
1761 oobreadlen -= toread;
1765 if (chip->options & NAND_NEED_READRDY) {
1766 /* Apply delay or wait for ready/busy pin */
1767 if (!chip->dev_ready)
1768 udelay(chip->chip_delay);
1770 nand_wait_ready(mtd);
1773 if (mtd->ecc_stats.failed - ecc_failures) {
1774 if (retry_mode + 1 < chip->read_retries) {
1776 ret = nand_setup_read_retry(mtd,
1781 /* Reset failures; retry */
1782 mtd->ecc_stats.failed = ecc_failures;
1785 /* No more retry modes; real failure */
1792 memcpy(buf, chip->buffers->databuf + col, bytes);
1794 max_bitflips = max_t(unsigned int, max_bitflips,
1795 chip->pagebuf_bitflips);
1800 /* Reset to retry mode 0 */
1802 ret = nand_setup_read_retry(mtd, 0);
1811 /* For subsequent reads align to page boundary */
1813 /* Increment page address */
1816 page = realpage & chip->pagemask;
1817 /* Check, if we cross a chip boundary */
1820 chip->select_chip(mtd, -1);
1821 chip->select_chip(mtd, chipnr);
1824 chip->select_chip(mtd, -1);
1826 ops->retlen = ops->len - (size_t) readlen;
1828 ops->oobretlen = ops->ooblen - oobreadlen;
1836 return max_bitflips;
1840 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1841 * @mtd: MTD device structure
1842 * @from: offset to read from
1843 * @len: number of bytes to read
1844 * @retlen: pointer to variable to store the number of read bytes
1845 * @buf: the databuffer to put data
1847 * Get hold of the chip and call nand_do_read.
1849 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1850 size_t *retlen, uint8_t *buf)
1852 struct mtd_oob_ops ops;
1855 nand_get_device(mtd, FL_READING);
1859 ops.mode = MTD_OPS_PLACE_OOB;
1860 ret = nand_do_read_ops(mtd, from, &ops);
1861 *retlen = ops.retlen;
1862 nand_release_device(mtd);
1867 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1868 * @mtd: mtd info structure
1869 * @chip: nand chip info structure
1870 * @page: page number to read
1872 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1875 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1876 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1881 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1883 * @mtd: mtd info structure
1884 * @chip: nand chip info structure
1885 * @page: page number to read
1887 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1890 uint8_t *buf = chip->oob_poi;
1891 int length = mtd->oobsize;
1892 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1893 int eccsize = chip->ecc.size;
1894 uint8_t *bufpoi = buf;
1895 int i, toread, sndrnd = 0, pos;
1897 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1898 for (i = 0; i < chip->ecc.steps; i++) {
1900 pos = eccsize + i * (eccsize + chunk);
1901 if (mtd->writesize > 512)
1902 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1904 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1907 toread = min_t(int, length, chunk);
1908 chip->read_buf(mtd, bufpoi, toread);
1913 chip->read_buf(mtd, bufpoi, length);
1919 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1920 * @mtd: mtd info structure
1921 * @chip: nand chip info structure
1922 * @page: page number to write
1924 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1928 const uint8_t *buf = chip->oob_poi;
1929 int length = mtd->oobsize;
1931 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1932 chip->write_buf(mtd, buf, length);
1933 /* Send command to program the OOB data */
1934 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1936 status = chip->waitfunc(mtd, chip);
1938 return status & NAND_STATUS_FAIL ? -EIO : 0;
1942 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1943 * with syndrome - only for large page flash
1944 * @mtd: mtd info structure
1945 * @chip: nand chip info structure
1946 * @page: page number to write
1948 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1949 struct nand_chip *chip, int page)
1951 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1952 int eccsize = chip->ecc.size, length = mtd->oobsize;
1953 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1954 const uint8_t *bufpoi = chip->oob_poi;
1957 * data-ecc-data-ecc ... ecc-oob
1959 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1961 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1962 pos = steps * (eccsize + chunk);
1967 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1968 for (i = 0; i < steps; i++) {
1970 if (mtd->writesize <= 512) {
1971 uint32_t fill = 0xFFFFFFFF;
1975 int num = min_t(int, len, 4);
1976 chip->write_buf(mtd, (uint8_t *)&fill,
1981 pos = eccsize + i * (eccsize + chunk);
1982 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1986 len = min_t(int, length, chunk);
1987 chip->write_buf(mtd, bufpoi, len);
1992 chip->write_buf(mtd, bufpoi, length);
1994 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1995 status = chip->waitfunc(mtd, chip);
1997 return status & NAND_STATUS_FAIL ? -EIO : 0;
2001 * nand_do_read_oob - [INTERN] NAND read out-of-band
2002 * @mtd: MTD device structure
2003 * @from: offset to read from
2004 * @ops: oob operations description structure
2006 * NAND read out-of-band data from the spare area.
2008 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2009 struct mtd_oob_ops *ops)
2011 int page, realpage, chipnr;
2012 struct nand_chip *chip = mtd->priv;
2013 struct mtd_ecc_stats stats;
2014 int readlen = ops->ooblen;
2016 uint8_t *buf = ops->oobbuf;
2019 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2020 __func__, (unsigned long long)from, readlen);
2022 stats = mtd->ecc_stats;
2024 if (ops->mode == MTD_OPS_AUTO_OOB)
2025 len = chip->ecc.layout->oobavail;
2029 if (unlikely(ops->ooboffs >= len)) {
2030 pr_debug("%s: attempt to start read outside oob\n",
2035 /* Do not allow reads past end of device */
2036 if (unlikely(from >= mtd->size ||
2037 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
2038 (from >> chip->page_shift)) * len)) {
2039 pr_debug("%s: attempt to read beyond end of device\n",
2044 chipnr = (int)(from >> chip->chip_shift);
2045 chip->select_chip(mtd, chipnr);
2047 /* Shift to get page */
2048 realpage = (int)(from >> chip->page_shift);
2049 page = realpage & chip->pagemask;
2054 if (ops->mode == MTD_OPS_RAW)
2055 ret = chip->ecc.read_oob_raw(mtd, chip, page);
2057 ret = chip->ecc.read_oob(mtd, chip, page);
2062 len = min(len, readlen);
2063 buf = nand_transfer_oob(chip, buf, ops, len);
2065 if (chip->options & NAND_NEED_READRDY) {
2066 /* Apply delay or wait for ready/busy pin */
2067 if (!chip->dev_ready)
2068 udelay(chip->chip_delay);
2070 nand_wait_ready(mtd);
2077 /* Increment page address */
2080 page = realpage & chip->pagemask;
2081 /* Check, if we cross a chip boundary */
2084 chip->select_chip(mtd, -1);
2085 chip->select_chip(mtd, chipnr);
2088 chip->select_chip(mtd, -1);
2090 ops->oobretlen = ops->ooblen - readlen;
2095 if (mtd->ecc_stats.failed - stats.failed)
2098 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
2102 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2103 * @mtd: MTD device structure
2104 * @from: offset to read from
2105 * @ops: oob operation description structure
2107 * NAND read data and/or out-of-band data.
2109 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2110 struct mtd_oob_ops *ops)
2112 int ret = -ENOTSUPP;
2116 /* Do not allow reads past end of device */
2117 if (ops->datbuf && (from + ops->len) > mtd->size) {
2118 pr_debug("%s: attempt to read beyond end of device\n",
2123 nand_get_device(mtd, FL_READING);
2125 switch (ops->mode) {
2126 case MTD_OPS_PLACE_OOB:
2127 case MTD_OPS_AUTO_OOB:
2136 ret = nand_do_read_oob(mtd, from, ops);
2138 ret = nand_do_read_ops(mtd, from, ops);
2141 nand_release_device(mtd);
2147 * nand_write_page_raw - [INTERN] raw page write function
2148 * @mtd: mtd info structure
2149 * @chip: nand chip info structure
2151 * @oob_required: must write chip->oob_poi to OOB
2153 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2155 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2156 const uint8_t *buf, int oob_required)
2158 chip->write_buf(mtd, buf, mtd->writesize);
2160 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2166 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2167 * @mtd: mtd info structure
2168 * @chip: nand chip info structure
2170 * @oob_required: must write chip->oob_poi to OOB
2172 * We need a special oob layout and handling even when ECC isn't checked.
2174 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
2175 struct nand_chip *chip,
2176 const uint8_t *buf, int oob_required)
2178 int eccsize = chip->ecc.size;
2179 int eccbytes = chip->ecc.bytes;
2180 uint8_t *oob = chip->oob_poi;
2183 for (steps = chip->ecc.steps; steps > 0; steps--) {
2184 chip->write_buf(mtd, buf, eccsize);
2187 if (chip->ecc.prepad) {
2188 chip->write_buf(mtd, oob, chip->ecc.prepad);
2189 oob += chip->ecc.prepad;
2192 chip->write_buf(mtd, oob, eccbytes);
2195 if (chip->ecc.postpad) {
2196 chip->write_buf(mtd, oob, chip->ecc.postpad);
2197 oob += chip->ecc.postpad;
2201 size = mtd->oobsize - (oob - chip->oob_poi);
2203 chip->write_buf(mtd, oob, size);
2208 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2209 * @mtd: mtd info structure
2210 * @chip: nand chip info structure
2212 * @oob_required: must write chip->oob_poi to OOB
2214 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
2215 const uint8_t *buf, int oob_required)
2217 int i, eccsize = chip->ecc.size;
2218 int eccbytes = chip->ecc.bytes;
2219 int eccsteps = chip->ecc.steps;
2220 uint8_t *ecc_calc = chip->buffers->ecccalc;
2221 const uint8_t *p = buf;
2222 uint32_t *eccpos = chip->ecc.layout->eccpos;
2224 /* Software ECC calculation */
2225 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2226 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2228 for (i = 0; i < chip->ecc.total; i++)
2229 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2231 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
2235 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2236 * @mtd: mtd info structure
2237 * @chip: nand chip info structure
2239 * @oob_required: must write chip->oob_poi to OOB
2241 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2242 const uint8_t *buf, int oob_required)
2244 int i, eccsize = chip->ecc.size;
2245 int eccbytes = chip->ecc.bytes;
2246 int eccsteps = chip->ecc.steps;
2247 uint8_t *ecc_calc = chip->buffers->ecccalc;
2248 const uint8_t *p = buf;
2249 uint32_t *eccpos = chip->ecc.layout->eccpos;
2251 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2252 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2253 chip->write_buf(mtd, p, eccsize);
2254 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2257 for (i = 0; i < chip->ecc.total; i++)
2258 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2260 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2267 * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
2268 * @mtd: mtd info structure
2269 * @chip: nand chip info structure
2270 * @offset: column address of subpage within the page
2271 * @data_len: data length
2273 * @oob_required: must write chip->oob_poi to OOB
2275 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2276 struct nand_chip *chip, uint32_t offset,
2277 uint32_t data_len, const uint8_t *buf,
2280 uint8_t *oob_buf = chip->oob_poi;
2281 uint8_t *ecc_calc = chip->buffers->ecccalc;
2282 int ecc_size = chip->ecc.size;
2283 int ecc_bytes = chip->ecc.bytes;
2284 int ecc_steps = chip->ecc.steps;
2285 uint32_t *eccpos = chip->ecc.layout->eccpos;
2286 uint32_t start_step = offset / ecc_size;
2287 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2288 int oob_bytes = mtd->oobsize / ecc_steps;
2291 for (step = 0; step < ecc_steps; step++) {
2292 /* configure controller for WRITE access */
2293 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2295 /* write data (untouched subpages already masked by 0xFF) */
2296 chip->write_buf(mtd, buf, ecc_size);
2298 /* mask ECC of un-touched subpages by padding 0xFF */
2299 if ((step < start_step) || (step > end_step))
2300 memset(ecc_calc, 0xff, ecc_bytes);
2302 chip->ecc.calculate(mtd, buf, ecc_calc);
2304 /* mask OOB of un-touched subpages by padding 0xFF */
2305 /* if oob_required, preserve OOB metadata of written subpage */
2306 if (!oob_required || (step < start_step) || (step > end_step))
2307 memset(oob_buf, 0xff, oob_bytes);
2310 ecc_calc += ecc_bytes;
2311 oob_buf += oob_bytes;
2314 /* copy calculated ECC for whole page to chip->buffer->oob */
2315 /* this include masked-value(0xFF) for unwritten subpages */
2316 ecc_calc = chip->buffers->ecccalc;
2317 for (i = 0; i < chip->ecc.total; i++)
2318 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2320 /* write OOB buffer to NAND device */
2321 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2328 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2329 * @mtd: mtd info structure
2330 * @chip: nand chip info structure
2332 * @oob_required: must write chip->oob_poi to OOB
2334 * The hw generator calculates the error syndrome automatically. Therefore we
2335 * need a special oob layout and handling.
2337 static int nand_write_page_syndrome(struct mtd_info *mtd,
2338 struct nand_chip *chip,
2339 const uint8_t *buf, int oob_required)
2341 int i, eccsize = chip->ecc.size;
2342 int eccbytes = chip->ecc.bytes;
2343 int eccsteps = chip->ecc.steps;
2344 const uint8_t *p = buf;
2345 uint8_t *oob = chip->oob_poi;
2347 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2349 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2350 chip->write_buf(mtd, p, eccsize);
2352 if (chip->ecc.prepad) {
2353 chip->write_buf(mtd, oob, chip->ecc.prepad);
2354 oob += chip->ecc.prepad;
2357 chip->ecc.calculate(mtd, p, oob);
2358 chip->write_buf(mtd, oob, eccbytes);
2361 if (chip->ecc.postpad) {
2362 chip->write_buf(mtd, oob, chip->ecc.postpad);
2363 oob += chip->ecc.postpad;
2367 /* Calculate remaining oob bytes */
2368 i = mtd->oobsize - (oob - chip->oob_poi);
2370 chip->write_buf(mtd, oob, i);
2376 * nand_write_page - [REPLACEABLE] write one page
2377 * @mtd: MTD device structure
2378 * @chip: NAND chip descriptor
2379 * @offset: address offset within the page
2380 * @data_len: length of actual data to be written
2381 * @buf: the data to write
2382 * @oob_required: must write chip->oob_poi to OOB
2383 * @page: page number to write
2384 * @cached: cached programming
2385 * @raw: use _raw version of write_page
2387 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2388 uint32_t offset, int data_len, const uint8_t *buf,
2389 int oob_required, int page, int cached, int raw)
2391 int status, subpage;
2393 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2394 chip->ecc.write_subpage)
2395 subpage = offset || (data_len < mtd->writesize);
2399 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2402 status = chip->ecc.write_page_raw(mtd, chip, buf,
2405 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2408 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2414 * Cached progamming disabled for now. Not sure if it's worth the
2415 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2419 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2421 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2422 status = chip->waitfunc(mtd, chip);
2424 * See if operation failed and additional status checks are
2427 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2428 status = chip->errstat(mtd, chip, FL_WRITING, status,
2431 if (status & NAND_STATUS_FAIL)
2434 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2435 status = chip->waitfunc(mtd, chip);
2440 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
2441 /* Send command to read back the data */
2442 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2444 if (chip->verify_buf(mtd, buf, mtd->writesize))
2447 /* Make sure the next page prog is preceded by a status read */
2448 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
2456 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2457 * @mtd: MTD device structure
2458 * @oob: oob data buffer
2459 * @len: oob data write length
2460 * @ops: oob ops structure
2462 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2463 struct mtd_oob_ops *ops)
2465 struct nand_chip *chip = mtd->priv;
2468 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2469 * data from a previous OOB read.
2471 memset(chip->oob_poi, 0xff, mtd->oobsize);
2473 switch (ops->mode) {
2475 case MTD_OPS_PLACE_OOB:
2477 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2480 case MTD_OPS_AUTO_OOB: {
2481 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2482 uint32_t boffs = 0, woffs = ops->ooboffs;
2485 for (; free->length && len; free++, len -= bytes) {
2486 /* Write request not from offset 0? */
2487 if (unlikely(woffs)) {
2488 if (woffs >= free->length) {
2489 woffs -= free->length;
2492 boffs = free->offset + woffs;
2493 bytes = min_t(size_t, len,
2494 (free->length - woffs));
2497 bytes = min_t(size_t, len, free->length);
2498 boffs = free->offset;
2500 memcpy(chip->oob_poi + boffs, oob, bytes);
2511 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2514 * nand_do_write_ops - [INTERN] NAND write with ECC
2515 * @mtd: MTD device structure
2516 * @to: offset to write to
2517 * @ops: oob operations description structure
2519 * NAND write with ECC.
2521 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2522 struct mtd_oob_ops *ops)
2524 int chipnr, realpage, page, blockmask, column;
2525 struct nand_chip *chip = mtd->priv;
2526 uint32_t writelen = ops->len;
2528 uint32_t oobwritelen = ops->ooblen;
2529 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2530 mtd->oobavail : mtd->oobsize;
2532 uint8_t *oob = ops->oobbuf;
2533 uint8_t *buf = ops->datbuf;
2535 int oob_required = oob ? 1 : 0;
2542 /* Reject writes, which are not page aligned */
2543 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2545 /* Reject writes, which are not page aligned */
2546 if (NOTALIGNED(to)) {
2548 pr_notice("%s: attempt to write non page aligned data\n",
2553 column = to & (mtd->writesize - 1);
2555 chipnr = (int)(to >> chip->chip_shift);
2556 chip->select_chip(mtd, chipnr);
2558 /* Check, if it is write protected */
2559 if (nand_check_wp(mtd)) {
2564 realpage = (int)(to >> chip->page_shift);
2565 page = realpage & chip->pagemask;
2566 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2568 /* Invalidate the page cache, when we write to the cached page */
2569 if (to <= (chip->pagebuf << chip->page_shift) &&
2570 (chip->pagebuf << chip->page_shift) < (to + ops->len))
2573 /* Don't allow multipage oob writes with offset */
2574 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2580 int bytes = mtd->writesize;
2581 int cached = writelen > bytes && page != blockmask;
2582 uint8_t *wbuf = buf;
2585 /* Partial page write? */
2586 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2588 bytes = min_t(int, bytes - column, (int) writelen);
2590 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2591 memcpy(&chip->buffers->databuf[column], buf, bytes);
2592 wbuf = chip->buffers->databuf;
2595 if (unlikely(oob)) {
2596 size_t len = min(oobwritelen, oobmaxlen);
2597 oob = nand_fill_oob(mtd, oob, len, ops);
2600 /* We still need to erase leftover OOB data */
2601 memset(chip->oob_poi, 0xff, mtd->oobsize);
2603 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2604 oob_required, page, cached,
2605 (ops->mode == MTD_OPS_RAW));
2617 page = realpage & chip->pagemask;
2618 /* Check, if we cross a chip boundary */
2621 chip->select_chip(mtd, -1);
2622 chip->select_chip(mtd, chipnr);
2626 ops->retlen = ops->len - writelen;
2628 ops->oobretlen = ops->ooblen;
2631 chip->select_chip(mtd, -1);
2636 * panic_nand_write - [MTD Interface] NAND write with ECC
2637 * @mtd: MTD device structure
2638 * @to: offset to write to
2639 * @len: number of bytes to write
2640 * @retlen: pointer to variable to store the number of written bytes
2641 * @buf: the data to write
2643 * NAND write with ECC. Used when performing writes in interrupt context, this
2644 * may for example be called by mtdoops when writing an oops while in panic.
2646 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2647 size_t *retlen, const uint8_t *buf)
2649 struct nand_chip *chip = mtd->priv;
2650 struct mtd_oob_ops ops;
2653 /* Wait for the device to get ready */
2654 panic_nand_wait(mtd, chip, 400);
2656 /* Grab the device */
2657 panic_nand_get_device(chip, mtd, FL_WRITING);
2660 ops.datbuf = (uint8_t *)buf;
2662 ops.mode = MTD_OPS_PLACE_OOB;
2664 ret = nand_do_write_ops(mtd, to, &ops);
2666 *retlen = ops.retlen;
2671 * nand_write - [MTD Interface] NAND write with ECC
2672 * @mtd: MTD device structure
2673 * @to: offset to write to
2674 * @len: number of bytes to write
2675 * @retlen: pointer to variable to store the number of written bytes
2676 * @buf: the data to write
2678 * NAND write with ECC.
2680 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2681 size_t *retlen, const uint8_t *buf)
2683 struct mtd_oob_ops ops;
2686 nand_get_device(mtd, FL_WRITING);
2688 ops.datbuf = (uint8_t *)buf;
2690 ops.mode = MTD_OPS_PLACE_OOB;
2691 ret = nand_do_write_ops(mtd, to, &ops);
2692 *retlen = ops.retlen;
2693 nand_release_device(mtd);
2698 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2699 * @mtd: MTD device structure
2700 * @to: offset to write to
2701 * @ops: oob operation description structure
2703 * NAND write out-of-band.
2705 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2706 struct mtd_oob_ops *ops)
2708 int chipnr, page, status, len;
2709 struct nand_chip *chip = mtd->priv;
2711 pr_debug("%s: to = 0x%08x, len = %i\n",
2712 __func__, (unsigned int)to, (int)ops->ooblen);
2714 if (ops->mode == MTD_OPS_AUTO_OOB)
2715 len = chip->ecc.layout->oobavail;
2719 /* Do not allow write past end of page */
2720 if ((ops->ooboffs + ops->ooblen) > len) {
2721 pr_debug("%s: attempt to write past end of page\n",
2726 if (unlikely(ops->ooboffs >= len)) {
2727 pr_debug("%s: attempt to start write outside oob\n",
2732 /* Do not allow write past end of device */
2733 if (unlikely(to >= mtd->size ||
2734 ops->ooboffs + ops->ooblen >
2735 ((mtd->size >> chip->page_shift) -
2736 (to >> chip->page_shift)) * len)) {
2737 pr_debug("%s: attempt to write beyond end of device\n",
2742 chipnr = (int)(to >> chip->chip_shift);
2743 chip->select_chip(mtd, chipnr);
2745 /* Shift to get page */
2746 page = (int)(to >> chip->page_shift);
2749 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2750 * of my DiskOnChip 2000 test units) will clear the whole data page too
2751 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2752 * it in the doc2000 driver in August 1999. dwmw2.
2754 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2756 /* Check, if it is write protected */
2757 if (nand_check_wp(mtd)) {
2758 chip->select_chip(mtd, -1);
2762 /* Invalidate the page cache, if we write to the cached page */
2763 if (page == chip->pagebuf)
2766 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2768 if (ops->mode == MTD_OPS_RAW)
2769 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2771 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2773 chip->select_chip(mtd, -1);
2778 ops->oobretlen = ops->ooblen;
2784 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2785 * @mtd: MTD device structure
2786 * @to: offset to write to
2787 * @ops: oob operation description structure
2789 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2790 struct mtd_oob_ops *ops)
2792 int ret = -ENOTSUPP;
2796 /* Do not allow writes past end of device */
2797 if (ops->datbuf && (to + ops->len) > mtd->size) {
2798 pr_debug("%s: attempt to write beyond end of device\n",
2803 nand_get_device(mtd, FL_WRITING);
2805 switch (ops->mode) {
2806 case MTD_OPS_PLACE_OOB:
2807 case MTD_OPS_AUTO_OOB:
2816 ret = nand_do_write_oob(mtd, to, ops);
2818 ret = nand_do_write_ops(mtd, to, ops);
2821 nand_release_device(mtd);
2826 * single_erase_cmd - [GENERIC] NAND standard block erase command function
2827 * @mtd: MTD device structure
2828 * @page: the page address of the block which will be erased
2830 * Standard erase command for NAND chips.
2832 static void single_erase_cmd(struct mtd_info *mtd, int page)
2834 struct nand_chip *chip = mtd->priv;
2835 /* Send commands to erase a block */
2836 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2837 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2841 * nand_erase - [MTD Interface] erase block(s)
2842 * @mtd: MTD device structure
2843 * @instr: erase instruction
2845 * Erase one ore more blocks.
2847 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2849 return nand_erase_nand(mtd, instr, 0);
2853 * nand_erase_nand - [INTERN] erase block(s)
2854 * @mtd: MTD device structure
2855 * @instr: erase instruction
2856 * @allowbbt: allow erasing the bbt area
2858 * Erase one ore more blocks.
2860 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2863 int page, status, pages_per_block, ret, chipnr;
2864 struct nand_chip *chip = mtd->priv;
2867 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2868 __func__, (unsigned long long)instr->addr,
2869 (unsigned long long)instr->len);
2871 if (check_offs_len(mtd, instr->addr, instr->len))
2874 /* Grab the lock and see if the device is available */
2875 nand_get_device(mtd, FL_ERASING);
2877 /* Shift to get first page */
2878 page = (int)(instr->addr >> chip->page_shift);
2879 chipnr = (int)(instr->addr >> chip->chip_shift);
2881 /* Calculate pages in each block */
2882 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2884 /* Select the NAND device */
2885 chip->select_chip(mtd, chipnr);
2887 /* Check, if it is write protected */
2888 if (nand_check_wp(mtd)) {
2889 pr_debug("%s: device is write protected!\n",
2891 instr->state = MTD_ERASE_FAILED;
2895 /* Loop through the pages */
2898 instr->state = MTD_ERASING;
2903 /* Check if we have a bad block, we do not erase bad blocks! */
2904 if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
2905 chip->page_shift, 0, allowbbt)) {
2906 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2908 instr->state = MTD_ERASE_FAILED;
2913 * Invalidate the page cache, if we erase the block which
2914 * contains the current cached page.
2916 if (page <= chip->pagebuf && chip->pagebuf <
2917 (page + pages_per_block))
2920 chip->erase_cmd(mtd, page & chip->pagemask);
2922 status = chip->waitfunc(mtd, chip);
2925 * See if operation failed and additional status checks are
2928 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2929 status = chip->errstat(mtd, chip, FL_ERASING,
2932 /* See if block erase succeeded */
2933 if (status & NAND_STATUS_FAIL) {
2934 pr_debug("%s: failed erase, page 0x%08x\n",
2936 instr->state = MTD_ERASE_FAILED;
2938 ((loff_t)page << chip->page_shift);
2942 /* Increment page address and decrement length */
2943 len -= (1ULL << chip->phys_erase_shift);
2944 page += pages_per_block;
2946 /* Check, if we cross a chip boundary */
2947 if (len && !(page & chip->pagemask)) {
2949 chip->select_chip(mtd, -1);
2950 chip->select_chip(mtd, chipnr);
2953 instr->state = MTD_ERASE_DONE;
2957 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2959 /* Deselect and wake up anyone waiting on the device */
2960 chip->select_chip(mtd, -1);
2961 nand_release_device(mtd);
2963 /* Do call back function */
2965 mtd_erase_callback(instr);
2967 /* Return more or less happy */
2972 * nand_sync - [MTD Interface] sync
2973 * @mtd: MTD device structure
2975 * Sync is actually a wait for chip ready function.
2977 static void nand_sync(struct mtd_info *mtd)
2979 pr_debug("%s: called\n", __func__);
2981 /* Grab the lock and see if the device is available */
2982 nand_get_device(mtd, FL_SYNCING);
2983 /* Release it and go back */
2984 nand_release_device(mtd);
2988 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2989 * @mtd: MTD device structure
2990 * @offs: offset relative to mtd start
2992 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2994 return nand_block_checkbad(mtd, offs, 1, 0);
2998 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2999 * @mtd: MTD device structure
3000 * @ofs: offset relative to mtd start
3002 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
3006 ret = nand_block_isbad(mtd, ofs);
3008 /* If it was bad already, return success and do nothing */
3014 return nand_block_markbad_lowlevel(mtd, ofs);
3018 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3019 * @mtd: MTD device structure
3020 * @chip: nand chip info structure
3021 * @addr: feature address.
3022 * @subfeature_param: the subfeature parameters, a four bytes array.
3024 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
3025 int addr, uint8_t *subfeature_param)
3030 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3031 if (!chip->onfi_version ||
3032 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3033 & ONFI_OPT_CMD_SET_GET_FEATURES))
3037 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
3038 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3039 chip->write_byte(mtd, subfeature_param[i]);
3041 status = chip->waitfunc(mtd, chip);
3042 if (status & NAND_STATUS_FAIL)
3048 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3049 * @mtd: MTD device structure
3050 * @chip: nand chip info structure
3051 * @addr: feature address.
3052 * @subfeature_param: the subfeature parameters, a four bytes array.
3054 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
3055 int addr, uint8_t *subfeature_param)
3059 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3060 if (!chip->onfi_version ||
3061 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3062 & ONFI_OPT_CMD_SET_GET_FEATURES))
3066 /* clear the sub feature parameters */
3067 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
3069 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
3070 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3071 *subfeature_param++ = chip->read_byte(mtd);
3077 * nand_suspend - [MTD Interface] Suspend the NAND flash
3078 * @mtd: MTD device structure
3080 static int nand_suspend(struct mtd_info *mtd)
3082 return nand_get_device(mtd, FL_PM_SUSPENDED);
3086 * nand_resume - [MTD Interface] Resume the NAND flash
3087 * @mtd: MTD device structure
3089 static void nand_resume(struct mtd_info *mtd)
3091 struct nand_chip *chip = mtd->priv;
3093 if (chip->state == FL_PM_SUSPENDED)
3094 nand_release_device(mtd);
3096 pr_err("%s called for a chip which is not in suspended state\n",
3101 /* Set default functions */
3102 static void nand_set_defaults(struct nand_chip *chip, int busw)
3104 /* check for proper chip_delay setup, set 20us if not */
3105 if (!chip->chip_delay)
3106 chip->chip_delay = 20;
3108 /* check, if a user supplied command function given */
3109 if (chip->cmdfunc == NULL)
3110 chip->cmdfunc = nand_command;
3112 /* check, if a user supplied wait function given */
3113 if (chip->waitfunc == NULL)
3114 chip->waitfunc = nand_wait;
3116 if (!chip->select_chip)
3117 chip->select_chip = nand_select_chip;
3119 /* set for ONFI nand */
3120 if (!chip->onfi_set_features)
3121 chip->onfi_set_features = nand_onfi_set_features;
3122 if (!chip->onfi_get_features)
3123 chip->onfi_get_features = nand_onfi_get_features;
3125 /* If called twice, pointers that depend on busw may need to be reset */
3126 if (!chip->read_byte || chip->read_byte == nand_read_byte)
3127 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3128 if (!chip->read_word)
3129 chip->read_word = nand_read_word;
3130 if (!chip->block_bad)
3131 chip->block_bad = nand_block_bad;
3132 if (!chip->block_markbad)
3133 chip->block_markbad = nand_default_block_markbad;
3134 if (!chip->write_buf || chip->write_buf == nand_write_buf)
3135 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
3136 if (!chip->write_byte || chip->write_byte == nand_write_byte)
3137 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
3138 if (!chip->read_buf || chip->read_buf == nand_read_buf)
3139 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
3140 if (!chip->scan_bbt)
3141 chip->scan_bbt = nand_default_bbt;
3143 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
3144 if (!chip->verify_buf)
3145 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
3149 if (!chip->controller) {
3150 chip->controller = &chip->hwcontrol;
3151 spin_lock_init(&chip->controller->lock);
3152 init_waitqueue_head(&chip->controller->wq);
3157 /* Sanitize ONFI strings so we can safely print them */
3159 static void sanitize_string(uint8_t *s, size_t len)
3161 static void sanitize_string(char *s, size_t len)
3166 /* Null terminate */
3169 /* Remove non printable chars */
3170 for (i = 0; i < len - 1; i++) {
3171 if (s[i] < ' ' || s[i] > 127)
3175 /* Remove trailing spaces */
3179 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3184 for (i = 0; i < 8; i++)
3185 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3191 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3192 /* Parse the Extended Parameter Page. */
3193 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3194 struct nand_chip *chip, struct nand_onfi_params *p)
3196 struct onfi_ext_param_page *ep;
3197 struct onfi_ext_section *s;
3198 struct onfi_ext_ecc_info *ecc;
3204 len = le16_to_cpu(p->ext_param_page_length) * 16;
3205 ep = kmalloc(len, GFP_KERNEL);
3209 /* Send our own NAND_CMD_PARAM. */
3210 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3212 /* Use the Change Read Column command to skip the ONFI param pages. */
3213 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3214 sizeof(*p) * p->num_of_param_pages , -1);
3216 /* Read out the Extended Parameter Page. */
3217 chip->read_buf(mtd, (uint8_t *)ep, len);
3218 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3219 != le16_to_cpu(ep->crc))) {
3220 pr_debug("fail in the CRC.\n");
3225 * Check the signature.
3226 * Do not strictly follow the ONFI spec, maybe changed in future.
3229 if (strncmp(ep->sig, "EPPS", 4)) {
3231 if (strncmp((char *)ep->sig, "EPPS", 4)) {
3233 pr_debug("The signature is invalid.\n");
3237 /* find the ECC section. */
3238 cursor = (uint8_t *)(ep + 1);
3239 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3240 s = ep->sections + i;
3241 if (s->type == ONFI_SECTION_TYPE_2)
3243 cursor += s->length * 16;
3245 if (i == ONFI_EXT_SECTION_MAX) {
3246 pr_debug("We can not find the ECC section.\n");
3250 /* get the info we want. */
3251 ecc = (struct onfi_ext_ecc_info *)cursor;
3253 if (!ecc->codeword_size) {
3254 pr_debug("Invalid codeword size\n");
3258 chip->ecc_strength_ds = ecc->ecc_bits;
3259 chip->ecc_step_ds = 1 << ecc->codeword_size;
3267 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3269 struct nand_chip *chip = mtd->priv;
3270 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3272 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3277 * Configure chip properties from Micron vendor-specific ONFI table
3279 static void nand_onfi_detect_micron(struct nand_chip *chip,
3280 struct nand_onfi_params *p)
3282 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3284 if (le16_to_cpu(p->vendor_revision) < 1)
3287 chip->read_retries = micron->read_retry_options;
3288 chip->setup_read_retry = nand_setup_read_retry_micron;
3292 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3294 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3297 struct nand_onfi_params *p = &chip->onfi_params;
3301 /* Try ONFI for unknown chip or LP */
3302 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3303 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3304 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3307 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3308 for (i = 0; i < 3; i++) {
3309 for (j = 0; j < sizeof(*p); j++)
3310 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3311 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3312 le16_to_cpu(p->crc)) {
3318 pr_err("Could not find valid ONFI parameter page; aborting\n");
3323 val = le16_to_cpu(p->revision);
3325 chip->onfi_version = 23;
3326 else if (val & (1 << 4))
3327 chip->onfi_version = 22;
3328 else if (val & (1 << 3))
3329 chip->onfi_version = 21;
3330 else if (val & (1 << 2))
3331 chip->onfi_version = 20;
3332 else if (val & (1 << 1))
3333 chip->onfi_version = 10;
3335 if (!chip->onfi_version) {
3336 pr_info("unsupported ONFI version: %d\n", val);
3340 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3341 sanitize_string(p->model, sizeof(p->model));
3343 mtd->name = p->model;
3345 mtd->writesize = le32_to_cpu(p->byte_per_page);
3348 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3349 * (don't ask me who thought of this...). MTD assumes that these
3350 * dimensions will be power-of-2, so just truncate the remaining area.
3352 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3353 mtd->erasesize *= mtd->writesize;
3355 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3357 /* See erasesize comment */
3358 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3359 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3360 chip->bits_per_cell = p->bits_per_cell;
3362 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3363 *busw = NAND_BUSWIDTH_16;
3367 if (p->ecc_bits != 0xff) {
3368 chip->ecc_strength_ds = p->ecc_bits;
3369 chip->ecc_step_ds = 512;
3370 } else if (chip->onfi_version >= 21 &&
3371 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3374 * The nand_flash_detect_ext_param_page() uses the
3375 * Change Read Column command which maybe not supported
3376 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3377 * now. We do not replace user supplied command function.
3379 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3380 chip->cmdfunc = nand_command_lp;
3382 /* The Extended Parameter Page is supported since ONFI 2.1. */
3383 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3384 pr_warn("Failed to detect ONFI extended param page\n");
3386 pr_warn("Could not retrieve ONFI ECC requirements\n");
3389 if (p->jedec_id == NAND_MFR_MICRON)
3390 nand_onfi_detect_micron(chip, p);
3395 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3403 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3405 static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3408 struct nand_jedec_params *p = &chip->jedec_params;
3409 struct jedec_ecc_info *ecc;
3413 /* Try JEDEC for unknown chip or LP */
3414 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3415 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3416 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3417 chip->read_byte(mtd) != 'C')
3420 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3421 for (i = 0; i < 3; i++) {
3422 for (j = 0; j < sizeof(*p); j++)
3423 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3425 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3426 le16_to_cpu(p->crc))
3431 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3436 val = le16_to_cpu(p->revision);
3438 chip->jedec_version = 10;
3439 else if (val & (1 << 1))
3440 chip->jedec_version = 1; /* vendor specific version */
3442 if (!chip->jedec_version) {
3443 pr_info("unsupported JEDEC version: %d\n", val);
3447 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3448 sanitize_string(p->model, sizeof(p->model));
3450 mtd->name = p->model;
3452 mtd->writesize = le32_to_cpu(p->byte_per_page);
3454 /* Please reference to the comment for nand_flash_detect_onfi. */
3455 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3456 mtd->erasesize *= mtd->writesize;
3458 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3460 /* Please reference to the comment for nand_flash_detect_onfi. */
3461 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3462 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3463 chip->bits_per_cell = p->bits_per_cell;
3465 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3466 *busw = NAND_BUSWIDTH_16;
3471 ecc = &p->ecc_info[0];
3473 if (ecc->codeword_size >= 9) {
3474 chip->ecc_strength_ds = ecc->ecc_bits;
3475 chip->ecc_step_ds = 1 << ecc->codeword_size;
3477 pr_warn("Invalid codeword size\n");
3484 * nand_id_has_period - Check if an ID string has a given wraparound period
3485 * @id_data: the ID string
3486 * @arrlen: the length of the @id_data array
3487 * @period: the period of repitition
3489 * Check if an ID string is repeated within a given sequence of bytes at
3490 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3491 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3492 * if the repetition has a period of @period; otherwise, returns zero.
3494 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3497 for (i = 0; i < period; i++)
3498 for (j = i + period; j < arrlen; j += period)
3499 if (id_data[i] != id_data[j])
3505 * nand_id_len - Get the length of an ID string returned by CMD_READID
3506 * @id_data: the ID string
3507 * @arrlen: the length of the @id_data array
3509 * Returns the length of the ID string, according to known wraparound/trailing
3510 * zero patterns. If no pattern exists, returns the length of the array.
3512 static int nand_id_len(u8 *id_data, int arrlen)
3514 int last_nonzero, period;
3516 /* Find last non-zero byte */
3517 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3518 if (id_data[last_nonzero])
3522 if (last_nonzero < 0)
3525 /* Calculate wraparound period */
3526 for (period = 1; period < arrlen; period++)
3527 if (nand_id_has_period(id_data, arrlen, period))
3530 /* There's a repeated pattern */
3531 if (period < arrlen)
3534 /* There are trailing zeros */
3535 if (last_nonzero < arrlen - 1)
3536 return last_nonzero + 1;
3538 /* No pattern detected */
3542 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3543 static int nand_get_bits_per_cell(u8 cellinfo)
3547 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3548 bits >>= NAND_CI_CELLTYPE_SHIFT;
3553 * Many new NAND share similar device ID codes, which represent the size of the
3554 * chip. The rest of the parameters must be decoded according to generic or
3555 * manufacturer-specific "extended ID" decoding patterns.
3557 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3558 u8 id_data[8], int *busw)
3561 /* The 3rd id byte holds MLC / multichip data */
3562 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3563 /* The 4th id byte is the important one */
3566 id_len = nand_id_len(id_data, 8);
3569 * Field definitions are in the following datasheets:
3570 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3571 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3572 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3574 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3575 * ID to decide what to do.
3577 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3578 !nand_is_slc(chip) && id_data[5] != 0x00) {
3580 mtd->writesize = 2048 << (extid & 0x03);
3583 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3603 default: /* Other cases are "reserved" (unknown) */
3604 mtd->oobsize = 1024;
3608 /* Calc blocksize */
3609 mtd->erasesize = (128 * 1024) <<
3610 (((extid >> 1) & 0x04) | (extid & 0x03));
3612 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3613 !nand_is_slc(chip)) {
3617 mtd->writesize = 2048 << (extid & 0x03);
3620 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3644 /* Calc blocksize */
3645 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3647 mtd->erasesize = (128 * 1024) << tmp;
3648 else if (tmp == 0x03)
3649 mtd->erasesize = 768 * 1024;
3651 mtd->erasesize = (64 * 1024) << tmp;
3655 mtd->writesize = 1024 << (extid & 0x03);
3658 mtd->oobsize = (8 << (extid & 0x01)) *
3659 (mtd->writesize >> 9);
3661 /* Calc blocksize. Blocksize is multiples of 64KiB */
3662 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3664 /* Get buswidth information */
3665 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3668 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3669 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3671 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3673 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3675 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3676 nand_is_slc(chip) &&
3677 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3678 !(id_data[4] & 0x80) /* !BENAND */) {
3679 mtd->oobsize = 32 * mtd->writesize >> 9;
3686 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3687 * decodes a matching ID table entry and assigns the MTD size parameters for
3690 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3691 struct nand_flash_dev *type, u8 id_data[8],
3694 int maf_id = id_data[0];
3696 mtd->erasesize = type->erasesize;
3697 mtd->writesize = type->pagesize;
3698 mtd->oobsize = mtd->writesize / 32;
3699 *busw = type->options & NAND_BUSWIDTH_16;
3701 /* All legacy ID NAND are small-page, SLC */
3702 chip->bits_per_cell = 1;
3705 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3706 * some Spansion chips have erasesize that conflicts with size
3707 * listed in nand_ids table.
3708 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3710 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3711 && id_data[6] == 0x00 && id_data[7] == 0x00
3712 && mtd->writesize == 512) {
3713 mtd->erasesize = 128 * 1024;
3714 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3719 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3720 * heuristic patterns using various detected parameters (e.g., manufacturer,
3721 * page size, cell-type information).
3723 static void nand_decode_bbm_options(struct mtd_info *mtd,
3724 struct nand_chip *chip, u8 id_data[8])
3726 int maf_id = id_data[0];
3728 /* Set the bad block position */
3729 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3730 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3732 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3735 * Bad block marker is stored in the last page of each block on Samsung
3736 * and Hynix MLC devices; stored in first two pages of each block on
3737 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3738 * AMD/Spansion, and Macronix. All others scan only the first page.
3740 if (!nand_is_slc(chip) &&
3741 (maf_id == NAND_MFR_SAMSUNG ||
3742 maf_id == NAND_MFR_HYNIX))
3743 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3744 else if ((nand_is_slc(chip) &&
3745 (maf_id == NAND_MFR_SAMSUNG ||
3746 maf_id == NAND_MFR_HYNIX ||
3747 maf_id == NAND_MFR_TOSHIBA ||
3748 maf_id == NAND_MFR_AMD ||
3749 maf_id == NAND_MFR_MACRONIX)) ||
3750 (mtd->writesize == 2048 &&
3751 maf_id == NAND_MFR_MICRON))
3752 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3755 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3757 return type->id_len;
3760 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3761 struct nand_flash_dev *type, u8 *id_data, int *busw)
3764 if (!strncmp(type->id, id_data, type->id_len)) {
3766 if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) {
3768 mtd->writesize = type->pagesize;
3769 mtd->erasesize = type->erasesize;
3770 mtd->oobsize = type->oobsize;
3772 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3773 chip->chipsize = (uint64_t)type->chipsize << 20;
3774 chip->options |= type->options;
3775 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3776 chip->ecc_step_ds = NAND_ECC_STEP(type);
3778 *busw = type->options & NAND_BUSWIDTH_16;
3781 mtd->name = type->name;
3789 * Get the flash and manufacturer id and lookup if the type is supported.
3791 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3792 struct nand_chip *chip,
3793 int *maf_id, int *dev_id,
3794 struct nand_flash_dev *type)
3800 /* Select the device */
3801 chip->select_chip(mtd, 0);
3804 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3807 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3809 /* Send the command for reading device ID */
3810 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3812 /* Read manufacturer and device IDs */
3813 *maf_id = chip->read_byte(mtd);
3814 *dev_id = chip->read_byte(mtd);
3817 * Try again to make sure, as some systems the bus-hold or other
3818 * interface concerns can cause random data which looks like a
3819 * possibly credible NAND flash to appear. If the two results do
3820 * not match, ignore the device completely.
3823 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3825 /* Read entire ID string */
3826 for (i = 0; i < 8; i++)
3827 id_data[i] = chip->read_byte(mtd);
3829 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3830 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3831 *maf_id, *dev_id, id_data[0], id_data[1]);
3832 return ERR_PTR(-ENODEV);
3836 type = nand_flash_ids;
3838 for (; type->name != NULL; type++) {
3839 if (is_full_id_nand(type)) {
3840 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3842 } else if (*dev_id == type->dev_id) {
3847 chip->onfi_version = 0;
3848 if (!type->name || !type->pagesize) {
3849 /* Check is chip is ONFI compliant */
3850 if (nand_flash_detect_onfi(mtd, chip, &busw))
3853 /* Check if the chip is JEDEC compliant */
3854 if (nand_flash_detect_jedec(mtd, chip, &busw))
3859 return ERR_PTR(-ENODEV);
3862 mtd->name = type->name;
3864 chip->chipsize = (uint64_t)type->chipsize << 20;
3866 if (!type->pagesize && chip->init_size) {
3867 /* Set the pagesize, oobsize, erasesize by the driver */
3868 busw = chip->init_size(mtd, chip, id_data);
3869 } else if (!type->pagesize) {
3870 /* Decode parameters from extended ID */
3871 nand_decode_ext_id(mtd, chip, id_data, &busw);
3873 nand_decode_id(mtd, chip, type, id_data, &busw);
3875 /* Get chip options */
3876 chip->options |= type->options;
3879 * Check if chip is not a Samsung device. Do not clear the
3880 * options for chips which do not have an extended id.
3882 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3883 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3886 /* Try to identify manufacturer */
3887 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3888 if (nand_manuf_ids[maf_idx].id == *maf_id)
3892 if (chip->options & NAND_BUSWIDTH_AUTO) {
3893 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3894 chip->options |= busw;
3895 nand_set_defaults(chip, busw);
3896 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3898 * Check, if buswidth is correct. Hardware drivers should set
3901 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3903 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3904 pr_warn("bus width %d instead %d bit\n",
3905 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3907 return ERR_PTR(-EINVAL);
3910 nand_decode_bbm_options(mtd, chip, id_data);
3912 /* Calculate the address shift from the page size */
3913 chip->page_shift = ffs(mtd->writesize) - 1;
3914 /* Convert chipsize to number of pages per chip -1 */
3915 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3917 chip->bbt_erase_shift = chip->phys_erase_shift =
3918 ffs(mtd->erasesize) - 1;
3919 if (chip->chipsize & 0xffffffff)
3920 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3922 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3923 chip->chip_shift += 32 - 1;
3926 chip->badblockbits = 8;
3927 chip->erase_cmd = single_erase_cmd;
3929 /* Do not replace user supplied command function! */
3930 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3931 chip->cmdfunc = nand_command_lp;
3933 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3936 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3937 if (chip->onfi_version)
3938 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3939 chip->onfi_params.model);
3940 else if (chip->jedec_version)
3941 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3942 chip->jedec_params.model);
3944 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3947 if (chip->jedec_version)
3948 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3949 chip->jedec_params.model);
3951 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3954 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3958 pr_info("%dMiB, %s, page size: %d, OOB size: %d\n",
3959 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3960 mtd->writesize, mtd->oobsize);
3965 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3966 * @mtd: MTD device structure
3967 * @maxchips: number of chips to scan for
3968 * @table: alternative NAND ID table
3970 * This is the first phase of the normal nand_scan() function. It reads the
3971 * flash ID and sets up MTD fields accordingly.
3973 * The mtd->owner field must be set to the module of the caller.
3975 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3976 struct nand_flash_dev *table)
3978 int i, nand_maf_id, nand_dev_id;
3979 struct nand_chip *chip = mtd->priv;
3980 struct nand_flash_dev *type;
3982 /* Set the default functions */
3983 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
3985 /* Read the flash type */
3986 type = nand_get_flash_type(mtd, chip, &nand_maf_id,
3987 &nand_dev_id, table);
3990 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3991 pr_warn("No NAND device found\n");
3992 chip->select_chip(mtd, -1);
3993 return PTR_ERR(type);
3996 chip->select_chip(mtd, -1);
3998 /* Check for a chip array */
3999 for (i = 1; i < maxchips; i++) {
4000 chip->select_chip(mtd, i);
4001 /* See comment in nand_get_flash_type for reset */
4002 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
4003 /* Send the command for reading device ID */
4004 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
4005 /* Read manufacturer and device IDs */
4006 if (nand_maf_id != chip->read_byte(mtd) ||
4007 nand_dev_id != chip->read_byte(mtd)) {
4008 chip->select_chip(mtd, -1);
4011 chip->select_chip(mtd, -1);
4016 pr_info("%d chips detected\n", i);
4019 /* Store the number of chips and calc total size for mtd */
4021 mtd->size = i * chip->chipsize;
4025 EXPORT_SYMBOL(nand_scan_ident);
4029 * nand_scan_tail - [NAND Interface] Scan for the NAND device
4030 * @mtd: MTD device structure
4032 * This is the second phase of the normal nand_scan() function. It fills out
4033 * all the uninitialized function pointers with the defaults and scans for a
4034 * bad block table if appropriate.
4036 int nand_scan_tail(struct mtd_info *mtd)
4039 struct nand_chip *chip = mtd->priv;
4040 struct nand_ecc_ctrl *ecc = &chip->ecc;
4041 struct nand_buffers *nbuf;
4043 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4044 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
4045 !(chip->bbt_options & NAND_BBT_USE_FLASH));
4047 if (!(chip->options & NAND_OWN_BUFFERS)) {
4049 nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
4050 + mtd->oobsize * 3, GFP_KERNEL);
4053 nbuf->ecccalc = (uint8_t *)(nbuf + 1);
4054 nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
4055 nbuf->databuf = nbuf->ecccode + mtd->oobsize;
4057 nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL);
4060 chip->buffers = nbuf;
4066 /* Set the internal oob buffer location, just after the page data */
4067 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
4070 * If no default placement scheme is given, select an appropriate one.
4072 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
4073 switch (mtd->oobsize) {
4075 ecc->layout = &nand_oob_8;
4078 ecc->layout = &nand_oob_16;
4081 ecc->layout = &nand_oob_64;
4084 ecc->layout = &nand_oob_128;
4087 pr_warn("No oob scheme defined for oobsize %d\n",
4093 if (!chip->write_page)
4094 chip->write_page = nand_write_page;
4097 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4098 * selected and we have 256 byte pagesize fallback to software ECC
4101 switch (ecc->mode) {
4102 case NAND_ECC_HW_OOB_FIRST:
4103 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4104 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
4105 pr_warn("No ECC functions supplied; "
4106 "hardware ECC not possible\n");
4109 if (!ecc->read_page)
4110 ecc->read_page = nand_read_page_hwecc_oob_first;
4113 /* Use standard hwecc read page function? */
4114 if (!ecc->read_page)
4115 ecc->read_page = nand_read_page_hwecc;
4116 if (!ecc->write_page)
4117 ecc->write_page = nand_write_page_hwecc;
4118 if (!ecc->read_page_raw)
4119 ecc->read_page_raw = nand_read_page_raw;
4120 if (!ecc->write_page_raw)
4121 ecc->write_page_raw = nand_write_page_raw;
4123 ecc->read_oob = nand_read_oob_std;
4124 if (!ecc->write_oob)
4125 ecc->write_oob = nand_write_oob_std;
4126 if (!ecc->read_subpage)
4127 ecc->read_subpage = nand_read_subpage;
4128 if (!ecc->write_subpage)
4129 ecc->write_subpage = nand_write_subpage_hwecc;
4131 case NAND_ECC_HW_SYNDROME:
4132 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
4134 ecc->read_page == nand_read_page_hwecc ||
4136 ecc->write_page == nand_write_page_hwecc)) {
4137 pr_warn("No ECC functions supplied; "
4138 "hardware ECC not possible\n");
4141 /* Use standard syndrome read/write page function? */
4142 if (!ecc->read_page)
4143 ecc->read_page = nand_read_page_syndrome;
4144 if (!ecc->write_page)
4145 ecc->write_page = nand_write_page_syndrome;
4146 if (!ecc->read_page_raw)
4147 ecc->read_page_raw = nand_read_page_raw_syndrome;
4148 if (!ecc->write_page_raw)
4149 ecc->write_page_raw = nand_write_page_raw_syndrome;
4151 ecc->read_oob = nand_read_oob_syndrome;
4152 if (!ecc->write_oob)
4153 ecc->write_oob = nand_write_oob_syndrome;
4155 if (mtd->writesize >= ecc->size) {
4156 if (!ecc->strength) {
4157 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4162 pr_warn("%d byte HW ECC not possible on "
4163 "%d byte page size, fallback to SW ECC\n",
4164 ecc->size, mtd->writesize);
4165 ecc->mode = NAND_ECC_SOFT;
4168 ecc->calculate = nand_calculate_ecc;
4169 ecc->correct = nand_correct_data;
4170 ecc->read_page = nand_read_page_swecc;
4171 ecc->read_subpage = nand_read_subpage;
4172 ecc->write_page = nand_write_page_swecc;
4173 ecc->read_page_raw = nand_read_page_raw;
4174 ecc->write_page_raw = nand_write_page_raw;
4175 ecc->read_oob = nand_read_oob_std;
4176 ecc->write_oob = nand_write_oob_std;
4183 case NAND_ECC_SOFT_BCH:
4184 if (!mtd_nand_has_bch()) {
4185 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4188 ecc->calculate = nand_bch_calculate_ecc;
4189 ecc->correct = nand_bch_correct_data;
4190 ecc->read_page = nand_read_page_swecc;
4191 ecc->read_subpage = nand_read_subpage;
4192 ecc->write_page = nand_write_page_swecc;
4193 ecc->read_page_raw = nand_read_page_raw;
4194 ecc->write_page_raw = nand_write_page_raw;
4195 ecc->read_oob = nand_read_oob_std;
4196 ecc->write_oob = nand_write_oob_std;
4198 * Board driver should supply ecc.size and ecc.bytes values to
4199 * select how many bits are correctable; see nand_bch_init()
4200 * for details. Otherwise, default to 4 bits for large page
4203 if (!ecc->size && (mtd->oobsize >= 64)) {
4207 ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
4210 pr_warn("BCH ECC initialization failed!\n");
4213 ecc->strength = ecc->bytes * 8 / fls(8 * ecc->size);
4217 pr_warn("NAND_ECC_NONE selected by board driver. "
4218 "This is not recommended!\n");
4219 ecc->read_page = nand_read_page_raw;
4220 ecc->write_page = nand_write_page_raw;
4221 ecc->read_oob = nand_read_oob_std;
4222 ecc->read_page_raw = nand_read_page_raw;
4223 ecc->write_page_raw = nand_write_page_raw;
4224 ecc->write_oob = nand_write_oob_std;
4225 ecc->size = mtd->writesize;
4231 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
4235 /* For many systems, the standard OOB write also works for raw */
4236 if (!ecc->read_oob_raw)
4237 ecc->read_oob_raw = ecc->read_oob;
4238 if (!ecc->write_oob_raw)
4239 ecc->write_oob_raw = ecc->write_oob;
4242 * The number of bytes available for a client to place data into
4243 * the out of band area.
4245 ecc->layout->oobavail = 0;
4246 for (i = 0; ecc->layout->oobfree[i].length
4247 && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
4248 ecc->layout->oobavail += ecc->layout->oobfree[i].length;
4249 mtd->oobavail = ecc->layout->oobavail;
4252 * Set the number of read / write steps for one page depending on ECC
4255 ecc->steps = mtd->writesize / ecc->size;
4256 if (ecc->steps * ecc->size != mtd->writesize) {
4257 pr_warn("Invalid ECC parameters\n");
4260 ecc->total = ecc->steps * ecc->bytes;
4262 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4263 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
4264 switch (ecc->steps) {
4266 mtd->subpage_sft = 1;
4271 mtd->subpage_sft = 2;
4275 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4277 /* Initialize state */
4278 chip->state = FL_READY;
4280 /* Invalidate the pagebuffer reference */
4283 /* Large page NAND with SOFT_ECC should support subpage reads */
4284 if ((ecc->mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
4285 chip->options |= NAND_SUBPAGE_READ;
4287 /* Fill in remaining MTD driver data */
4288 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
4289 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4291 mtd->_erase = nand_erase;
4294 mtd->_unpoint = NULL;
4296 mtd->_read = nand_read;
4297 mtd->_write = nand_write;
4298 mtd->_panic_write = panic_nand_write;
4299 mtd->_read_oob = nand_read_oob;
4300 mtd->_write_oob = nand_write_oob;
4301 mtd->_sync = nand_sync;
4303 mtd->_unlock = NULL;
4305 mtd->_suspend = nand_suspend;
4306 mtd->_resume = nand_resume;
4308 mtd->_block_isbad = nand_block_isbad;
4309 mtd->_block_markbad = nand_block_markbad;
4310 mtd->writebufsize = mtd->writesize;
4312 /* propagate ecc info to mtd_info */
4313 mtd->ecclayout = ecc->layout;
4314 mtd->ecc_strength = ecc->strength;
4315 mtd->ecc_step_size = ecc->size;
4317 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4318 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4321 if (!mtd->bitflip_threshold)
4322 mtd->bitflip_threshold = mtd->ecc_strength;
4326 EXPORT_SYMBOL(nand_scan_tail);
4329 * is_module_text_address() isn't exported, and it's mostly a pointless
4330 * test if this is a module _anyway_ -- they'd have to try _really_ hard
4331 * to call us from in-kernel code if the core NAND support is modular.
4334 #define caller_is_module() (1)
4336 #define caller_is_module() \
4337 is_module_text_address((unsigned long)__builtin_return_address(0))
4341 * nand_scan - [NAND Interface] Scan for the NAND device
4342 * @mtd: MTD device structure
4343 * @maxchips: number of chips to scan for
4345 * This fills out all the uninitialized function pointers with the defaults.
4346 * The flash ID is read and the mtd/chip structures are filled with the
4347 * appropriate values. The mtd->owner field must be set to the module of the
4350 int nand_scan(struct mtd_info *mtd, int maxchips)
4354 /* Many callers got this wrong, so check for it for a while... */
4355 if (!mtd->owner && caller_is_module()) {
4356 pr_crit("%s called with NULL mtd->owner!\n", __func__);
4360 ret = nand_scan_ident(mtd, maxchips, NULL);
4362 ret = nand_scan_tail(mtd);
4365 EXPORT_SYMBOL(nand_scan);
4369 * nand_release - [NAND Interface] Free resources held by the NAND device
4370 * @mtd: MTD device structure
4372 void nand_release(struct mtd_info *mtd)
4374 struct nand_chip *chip = mtd->priv;
4376 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
4377 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4379 mtd_device_unregister(mtd);
4381 /* Free bad block table memory */
4383 if (!(chip->options & NAND_OWN_BUFFERS))
4384 kfree(chip->buffers);
4386 /* Free bad block descriptor memory */
4387 if (chip->badblock_pattern && chip->badblock_pattern->options
4388 & NAND_BBT_DYNAMICSTRUCT)
4389 kfree(chip->badblock_pattern);
4391 EXPORT_SYMBOL_GPL(nand_release);
4393 static int __init nand_base_init(void)
4395 led_trigger_register_simple("nand-disk", &nand_led_trigger);
4399 static void __exit nand_base_exit(void)
4401 led_trigger_unregister_simple(nand_led_trigger);
4405 module_init(nand_base_init);
4406 module_exit(nand_base_exit);
4408 MODULE_LICENSE("GPL");
4409 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4410 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4411 MODULE_DESCRIPTION("Generic NAND flash driver code");