5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
37 #define ENOTSUPP 524 /* Operation is not supported */
41 #include <linux/err.h>
42 #include <linux/mtd/compat.h>
43 #include <linux/mtd/mtd.h>
44 #include <linux/mtd/nand.h>
45 #include <linux/mtd/nand_ecc.h>
46 #include <linux/mtd/nand_bch.h>
48 #ifdef CONFIG_MTD_PARTITIONS
49 #include <linux/mtd/partitions.h>
53 #include <asm/errno.h>
56 * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
57 * a flash. NAND flash is initialized prior to interrupts so standard timers
58 * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
59 * which is greater than (max NAND reset time / NAND status read time).
60 * A conservative default of 200000 (500 us / 25 ns) is used as a default.
62 #ifndef CONFIG_SYS_NAND_RESET_CNT
63 #define CONFIG_SYS_NAND_RESET_CNT 200000
66 /* Define default oob placement schemes for large and small page devices */
67 static struct nand_ecclayout nand_oob_8 = {
77 static struct nand_ecclayout nand_oob_16 = {
79 .eccpos = {0, 1, 2, 3, 6, 7},
85 static struct nand_ecclayout nand_oob_64 = {
88 40, 41, 42, 43, 44, 45, 46, 47,
89 48, 49, 50, 51, 52, 53, 54, 55,
90 56, 57, 58, 59, 60, 61, 62, 63},
96 static struct nand_ecclayout nand_oob_128 = {
99 80, 81, 82, 83, 84, 85, 86, 87,
100 88, 89, 90, 91, 92, 93, 94, 95,
101 96, 97, 98, 99, 100, 101, 102, 103,
102 104, 105, 106, 107, 108, 109, 110, 111,
103 112, 113, 114, 115, 116, 117, 118, 119,
104 120, 121, 122, 123, 124, 125, 126, 127},
110 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
113 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
114 struct mtd_oob_ops *ops);
116 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
119 * nand_release_device - [GENERIC] release chip
120 * @mtd: MTD device structure
122 * Deselect, release chip lock and wake up anyone waiting on the device
124 static void nand_release_device(struct mtd_info *mtd)
126 struct nand_chip *this = mtd->priv;
127 this->select_chip(mtd, -1); /* De-select the NAND device */
131 * nand_read_byte - [DEFAULT] read one byte from the chip
132 * @mtd: MTD device structure
134 * Default read function for 8bit buswith
136 uint8_t nand_read_byte(struct mtd_info *mtd)
138 struct nand_chip *chip = mtd->priv;
139 return readb(chip->IO_ADDR_R);
143 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
144 * @mtd: MTD device structure
146 * Default read function for 16bit buswith with
147 * endianess conversion
149 static uint8_t nand_read_byte16(struct mtd_info *mtd)
151 struct nand_chip *chip = mtd->priv;
152 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
156 * nand_read_word - [DEFAULT] read one word from the chip
157 * @mtd: MTD device structure
159 * Default read function for 16bit buswith without
160 * endianess conversion
162 static u16 nand_read_word(struct mtd_info *mtd)
164 struct nand_chip *chip = mtd->priv;
165 return readw(chip->IO_ADDR_R);
169 * nand_select_chip - [DEFAULT] control CE line
170 * @mtd: MTD device structure
171 * @chipnr: chipnumber to select, -1 for deselect
173 * Default select function for 1 chip devices.
175 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
177 struct nand_chip *chip = mtd->priv;
181 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
192 * nand_write_buf - [DEFAULT] write buffer to chip
193 * @mtd: MTD device structure
195 * @len: number of bytes to write
197 * Default write function for 8bit buswith
199 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
202 struct nand_chip *chip = mtd->priv;
204 for (i = 0; i < len; i++)
205 writeb(buf[i], chip->IO_ADDR_W);
209 * nand_read_buf - [DEFAULT] read chip data into buffer
210 * @mtd: MTD device structure
211 * @buf: buffer to store date
212 * @len: number of bytes to read
214 * Default read function for 8bit buswith
216 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
219 struct nand_chip *chip = mtd->priv;
221 for (i = 0; i < len; i++)
222 buf[i] = readb(chip->IO_ADDR_R);
226 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
227 * @mtd: MTD device structure
228 * @buf: buffer containing the data to compare
229 * @len: number of bytes to compare
231 * Default verify function for 8bit buswith
233 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
236 struct nand_chip *chip = mtd->priv;
238 for (i = 0; i < len; i++)
239 if (buf[i] != readb(chip->IO_ADDR_R))
245 * nand_write_buf16 - [DEFAULT] write buffer to chip
246 * @mtd: MTD device structure
248 * @len: number of bytes to write
250 * Default write function for 16bit buswith
252 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
255 struct nand_chip *chip = mtd->priv;
256 u16 *p = (u16 *) buf;
259 for (i = 0; i < len; i++)
260 writew(p[i], chip->IO_ADDR_W);
265 * nand_read_buf16 - [DEFAULT] read chip data into buffer
266 * @mtd: MTD device structure
267 * @buf: buffer to store date
268 * @len: number of bytes to read
270 * Default read function for 16bit buswith
272 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
275 struct nand_chip *chip = mtd->priv;
276 u16 *p = (u16 *) buf;
279 for (i = 0; i < len; i++)
280 p[i] = readw(chip->IO_ADDR_R);
284 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
285 * @mtd: MTD device structure
286 * @buf: buffer containing the data to compare
287 * @len: number of bytes to compare
289 * Default verify function for 16bit buswith
291 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
294 struct nand_chip *chip = mtd->priv;
295 u16 *p = (u16 *) buf;
298 for (i = 0; i < len; i++)
299 if (p[i] != readw(chip->IO_ADDR_R))
306 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
307 * @mtd: MTD device structure
308 * @ofs: offset from device start
309 * @getchip: 0, if the chip is already selected
311 * Check, if the block is bad.
313 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
315 int page, chipnr, res = 0;
316 struct nand_chip *chip = mtd->priv;
319 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
322 chipnr = (int)(ofs >> chip->chip_shift);
324 nand_get_device(chip, mtd, FL_READING);
326 /* Select the NAND device */
327 chip->select_chip(mtd, chipnr);
330 if (chip->options & NAND_BUSWIDTH_16) {
331 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
333 bad = cpu_to_le16(chip->read_word(mtd));
334 if (chip->badblockpos & 0x1)
336 if ((bad & 0xFF) != 0xff)
339 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
340 if (chip->read_byte(mtd) != 0xff)
345 nand_release_device(mtd);
351 * nand_default_block_markbad - [DEFAULT] mark a block bad
352 * @mtd: MTD device structure
353 * @ofs: offset from device start
355 * This is the default implementation, which can be overridden by
356 * a hardware specific driver.
358 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
360 struct nand_chip *chip = mtd->priv;
361 uint8_t buf[2] = { 0, 0 };
364 /* Get block number */
365 block = (int)(ofs >> chip->bbt_erase_shift);
367 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
369 /* Do we have a flash based bad block table ? */
370 if (chip->options & NAND_USE_FLASH_BBT)
371 ret = nand_update_bbt(mtd, ofs);
373 /* We write two bytes, so we dont have to mess with 16 bit
376 nand_get_device(chip, mtd, FL_WRITING);
378 chip->ops.len = chip->ops.ooblen = 2;
379 chip->ops.datbuf = NULL;
380 chip->ops.oobbuf = buf;
381 chip->ops.ooboffs = chip->badblockpos & ~0x01;
383 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
384 nand_release_device(mtd);
387 mtd->ecc_stats.badblocks++;
393 * nand_check_wp - [GENERIC] check if the chip is write protected
394 * @mtd: MTD device structure
395 * Check, if the device is write protected
397 * The function expects, that the device is already selected
399 static int nand_check_wp(struct mtd_info *mtd)
401 struct nand_chip *chip = mtd->priv;
402 /* Check the WP bit */
403 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
404 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
408 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
409 * @mtd: MTD device structure
410 * @ofs: offset from device start
411 * @getchip: 0, if the chip is already selected
412 * @allowbbt: 1, if its allowed to access the bbt area
414 * Check, if the block is bad. Either by reading the bad block table or
415 * calling of the scan function.
417 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
420 struct nand_chip *chip = mtd->priv;
422 if (!(chip->options & NAND_BBT_SCANNED)) {
423 chip->options |= NAND_BBT_SCANNED;
428 return chip->block_bad(mtd, ofs, getchip);
430 /* Return info from the table */
431 return nand_isbad_bbt(mtd, ofs, allowbbt);
435 * Wait for the ready pin, after a command
436 * The timeout is catched later.
438 void nand_wait_ready(struct mtd_info *mtd)
440 struct nand_chip *chip = mtd->priv;
441 u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
444 time_start = get_timer(0);
446 /* wait until command is processed or timeout occures */
447 while (get_timer(time_start) < timeo) {
449 if (chip->dev_ready(mtd))
455 * nand_command - [DEFAULT] Send command to NAND device
456 * @mtd: MTD device structure
457 * @command: the command to be sent
458 * @column: the column address for this command, -1 if none
459 * @page_addr: the page address for this command, -1 if none
461 * Send command to NAND device. This function is used for small page
462 * devices (256/512 Bytes per page)
464 static void nand_command(struct mtd_info *mtd, unsigned int command,
465 int column, int page_addr)
467 register struct nand_chip *chip = mtd->priv;
468 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
469 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
472 * Write out the command to the device.
474 if (command == NAND_CMD_SEQIN) {
477 if (column >= mtd->writesize) {
479 column -= mtd->writesize;
480 readcmd = NAND_CMD_READOOB;
481 } else if (column < 256) {
482 /* First 256 bytes --> READ0 */
483 readcmd = NAND_CMD_READ0;
486 readcmd = NAND_CMD_READ1;
488 chip->cmd_ctrl(mtd, readcmd, ctrl);
489 ctrl &= ~NAND_CTRL_CHANGE;
491 chip->cmd_ctrl(mtd, command, ctrl);
494 * Address cycle, when necessary
496 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
497 /* Serially input address */
499 /* Adjust columns for 16 bit buswidth */
500 if (chip->options & NAND_BUSWIDTH_16)
502 chip->cmd_ctrl(mtd, column, ctrl);
503 ctrl &= ~NAND_CTRL_CHANGE;
505 if (page_addr != -1) {
506 chip->cmd_ctrl(mtd, page_addr, ctrl);
507 ctrl &= ~NAND_CTRL_CHANGE;
508 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
509 /* One more address cycle for devices > 32MiB */
510 if (chip->chipsize > (32 << 20))
511 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
513 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
516 * program and erase have their own busy handlers
517 * status and sequential in needs no delay
521 case NAND_CMD_PAGEPROG:
522 case NAND_CMD_ERASE1:
523 case NAND_CMD_ERASE2:
525 case NAND_CMD_STATUS:
531 udelay(chip->chip_delay);
532 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
533 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
535 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
536 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
540 /* This applies to read commands */
543 * If we don't have access to the busy pin, we apply the given
546 if (!chip->dev_ready) {
547 udelay(chip->chip_delay);
551 /* Apply this short delay always to ensure that we do wait tWB in
552 * any case on any machine. */
555 nand_wait_ready(mtd);
559 * nand_command_lp - [DEFAULT] Send command to NAND large page device
560 * @mtd: MTD device structure
561 * @command: the command to be sent
562 * @column: the column address for this command, -1 if none
563 * @page_addr: the page address for this command, -1 if none
565 * Send command to NAND device. This is the version for the new large page
566 * devices We dont have the separate regions as we have in the small page
567 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
569 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
570 int column, int page_addr)
572 register struct nand_chip *chip = mtd->priv;
573 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
575 /* Emulate NAND_CMD_READOOB */
576 if (command == NAND_CMD_READOOB) {
577 column += mtd->writesize;
578 command = NAND_CMD_READ0;
581 /* Command latch cycle */
582 chip->cmd_ctrl(mtd, command & 0xff,
583 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
585 if (column != -1 || page_addr != -1) {
586 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
588 /* Serially input address */
590 /* Adjust columns for 16 bit buswidth */
591 if (chip->options & NAND_BUSWIDTH_16)
593 chip->cmd_ctrl(mtd, column, ctrl);
594 ctrl &= ~NAND_CTRL_CHANGE;
595 chip->cmd_ctrl(mtd, column >> 8, ctrl);
597 if (page_addr != -1) {
598 chip->cmd_ctrl(mtd, page_addr, ctrl);
599 chip->cmd_ctrl(mtd, page_addr >> 8,
600 NAND_NCE | NAND_ALE);
601 /* One more address cycle for devices > 128MiB */
602 if (chip->chipsize > (128 << 20))
603 chip->cmd_ctrl(mtd, page_addr >> 16,
604 NAND_NCE | NAND_ALE);
607 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
610 * program and erase have their own busy handlers
611 * status, sequential in, and deplete1 need no delay
615 case NAND_CMD_CACHEDPROG:
616 case NAND_CMD_PAGEPROG:
617 case NAND_CMD_ERASE1:
618 case NAND_CMD_ERASE2:
621 case NAND_CMD_STATUS:
622 case NAND_CMD_DEPLETE1:
626 * read error status commands require only a short delay
628 case NAND_CMD_STATUS_ERROR:
629 case NAND_CMD_STATUS_ERROR0:
630 case NAND_CMD_STATUS_ERROR1:
631 case NAND_CMD_STATUS_ERROR2:
632 case NAND_CMD_STATUS_ERROR3:
633 udelay(chip->chip_delay);
639 udelay(chip->chip_delay);
640 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
641 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
642 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
643 NAND_NCE | NAND_CTRL_CHANGE);
644 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
648 case NAND_CMD_RNDOUT:
649 /* No ready / busy check necessary */
650 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
651 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
652 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
653 NAND_NCE | NAND_CTRL_CHANGE);
657 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
658 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
659 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
660 NAND_NCE | NAND_CTRL_CHANGE);
662 /* This applies to read commands */
665 * If we don't have access to the busy pin, we apply the given
668 if (!chip->dev_ready) {
669 udelay(chip->chip_delay);
674 /* Apply this short delay always to ensure that we do wait tWB in
675 * any case on any machine. */
678 nand_wait_ready(mtd);
682 * nand_get_device - [GENERIC] Get chip for selected access
683 * @chip: the nand chip descriptor
684 * @mtd: MTD device structure
685 * @new_state: the state which is requested
687 * Get the device and lock it for exclusive access
689 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
691 this->state = new_state;
696 * nand_wait - [DEFAULT] wait until the command is done
697 * @mtd: MTD device structure
698 * @chip: NAND chip structure
700 * Wait for command done. This applies to erase and program only
701 * Erase can take up to 400ms and program up to 20ms according to
702 * general NAND and SmartMedia specs
704 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
707 int state = this->state;
710 if (state == FL_ERASING)
711 timeo = (CONFIG_SYS_HZ * 400) / 1000;
713 timeo = (CONFIG_SYS_HZ * 20) / 1000;
715 if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
716 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
718 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
720 time_start = get_timer(0);
723 if (get_timer(time_start) > timeo) {
728 if (this->dev_ready) {
729 if (this->dev_ready(mtd))
732 if (this->read_byte(mtd) & NAND_STATUS_READY)
736 #ifdef PPCHAMELON_NAND_TIMER_HACK
737 time_start = get_timer(0);
738 while (get_timer(time_start) < 10)
740 #endif /* PPCHAMELON_NAND_TIMER_HACK */
742 return this->read_byte(mtd);
746 * nand_read_page_raw - [Intern] read raw page data without ecc
747 * @mtd: mtd info structure
748 * @chip: nand chip info structure
749 * @buf: buffer to store read data
750 * @page: page number to read
752 * Not for syndrome calculating ecc controllers, which use a special oob layout
754 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
755 uint8_t *buf, int page)
757 chip->read_buf(mtd, buf, mtd->writesize);
758 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
763 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
764 * @mtd: mtd info structure
765 * @chip: nand chip info structure
766 * @buf: buffer to store read data
767 * @page: page number to read
769 * We need a special oob layout and handling even when OOB isn't used.
771 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
772 struct nand_chip *chip,
773 uint8_t *buf, int page)
775 int eccsize = chip->ecc.size;
776 int eccbytes = chip->ecc.bytes;
777 uint8_t *oob = chip->oob_poi;
780 for (steps = chip->ecc.steps; steps > 0; steps--) {
781 chip->read_buf(mtd, buf, eccsize);
784 if (chip->ecc.prepad) {
785 chip->read_buf(mtd, oob, chip->ecc.prepad);
786 oob += chip->ecc.prepad;
789 chip->read_buf(mtd, oob, eccbytes);
792 if (chip->ecc.postpad) {
793 chip->read_buf(mtd, oob, chip->ecc.postpad);
794 oob += chip->ecc.postpad;
798 size = mtd->oobsize - (oob - chip->oob_poi);
800 chip->read_buf(mtd, oob, size);
806 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
807 * @mtd: mtd info structure
808 * @chip: nand chip info structure
809 * @buf: buffer to store read data
810 * @page: page number to read
812 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
813 uint8_t *buf, int page)
815 int i, eccsize = chip->ecc.size;
816 int eccbytes = chip->ecc.bytes;
817 int eccsteps = chip->ecc.steps;
819 uint8_t *ecc_calc = chip->buffers->ecccalc;
820 uint8_t *ecc_code = chip->buffers->ecccode;
821 uint32_t *eccpos = chip->ecc.layout->eccpos;
823 chip->ecc.read_page_raw(mtd, chip, buf, page);
825 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
826 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
828 for (i = 0; i < chip->ecc.total; i++)
829 ecc_code[i] = chip->oob_poi[eccpos[i]];
831 eccsteps = chip->ecc.steps;
834 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
837 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
839 mtd->ecc_stats.failed++;
841 mtd->ecc_stats.corrected += stat;
847 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
848 * @mtd: mtd info structure
849 * @chip: nand chip info structure
850 * @data_offs: offset of requested data within the page
851 * @readlen: data length
852 * @bufpoi: buffer to store read data
854 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
855 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
857 int start_step, end_step, num_steps;
858 uint32_t *eccpos = chip->ecc.layout->eccpos;
860 int data_col_addr, i, gaps = 0;
861 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
862 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
864 /* Column address wihin the page aligned to ECC size (256bytes). */
865 start_step = data_offs / chip->ecc.size;
866 end_step = (data_offs + readlen - 1) / chip->ecc.size;
867 num_steps = end_step - start_step + 1;
869 /* Data size aligned to ECC ecc.size*/
870 datafrag_len = num_steps * chip->ecc.size;
871 eccfrag_len = num_steps * chip->ecc.bytes;
873 data_col_addr = start_step * chip->ecc.size;
874 /* If we read not a page aligned data */
875 if (data_col_addr != 0)
876 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
878 p = bufpoi + data_col_addr;
879 chip->read_buf(mtd, p, datafrag_len);
882 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
883 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
885 /* The performance is faster if to position offsets
886 according to ecc.pos. Let make sure here that
887 there are no gaps in ecc positions */
888 for (i = 0; i < eccfrag_len - 1; i++) {
889 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
890 eccpos[i + start_step * chip->ecc.bytes + 1]) {
896 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
897 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
899 /* send the command to read the particular ecc bytes */
900 /* take care about buswidth alignment in read_buf */
901 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
902 aligned_len = eccfrag_len;
903 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
905 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
908 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
909 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
912 for (i = 0; i < eccfrag_len; i++)
913 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
915 p = bufpoi + data_col_addr;
916 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
919 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
921 mtd->ecc_stats.failed++;
923 mtd->ecc_stats.corrected += stat;
929 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
930 * @mtd: mtd info structure
931 * @chip: nand chip info structure
932 * @buf: buffer to store read data
933 * @page: page number to read
935 * Not for syndrome calculating ecc controllers which need a special oob layout
937 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
938 uint8_t *buf, int page)
940 int i, eccsize = chip->ecc.size;
941 int eccbytes = chip->ecc.bytes;
942 int eccsteps = chip->ecc.steps;
944 uint8_t *ecc_calc = chip->buffers->ecccalc;
945 uint8_t *ecc_code = chip->buffers->ecccode;
946 uint32_t *eccpos = chip->ecc.layout->eccpos;
948 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
949 chip->ecc.hwctl(mtd, NAND_ECC_READ);
950 chip->read_buf(mtd, p, eccsize);
951 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
953 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
955 for (i = 0; i < chip->ecc.total; i++)
956 ecc_code[i] = chip->oob_poi[eccpos[i]];
958 eccsteps = chip->ecc.steps;
961 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
964 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
966 mtd->ecc_stats.failed++;
968 mtd->ecc_stats.corrected += stat;
974 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
975 * @mtd: mtd info structure
976 * @chip: nand chip info structure
977 * @buf: buffer to store read data
978 * @page: page number to read
980 * Hardware ECC for large page chips, require OOB to be read first.
981 * For this ECC mode, the write_page method is re-used from ECC_HW.
982 * These methods read/write ECC from the OOB area, unlike the
983 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
984 * "infix ECC" scheme and reads/writes ECC from the data area, by
985 * overwriting the NAND manufacturer bad block markings.
987 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
988 struct nand_chip *chip, uint8_t *buf, int page)
990 int i, eccsize = chip->ecc.size;
991 int eccbytes = chip->ecc.bytes;
992 int eccsteps = chip->ecc.steps;
994 uint8_t *ecc_code = chip->buffers->ecccode;
995 uint32_t *eccpos = chip->ecc.layout->eccpos;
996 uint8_t *ecc_calc = chip->buffers->ecccalc;
998 /* Read the OOB area first */
999 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1000 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1001 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1003 for (i = 0; i < chip->ecc.total; i++)
1004 ecc_code[i] = chip->oob_poi[eccpos[i]];
1006 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1009 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1010 chip->read_buf(mtd, p, eccsize);
1011 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1013 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1015 mtd->ecc_stats.failed++;
1017 mtd->ecc_stats.corrected += stat;
1023 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1024 * @mtd: mtd info structure
1025 * @chip: nand chip info structure
1026 * @buf: buffer to store read data
1027 * @page: page number to read
1029 * The hw generator calculates the error syndrome automatically. Therefor
1030 * we need a special oob layout and handling.
1032 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1033 uint8_t *buf, int page)
1035 int i, eccsize = chip->ecc.size;
1036 int eccbytes = chip->ecc.bytes;
1037 int eccsteps = chip->ecc.steps;
1039 uint8_t *oob = chip->oob_poi;
1041 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1044 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1045 chip->read_buf(mtd, p, eccsize);
1047 if (chip->ecc.prepad) {
1048 chip->read_buf(mtd, oob, chip->ecc.prepad);
1049 oob += chip->ecc.prepad;
1052 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1053 chip->read_buf(mtd, oob, eccbytes);
1054 stat = chip->ecc.correct(mtd, p, oob, NULL);
1057 mtd->ecc_stats.failed++;
1059 mtd->ecc_stats.corrected += stat;
1063 if (chip->ecc.postpad) {
1064 chip->read_buf(mtd, oob, chip->ecc.postpad);
1065 oob += chip->ecc.postpad;
1069 /* Calculate remaining oob bytes */
1070 i = mtd->oobsize - (oob - chip->oob_poi);
1072 chip->read_buf(mtd, oob, i);
1078 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1079 * @chip: nand chip structure
1080 * @oob: oob destination address
1081 * @ops: oob ops structure
1082 * @len: size of oob to transfer
1084 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1085 struct mtd_oob_ops *ops, size_t len)
1087 switch (ops->mode) {
1091 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1094 case MTD_OOB_AUTO: {
1095 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1096 uint32_t boffs = 0, roffs = ops->ooboffs;
1099 for (; free->length && len; free++, len -= bytes) {
1100 /* Read request not from offset 0 ? */
1101 if (unlikely(roffs)) {
1102 if (roffs >= free->length) {
1103 roffs -= free->length;
1106 boffs = free->offset + roffs;
1107 bytes = min_t(size_t, len,
1108 (free->length - roffs));
1111 bytes = min_t(size_t, len, free->length);
1112 boffs = free->offset;
1114 memcpy(oob, chip->oob_poi + boffs, bytes);
1126 * nand_do_read_ops - [Internal] Read data with ECC
1128 * @mtd: MTD device structure
1129 * @from: offset to read from
1130 * @ops: oob ops structure
1132 * Internal function. Called with chip held.
1134 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1135 struct mtd_oob_ops *ops)
1137 int chipnr, page, realpage, col, bytes, aligned;
1138 struct nand_chip *chip = mtd->priv;
1139 struct mtd_ecc_stats stats;
1140 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1143 uint32_t readlen = ops->len;
1144 uint32_t oobreadlen = ops->ooblen;
1145 uint8_t *bufpoi, *oob, *buf;
1147 stats = mtd->ecc_stats;
1149 chipnr = (int)(from >> chip->chip_shift);
1150 chip->select_chip(mtd, chipnr);
1152 realpage = (int)(from >> chip->page_shift);
1153 page = realpage & chip->pagemask;
1155 col = (int)(from & (mtd->writesize - 1));
1163 bytes = min(mtd->writesize - col, readlen);
1164 aligned = (bytes == mtd->writesize);
1166 /* Is the current page in the buffer ? */
1167 if (realpage != chip->pagebuf || oob) {
1168 bufpoi = aligned ? buf : chip->buffers->databuf;
1170 if (likely(sndcmd)) {
1171 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1175 /* Now read the page into the buffer */
1176 if (unlikely(ops->mode == MTD_OOB_RAW))
1177 ret = chip->ecc.read_page_raw(mtd, chip,
1179 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1180 ret = chip->ecc.read_subpage(mtd, chip,
1181 col, bytes, bufpoi);
1183 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1188 /* Transfer not aligned data */
1190 if (!NAND_SUBPAGE_READ(chip) && !oob)
1191 chip->pagebuf = realpage;
1192 memcpy(buf, chip->buffers->databuf + col, bytes);
1197 if (unlikely(oob)) {
1198 /* Raw mode does data:oob:data:oob */
1199 if (ops->mode != MTD_OOB_RAW) {
1200 int toread = min(oobreadlen,
1201 chip->ecc.layout->oobavail);
1203 oob = nand_transfer_oob(chip,
1205 oobreadlen -= toread;
1208 buf = nand_transfer_oob(chip,
1209 buf, ops, mtd->oobsize);
1212 if (!(chip->options & NAND_NO_READRDY)) {
1214 * Apply delay or wait for ready/busy pin. Do
1215 * this before the AUTOINCR check, so no
1216 * problems arise if a chip which does auto
1217 * increment is marked as NOAUTOINCR by the
1220 if (!chip->dev_ready)
1221 udelay(chip->chip_delay);
1223 nand_wait_ready(mtd);
1226 memcpy(buf, chip->buffers->databuf + col, bytes);
1235 /* For subsequent reads align to page boundary. */
1237 /* Increment page address */
1240 page = realpage & chip->pagemask;
1241 /* Check, if we cross a chip boundary */
1244 chip->select_chip(mtd, -1);
1245 chip->select_chip(mtd, chipnr);
1248 /* Check, if the chip supports auto page increment
1249 * or if we have hit a block boundary.
1251 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1255 ops->retlen = ops->len - (size_t) readlen;
1257 ops->oobretlen = ops->ooblen - oobreadlen;
1262 if (mtd->ecc_stats.failed - stats.failed)
1265 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1269 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1270 * @mtd: MTD device structure
1271 * @from: offset to read from
1272 * @len: number of bytes to read
1273 * @retlen: pointer to variable to store the number of read bytes
1274 * @buf: the databuffer to put data
1276 * Get hold of the chip and call nand_do_read
1278 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1279 size_t *retlen, uint8_t *buf)
1281 struct nand_chip *chip = mtd->priv;
1284 /* Do not allow reads past end of device */
1285 if ((from + len) > mtd->size)
1290 nand_get_device(chip, mtd, FL_READING);
1292 chip->ops.len = len;
1293 chip->ops.datbuf = buf;
1294 chip->ops.oobbuf = NULL;
1296 ret = nand_do_read_ops(mtd, from, &chip->ops);
1298 *retlen = chip->ops.retlen;
1300 nand_release_device(mtd);
1306 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1307 * @mtd: mtd info structure
1308 * @chip: nand chip info structure
1309 * @page: page number to read
1310 * @sndcmd: flag whether to issue read command or not
1312 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1313 int page, int sndcmd)
1316 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1319 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1324 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1326 * @mtd: mtd info structure
1327 * @chip: nand chip info structure
1328 * @page: page number to read
1329 * @sndcmd: flag whether to issue read command or not
1331 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1332 int page, int sndcmd)
1334 uint8_t *buf = chip->oob_poi;
1335 int length = mtd->oobsize;
1336 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1337 int eccsize = chip->ecc.size;
1338 uint8_t *bufpoi = buf;
1339 int i, toread, sndrnd = 0, pos;
1341 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1342 for (i = 0; i < chip->ecc.steps; i++) {
1344 pos = eccsize + i * (eccsize + chunk);
1345 if (mtd->writesize > 512)
1346 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1348 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1351 toread = min_t(int, length, chunk);
1352 chip->read_buf(mtd, bufpoi, toread);
1357 chip->read_buf(mtd, bufpoi, length);
1363 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1364 * @mtd: mtd info structure
1365 * @chip: nand chip info structure
1366 * @page: page number to write
1368 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1372 const uint8_t *buf = chip->oob_poi;
1373 int length = mtd->oobsize;
1375 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1376 chip->write_buf(mtd, buf, length);
1377 /* Send command to program the OOB data */
1378 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1380 status = chip->waitfunc(mtd, chip);
1382 return status & NAND_STATUS_FAIL ? -EIO : 0;
1386 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1387 * with syndrome - only for large page flash !
1388 * @mtd: mtd info structure
1389 * @chip: nand chip info structure
1390 * @page: page number to write
1392 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1393 struct nand_chip *chip, int page)
1395 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1396 int eccsize = chip->ecc.size, length = mtd->oobsize;
1397 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1398 const uint8_t *bufpoi = chip->oob_poi;
1401 * data-ecc-data-ecc ... ecc-oob
1403 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1405 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1406 pos = steps * (eccsize + chunk);
1411 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1412 for (i = 0; i < steps; i++) {
1414 if (mtd->writesize <= 512) {
1415 uint32_t fill = 0xFFFFFFFF;
1419 int num = min_t(int, len, 4);
1420 chip->write_buf(mtd, (uint8_t *)&fill,
1425 pos = eccsize + i * (eccsize + chunk);
1426 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1430 len = min_t(int, length, chunk);
1431 chip->write_buf(mtd, bufpoi, len);
1436 chip->write_buf(mtd, bufpoi, length);
1438 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1439 status = chip->waitfunc(mtd, chip);
1441 return status & NAND_STATUS_FAIL ? -EIO : 0;
1445 * nand_do_read_oob - [Intern] NAND read out-of-band
1446 * @mtd: MTD device structure
1447 * @from: offset to read from
1448 * @ops: oob operations description structure
1450 * NAND read out-of-band data from the spare area
1452 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1453 struct mtd_oob_ops *ops)
1455 int page, realpage, chipnr, sndcmd = 1;
1456 struct nand_chip *chip = mtd->priv;
1457 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1458 int readlen = ops->ooblen;
1460 uint8_t *buf = ops->oobbuf;
1462 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1463 __func__, (unsigned long long)from, readlen);
1465 if (ops->mode == MTD_OOB_AUTO)
1466 len = chip->ecc.layout->oobavail;
1470 if (unlikely(ops->ooboffs >= len)) {
1471 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1472 "outside oob\n", __func__);
1476 /* Do not allow reads past end of device */
1477 if (unlikely(from >= mtd->size ||
1478 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1479 (from >> chip->page_shift)) * len)) {
1480 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1481 "of device\n", __func__);
1485 chipnr = (int)(from >> chip->chip_shift);
1486 chip->select_chip(mtd, chipnr);
1488 /* Shift to get page */
1489 realpage = (int)(from >> chip->page_shift);
1490 page = realpage & chip->pagemask;
1494 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1496 len = min(len, readlen);
1497 buf = nand_transfer_oob(chip, buf, ops, len);
1499 if (!(chip->options & NAND_NO_READRDY)) {
1501 * Apply delay or wait for ready/busy pin. Do this
1502 * before the AUTOINCR check, so no problems arise if a
1503 * chip which does auto increment is marked as
1504 * NOAUTOINCR by the board driver.
1506 if (!chip->dev_ready)
1507 udelay(chip->chip_delay);
1509 nand_wait_ready(mtd);
1516 /* Increment page address */
1519 page = realpage & chip->pagemask;
1520 /* Check, if we cross a chip boundary */
1523 chip->select_chip(mtd, -1);
1524 chip->select_chip(mtd, chipnr);
1527 /* Check, if the chip supports auto page increment
1528 * or if we have hit a block boundary.
1530 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1534 ops->oobretlen = ops->ooblen;
1539 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1540 * @mtd: MTD device structure
1541 * @from: offset to read from
1542 * @ops: oob operation description structure
1544 * NAND read data and/or out-of-band data
1546 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1547 struct mtd_oob_ops *ops)
1549 struct nand_chip *chip = mtd->priv;
1550 int ret = -ENOTSUPP;
1554 /* Do not allow reads past end of device */
1555 if (ops->datbuf && (from + ops->len) > mtd->size) {
1556 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1557 "beyond end of device\n", __func__);
1561 nand_get_device(chip, mtd, FL_READING);
1563 switch (ops->mode) {
1574 ret = nand_do_read_oob(mtd, from, ops);
1576 ret = nand_do_read_ops(mtd, from, ops);
1579 nand_release_device(mtd);
1585 * nand_write_page_raw - [Intern] raw page write function
1586 * @mtd: mtd info structure
1587 * @chip: nand chip info structure
1590 * Not for syndrome calculating ecc controllers, which use a special oob layout
1592 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1595 chip->write_buf(mtd, buf, mtd->writesize);
1596 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1600 * nand_write_page_raw_syndrome - [Intern] raw page write function
1601 * @mtd: mtd info structure
1602 * @chip: nand chip info structure
1605 * We need a special oob layout and handling even when ECC isn't checked.
1607 static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1608 struct nand_chip *chip,
1611 int eccsize = chip->ecc.size;
1612 int eccbytes = chip->ecc.bytes;
1613 uint8_t *oob = chip->oob_poi;
1616 for (steps = chip->ecc.steps; steps > 0; steps--) {
1617 chip->write_buf(mtd, buf, eccsize);
1620 if (chip->ecc.prepad) {
1621 chip->write_buf(mtd, oob, chip->ecc.prepad);
1622 oob += chip->ecc.prepad;
1625 chip->read_buf(mtd, oob, eccbytes);
1628 if (chip->ecc.postpad) {
1629 chip->write_buf(mtd, oob, chip->ecc.postpad);
1630 oob += chip->ecc.postpad;
1634 size = mtd->oobsize - (oob - chip->oob_poi);
1636 chip->write_buf(mtd, oob, size);
1639 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1640 * @mtd: mtd info structure
1641 * @chip: nand chip info structure
1644 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1647 int i, eccsize = chip->ecc.size;
1648 int eccbytes = chip->ecc.bytes;
1649 int eccsteps = chip->ecc.steps;
1650 uint8_t *ecc_calc = chip->buffers->ecccalc;
1651 const uint8_t *p = buf;
1652 uint32_t *eccpos = chip->ecc.layout->eccpos;
1654 /* Software ecc calculation */
1655 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1656 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1658 for (i = 0; i < chip->ecc.total; i++)
1659 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1661 chip->ecc.write_page_raw(mtd, chip, buf);
1665 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1666 * @mtd: mtd info structure
1667 * @chip: nand chip info structure
1670 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1673 int i, eccsize = chip->ecc.size;
1674 int eccbytes = chip->ecc.bytes;
1675 int eccsteps = chip->ecc.steps;
1676 uint8_t *ecc_calc = chip->buffers->ecccalc;
1677 const uint8_t *p = buf;
1678 uint32_t *eccpos = chip->ecc.layout->eccpos;
1680 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1681 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1682 chip->write_buf(mtd, p, eccsize);
1683 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1686 for (i = 0; i < chip->ecc.total; i++)
1687 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1689 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1693 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1694 * @mtd: mtd info structure
1695 * @chip: nand chip info structure
1698 * The hw generator calculates the error syndrome automatically. Therefor
1699 * we need a special oob layout and handling.
1701 static void nand_write_page_syndrome(struct mtd_info *mtd,
1702 struct nand_chip *chip, const uint8_t *buf)
1704 int i, eccsize = chip->ecc.size;
1705 int eccbytes = chip->ecc.bytes;
1706 int eccsteps = chip->ecc.steps;
1707 const uint8_t *p = buf;
1708 uint8_t *oob = chip->oob_poi;
1710 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1712 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1713 chip->write_buf(mtd, p, eccsize);
1715 if (chip->ecc.prepad) {
1716 chip->write_buf(mtd, oob, chip->ecc.prepad);
1717 oob += chip->ecc.prepad;
1720 chip->ecc.calculate(mtd, p, oob);
1721 chip->write_buf(mtd, oob, eccbytes);
1724 if (chip->ecc.postpad) {
1725 chip->write_buf(mtd, oob, chip->ecc.postpad);
1726 oob += chip->ecc.postpad;
1730 /* Calculate remaining oob bytes */
1731 i = mtd->oobsize - (oob - chip->oob_poi);
1733 chip->write_buf(mtd, oob, i);
1737 * nand_write_page - [REPLACEABLE] write one page
1738 * @mtd: MTD device structure
1739 * @chip: NAND chip descriptor
1740 * @buf: the data to write
1741 * @page: page number to write
1742 * @cached: cached programming
1743 * @raw: use _raw version of write_page
1745 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1746 const uint8_t *buf, int page, int cached, int raw)
1750 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1753 chip->ecc.write_page_raw(mtd, chip, buf);
1755 chip->ecc.write_page(mtd, chip, buf);
1758 * Cached progamming disabled for now, Not sure if its worth the
1759 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1763 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1765 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1766 status = chip->waitfunc(mtd, chip);
1768 * See if operation failed and additional status checks are
1771 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1772 status = chip->errstat(mtd, chip, FL_WRITING, status,
1775 if (status & NAND_STATUS_FAIL)
1778 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1779 status = chip->waitfunc(mtd, chip);
1782 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1783 /* Send command to read back the data */
1784 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1786 if (chip->verify_buf(mtd, buf, mtd->writesize))
1793 * nand_fill_oob - [Internal] Transfer client buffer to oob
1794 * @chip: nand chip structure
1795 * @oob: oob data buffer
1796 * @ops: oob ops structure
1798 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1799 struct mtd_oob_ops *ops)
1801 size_t len = ops->ooblen;
1803 switch (ops->mode) {
1807 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1810 case MTD_OOB_AUTO: {
1811 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1812 uint32_t boffs = 0, woffs = ops->ooboffs;
1815 for (; free->length && len; free++, len -= bytes) {
1816 /* Write request not from offset 0 ? */
1817 if (unlikely(woffs)) {
1818 if (woffs >= free->length) {
1819 woffs -= free->length;
1822 boffs = free->offset + woffs;
1823 bytes = min_t(size_t, len,
1824 (free->length - woffs));
1827 bytes = min_t(size_t, len, free->length);
1828 boffs = free->offset;
1830 memcpy(chip->oob_poi + boffs, oob, bytes);
1841 #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
1844 * nand_do_write_ops - [Internal] NAND write with ECC
1845 * @mtd: MTD device structure
1846 * @to: offset to write to
1847 * @ops: oob operations description structure
1849 * NAND write with ECC
1851 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1852 struct mtd_oob_ops *ops)
1854 int chipnr, realpage, page, blockmask, column;
1855 struct nand_chip *chip = mtd->priv;
1856 uint32_t writelen = ops->len;
1857 uint8_t *oob = ops->oobbuf;
1858 uint8_t *buf = ops->datbuf;
1865 column = to & (mtd->writesize - 1);
1866 subpage = column || (writelen & (mtd->writesize - 1));
1871 chipnr = (int)(to >> chip->chip_shift);
1872 chip->select_chip(mtd, chipnr);
1874 /* Check, if it is write protected */
1875 if (nand_check_wp(mtd)) {
1876 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1880 realpage = (int)(to >> chip->page_shift);
1881 page = realpage & chip->pagemask;
1882 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1884 /* Invalidate the page cache, when we write to the cached page */
1885 if (to <= (chip->pagebuf << chip->page_shift) &&
1886 (chip->pagebuf << chip->page_shift) < (to + ops->len))
1889 /* If we're not given explicit OOB data, let it be 0xFF */
1891 memset(chip->oob_poi, 0xff, mtd->oobsize);
1896 int bytes = mtd->writesize;
1897 int cached = writelen > bytes && page != blockmask;
1898 uint8_t *wbuf = buf;
1900 /* Partial page write ? */
1901 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1903 bytes = min_t(int, bytes - column, (int) writelen);
1905 memset(chip->buffers->databuf, 0xff, mtd->writesize);
1906 memcpy(&chip->buffers->databuf[column], buf, bytes);
1907 wbuf = chip->buffers->databuf;
1911 oob = nand_fill_oob(chip, oob, ops);
1913 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1914 (ops->mode == MTD_OOB_RAW));
1926 page = realpage & chip->pagemask;
1927 /* Check, if we cross a chip boundary */
1930 chip->select_chip(mtd, -1);
1931 chip->select_chip(mtd, chipnr);
1935 ops->retlen = ops->len - writelen;
1937 ops->oobretlen = ops->ooblen;
1942 * nand_write - [MTD Interface] NAND write with ECC
1943 * @mtd: MTD device structure
1944 * @to: offset to write to
1945 * @len: number of bytes to write
1946 * @retlen: pointer to variable to store the number of written bytes
1947 * @buf: the data to write
1949 * NAND write with ECC
1951 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1952 size_t *retlen, const uint8_t *buf)
1954 struct nand_chip *chip = mtd->priv;
1957 /* Do not allow writes past end of device */
1958 if ((to + len) > mtd->size)
1963 nand_get_device(chip, mtd, FL_WRITING);
1965 chip->ops.len = len;
1966 chip->ops.datbuf = (uint8_t *)buf;
1967 chip->ops.oobbuf = NULL;
1969 ret = nand_do_write_ops(mtd, to, &chip->ops);
1971 *retlen = chip->ops.retlen;
1973 nand_release_device(mtd);
1979 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1980 * @mtd: MTD device structure
1981 * @to: offset to write to
1982 * @ops: oob operation description structure
1984 * NAND write out-of-band
1986 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1987 struct mtd_oob_ops *ops)
1989 int chipnr, page, status, len;
1990 struct nand_chip *chip = mtd->priv;
1992 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
1993 __func__, (unsigned int)to, (int)ops->ooblen);
1995 if (ops->mode == MTD_OOB_AUTO)
1996 len = chip->ecc.layout->oobavail;
2000 /* Do not allow write past end of page */
2001 if ((ops->ooboffs + ops->ooblen) > len) {
2002 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2003 "past end of page\n", __func__);
2007 if (unlikely(ops->ooboffs >= len)) {
2008 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2009 "write outside oob\n", __func__);
2013 /* Do not allow write past end of device */
2014 if (unlikely(to >= mtd->size ||
2015 ops->ooboffs + ops->ooblen >
2016 ((mtd->size >> chip->page_shift) -
2017 (to >> chip->page_shift)) * len)) {
2018 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2019 "end of device\n", __func__);
2023 chipnr = (int)(to >> chip->chip_shift);
2024 chip->select_chip(mtd, chipnr);
2026 /* Shift to get page */
2027 page = (int)(to >> chip->page_shift);
2030 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2031 * of my DiskOnChip 2000 test units) will clear the whole data page too
2032 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2033 * it in the doc2000 driver in August 1999. dwmw2.
2035 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2037 /* Check, if it is write protected */
2038 if (nand_check_wp(mtd))
2041 /* Invalidate the page cache, if we write to the cached page */
2042 if (page == chip->pagebuf)
2045 memset(chip->oob_poi, 0xff, mtd->oobsize);
2046 nand_fill_oob(chip, ops->oobbuf, ops);
2047 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2048 memset(chip->oob_poi, 0xff, mtd->oobsize);
2053 ops->oobretlen = ops->ooblen;
2059 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2060 * @mtd: MTD device structure
2061 * @to: offset to write to
2062 * @ops: oob operation description structure
2064 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2065 struct mtd_oob_ops *ops)
2067 struct nand_chip *chip = mtd->priv;
2068 int ret = -ENOTSUPP;
2072 /* Do not allow writes past end of device */
2073 if (ops->datbuf && (to + ops->len) > mtd->size) {
2074 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2075 "end of device\n", __func__);
2079 nand_get_device(chip, mtd, FL_WRITING);
2081 switch (ops->mode) {
2092 ret = nand_do_write_oob(mtd, to, ops);
2094 ret = nand_do_write_ops(mtd, to, ops);
2097 nand_release_device(mtd);
2102 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2103 * @mtd: MTD device structure
2104 * @page: the page address of the block which will be erased
2106 * Standard erase command for NAND chips
2108 static void single_erase_cmd(struct mtd_info *mtd, int page)
2110 struct nand_chip *chip = mtd->priv;
2111 /* Send commands to erase a block */
2112 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2113 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2117 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2118 * @mtd: MTD device structure
2119 * @page: the page address of the block which will be erased
2121 * AND multi block erase command function
2122 * Erase 4 consecutive blocks
2124 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2126 struct nand_chip *chip = mtd->priv;
2127 /* Send commands to erase a block */
2128 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2129 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2130 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2131 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2132 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2136 * nand_erase - [MTD Interface] erase block(s)
2137 * @mtd: MTD device structure
2138 * @instr: erase instruction
2140 * Erase one ore more blocks
2142 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2144 return nand_erase_nand(mtd, instr, 0);
2147 #define BBT_PAGE_MASK 0xffffff3f
2149 * nand_erase_nand - [Internal] erase block(s)
2150 * @mtd: MTD device structure
2151 * @instr: erase instruction
2152 * @allowbbt: allow erasing the bbt area
2154 * Erase one ore more blocks
2156 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2159 int page, status, pages_per_block, ret, chipnr;
2160 struct nand_chip *chip = mtd->priv;
2161 loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0};
2162 unsigned int bbt_masked_page = 0xffffffff;
2165 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2166 __func__, (unsigned long long)instr->addr,
2167 (unsigned long long)instr->len);
2169 /* Start address must align on block boundary */
2170 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2171 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2175 /* Length must align on block boundary */
2176 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2177 MTDDEBUG (MTD_DEBUG_LEVEL0,
2178 "nand_erase: Length not block aligned\n");
2182 /* Do not allow erase past end of device */
2183 if ((instr->len + instr->addr) > mtd->size) {
2184 MTDDEBUG (MTD_DEBUG_LEVEL0,
2185 "nand_erase: Erase past end of device\n");
2189 instr->fail_addr = 0xffffffff;
2191 /* Grab the lock and see if the device is available */
2192 nand_get_device(chip, mtd, FL_ERASING);
2194 /* Shift to get first page */
2195 page = (int)(instr->addr >> chip->page_shift);
2196 chipnr = (int)(instr->addr >> chip->chip_shift);
2198 /* Calculate pages in each block */
2199 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2201 /* Select the NAND device */
2202 chip->select_chip(mtd, chipnr);
2204 /* Check, if it is write protected */
2205 if (nand_check_wp(mtd)) {
2206 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2208 instr->state = MTD_ERASE_FAILED;
2213 * If BBT requires refresh, set the BBT page mask to see if the BBT
2214 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2215 * can not be matched. This is also done when the bbt is actually
2216 * erased to avoid recusrsive updates
2218 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2219 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2221 /* Loop through the pages */
2224 instr->state = MTD_ERASING;
2229 * heck if we have a bad block, we do not erase bad blocks !
2231 if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
2232 chip->page_shift, 0, allowbbt)) {
2233 printk(KERN_WARNING "%s: attempt to erase a bad block "
2234 "at page 0x%08x\n", __func__, page);
2235 instr->state = MTD_ERASE_FAILED;
2240 * Invalidate the page cache, if we erase the block which
2241 * contains the current cached page
2243 if (page <= chip->pagebuf && chip->pagebuf <
2244 (page + pages_per_block))
2247 chip->erase_cmd(mtd, page & chip->pagemask);
2249 status = chip->waitfunc(mtd, chip);
2252 * See if operation failed and additional status checks are
2255 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2256 status = chip->errstat(mtd, chip, FL_ERASING,
2259 /* See if block erase succeeded */
2260 if (status & NAND_STATUS_FAIL) {
2261 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2262 "page 0x%08x\n", __func__, page);
2263 instr->state = MTD_ERASE_FAILED;
2265 ((loff_t)page << chip->page_shift);
2270 * If BBT requires refresh, set the BBT rewrite flag to the
2273 if (bbt_masked_page != 0xffffffff &&
2274 (page & BBT_PAGE_MASK) == bbt_masked_page)
2275 rewrite_bbt[chipnr] =
2276 ((loff_t)page << chip->page_shift);
2278 /* Increment page address and decrement length */
2279 len -= (1 << chip->phys_erase_shift);
2280 page += pages_per_block;
2282 /* Check, if we cross a chip boundary */
2283 if (len && !(page & chip->pagemask)) {
2285 chip->select_chip(mtd, -1);
2286 chip->select_chip(mtd, chipnr);
2289 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2290 * page mask to see if this BBT should be rewritten
2292 if (bbt_masked_page != 0xffffffff &&
2293 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2294 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2298 instr->state = MTD_ERASE_DONE;
2302 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2304 /* Deselect and wake up anyone waiting on the device */
2305 nand_release_device(mtd);
2307 /* Do call back function */
2309 mtd_erase_callback(instr);
2312 * If BBT requires refresh and erase was successful, rewrite any
2313 * selected bad block tables
2315 if (bbt_masked_page == 0xffffffff || ret)
2318 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2319 if (!rewrite_bbt[chipnr])
2321 /* update the BBT for chip */
2322 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2323 "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2324 rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
2325 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2328 /* Return more or less happy */
2333 * nand_sync - [MTD Interface] sync
2334 * @mtd: MTD device structure
2336 * Sync is actually a wait for chip ready function
2338 static void nand_sync(struct mtd_info *mtd)
2340 struct nand_chip *chip = mtd->priv;
2342 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
2344 /* Grab the lock and see if the device is available */
2345 nand_get_device(chip, mtd, FL_SYNCING);
2346 /* Release it and go back */
2347 nand_release_device(mtd);
2351 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2352 * @mtd: MTD device structure
2353 * @offs: offset relative to mtd start
2355 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2357 /* Check for invalid offset */
2358 if (offs > mtd->size)
2361 return nand_block_checkbad(mtd, offs, 1, 0);
2365 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2366 * @mtd: MTD device structure
2367 * @ofs: offset relative to mtd start
2369 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2371 struct nand_chip *chip = mtd->priv;
2374 if ((ret = nand_block_isbad(mtd, ofs))) {
2375 /* If it was bad already, return success and do nothing. */
2381 return chip->block_markbad(mtd, ofs);
2385 * Set default functions
2387 static void nand_set_defaults(struct nand_chip *chip, int busw)
2389 /* check for proper chip_delay setup, set 20us if not */
2390 if (!chip->chip_delay)
2391 chip->chip_delay = 20;
2393 /* check, if a user supplied command function given */
2394 if (chip->cmdfunc == NULL)
2395 chip->cmdfunc = nand_command;
2397 /* check, if a user supplied wait function given */
2398 if (chip->waitfunc == NULL)
2399 chip->waitfunc = nand_wait;
2401 if (!chip->select_chip)
2402 chip->select_chip = nand_select_chip;
2403 if (!chip->read_byte)
2404 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2405 if (!chip->read_word)
2406 chip->read_word = nand_read_word;
2407 if (!chip->block_bad)
2408 chip->block_bad = nand_block_bad;
2409 if (!chip->block_markbad)
2410 chip->block_markbad = nand_default_block_markbad;
2411 if (!chip->write_buf)
2412 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2413 if (!chip->read_buf)
2414 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2415 if (!chip->verify_buf)
2416 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2417 if (!chip->scan_bbt)
2418 chip->scan_bbt = nand_default_bbt;
2419 if (!chip->controller)
2420 chip->controller = &chip->hwcontrol;
2423 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2424 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2430 for (i = 0; i < 8; i++)
2431 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2438 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise
2440 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2443 struct nand_onfi_params *p = &chip->onfi_params;
2447 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2448 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2449 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2452 printk(KERN_INFO "ONFI flash detected\n");
2453 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2454 for (i = 0; i < 3; i++) {
2455 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2456 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2457 le16_to_cpu(p->crc)) {
2458 printk(KERN_INFO "ONFI param page %d valid\n", i);
2467 val = le16_to_cpu(p->revision);
2469 chip->onfi_version = 23;
2470 else if (val & (1 << 4))
2471 chip->onfi_version = 22;
2472 else if (val & (1 << 3))
2473 chip->onfi_version = 21;
2474 else if (val & (1 << 2))
2475 chip->onfi_version = 20;
2476 else if (val & (1 << 1))
2477 chip->onfi_version = 10;
2479 chip->onfi_version = 0;
2481 if (!chip->onfi_version) {
2482 printk(KERN_INFO "%s: unsupported ONFI version: %d\n",
2488 mtd->name = p->model;
2490 mtd->writesize = le32_to_cpu(p->byte_per_page);
2491 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2492 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2493 chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
2495 if (le16_to_cpu(p->features) & 1)
2496 *busw = NAND_BUSWIDTH_16;
2501 static inline int nand_flash_detect_onfi(struct mtd_info *mtd,
2502 struct nand_chip *chip,
2509 static void nand_flash_detect_non_onfi(struct mtd_info *mtd,
2510 struct nand_chip *chip,
2511 const struct nand_flash_dev *type,
2514 /* Newer devices have all the information in additional id bytes */
2515 if (!type->pagesize) {
2517 /* The 3rd id byte holds MLC / multichip data */
2518 chip->cellinfo = chip->read_byte(mtd);
2519 /* The 4th id byte is the important one */
2520 extid = chip->read_byte(mtd);
2522 mtd->writesize = 1024 << (extid & 0x3);
2525 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2527 /* Calc blocksize. Blocksize is multiples of 64KiB */
2528 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2530 /* Get buswidth information */
2531 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2535 * Old devices have chip data hardcoded in the device id table
2537 mtd->erasesize = type->erasesize;
2538 mtd->writesize = type->pagesize;
2539 mtd->oobsize = mtd->writesize / 32;
2540 *busw = type->options & NAND_BUSWIDTH_16;
2545 * Get the flash and manufacturer id and lookup if the type is supported
2547 static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2548 struct nand_chip *chip,
2550 int *maf_id, int *dev_id,
2551 const struct nand_flash_dev *type)
2554 int tmp_id, tmp_manf;
2556 /* Select the device */
2557 chip->select_chip(mtd, 0);
2560 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2563 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2565 /* Send the command for reading device ID */
2566 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2568 /* Read manufacturer and device IDs */
2569 *maf_id = chip->read_byte(mtd);
2570 *dev_id = chip->read_byte(mtd);
2572 /* Try again to make sure, as some systems the bus-hold or other
2573 * interface concerns can cause random data which looks like a
2574 * possibly credible NAND flash to appear. If the two results do
2575 * not match, ignore the device completely.
2578 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2580 /* Read manufacturer and device IDs */
2582 tmp_manf = chip->read_byte(mtd);
2583 tmp_id = chip->read_byte(mtd);
2585 if (tmp_manf != *maf_id || tmp_id != *dev_id) {
2586 printk(KERN_INFO "%s: second ID read did not match "
2587 "%02x,%02x against %02x,%02x\n", __func__,
2588 *maf_id, *dev_id, tmp_manf, tmp_id);
2589 return ERR_PTR(-ENODEV);
2593 type = nand_flash_ids;
2595 for (; type->name != NULL; type++)
2596 if (*dev_id == type->id)
2600 /* supress warning if there is no nand */
2601 if (*maf_id != 0x00 && *maf_id != 0xff &&
2602 *dev_id != 0x00 && *dev_id != 0xff)
2603 printk(KERN_INFO "%s: unknown NAND device: "
2604 "Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
2605 __func__, *maf_id, *dev_id);
2606 return ERR_PTR(-ENODEV);
2610 mtd->name = type->name;
2612 chip->chipsize = (uint64_t)type->chipsize << 20;
2613 chip->onfi_version = 0;
2615 ret = nand_flash_detect_onfi(mtd, chip, &busw);
2617 nand_flash_detect_non_onfi(mtd, chip, type, &busw);
2619 /* Get chip options, preserve non chip based options */
2620 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2621 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2624 * Set chip as a default. Board drivers can override it, if necessary
2626 chip->options |= NAND_NO_AUTOINCR;
2628 /* Try to identify manufacturer */
2629 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2630 if (nand_manuf_ids[maf_idx].id == *maf_id)
2635 * Check, if buswidth is correct. Hardware drivers should set
2638 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2639 printk(KERN_INFO "NAND device: Manufacturer ID:"
2640 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2641 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2642 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2643 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2645 return ERR_PTR(-EINVAL);
2648 /* Calculate the address shift from the page size */
2649 chip->page_shift = ffs(mtd->writesize) - 1;
2650 /* Convert chipsize to number of pages per chip -1. */
2651 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2653 chip->bbt_erase_shift = chip->phys_erase_shift =
2654 ffs(mtd->erasesize) - 1;
2655 if (chip->chipsize & 0xffffffff)
2656 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2658 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 31;
2660 /* Set the bad block position */
2661 chip->badblockpos = mtd->writesize > 512 ?
2662 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2664 /* Check if chip is a not a samsung device. Do not clear the
2665 * options for chips which are not having an extended id.
2667 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2668 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2670 /* Check for AND chips with 4 page planes */
2671 if (chip->options & NAND_4PAGE_ARRAY)
2672 chip->erase_cmd = multi_erase_cmd;
2674 chip->erase_cmd = single_erase_cmd;
2676 /* Do not replace user supplied command function ! */
2677 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2678 chip->cmdfunc = nand_command_lp;
2680 MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2681 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
2682 nand_manuf_ids[maf_idx].name, type->name);
2688 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2689 * @mtd: MTD device structure
2690 * @maxchips: Number of chips to scan for
2691 * @table: Alternative NAND ID table
2693 * This is the first phase of the normal nand_scan() function. It
2694 * reads the flash ID and sets up MTD fields accordingly.
2696 * The mtd->owner field must be set to the module of the caller.
2698 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
2699 const struct nand_flash_dev *table)
2701 int i, busw, nand_maf_id, nand_dev_id;
2702 struct nand_chip *chip = mtd->priv;
2703 const struct nand_flash_dev *type;
2705 /* Get buswidth to select the correct functions */
2706 busw = chip->options & NAND_BUSWIDTH_16;
2707 /* Set the default functions */
2708 nand_set_defaults(chip, busw);
2710 /* Read the flash type */
2711 type = nand_get_flash_type(mtd, chip, busw,
2712 &nand_maf_id, &nand_dev_id, table);
2715 #ifndef CONFIG_SYS_NAND_QUIET_TEST
2716 printk(KERN_WARNING "No NAND device found!!!\n");
2718 chip->select_chip(mtd, -1);
2719 return PTR_ERR(type);
2722 /* Check for a chip array */
2723 for (i = 1; i < maxchips; i++) {
2724 chip->select_chip(mtd, i);
2725 /* See comment in nand_get_flash_type for reset */
2726 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2727 /* Send the command for reading device ID */
2728 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2729 /* Read manufacturer and device IDs */
2730 if (nand_maf_id != chip->read_byte(mtd) ||
2731 nand_dev_id != chip->read_byte(mtd))
2736 printk(KERN_INFO "%d NAND chips detected\n", i);
2739 /* Store the number of chips and calc total size for mtd */
2741 mtd->size = i * chip->chipsize;
2748 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2749 * @mtd: MTD device structure
2751 * This is the second phase of the normal nand_scan() function. It
2752 * fills out all the uninitialized function pointers with the defaults
2753 * and scans for a bad block table if appropriate.
2755 int nand_scan_tail(struct mtd_info *mtd)
2758 struct nand_chip *chip = mtd->priv;
2760 if (!(chip->options & NAND_OWN_BUFFERS))
2761 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2765 /* Set the internal oob buffer location, just after the page data */
2766 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2769 * If no default placement scheme is given, select an appropriate one
2771 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
2772 switch (mtd->oobsize) {
2774 chip->ecc.layout = &nand_oob_8;
2777 chip->ecc.layout = &nand_oob_16;
2780 chip->ecc.layout = &nand_oob_64;
2783 chip->ecc.layout = &nand_oob_128;
2786 printk(KERN_WARNING "No oob scheme defined for "
2787 "oobsize %d\n", mtd->oobsize);
2791 if (!chip->write_page)
2792 chip->write_page = nand_write_page;
2795 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2796 * selected and we have 256 byte pagesize fallback to software ECC
2799 switch (chip->ecc.mode) {
2800 case NAND_ECC_HW_OOB_FIRST:
2801 /* Similar to NAND_ECC_HW, but a separate read_page handle */
2802 if (!chip->ecc.calculate || !chip->ecc.correct ||
2804 printk(KERN_WARNING "No ECC functions supplied; "
2805 "Hardware ECC not possible\n");
2808 if (!chip->ecc.read_page)
2809 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
2812 /* Use standard hwecc read page function ? */
2813 if (!chip->ecc.read_page)
2814 chip->ecc.read_page = nand_read_page_hwecc;
2815 if (!chip->ecc.write_page)
2816 chip->ecc.write_page = nand_write_page_hwecc;
2817 if (!chip->ecc.read_page_raw)
2818 chip->ecc.read_page_raw = nand_read_page_raw;
2819 if (!chip->ecc.write_page_raw)
2820 chip->ecc.write_page_raw = nand_write_page_raw;
2821 if (!chip->ecc.read_oob)
2822 chip->ecc.read_oob = nand_read_oob_std;
2823 if (!chip->ecc.write_oob)
2824 chip->ecc.write_oob = nand_write_oob_std;
2826 case NAND_ECC_HW_SYNDROME:
2827 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2828 !chip->ecc.hwctl) &&
2829 (!chip->ecc.read_page ||
2830 chip->ecc.read_page == nand_read_page_hwecc ||
2831 !chip->ecc.write_page ||
2832 chip->ecc.write_page == nand_write_page_hwecc)) {
2833 printk(KERN_WARNING "No ECC functions supplied; "
2834 "Hardware ECC not possible\n");
2837 /* Use standard syndrome read/write page function ? */
2838 if (!chip->ecc.read_page)
2839 chip->ecc.read_page = nand_read_page_syndrome;
2840 if (!chip->ecc.write_page)
2841 chip->ecc.write_page = nand_write_page_syndrome;
2842 if (!chip->ecc.read_page_raw)
2843 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
2844 if (!chip->ecc.write_page_raw)
2845 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
2846 if (!chip->ecc.read_oob)
2847 chip->ecc.read_oob = nand_read_oob_syndrome;
2848 if (!chip->ecc.write_oob)
2849 chip->ecc.write_oob = nand_write_oob_syndrome;
2851 if (mtd->writesize >= chip->ecc.size)
2853 printk(KERN_WARNING "%d byte HW ECC not possible on "
2854 "%d byte page size, fallback to SW ECC\n",
2855 chip->ecc.size, mtd->writesize);
2856 chip->ecc.mode = NAND_ECC_SOFT;
2859 chip->ecc.calculate = nand_calculate_ecc;
2860 chip->ecc.correct = nand_correct_data;
2861 chip->ecc.read_page = nand_read_page_swecc;
2862 chip->ecc.read_subpage = nand_read_subpage;
2863 chip->ecc.write_page = nand_write_page_swecc;
2864 chip->ecc.read_page_raw = nand_read_page_raw;
2865 chip->ecc.write_page_raw = nand_write_page_raw;
2866 chip->ecc.read_oob = nand_read_oob_std;
2867 chip->ecc.write_oob = nand_write_oob_std;
2868 chip->ecc.size = 256;
2869 chip->ecc.bytes = 3;
2872 case NAND_ECC_SOFT_BCH:
2873 if (!mtd_nand_has_bch()) {
2874 printk(KERN_WARNING "CONFIG_MTD_ECC_BCH not enabled\n");
2877 chip->ecc.calculate = nand_bch_calculate_ecc;
2878 chip->ecc.correct = nand_bch_correct_data;
2879 chip->ecc.read_page = nand_read_page_swecc;
2880 chip->ecc.read_subpage = nand_read_subpage;
2881 chip->ecc.write_page = nand_write_page_swecc;
2882 chip->ecc.read_page_raw = nand_read_page_raw;
2883 chip->ecc.write_page_raw = nand_write_page_raw;
2884 chip->ecc.read_oob = nand_read_oob_std;
2885 chip->ecc.write_oob = nand_write_oob_std;
2887 * Board driver should supply ecc.size and ecc.bytes values to
2888 * select how many bits are correctable; see nand_bch_init()
2890 * Otherwise, default to 4 bits for large page devices
2892 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
2893 chip->ecc.size = 512;
2894 chip->ecc.bytes = 7;
2896 chip->ecc.priv = nand_bch_init(mtd,
2900 if (!chip->ecc.priv)
2901 printk(KERN_WARNING "BCH ECC initialization failed!\n");
2906 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2907 "This is not recommended !!\n");
2908 chip->ecc.read_page = nand_read_page_raw;
2909 chip->ecc.write_page = nand_write_page_raw;
2910 chip->ecc.read_oob = nand_read_oob_std;
2911 chip->ecc.read_page_raw = nand_read_page_raw;
2912 chip->ecc.write_page_raw = nand_write_page_raw;
2913 chip->ecc.write_oob = nand_write_oob_std;
2914 chip->ecc.size = mtd->writesize;
2915 chip->ecc.bytes = 0;
2919 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2925 * The number of bytes available for a client to place data into
2926 * the out of band area
2928 chip->ecc.layout->oobavail = 0;
2929 for (i = 0; chip->ecc.layout->oobfree[i].length
2930 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
2931 chip->ecc.layout->oobavail +=
2932 chip->ecc.layout->oobfree[i].length;
2933 mtd->oobavail = chip->ecc.layout->oobavail;
2936 * Set the number of read / write steps for one page depending on ECC
2939 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2940 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2941 printk(KERN_WARNING "Invalid ecc parameters\n");
2944 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2947 * Allow subpage writes up to ecc.steps. Not possible for MLC
2950 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2951 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2952 switch (chip->ecc.steps) {
2954 mtd->subpage_sft = 1;
2959 mtd->subpage_sft = 2;
2963 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2965 /* Initialize state */
2966 chip->state = FL_READY;
2968 /* De-select the device */
2969 chip->select_chip(mtd, -1);
2971 /* Invalidate the pagebuffer reference */
2974 /* Fill in remaining MTD driver data */
2975 mtd->type = MTD_NANDFLASH;
2976 mtd->flags = MTD_CAP_NANDFLASH;
2977 mtd->erase = nand_erase;
2979 mtd->unpoint = NULL;
2980 mtd->read = nand_read;
2981 mtd->write = nand_write;
2982 mtd->read_oob = nand_read_oob;
2983 mtd->write_oob = nand_write_oob;
2984 mtd->sync = nand_sync;
2987 mtd->block_isbad = nand_block_isbad;
2988 mtd->block_markbad = nand_block_markbad;
2990 /* propagate ecc.layout to mtd_info */
2991 mtd->ecclayout = chip->ecc.layout;
2993 /* Check, if we should skip the bad block table scan */
2994 if (chip->options & NAND_SKIP_BBTSCAN)
2995 chip->options |= NAND_BBT_SCANNED;
3001 * nand_scan - [NAND Interface] Scan for the NAND device
3002 * @mtd: MTD device structure
3003 * @maxchips: Number of chips to scan for
3005 * This fills out all the uninitialized function pointers
3006 * with the defaults.
3007 * The flash ID is read and the mtd/chip structures are
3008 * filled with the appropriate values.
3009 * The mtd->owner field must be set to the module of the caller
3012 int nand_scan(struct mtd_info *mtd, int maxchips)
3016 ret = nand_scan_ident(mtd, maxchips, NULL);
3018 ret = nand_scan_tail(mtd);
3023 * nand_release - [NAND Interface] Free resources held by the NAND device
3024 * @mtd: MTD device structure
3026 void nand_release(struct mtd_info *mtd)
3028 struct nand_chip *chip = mtd->priv;
3030 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3031 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3033 #ifdef CONFIG_MTD_PARTITIONS
3034 /* Deregister partitions */
3035 del_mtd_partitions(mtd);
3038 /* Free bad block table memory */
3040 if (!(chip->options & NAND_OWN_BUFFERS))
3041 kfree(chip->buffers);