5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
8 * Additional technical information is available on
9 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
12 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
15 * David Woodhouse for adding multichip support
17 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
18 * rework for 2K page size chips
21 * Enable cached programming for 2k page size chips
22 * Check, if mtd->ecctype should be set to MTD_ECC_HW
23 * if we have HW ECC support.
24 * BBT table is not serialized, has to be fixed
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License version 2 as
28 * published by the Free Software Foundation.
34 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36 #include <linux/module.h>
37 #include <linux/delay.h>
38 #include <linux/errno.h>
39 #include <linux/err.h>
40 #include <linux/sched.h>
41 #include <linux/slab.h>
42 #include <linux/types.h>
43 #include <linux/mtd/mtd.h>
44 #include <linux/mtd/nand.h>
45 #include <linux/mtd/nand_ecc.h>
46 #include <linux/mtd/nand_bch.h>
47 #include <linux/interrupt.h>
48 #include <linux/bitops.h>
49 #include <linux/leds.h>
51 #include <linux/mtd/partitions.h>
53 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
57 #include <linux/err.h>
58 #include <linux/compat.h>
59 #include <linux/mtd/mtd.h>
60 #include <linux/mtd/nand.h>
61 #include <linux/mtd/nand_ecc.h>
62 #include <linux/mtd/nand_bch.h>
63 #ifdef CONFIG_MTD_PARTITIONS
64 #include <linux/mtd/partitions.h>
67 #include <asm/errno.h>
70 * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
71 * a flash. NAND flash is initialized prior to interrupts so standard timers
72 * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
73 * which is greater than (max NAND reset time / NAND status read time).
74 * A conservative default of 200000 (500 us / 25 ns) is used as a default.
76 #ifndef CONFIG_SYS_NAND_RESET_CNT
77 #define CONFIG_SYS_NAND_RESET_CNT 200000
80 static bool is_module_text_address(unsigned long addr) {return 0;}
83 /* Define default oob placement schemes for large and small page devices */
84 static struct nand_ecclayout nand_oob_8 = {
94 static struct nand_ecclayout nand_oob_16 = {
96 .eccpos = {0, 1, 2, 3, 6, 7},
102 static struct nand_ecclayout nand_oob_64 = {
105 40, 41, 42, 43, 44, 45, 46, 47,
106 48, 49, 50, 51, 52, 53, 54, 55,
107 56, 57, 58, 59, 60, 61, 62, 63},
113 static struct nand_ecclayout nand_oob_128 = {
116 80, 81, 82, 83, 84, 85, 86, 87,
117 88, 89, 90, 91, 92, 93, 94, 95,
118 96, 97, 98, 99, 100, 101, 102, 103,
119 104, 105, 106, 107, 108, 109, 110, 111,
120 112, 113, 114, 115, 116, 117, 118, 119,
121 120, 121, 122, 123, 124, 125, 126, 127},
127 static int nand_get_device(struct mtd_info *mtd, int new_state);
129 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
130 struct mtd_oob_ops *ops);
133 * For devices which display every fart in the system on a separate LED. Is
134 * compiled away when LED support is disabled.
136 DEFINE_LED_TRIGGER(nand_led_trigger);
138 static int check_offs_len(struct mtd_info *mtd,
139 loff_t ofs, uint64_t len)
141 struct nand_chip *chip = mtd->priv;
144 /* Start address must align on block boundary */
145 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
146 pr_debug("%s: unaligned address\n", __func__);
150 /* Length must align on block boundary */
151 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
152 pr_debug("%s: length not block aligned\n", __func__);
160 * nand_release_device - [GENERIC] release chip
161 * @mtd: MTD device structure
163 * Release chip lock and wake up anyone waiting on the device.
165 static void nand_release_device(struct mtd_info *mtd)
167 struct nand_chip *chip = mtd->priv;
170 /* Release the controller and the chip */
171 spin_lock(&chip->controller->lock);
172 chip->controller->active = NULL;
173 chip->state = FL_READY;
174 wake_up(&chip->controller->wq);
175 spin_unlock(&chip->controller->lock);
177 /* De-select the NAND device */
178 chip->select_chip(mtd, -1);
183 * nand_read_byte - [DEFAULT] read one byte from the chip
184 * @mtd: MTD device structure
186 * Default read function for 8bit buswidth
189 static uint8_t nand_read_byte(struct mtd_info *mtd)
191 uint8_t nand_read_byte(struct mtd_info *mtd)
194 struct nand_chip *chip = mtd->priv;
195 return readb(chip->IO_ADDR_R);
199 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
200 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
201 * @mtd: MTD device structure
203 * Default read function for 16bit buswidth with endianness conversion.
206 static uint8_t nand_read_byte16(struct mtd_info *mtd)
208 struct nand_chip *chip = mtd->priv;
209 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
213 * nand_read_word - [DEFAULT] read one word from the chip
214 * @mtd: MTD device structure
216 * Default read function for 16bit buswidth without endianness conversion.
218 static u16 nand_read_word(struct mtd_info *mtd)
220 struct nand_chip *chip = mtd->priv;
221 return readw(chip->IO_ADDR_R);
225 * nand_select_chip - [DEFAULT] control CE line
226 * @mtd: MTD device structure
227 * @chipnr: chipnumber to select, -1 for deselect
229 * Default select function for 1 chip devices.
231 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
233 struct nand_chip *chip = mtd->priv;
237 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
248 * nand_write_byte - [DEFAULT] write single byte to chip
249 * @mtd: MTD device structure
250 * @byte: value to write
252 * Default function to write a byte to I/O[7:0]
254 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
256 struct nand_chip *chip = mtd->priv;
258 chip->write_buf(mtd, &byte, 1);
262 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
263 * @mtd: MTD device structure
264 * @byte: value to write
266 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
268 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
270 struct nand_chip *chip = mtd->priv;
271 uint16_t word = byte;
274 * It's not entirely clear what should happen to I/O[15:8] when writing
275 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
277 * When the host supports a 16-bit bus width, only data is
278 * transferred at the 16-bit width. All address and command line
279 * transfers shall use only the lower 8-bits of the data bus. During
280 * command transfers, the host may place any value on the upper
281 * 8-bits of the data bus. During address transfers, the host shall
282 * set the upper 8-bits of the data bus to 00h.
284 * One user of the write_byte callback is nand_onfi_set_features. The
285 * four parameters are specified to be written to I/O[7:0], but this is
286 * neither an address nor a command transfer. Let's assume a 0 on the
287 * upper I/O lines is OK.
289 chip->write_buf(mtd, (uint8_t *)&word, 2);
292 #if defined(__UBOOT__) && !defined(CONFIG_BLACKFIN)
293 static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
297 for (i = 0; i < len; i++)
298 writeb(buf[i], addr);
300 static void ioread8_rep(void *addr, uint8_t *buf, int len)
304 for (i = 0; i < len; i++)
305 buf[i] = readb(addr);
308 static void ioread16_rep(void *addr, void *buf, int len)
311 u16 *p = (u16 *) buf;
314 for (i = 0; i < len; i++)
318 static void iowrite16_rep(void *addr, void *buf, int len)
321 u16 *p = (u16 *) buf;
324 for (i = 0; i < len; i++)
330 * nand_write_buf - [DEFAULT] write buffer to chip
331 * @mtd: MTD device structure
333 * @len: number of bytes to write
335 * Default write function for 8bit buswidth.
338 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
340 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
343 struct nand_chip *chip = mtd->priv;
345 iowrite8_rep(chip->IO_ADDR_W, buf, len);
349 * nand_read_buf - [DEFAULT] read chip data into buffer
350 * @mtd: MTD device structure
351 * @buf: buffer to store date
352 * @len: number of bytes to read
354 * Default read function for 8bit buswidth.
357 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
359 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
362 struct nand_chip *chip = mtd->priv;
364 ioread8_rep(chip->IO_ADDR_R, buf, len);
368 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
370 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
371 * @mtd: MTD device structure
372 * @buf: buffer containing the data to compare
373 * @len: number of bytes to compare
375 * Default verify function for 8bit buswidth.
377 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
380 struct nand_chip *chip = mtd->priv;
382 for (i = 0; i < len; i++)
383 if (buf[i] != readb(chip->IO_ADDR_R))
389 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
390 * @mtd: MTD device structure
391 * @buf: buffer containing the data to compare
392 * @len: number of bytes to compare
394 * Default verify function for 16bit buswidth.
396 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
399 struct nand_chip *chip = mtd->priv;
400 u16 *p = (u16 *) buf;
403 for (i = 0; i < len; i++)
404 if (p[i] != readw(chip->IO_ADDR_R))
413 * nand_write_buf16 - [DEFAULT] write buffer to chip
414 * @mtd: MTD device structure
416 * @len: number of bytes to write
418 * Default write function for 16bit buswidth.
421 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
423 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
426 struct nand_chip *chip = mtd->priv;
427 u16 *p = (u16 *) buf;
429 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
433 * nand_read_buf16 - [DEFAULT] read chip data into buffer
434 * @mtd: MTD device structure
435 * @buf: buffer to store date
436 * @len: number of bytes to read
438 * Default read function for 16bit buswidth.
441 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
443 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
446 struct nand_chip *chip = mtd->priv;
447 u16 *p = (u16 *) buf;
449 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
453 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
454 * @mtd: MTD device structure
455 * @ofs: offset from device start
456 * @getchip: 0, if the chip is already selected
458 * Check, if the block is bad.
460 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
462 int page, chipnr, res = 0, i = 0;
463 struct nand_chip *chip = mtd->priv;
466 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
467 ofs += mtd->erasesize - mtd->writesize;
469 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
472 chipnr = (int)(ofs >> chip->chip_shift);
474 nand_get_device(mtd, FL_READING);
476 /* Select the NAND device */
477 chip->select_chip(mtd, chipnr);
481 if (chip->options & NAND_BUSWIDTH_16) {
482 chip->cmdfunc(mtd, NAND_CMD_READOOB,
483 chip->badblockpos & 0xFE, page);
484 bad = cpu_to_le16(chip->read_word(mtd));
485 if (chip->badblockpos & 0x1)
490 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
492 bad = chip->read_byte(mtd);
495 if (likely(chip->badblockbits == 8))
498 res = hweight8(bad) < chip->badblockbits;
499 ofs += mtd->writesize;
500 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
502 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
505 chip->select_chip(mtd, -1);
506 nand_release_device(mtd);
513 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
514 * @mtd: MTD device structure
515 * @ofs: offset from device start
517 * This is the default implementation, which can be overridden by a hardware
518 * specific driver. It provides the details for writing a bad block marker to a
521 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
523 struct nand_chip *chip = mtd->priv;
524 struct mtd_oob_ops ops;
525 uint8_t buf[2] = { 0, 0 };
526 int ret = 0, res, i = 0;
530 ops.ooboffs = chip->badblockpos;
531 if (chip->options & NAND_BUSWIDTH_16) {
532 ops.ooboffs &= ~0x01;
533 ops.len = ops.ooblen = 2;
535 ops.len = ops.ooblen = 1;
537 ops.mode = MTD_OPS_PLACE_OOB;
539 /* Write to first/last page(s) if necessary */
540 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
541 ofs += mtd->erasesize - mtd->writesize;
543 res = nand_do_write_oob(mtd, ofs, &ops);
548 ofs += mtd->writesize;
549 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
555 * nand_block_markbad_lowlevel - mark a block bad
556 * @mtd: MTD device structure
557 * @ofs: offset from device start
559 * This function performs the generic NAND bad block marking steps (i.e., bad
560 * block table(s) and/or marker(s)). We only allow the hardware driver to
561 * specify how to write bad block markers to OOB (chip->block_markbad).
563 * We try operations in the following order:
564 * (1) erase the affected block, to allow OOB marker to be written cleanly
565 * (2) write bad block marker to OOB area of affected block (unless flag
566 * NAND_BBT_NO_OOB_BBM is present)
568 * Note that we retain the first error encountered in (2) or (3), finish the
569 * procedures, and dump the error in the end.
571 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
573 struct nand_chip *chip = mtd->priv;
576 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
577 struct erase_info einfo;
579 /* Attempt erase before marking OOB */
580 memset(&einfo, 0, sizeof(einfo));
583 einfo.len = 1ULL << chip->phys_erase_shift;
584 nand_erase_nand(mtd, &einfo, 0);
586 /* Write bad block marker to OOB */
587 nand_get_device(mtd, FL_WRITING);
588 ret = chip->block_markbad(mtd, ofs);
589 nand_release_device(mtd);
592 /* Mark block bad in BBT */
594 res = nand_markbad_bbt(mtd, ofs);
600 mtd->ecc_stats.badblocks++;
606 * nand_check_wp - [GENERIC] check if the chip is write protected
607 * @mtd: MTD device structure
609 * Check, if the device is write protected. The function expects, that the
610 * device is already selected.
612 static int nand_check_wp(struct mtd_info *mtd)
614 struct nand_chip *chip = mtd->priv;
616 /* Broken xD cards report WP despite being writable */
617 if (chip->options & NAND_BROKEN_XD)
620 /* Check the WP bit */
621 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
622 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
626 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
627 * @mtd: MTD device structure
628 * @ofs: offset from device start
629 * @getchip: 0, if the chip is already selected
630 * @allowbbt: 1, if its allowed to access the bbt area
632 * Check, if the block is bad. Either by reading the bad block table or
633 * calling of the scan function.
635 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
638 struct nand_chip *chip = mtd->priv;
641 return chip->block_bad(mtd, ofs, getchip);
643 /* Return info from the table */
644 return nand_isbad_bbt(mtd, ofs, allowbbt);
649 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
650 * @mtd: MTD device structure
653 * Helper function for nand_wait_ready used when needing to wait in interrupt
656 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
658 struct nand_chip *chip = mtd->priv;
661 /* Wait for the device to get ready */
662 for (i = 0; i < timeo; i++) {
663 if (chip->dev_ready(mtd))
665 touch_softlockup_watchdog();
671 /* Wait for the ready pin, after a command. The timeout is caught later. */
672 void nand_wait_ready(struct mtd_info *mtd)
674 struct nand_chip *chip = mtd->priv;
676 unsigned long timeo = jiffies + msecs_to_jiffies(20);
679 if (in_interrupt() || oops_in_progress)
680 return panic_nand_wait_ready(mtd, 400);
682 led_trigger_event(nand_led_trigger, LED_FULL);
683 /* Wait until command is processed or timeout occurs */
685 if (chip->dev_ready(mtd))
687 touch_softlockup_watchdog();
688 } while (time_before(jiffies, timeo));
689 led_trigger_event(nand_led_trigger, LED_OFF);
691 u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
694 time_start = get_timer(0);
695 /* Wait until command is processed or timeout occurs */
696 while (get_timer(time_start) < timeo) {
698 if (chip->dev_ready(mtd))
703 EXPORT_SYMBOL_GPL(nand_wait_ready);
706 * nand_command - [DEFAULT] Send command to NAND device
707 * @mtd: MTD device structure
708 * @command: the command to be sent
709 * @column: the column address for this command, -1 if none
710 * @page_addr: the page address for this command, -1 if none
712 * Send command to NAND device. This function is used for small page devices
713 * (512 Bytes per page).
715 static void nand_command(struct mtd_info *mtd, unsigned int command,
716 int column, int page_addr)
718 register struct nand_chip *chip = mtd->priv;
719 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
720 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
722 /* Write out the command to the device */
723 if (command == NAND_CMD_SEQIN) {
726 if (column >= mtd->writesize) {
728 column -= mtd->writesize;
729 readcmd = NAND_CMD_READOOB;
730 } else if (column < 256) {
731 /* First 256 bytes --> READ0 */
732 readcmd = NAND_CMD_READ0;
735 readcmd = NAND_CMD_READ1;
737 chip->cmd_ctrl(mtd, readcmd, ctrl);
738 ctrl &= ~NAND_CTRL_CHANGE;
740 chip->cmd_ctrl(mtd, command, ctrl);
742 /* Address cycle, when necessary */
743 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
744 /* Serially input address */
746 /* Adjust columns for 16 bit buswidth */
747 if ((chip->options & NAND_BUSWIDTH_16) &&
748 !nand_opcode_8bits(command))
750 chip->cmd_ctrl(mtd, column, ctrl);
751 ctrl &= ~NAND_CTRL_CHANGE;
753 if (page_addr != -1) {
754 chip->cmd_ctrl(mtd, page_addr, ctrl);
755 ctrl &= ~NAND_CTRL_CHANGE;
756 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
757 /* One more address cycle for devices > 32MiB */
758 if (chip->chipsize > (32 << 20))
759 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
761 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
764 * Program and erase have their own busy handlers status and sequential
769 case NAND_CMD_PAGEPROG:
770 case NAND_CMD_ERASE1:
771 case NAND_CMD_ERASE2:
773 case NAND_CMD_STATUS:
779 udelay(chip->chip_delay);
780 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
781 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
783 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
784 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
788 /* This applies to read commands */
791 * If we don't have access to the busy pin, we apply the given
794 if (!chip->dev_ready) {
795 udelay(chip->chip_delay);
800 * Apply this short delay always to ensure that we do wait tWB in
801 * any case on any machine.
805 nand_wait_ready(mtd);
809 * nand_command_lp - [DEFAULT] Send command to NAND large page device
810 * @mtd: MTD device structure
811 * @command: the command to be sent
812 * @column: the column address for this command, -1 if none
813 * @page_addr: the page address for this command, -1 if none
815 * Send command to NAND device. This is the version for the new large page
816 * devices. We don't have the separate regions as we have in the small page
817 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
819 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
820 int column, int page_addr)
822 register struct nand_chip *chip = mtd->priv;
823 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
825 /* Emulate NAND_CMD_READOOB */
826 if (command == NAND_CMD_READOOB) {
827 column += mtd->writesize;
828 command = NAND_CMD_READ0;
831 /* Command latch cycle */
832 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
834 if (column != -1 || page_addr != -1) {
835 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
837 /* Serially input address */
839 /* Adjust columns for 16 bit buswidth */
840 if ((chip->options & NAND_BUSWIDTH_16) &&
841 !nand_opcode_8bits(command))
843 chip->cmd_ctrl(mtd, column, ctrl);
844 ctrl &= ~NAND_CTRL_CHANGE;
845 chip->cmd_ctrl(mtd, column >> 8, ctrl);
847 if (page_addr != -1) {
848 chip->cmd_ctrl(mtd, page_addr, ctrl);
849 chip->cmd_ctrl(mtd, page_addr >> 8,
850 NAND_NCE | NAND_ALE);
851 /* One more address cycle for devices > 128MiB */
852 if (chip->chipsize > (128 << 20))
853 chip->cmd_ctrl(mtd, page_addr >> 16,
854 NAND_NCE | NAND_ALE);
857 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
860 * Program and erase have their own busy handlers status, sequential
861 * in, and deplete1 need no delay.
865 case NAND_CMD_CACHEDPROG:
866 case NAND_CMD_PAGEPROG:
867 case NAND_CMD_ERASE1:
868 case NAND_CMD_ERASE2:
871 case NAND_CMD_STATUS:
877 udelay(chip->chip_delay);
878 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
879 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
880 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
881 NAND_NCE | NAND_CTRL_CHANGE);
882 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
886 case NAND_CMD_RNDOUT:
887 /* No ready / busy check necessary */
888 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
889 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
890 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
891 NAND_NCE | NAND_CTRL_CHANGE);
895 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
896 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
897 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
898 NAND_NCE | NAND_CTRL_CHANGE);
900 /* This applies to read commands */
903 * If we don't have access to the busy pin, we apply the given
906 if (!chip->dev_ready) {
907 udelay(chip->chip_delay);
913 * Apply this short delay always to ensure that we do wait tWB in
914 * any case on any machine.
918 nand_wait_ready(mtd);
922 * panic_nand_get_device - [GENERIC] Get chip for selected access
923 * @chip: the nand chip descriptor
924 * @mtd: MTD device structure
925 * @new_state: the state which is requested
927 * Used when in panic, no locks are taken.
929 static void panic_nand_get_device(struct nand_chip *chip,
930 struct mtd_info *mtd, int new_state)
932 /* Hardware controller shared among independent devices */
933 chip->controller->active = chip;
934 chip->state = new_state;
938 * nand_get_device - [GENERIC] Get chip for selected access
939 * @mtd: MTD device structure
940 * @new_state: the state which is requested
942 * Get the device and lock it for exclusive access
945 nand_get_device(struct mtd_info *mtd, int new_state)
947 struct nand_chip *chip = mtd->priv;
949 spinlock_t *lock = &chip->controller->lock;
950 wait_queue_head_t *wq = &chip->controller->wq;
951 DECLARE_WAITQUEUE(wait, current);
955 /* Hardware controller shared among independent devices */
956 if (!chip->controller->active)
957 chip->controller->active = chip;
959 if (chip->controller->active == chip && chip->state == FL_READY) {
960 chip->state = new_state;
964 if (new_state == FL_PM_SUSPENDED) {
965 if (chip->controller->active->state == FL_PM_SUSPENDED) {
966 chip->state = FL_PM_SUSPENDED;
971 set_current_state(TASK_UNINTERRUPTIBLE);
972 add_wait_queue(wq, &wait);
975 remove_wait_queue(wq, &wait);
978 chip->state = new_state;
984 * panic_nand_wait - [GENERIC] wait until the command is done
985 * @mtd: MTD device structure
986 * @chip: NAND chip structure
989 * Wait for command done. This is a helper function for nand_wait used when
990 * we are in interrupt context. May happen when in panic and trying to write
991 * an oops through mtdoops.
993 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
997 for (i = 0; i < timeo; i++) {
998 if (chip->dev_ready) {
999 if (chip->dev_ready(mtd))
1002 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1010 * nand_wait - [DEFAULT] wait until the command is done
1011 * @mtd: MTD device structure
1012 * @chip: NAND chip structure
1014 * Wait for command done. This applies to erase and program only. Erase can
1015 * take up to 400ms and program up to 20ms according to general NAND and
1018 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1021 int status, state = chip->state;
1022 unsigned long timeo = (state == FL_ERASING ? 400 : 20);
1024 led_trigger_event(nand_led_trigger, LED_FULL);
1027 * Apply this short delay always to ensure that we do wait tWB in any
1028 * case on any machine.
1032 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1035 if (in_interrupt() || oops_in_progress)
1036 panic_nand_wait(mtd, chip, timeo);
1038 timeo = jiffies + msecs_to_jiffies(timeo);
1039 while (time_before(jiffies, timeo)) {
1040 if (chip->dev_ready) {
1041 if (chip->dev_ready(mtd))
1044 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1051 u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
1054 time_start = get_timer(0);
1055 while (get_timer(time_start) < timer) {
1056 if (chip->dev_ready) {
1057 if (chip->dev_ready(mtd))
1060 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1065 #ifdef PPCHAMELON_NAND_TIMER_HACK
1066 time_start = get_timer(0);
1067 while (get_timer(time_start) < 10)
1069 #endif /* PPCHAMELON_NAND_TIMER_HACK */
1070 led_trigger_event(nand_led_trigger, LED_OFF);
1072 status = (int)chip->read_byte(mtd);
1073 /* This can happen if in case of timeout or buggy dev_ready */
1074 WARN_ON(!(status & NAND_STATUS_READY));
1080 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1082 * @ofs: offset to start unlock from
1083 * @len: length to unlock
1084 * @invert: when = 0, unlock the range of blocks within the lower and
1085 * upper boundary address
1086 * when = 1, unlock the range of blocks outside the boundaries
1087 * of the lower and upper boundary address
1089 * Returs unlock status.
1091 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
1092 uint64_t len, int invert)
1096 struct nand_chip *chip = mtd->priv;
1098 /* Submit address of first page to unlock */
1099 page = ofs >> chip->page_shift;
1100 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
1102 /* Submit address of last page to unlock */
1103 page = (ofs + len) >> chip->page_shift;
1104 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
1105 (page | invert) & chip->pagemask);
1107 /* Call wait ready function */
1108 status = chip->waitfunc(mtd, chip);
1109 /* See if device thinks it succeeded */
1110 if (status & NAND_STATUS_FAIL) {
1111 pr_debug("%s: error status = 0x%08x\n",
1120 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1122 * @ofs: offset to start unlock from
1123 * @len: length to unlock
1125 * Returns unlock status.
1127 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1131 struct nand_chip *chip = mtd->priv;
1133 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1134 __func__, (unsigned long long)ofs, len);
1136 if (check_offs_len(mtd, ofs, len))
1139 /* Align to last block address if size addresses end of the device */
1140 if (ofs + len == mtd->size)
1141 len -= mtd->erasesize;
1143 nand_get_device(mtd, FL_UNLOCKING);
1145 /* Shift to get chip number */
1146 chipnr = ofs >> chip->chip_shift;
1148 chip->select_chip(mtd, chipnr);
1150 /* Check, if it is write protected */
1151 if (nand_check_wp(mtd)) {
1152 pr_debug("%s: device is write protected!\n",
1158 ret = __nand_unlock(mtd, ofs, len, 0);
1161 chip->select_chip(mtd, -1);
1162 nand_release_device(mtd);
1166 EXPORT_SYMBOL(nand_unlock);
1169 * nand_lock - [REPLACEABLE] locks all blocks present in the device
1171 * @ofs: offset to start unlock from
1172 * @len: length to unlock
1174 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1175 * have this feature, but it allows only to lock all blocks, not for specified
1176 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1179 * Returns lock status.
1181 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1184 int chipnr, status, page;
1185 struct nand_chip *chip = mtd->priv;
1187 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1188 __func__, (unsigned long long)ofs, len);
1190 if (check_offs_len(mtd, ofs, len))
1193 nand_get_device(mtd, FL_LOCKING);
1195 /* Shift to get chip number */
1196 chipnr = ofs >> chip->chip_shift;
1198 chip->select_chip(mtd, chipnr);
1200 /* Check, if it is write protected */
1201 if (nand_check_wp(mtd)) {
1202 pr_debug("%s: device is write protected!\n",
1204 status = MTD_ERASE_FAILED;
1209 /* Submit address of first page to lock */
1210 page = ofs >> chip->page_shift;
1211 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1213 /* Call wait ready function */
1214 status = chip->waitfunc(mtd, chip);
1215 /* See if device thinks it succeeded */
1216 if (status & NAND_STATUS_FAIL) {
1217 pr_debug("%s: error status = 0x%08x\n",
1223 ret = __nand_unlock(mtd, ofs, len, 0x1);
1226 chip->select_chip(mtd, -1);
1227 nand_release_device(mtd);
1231 EXPORT_SYMBOL(nand_lock);
1235 * nand_read_page_raw - [INTERN] read raw page data without ecc
1236 * @mtd: mtd info structure
1237 * @chip: nand chip info structure
1238 * @buf: buffer to store read data
1239 * @oob_required: caller requires OOB data read to chip->oob_poi
1240 * @page: page number to read
1242 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1244 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1245 uint8_t *buf, int oob_required, int page)
1247 chip->read_buf(mtd, buf, mtd->writesize);
1249 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1254 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1255 * @mtd: mtd info structure
1256 * @chip: nand chip info structure
1257 * @buf: buffer to store read data
1258 * @oob_required: caller requires OOB data read to chip->oob_poi
1259 * @page: page number to read
1261 * We need a special oob layout and handling even when OOB isn't used.
1263 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1264 struct nand_chip *chip, uint8_t *buf,
1265 int oob_required, int page)
1267 int eccsize = chip->ecc.size;
1268 int eccbytes = chip->ecc.bytes;
1269 uint8_t *oob = chip->oob_poi;
1272 for (steps = chip->ecc.steps; steps > 0; steps--) {
1273 chip->read_buf(mtd, buf, eccsize);
1276 if (chip->ecc.prepad) {
1277 chip->read_buf(mtd, oob, chip->ecc.prepad);
1278 oob += chip->ecc.prepad;
1281 chip->read_buf(mtd, oob, eccbytes);
1284 if (chip->ecc.postpad) {
1285 chip->read_buf(mtd, oob, chip->ecc.postpad);
1286 oob += chip->ecc.postpad;
1290 size = mtd->oobsize - (oob - chip->oob_poi);
1292 chip->read_buf(mtd, oob, size);
1298 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1299 * @mtd: mtd info structure
1300 * @chip: nand chip info structure
1301 * @buf: buffer to store read data
1302 * @oob_required: caller requires OOB data read to chip->oob_poi
1303 * @page: page number to read
1305 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1306 uint8_t *buf, int oob_required, int page)
1308 int i, eccsize = chip->ecc.size;
1309 int eccbytes = chip->ecc.bytes;
1310 int eccsteps = chip->ecc.steps;
1312 uint8_t *ecc_calc = chip->buffers->ecccalc;
1313 uint8_t *ecc_code = chip->buffers->ecccode;
1314 uint32_t *eccpos = chip->ecc.layout->eccpos;
1315 unsigned int max_bitflips = 0;
1317 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1319 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1320 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1322 for (i = 0; i < chip->ecc.total; i++)
1323 ecc_code[i] = chip->oob_poi[eccpos[i]];
1325 eccsteps = chip->ecc.steps;
1328 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1331 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1333 mtd->ecc_stats.failed++;
1335 mtd->ecc_stats.corrected += stat;
1336 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1339 return max_bitflips;
1343 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1344 * @mtd: mtd info structure
1345 * @chip: nand chip info structure
1346 * @data_offs: offset of requested data within the page
1347 * @readlen: data length
1348 * @bufpoi: buffer to store read data
1350 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1351 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1353 int start_step, end_step, num_steps;
1354 uint32_t *eccpos = chip->ecc.layout->eccpos;
1356 int data_col_addr, i, gaps = 0;
1357 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1358 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1360 unsigned int max_bitflips = 0;
1362 /* Column address within the page aligned to ECC size (256bytes) */
1363 start_step = data_offs / chip->ecc.size;
1364 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1365 num_steps = end_step - start_step + 1;
1367 /* Data size aligned to ECC ecc.size */
1368 datafrag_len = num_steps * chip->ecc.size;
1369 eccfrag_len = num_steps * chip->ecc.bytes;
1371 data_col_addr = start_step * chip->ecc.size;
1372 /* If we read not a page aligned data */
1373 if (data_col_addr != 0)
1374 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1376 p = bufpoi + data_col_addr;
1377 chip->read_buf(mtd, p, datafrag_len);
1380 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1381 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1384 * The performance is faster if we position offsets according to
1385 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1387 for (i = 0; i < eccfrag_len - 1; i++) {
1388 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1389 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1395 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1396 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1399 * Send the command to read the particular ECC bytes take care
1400 * about buswidth alignment in read_buf.
1402 index = start_step * chip->ecc.bytes;
1404 aligned_pos = eccpos[index] & ~(busw - 1);
1405 aligned_len = eccfrag_len;
1406 if (eccpos[index] & (busw - 1))
1408 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1411 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1412 mtd->writesize + aligned_pos, -1);
1413 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1416 for (i = 0; i < eccfrag_len; i++)
1417 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1419 p = bufpoi + data_col_addr;
1420 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1423 stat = chip->ecc.correct(mtd, p,
1424 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1426 mtd->ecc_stats.failed++;
1428 mtd->ecc_stats.corrected += stat;
1429 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1432 return max_bitflips;
1436 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1437 * @mtd: mtd info structure
1438 * @chip: nand chip info structure
1439 * @buf: buffer to store read data
1440 * @oob_required: caller requires OOB data read to chip->oob_poi
1441 * @page: page number to read
1443 * Not for syndrome calculating ECC controllers which need a special oob layout.
1445 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1446 uint8_t *buf, int oob_required, int page)
1448 int i, eccsize = chip->ecc.size;
1449 int eccbytes = chip->ecc.bytes;
1450 int eccsteps = chip->ecc.steps;
1452 uint8_t *ecc_calc = chip->buffers->ecccalc;
1453 uint8_t *ecc_code = chip->buffers->ecccode;
1454 uint32_t *eccpos = chip->ecc.layout->eccpos;
1455 unsigned int max_bitflips = 0;
1457 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1458 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1459 chip->read_buf(mtd, p, eccsize);
1460 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1462 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1464 for (i = 0; i < chip->ecc.total; i++)
1465 ecc_code[i] = chip->oob_poi[eccpos[i]];
1467 eccsteps = chip->ecc.steps;
1470 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1473 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1475 mtd->ecc_stats.failed++;
1477 mtd->ecc_stats.corrected += stat;
1478 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1481 return max_bitflips;
1485 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1486 * @mtd: mtd info structure
1487 * @chip: nand chip info structure
1488 * @buf: buffer to store read data
1489 * @oob_required: caller requires OOB data read to chip->oob_poi
1490 * @page: page number to read
1492 * Hardware ECC for large page chips, require OOB to be read first. For this
1493 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1494 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1495 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1496 * the data area, by overwriting the NAND manufacturer bad block markings.
1498 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1499 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1501 int i, eccsize = chip->ecc.size;
1502 int eccbytes = chip->ecc.bytes;
1503 int eccsteps = chip->ecc.steps;
1505 uint8_t *ecc_code = chip->buffers->ecccode;
1506 uint32_t *eccpos = chip->ecc.layout->eccpos;
1507 uint8_t *ecc_calc = chip->buffers->ecccalc;
1508 unsigned int max_bitflips = 0;
1510 /* Read the OOB area first */
1511 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1512 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1513 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1515 for (i = 0; i < chip->ecc.total; i++)
1516 ecc_code[i] = chip->oob_poi[eccpos[i]];
1518 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1521 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1522 chip->read_buf(mtd, p, eccsize);
1523 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1525 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1527 mtd->ecc_stats.failed++;
1529 mtd->ecc_stats.corrected += stat;
1530 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1533 return max_bitflips;
1537 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1538 * @mtd: mtd info structure
1539 * @chip: nand chip info structure
1540 * @buf: buffer to store read data
1541 * @oob_required: caller requires OOB data read to chip->oob_poi
1542 * @page: page number to read
1544 * The hw generator calculates the error syndrome automatically. Therefore we
1545 * need a special oob layout and handling.
1547 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1548 uint8_t *buf, int oob_required, int page)
1550 int i, eccsize = chip->ecc.size;
1551 int eccbytes = chip->ecc.bytes;
1552 int eccsteps = chip->ecc.steps;
1554 uint8_t *oob = chip->oob_poi;
1555 unsigned int max_bitflips = 0;
1557 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1560 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1561 chip->read_buf(mtd, p, eccsize);
1563 if (chip->ecc.prepad) {
1564 chip->read_buf(mtd, oob, chip->ecc.prepad);
1565 oob += chip->ecc.prepad;
1568 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1569 chip->read_buf(mtd, oob, eccbytes);
1570 stat = chip->ecc.correct(mtd, p, oob, NULL);
1573 mtd->ecc_stats.failed++;
1575 mtd->ecc_stats.corrected += stat;
1576 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1581 if (chip->ecc.postpad) {
1582 chip->read_buf(mtd, oob, chip->ecc.postpad);
1583 oob += chip->ecc.postpad;
1587 /* Calculate remaining oob bytes */
1588 i = mtd->oobsize - (oob - chip->oob_poi);
1590 chip->read_buf(mtd, oob, i);
1592 return max_bitflips;
1596 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1597 * @chip: nand chip structure
1598 * @oob: oob destination address
1599 * @ops: oob ops structure
1600 * @len: size of oob to transfer
1602 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1603 struct mtd_oob_ops *ops, size_t len)
1605 switch (ops->mode) {
1607 case MTD_OPS_PLACE_OOB:
1609 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1612 case MTD_OPS_AUTO_OOB: {
1613 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1614 uint32_t boffs = 0, roffs = ops->ooboffs;
1617 for (; free->length && len; free++, len -= bytes) {
1618 /* Read request not from offset 0? */
1619 if (unlikely(roffs)) {
1620 if (roffs >= free->length) {
1621 roffs -= free->length;
1624 boffs = free->offset + roffs;
1625 bytes = min_t(size_t, len,
1626 (free->length - roffs));
1629 bytes = min_t(size_t, len, free->length);
1630 boffs = free->offset;
1632 memcpy(oob, chip->oob_poi + boffs, bytes);
1644 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1645 * @mtd: MTD device structure
1646 * @retry_mode: the retry mode to use
1648 * Some vendors supply a special command to shift the Vt threshold, to be used
1649 * when there are too many bitflips in a page (i.e., ECC error). After setting
1650 * a new threshold, the host should retry reading the page.
1652 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1654 struct nand_chip *chip = mtd->priv;
1656 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1658 if (retry_mode >= chip->read_retries)
1661 if (!chip->setup_read_retry)
1664 return chip->setup_read_retry(mtd, retry_mode);
1668 * nand_do_read_ops - [INTERN] Read data with ECC
1669 * @mtd: MTD device structure
1670 * @from: offset to read from
1671 * @ops: oob ops structure
1673 * Internal function. Called with chip held.
1675 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1676 struct mtd_oob_ops *ops)
1678 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1679 struct nand_chip *chip = mtd->priv;
1681 uint32_t readlen = ops->len;
1682 uint32_t oobreadlen = ops->ooblen;
1683 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1684 mtd->oobavail : mtd->oobsize;
1686 uint8_t *bufpoi, *oob, *buf;
1687 unsigned int max_bitflips = 0;
1689 bool ecc_fail = false;
1691 chipnr = (int)(from >> chip->chip_shift);
1692 chip->select_chip(mtd, chipnr);
1694 realpage = (int)(from >> chip->page_shift);
1695 page = realpage & chip->pagemask;
1697 col = (int)(from & (mtd->writesize - 1));
1701 oob_required = oob ? 1 : 0;
1704 unsigned int ecc_failures = mtd->ecc_stats.failed;
1707 bytes = min(mtd->writesize - col, readlen);
1708 aligned = (bytes == mtd->writesize);
1710 /* Is the current page in the buffer? */
1711 if (realpage != chip->pagebuf || oob) {
1712 bufpoi = aligned ? buf : chip->buffers->databuf;
1715 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1718 * Now read the page into the buffer. Absent an error,
1719 * the read methods return max bitflips per ecc step.
1721 if (unlikely(ops->mode == MTD_OPS_RAW))
1722 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1725 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1727 ret = chip->ecc.read_subpage(mtd, chip,
1728 col, bytes, bufpoi);
1730 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1731 oob_required, page);
1734 /* Invalidate page cache */
1739 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1741 /* Transfer not aligned data */
1743 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1744 !(mtd->ecc_stats.failed - ecc_failures) &&
1745 (ops->mode != MTD_OPS_RAW)) {
1746 chip->pagebuf = realpage;
1747 chip->pagebuf_bitflips = ret;
1749 /* Invalidate page cache */
1752 memcpy(buf, chip->buffers->databuf + col, bytes);
1755 if (unlikely(oob)) {
1756 int toread = min(oobreadlen, max_oobsize);
1759 oob = nand_transfer_oob(chip,
1761 oobreadlen -= toread;
1765 if (chip->options & NAND_NEED_READRDY) {
1766 /* Apply delay or wait for ready/busy pin */
1767 if (!chip->dev_ready)
1768 udelay(chip->chip_delay);
1770 nand_wait_ready(mtd);
1773 if (mtd->ecc_stats.failed - ecc_failures) {
1774 if (retry_mode + 1 < chip->read_retries) {
1776 ret = nand_setup_read_retry(mtd,
1781 /* Reset failures; retry */
1782 mtd->ecc_stats.failed = ecc_failures;
1785 /* No more retry modes; real failure */
1792 memcpy(buf, chip->buffers->databuf + col, bytes);
1794 max_bitflips = max_t(unsigned int, max_bitflips,
1795 chip->pagebuf_bitflips);
1800 /* Reset to retry mode 0 */
1802 ret = nand_setup_read_retry(mtd, 0);
1811 /* For subsequent reads align to page boundary */
1813 /* Increment page address */
1816 page = realpage & chip->pagemask;
1817 /* Check, if we cross a chip boundary */
1820 chip->select_chip(mtd, -1);
1821 chip->select_chip(mtd, chipnr);
1824 chip->select_chip(mtd, -1);
1826 ops->retlen = ops->len - (size_t) readlen;
1828 ops->oobretlen = ops->ooblen - oobreadlen;
1836 return max_bitflips;
1840 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1841 * @mtd: MTD device structure
1842 * @from: offset to read from
1843 * @len: number of bytes to read
1844 * @retlen: pointer to variable to store the number of read bytes
1845 * @buf: the databuffer to put data
1847 * Get hold of the chip and call nand_do_read.
1849 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1850 size_t *retlen, uint8_t *buf)
1852 struct mtd_oob_ops ops;
1855 nand_get_device(mtd, FL_READING);
1859 ops.mode = MTD_OPS_PLACE_OOB;
1860 ret = nand_do_read_ops(mtd, from, &ops);
1861 *retlen = ops.retlen;
1862 nand_release_device(mtd);
1867 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1868 * @mtd: mtd info structure
1869 * @chip: nand chip info structure
1870 * @page: page number to read
1872 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1875 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1876 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1881 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1883 * @mtd: mtd info structure
1884 * @chip: nand chip info structure
1885 * @page: page number to read
1887 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1890 uint8_t *buf = chip->oob_poi;
1891 int length = mtd->oobsize;
1892 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1893 int eccsize = chip->ecc.size;
1894 uint8_t *bufpoi = buf;
1895 int i, toread, sndrnd = 0, pos;
1897 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1898 for (i = 0; i < chip->ecc.steps; i++) {
1900 pos = eccsize + i * (eccsize + chunk);
1901 if (mtd->writesize > 512)
1902 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1904 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1907 toread = min_t(int, length, chunk);
1908 chip->read_buf(mtd, bufpoi, toread);
1913 chip->read_buf(mtd, bufpoi, length);
1919 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1920 * @mtd: mtd info structure
1921 * @chip: nand chip info structure
1922 * @page: page number to write
1924 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1928 const uint8_t *buf = chip->oob_poi;
1929 int length = mtd->oobsize;
1931 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1932 chip->write_buf(mtd, buf, length);
1933 /* Send command to program the OOB data */
1934 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1936 status = chip->waitfunc(mtd, chip);
1938 return status & NAND_STATUS_FAIL ? -EIO : 0;
1942 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1943 * with syndrome - only for large page flash
1944 * @mtd: mtd info structure
1945 * @chip: nand chip info structure
1946 * @page: page number to write
1948 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1949 struct nand_chip *chip, int page)
1951 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1952 int eccsize = chip->ecc.size, length = mtd->oobsize;
1953 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1954 const uint8_t *bufpoi = chip->oob_poi;
1957 * data-ecc-data-ecc ... ecc-oob
1959 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1961 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1962 pos = steps * (eccsize + chunk);
1967 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1968 for (i = 0; i < steps; i++) {
1970 if (mtd->writesize <= 512) {
1971 uint32_t fill = 0xFFFFFFFF;
1975 int num = min_t(int, len, 4);
1976 chip->write_buf(mtd, (uint8_t *)&fill,
1981 pos = eccsize + i * (eccsize + chunk);
1982 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1986 len = min_t(int, length, chunk);
1987 chip->write_buf(mtd, bufpoi, len);
1992 chip->write_buf(mtd, bufpoi, length);
1994 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1995 status = chip->waitfunc(mtd, chip);
1997 return status & NAND_STATUS_FAIL ? -EIO : 0;
2001 * nand_do_read_oob - [INTERN] NAND read out-of-band
2002 * @mtd: MTD device structure
2003 * @from: offset to read from
2004 * @ops: oob operations description structure
2006 * NAND read out-of-band data from the spare area.
2008 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2009 struct mtd_oob_ops *ops)
2011 int page, realpage, chipnr;
2012 struct nand_chip *chip = mtd->priv;
2013 struct mtd_ecc_stats stats;
2014 int readlen = ops->ooblen;
2016 uint8_t *buf = ops->oobbuf;
2019 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2020 __func__, (unsigned long long)from, readlen);
2022 stats = mtd->ecc_stats;
2024 if (ops->mode == MTD_OPS_AUTO_OOB)
2025 len = chip->ecc.layout->oobavail;
2029 if (unlikely(ops->ooboffs >= len)) {
2030 pr_debug("%s: attempt to start read outside oob\n",
2035 /* Do not allow reads past end of device */
2036 if (unlikely(from >= mtd->size ||
2037 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
2038 (from >> chip->page_shift)) * len)) {
2039 pr_debug("%s: attempt to read beyond end of device\n",
2044 chipnr = (int)(from >> chip->chip_shift);
2045 chip->select_chip(mtd, chipnr);
2047 /* Shift to get page */
2048 realpage = (int)(from >> chip->page_shift);
2049 page = realpage & chip->pagemask;
2054 if (ops->mode == MTD_OPS_RAW)
2055 ret = chip->ecc.read_oob_raw(mtd, chip, page);
2057 ret = chip->ecc.read_oob(mtd, chip, page);
2062 len = min(len, readlen);
2063 buf = nand_transfer_oob(chip, buf, ops, len);
2065 if (chip->options & NAND_NEED_READRDY) {
2066 /* Apply delay or wait for ready/busy pin */
2067 if (!chip->dev_ready)
2068 udelay(chip->chip_delay);
2070 nand_wait_ready(mtd);
2077 /* Increment page address */
2080 page = realpage & chip->pagemask;
2081 /* Check, if we cross a chip boundary */
2084 chip->select_chip(mtd, -1);
2085 chip->select_chip(mtd, chipnr);
2088 chip->select_chip(mtd, -1);
2090 ops->oobretlen = ops->ooblen - readlen;
2095 if (mtd->ecc_stats.failed - stats.failed)
2098 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
2102 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2103 * @mtd: MTD device structure
2104 * @from: offset to read from
2105 * @ops: oob operation description structure
2107 * NAND read data and/or out-of-band data.
2109 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2110 struct mtd_oob_ops *ops)
2112 int ret = -ENOTSUPP;
2116 /* Do not allow reads past end of device */
2117 if (ops->datbuf && (from + ops->len) > mtd->size) {
2118 pr_debug("%s: attempt to read beyond end of device\n",
2123 nand_get_device(mtd, FL_READING);
2125 switch (ops->mode) {
2126 case MTD_OPS_PLACE_OOB:
2127 case MTD_OPS_AUTO_OOB:
2136 ret = nand_do_read_oob(mtd, from, ops);
2138 ret = nand_do_read_ops(mtd, from, ops);
2141 nand_release_device(mtd);
2147 * nand_write_page_raw - [INTERN] raw page write function
2148 * @mtd: mtd info structure
2149 * @chip: nand chip info structure
2151 * @oob_required: must write chip->oob_poi to OOB
2153 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2155 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2156 const uint8_t *buf, int oob_required)
2158 chip->write_buf(mtd, buf, mtd->writesize);
2160 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2166 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2167 * @mtd: mtd info structure
2168 * @chip: nand chip info structure
2170 * @oob_required: must write chip->oob_poi to OOB
2172 * We need a special oob layout and handling even when ECC isn't checked.
2174 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
2175 struct nand_chip *chip,
2176 const uint8_t *buf, int oob_required)
2178 int eccsize = chip->ecc.size;
2179 int eccbytes = chip->ecc.bytes;
2180 uint8_t *oob = chip->oob_poi;
2183 for (steps = chip->ecc.steps; steps > 0; steps--) {
2184 chip->write_buf(mtd, buf, eccsize);
2187 if (chip->ecc.prepad) {
2188 chip->write_buf(mtd, oob, chip->ecc.prepad);
2189 oob += chip->ecc.prepad;
2192 chip->read_buf(mtd, oob, eccbytes);
2195 if (chip->ecc.postpad) {
2196 chip->write_buf(mtd, oob, chip->ecc.postpad);
2197 oob += chip->ecc.postpad;
2201 size = mtd->oobsize - (oob - chip->oob_poi);
2203 chip->write_buf(mtd, oob, size);
2208 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2209 * @mtd: mtd info structure
2210 * @chip: nand chip info structure
2212 * @oob_required: must write chip->oob_poi to OOB
2214 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
2215 const uint8_t *buf, int oob_required)
2217 int i, eccsize = chip->ecc.size;
2218 int eccbytes = chip->ecc.bytes;
2219 int eccsteps = chip->ecc.steps;
2220 uint8_t *ecc_calc = chip->buffers->ecccalc;
2221 const uint8_t *p = buf;
2222 uint32_t *eccpos = chip->ecc.layout->eccpos;
2224 /* Software ECC calculation */
2225 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2226 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2228 for (i = 0; i < chip->ecc.total; i++)
2229 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2231 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
2235 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2236 * @mtd: mtd info structure
2237 * @chip: nand chip info structure
2239 * @oob_required: must write chip->oob_poi to OOB
2241 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2242 const uint8_t *buf, int oob_required)
2244 int i, eccsize = chip->ecc.size;
2245 int eccbytes = chip->ecc.bytes;
2246 int eccsteps = chip->ecc.steps;
2247 uint8_t *ecc_calc = chip->buffers->ecccalc;
2248 const uint8_t *p = buf;
2249 uint32_t *eccpos = chip->ecc.layout->eccpos;
2251 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2252 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2253 chip->write_buf(mtd, p, eccsize);
2254 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2257 for (i = 0; i < chip->ecc.total; i++)
2258 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2260 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2267 * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
2268 * @mtd: mtd info structure
2269 * @chip: nand chip info structure
2270 * @offset: column address of subpage within the page
2271 * @data_len: data length
2273 * @oob_required: must write chip->oob_poi to OOB
2275 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2276 struct nand_chip *chip, uint32_t offset,
2277 uint32_t data_len, const uint8_t *buf,
2280 uint8_t *oob_buf = chip->oob_poi;
2281 uint8_t *ecc_calc = chip->buffers->ecccalc;
2282 int ecc_size = chip->ecc.size;
2283 int ecc_bytes = chip->ecc.bytes;
2284 int ecc_steps = chip->ecc.steps;
2285 uint32_t *eccpos = chip->ecc.layout->eccpos;
2286 uint32_t start_step = offset / ecc_size;
2287 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2288 int oob_bytes = mtd->oobsize / ecc_steps;
2291 for (step = 0; step < ecc_steps; step++) {
2292 /* configure controller for WRITE access */
2293 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2295 /* write data (untouched subpages already masked by 0xFF) */
2296 chip->write_buf(mtd, buf, ecc_size);
2298 /* mask ECC of un-touched subpages by padding 0xFF */
2299 if ((step < start_step) || (step > end_step))
2300 memset(ecc_calc, 0xff, ecc_bytes);
2302 chip->ecc.calculate(mtd, buf, ecc_calc);
2304 /* mask OOB of un-touched subpages by padding 0xFF */
2305 /* if oob_required, preserve OOB metadata of written subpage */
2306 if (!oob_required || (step < start_step) || (step > end_step))
2307 memset(oob_buf, 0xff, oob_bytes);
2310 ecc_calc += ecc_bytes;
2311 oob_buf += oob_bytes;
2314 /* copy calculated ECC for whole page to chip->buffer->oob */
2315 /* this include masked-value(0xFF) for unwritten subpages */
2316 ecc_calc = chip->buffers->ecccalc;
2317 for (i = 0; i < chip->ecc.total; i++)
2318 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2320 /* write OOB buffer to NAND device */
2321 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2328 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2329 * @mtd: mtd info structure
2330 * @chip: nand chip info structure
2332 * @oob_required: must write chip->oob_poi to OOB
2334 * The hw generator calculates the error syndrome automatically. Therefore we
2335 * need a special oob layout and handling.
2337 static int nand_write_page_syndrome(struct mtd_info *mtd,
2338 struct nand_chip *chip,
2339 const uint8_t *buf, int oob_required)
2341 int i, eccsize = chip->ecc.size;
2342 int eccbytes = chip->ecc.bytes;
2343 int eccsteps = chip->ecc.steps;
2344 const uint8_t *p = buf;
2345 uint8_t *oob = chip->oob_poi;
2347 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2349 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2350 chip->write_buf(mtd, p, eccsize);
2352 if (chip->ecc.prepad) {
2353 chip->write_buf(mtd, oob, chip->ecc.prepad);
2354 oob += chip->ecc.prepad;
2357 chip->ecc.calculate(mtd, p, oob);
2358 chip->write_buf(mtd, oob, eccbytes);
2361 if (chip->ecc.postpad) {
2362 chip->write_buf(mtd, oob, chip->ecc.postpad);
2363 oob += chip->ecc.postpad;
2367 /* Calculate remaining oob bytes */
2368 i = mtd->oobsize - (oob - chip->oob_poi);
2370 chip->write_buf(mtd, oob, i);
2376 * nand_write_page - [REPLACEABLE] write one page
2377 * @mtd: MTD device structure
2378 * @chip: NAND chip descriptor
2379 * @offset: address offset within the page
2380 * @data_len: length of actual data to be written
2381 * @buf: the data to write
2382 * @oob_required: must write chip->oob_poi to OOB
2383 * @page: page number to write
2384 * @cached: cached programming
2385 * @raw: use _raw version of write_page
2387 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2388 uint32_t offset, int data_len, const uint8_t *buf,
2389 int oob_required, int page, int cached, int raw)
2391 int status, subpage;
2393 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2394 chip->ecc.write_subpage)
2395 subpage = offset || (data_len < mtd->writesize);
2399 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2402 status = chip->ecc.write_page_raw(mtd, chip, buf,
2405 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2408 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2414 * Cached progamming disabled for now. Not sure if it's worth the
2415 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2419 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2421 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2422 status = chip->waitfunc(mtd, chip);
2424 * See if operation failed and additional status checks are
2427 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2428 status = chip->errstat(mtd, chip, FL_WRITING, status,
2431 if (status & NAND_STATUS_FAIL)
2434 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2435 status = chip->waitfunc(mtd, chip);
2440 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
2441 /* Send command to read back the data */
2442 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2444 if (chip->verify_buf(mtd, buf, mtd->writesize))
2447 /* Make sure the next page prog is preceded by a status read */
2448 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
2456 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2457 * @mtd: MTD device structure
2458 * @oob: oob data buffer
2459 * @len: oob data write length
2460 * @ops: oob ops structure
2462 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2463 struct mtd_oob_ops *ops)
2465 struct nand_chip *chip = mtd->priv;
2468 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2469 * data from a previous OOB read.
2471 memset(chip->oob_poi, 0xff, mtd->oobsize);
2473 switch (ops->mode) {
2475 case MTD_OPS_PLACE_OOB:
2477 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2480 case MTD_OPS_AUTO_OOB: {
2481 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2482 uint32_t boffs = 0, woffs = ops->ooboffs;
2485 for (; free->length && len; free++, len -= bytes) {
2486 /* Write request not from offset 0? */
2487 if (unlikely(woffs)) {
2488 if (woffs >= free->length) {
2489 woffs -= free->length;
2492 boffs = free->offset + woffs;
2493 bytes = min_t(size_t, len,
2494 (free->length - woffs));
2497 bytes = min_t(size_t, len, free->length);
2498 boffs = free->offset;
2500 memcpy(chip->oob_poi + boffs, oob, bytes);
2511 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2514 * nand_do_write_ops - [INTERN] NAND write with ECC
2515 * @mtd: MTD device structure
2516 * @to: offset to write to
2517 * @ops: oob operations description structure
2519 * NAND write with ECC.
2521 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2522 struct mtd_oob_ops *ops)
2524 int chipnr, realpage, page, blockmask, column;
2525 struct nand_chip *chip = mtd->priv;
2526 uint32_t writelen = ops->len;
2528 uint32_t oobwritelen = ops->ooblen;
2529 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2530 mtd->oobavail : mtd->oobsize;
2532 uint8_t *oob = ops->oobbuf;
2533 uint8_t *buf = ops->datbuf;
2535 int oob_required = oob ? 1 : 0;
2542 /* Reject writes, which are not page aligned */
2543 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2545 /* Reject writes, which are not page aligned */
2546 if (NOTALIGNED(to)) {
2548 pr_notice("%s: attempt to write non page aligned data\n",
2553 column = to & (mtd->writesize - 1);
2555 chipnr = (int)(to >> chip->chip_shift);
2556 chip->select_chip(mtd, chipnr);
2558 /* Check, if it is write protected */
2559 if (nand_check_wp(mtd)) {
2564 realpage = (int)(to >> chip->page_shift);
2565 page = realpage & chip->pagemask;
2566 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2568 /* Invalidate the page cache, when we write to the cached page */
2569 if (to <= (chip->pagebuf << chip->page_shift) &&
2570 (chip->pagebuf << chip->page_shift) < (to + ops->len))
2573 /* Don't allow multipage oob writes with offset */
2574 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2580 int bytes = mtd->writesize;
2581 int cached = writelen > bytes && page != blockmask;
2582 uint8_t *wbuf = buf;
2585 /* Partial page write? */
2586 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2588 bytes = min_t(int, bytes - column, (int) writelen);
2590 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2591 memcpy(&chip->buffers->databuf[column], buf, bytes);
2592 wbuf = chip->buffers->databuf;
2595 if (unlikely(oob)) {
2596 size_t len = min(oobwritelen, oobmaxlen);
2597 oob = nand_fill_oob(mtd, oob, len, ops);
2600 /* We still need to erase leftover OOB data */
2601 memset(chip->oob_poi, 0xff, mtd->oobsize);
2603 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2604 oob_required, page, cached,
2605 (ops->mode == MTD_OPS_RAW));
2617 page = realpage & chip->pagemask;
2618 /* Check, if we cross a chip boundary */
2621 chip->select_chip(mtd, -1);
2622 chip->select_chip(mtd, chipnr);
2626 ops->retlen = ops->len - writelen;
2628 ops->oobretlen = ops->ooblen;
2631 chip->select_chip(mtd, -1);
2636 * panic_nand_write - [MTD Interface] NAND write with ECC
2637 * @mtd: MTD device structure
2638 * @to: offset to write to
2639 * @len: number of bytes to write
2640 * @retlen: pointer to variable to store the number of written bytes
2641 * @buf: the data to write
2643 * NAND write with ECC. Used when performing writes in interrupt context, this
2644 * may for example be called by mtdoops when writing an oops while in panic.
2646 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2647 size_t *retlen, const uint8_t *buf)
2649 struct nand_chip *chip = mtd->priv;
2650 struct mtd_oob_ops ops;
2653 /* Wait for the device to get ready */
2654 panic_nand_wait(mtd, chip, 400);
2656 /* Grab the device */
2657 panic_nand_get_device(chip, mtd, FL_WRITING);
2660 ops.datbuf = (uint8_t *)buf;
2662 ops.mode = MTD_OPS_PLACE_OOB;
2664 ret = nand_do_write_ops(mtd, to, &ops);
2666 *retlen = ops.retlen;
2671 * nand_write - [MTD Interface] NAND write with ECC
2672 * @mtd: MTD device structure
2673 * @to: offset to write to
2674 * @len: number of bytes to write
2675 * @retlen: pointer to variable to store the number of written bytes
2676 * @buf: the data to write
2678 * NAND write with ECC.
2680 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2681 size_t *retlen, const uint8_t *buf)
2683 struct mtd_oob_ops ops;
2686 nand_get_device(mtd, FL_WRITING);
2688 ops.datbuf = (uint8_t *)buf;
2690 ops.mode = MTD_OPS_PLACE_OOB;
2691 ret = nand_do_write_ops(mtd, to, &ops);
2692 *retlen = ops.retlen;
2693 nand_release_device(mtd);
2698 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2699 * @mtd: MTD device structure
2700 * @to: offset to write to
2701 * @ops: oob operation description structure
2703 * NAND write out-of-band.
2705 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2706 struct mtd_oob_ops *ops)
2708 int chipnr, page, status, len;
2709 struct nand_chip *chip = mtd->priv;
2711 pr_debug("%s: to = 0x%08x, len = %i\n",
2712 __func__, (unsigned int)to, (int)ops->ooblen);
2714 if (ops->mode == MTD_OPS_AUTO_OOB)
2715 len = chip->ecc.layout->oobavail;
2719 /* Do not allow write past end of page */
2720 if ((ops->ooboffs + ops->ooblen) > len) {
2721 pr_debug("%s: attempt to write past end of page\n",
2726 if (unlikely(ops->ooboffs >= len)) {
2727 pr_debug("%s: attempt to start write outside oob\n",
2732 /* Do not allow write past end of device */
2733 if (unlikely(to >= mtd->size ||
2734 ops->ooboffs + ops->ooblen >
2735 ((mtd->size >> chip->page_shift) -
2736 (to >> chip->page_shift)) * len)) {
2737 pr_debug("%s: attempt to write beyond end of device\n",
2742 chipnr = (int)(to >> chip->chip_shift);
2743 chip->select_chip(mtd, chipnr);
2745 /* Shift to get page */
2746 page = (int)(to >> chip->page_shift);
2749 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2750 * of my DiskOnChip 2000 test units) will clear the whole data page too
2751 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2752 * it in the doc2000 driver in August 1999. dwmw2.
2754 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2756 /* Check, if it is write protected */
2757 if (nand_check_wp(mtd)) {
2758 chip->select_chip(mtd, -1);
2762 /* Invalidate the page cache, if we write to the cached page */
2763 if (page == chip->pagebuf)
2766 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2768 if (ops->mode == MTD_OPS_RAW)
2769 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2771 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2773 chip->select_chip(mtd, -1);
2778 ops->oobretlen = ops->ooblen;
2784 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2785 * @mtd: MTD device structure
2786 * @to: offset to write to
2787 * @ops: oob operation description structure
2789 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2790 struct mtd_oob_ops *ops)
2792 int ret = -ENOTSUPP;
2796 /* Do not allow writes past end of device */
2797 if (ops->datbuf && (to + ops->len) > mtd->size) {
2798 pr_debug("%s: attempt to write beyond end of device\n",
2803 nand_get_device(mtd, FL_WRITING);
2805 switch (ops->mode) {
2806 case MTD_OPS_PLACE_OOB:
2807 case MTD_OPS_AUTO_OOB:
2816 ret = nand_do_write_oob(mtd, to, ops);
2818 ret = nand_do_write_ops(mtd, to, ops);
2821 nand_release_device(mtd);
2826 * single_erase_cmd - [GENERIC] NAND standard block erase command function
2827 * @mtd: MTD device structure
2828 * @page: the page address of the block which will be erased
2830 * Standard erase command for NAND chips.
2832 static void single_erase_cmd(struct mtd_info *mtd, int page)
2834 struct nand_chip *chip = mtd->priv;
2835 /* Send commands to erase a block */
2836 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2837 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2841 * nand_erase - [MTD Interface] erase block(s)
2842 * @mtd: MTD device structure
2843 * @instr: erase instruction
2845 * Erase one ore more blocks.
2847 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2849 return nand_erase_nand(mtd, instr, 0);
2853 * nand_erase_nand - [INTERN] erase block(s)
2854 * @mtd: MTD device structure
2855 * @instr: erase instruction
2856 * @allowbbt: allow erasing the bbt area
2858 * Erase one ore more blocks.
2860 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2863 int page, status, pages_per_block, ret, chipnr;
2864 struct nand_chip *chip = mtd->priv;
2867 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2868 __func__, (unsigned long long)instr->addr,
2869 (unsigned long long)instr->len);
2871 if (check_offs_len(mtd, instr->addr, instr->len))
2874 /* Grab the lock and see if the device is available */
2875 nand_get_device(mtd, FL_ERASING);
2877 /* Shift to get first page */
2878 page = (int)(instr->addr >> chip->page_shift);
2879 chipnr = (int)(instr->addr >> chip->chip_shift);
2881 /* Calculate pages in each block */
2882 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2884 /* Select the NAND device */
2885 chip->select_chip(mtd, chipnr);
2887 /* Check, if it is write protected */
2888 if (nand_check_wp(mtd)) {
2889 pr_debug("%s: device is write protected!\n",
2891 instr->state = MTD_ERASE_FAILED;
2895 /* Loop through the pages */
2898 instr->state = MTD_ERASING;
2903 /* Check if we have a bad block, we do not erase bad blocks! */
2904 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2905 chip->page_shift, 0, allowbbt)) {
2906 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2908 instr->state = MTD_ERASE_FAILED;
2913 * Invalidate the page cache, if we erase the block which
2914 * contains the current cached page.
2916 if (page <= chip->pagebuf && chip->pagebuf <
2917 (page + pages_per_block))
2920 chip->erase_cmd(mtd, page & chip->pagemask);
2922 status = chip->waitfunc(mtd, chip);
2925 * See if operation failed and additional status checks are
2928 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2929 status = chip->errstat(mtd, chip, FL_ERASING,
2932 /* See if block erase succeeded */
2933 if (status & NAND_STATUS_FAIL) {
2934 pr_debug("%s: failed erase, page 0x%08x\n",
2936 instr->state = MTD_ERASE_FAILED;
2938 ((loff_t)page << chip->page_shift);
2942 /* Increment page address and decrement length */
2943 len -= (1ULL << chip->phys_erase_shift);
2944 page += pages_per_block;
2946 /* Check, if we cross a chip boundary */
2947 if (len && !(page & chip->pagemask)) {
2949 chip->select_chip(mtd, -1);
2950 chip->select_chip(mtd, chipnr);
2953 instr->state = MTD_ERASE_DONE;
2957 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2959 /* Deselect and wake up anyone waiting on the device */
2960 chip->select_chip(mtd, -1);
2961 nand_release_device(mtd);
2963 /* Do call back function */
2965 mtd_erase_callback(instr);
2967 /* Return more or less happy */
2972 * nand_sync - [MTD Interface] sync
2973 * @mtd: MTD device structure
2975 * Sync is actually a wait for chip ready function.
2977 static void nand_sync(struct mtd_info *mtd)
2979 pr_debug("%s: called\n", __func__);
2981 /* Grab the lock and see if the device is available */
2982 nand_get_device(mtd, FL_SYNCING);
2983 /* Release it and go back */
2984 nand_release_device(mtd);
2988 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2989 * @mtd: MTD device structure
2990 * @offs: offset relative to mtd start
2992 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2994 return nand_block_checkbad(mtd, offs, 1, 0);
2998 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2999 * @mtd: MTD device structure
3000 * @ofs: offset relative to mtd start
3002 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
3006 ret = nand_block_isbad(mtd, ofs);
3008 /* If it was bad already, return success and do nothing */
3014 return nand_block_markbad_lowlevel(mtd, ofs);
3018 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3019 * @mtd: MTD device structure
3020 * @chip: nand chip info structure
3021 * @addr: feature address.
3022 * @subfeature_param: the subfeature parameters, a four bytes array.
3024 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
3025 int addr, uint8_t *subfeature_param)
3030 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3031 if (!chip->onfi_version ||
3032 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3033 & ONFI_OPT_CMD_SET_GET_FEATURES))
3037 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
3038 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3039 chip->write_byte(mtd, subfeature_param[i]);
3041 status = chip->waitfunc(mtd, chip);
3042 if (status & NAND_STATUS_FAIL)
3048 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3049 * @mtd: MTD device structure
3050 * @chip: nand chip info structure
3051 * @addr: feature address.
3052 * @subfeature_param: the subfeature parameters, a four bytes array.
3054 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
3055 int addr, uint8_t *subfeature_param)
3059 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3060 if (!chip->onfi_version ||
3061 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3062 & ONFI_OPT_CMD_SET_GET_FEATURES))
3066 /* clear the sub feature parameters */
3067 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
3069 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
3070 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3071 *subfeature_param++ = chip->read_byte(mtd);
3077 * nand_suspend - [MTD Interface] Suspend the NAND flash
3078 * @mtd: MTD device structure
3080 static int nand_suspend(struct mtd_info *mtd)
3082 return nand_get_device(mtd, FL_PM_SUSPENDED);
3086 * nand_resume - [MTD Interface] Resume the NAND flash
3087 * @mtd: MTD device structure
3089 static void nand_resume(struct mtd_info *mtd)
3091 struct nand_chip *chip = mtd->priv;
3093 if (chip->state == FL_PM_SUSPENDED)
3094 nand_release_device(mtd);
3096 pr_err("%s called for a chip which is not in suspended state\n",
3101 /* Set default functions */
3102 static void nand_set_defaults(struct nand_chip *chip, int busw)
3104 /* check for proper chip_delay setup, set 20us if not */
3105 if (!chip->chip_delay)
3106 chip->chip_delay = 20;
3108 /* check, if a user supplied command function given */
3109 if (chip->cmdfunc == NULL)
3110 chip->cmdfunc = nand_command;
3112 /* check, if a user supplied wait function given */
3113 if (chip->waitfunc == NULL)
3114 chip->waitfunc = nand_wait;
3116 if (!chip->select_chip)
3117 chip->select_chip = nand_select_chip;
3119 /* set for ONFI nand */
3120 if (!chip->onfi_set_features)
3121 chip->onfi_set_features = nand_onfi_set_features;
3122 if (!chip->onfi_get_features)
3123 chip->onfi_get_features = nand_onfi_get_features;
3125 /* If called twice, pointers that depend on busw may need to be reset */
3126 if (!chip->read_byte || chip->read_byte == nand_read_byte)
3127 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3128 if (!chip->read_word)
3129 chip->read_word = nand_read_word;
3130 if (!chip->block_bad)
3131 chip->block_bad = nand_block_bad;
3132 if (!chip->block_markbad)
3133 chip->block_markbad = nand_default_block_markbad;
3134 if (!chip->write_buf || chip->write_buf == nand_write_buf)
3135 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
3136 if (!chip->write_byte || chip->write_byte == nand_write_byte)
3137 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
3138 if (!chip->read_buf || chip->read_buf == nand_read_buf)
3139 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
3140 if (!chip->scan_bbt)
3141 chip->scan_bbt = nand_default_bbt;
3143 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
3144 if (!chip->verify_buf)
3145 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
3149 if (!chip->controller) {
3150 chip->controller = &chip->hwcontrol;
3151 spin_lock_init(&chip->controller->lock);
3152 init_waitqueue_head(&chip->controller->wq);
3157 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3158 /* Sanitize ONFI strings so we can safely print them */
3160 static void sanitize_string(uint8_t *s, size_t len)
3162 static void sanitize_string(char *s, size_t len)
3167 /* Null terminate */
3170 /* Remove non printable chars */
3171 for (i = 0; i < len - 1; i++) {
3172 if (s[i] < ' ' || s[i] > 127)
3176 /* Remove trailing spaces */
3180 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3185 for (i = 0; i < 8; i++)
3186 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3192 /* Parse the Extended Parameter Page. */
3193 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3194 struct nand_chip *chip, struct nand_onfi_params *p)
3196 struct onfi_ext_param_page *ep;
3197 struct onfi_ext_section *s;
3198 struct onfi_ext_ecc_info *ecc;
3204 len = le16_to_cpu(p->ext_param_page_length) * 16;
3205 ep = kmalloc(len, GFP_KERNEL);
3209 /* Send our own NAND_CMD_PARAM. */
3210 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3212 /* Use the Change Read Column command to skip the ONFI param pages. */
3213 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3214 sizeof(*p) * p->num_of_param_pages , -1);
3216 /* Read out the Extended Parameter Page. */
3217 chip->read_buf(mtd, (uint8_t *)ep, len);
3218 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3219 != le16_to_cpu(ep->crc))) {
3220 pr_debug("fail in the CRC.\n");
3225 * Check the signature.
3226 * Do not strictly follow the ONFI spec, maybe changed in future.
3229 if (strncmp(ep->sig, "EPPS", 4)) {
3231 if (strncmp((char *)ep->sig, "EPPS", 4)) {
3233 pr_debug("The signature is invalid.\n");
3237 /* find the ECC section. */
3238 cursor = (uint8_t *)(ep + 1);
3239 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3240 s = ep->sections + i;
3241 if (s->type == ONFI_SECTION_TYPE_2)
3243 cursor += s->length * 16;
3245 if (i == ONFI_EXT_SECTION_MAX) {
3246 pr_debug("We can not find the ECC section.\n");
3250 /* get the info we want. */
3251 ecc = (struct onfi_ext_ecc_info *)cursor;
3253 if (!ecc->codeword_size) {
3254 pr_debug("Invalid codeword size\n");
3258 chip->ecc_strength_ds = ecc->ecc_bits;
3259 chip->ecc_step_ds = 1 << ecc->codeword_size;
3267 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3269 struct nand_chip *chip = mtd->priv;
3270 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3272 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3277 * Configure chip properties from Micron vendor-specific ONFI table
3279 static void nand_onfi_detect_micron(struct nand_chip *chip,
3280 struct nand_onfi_params *p)
3282 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3284 if (le16_to_cpu(p->vendor_revision) < 1)
3287 chip->read_retries = micron->read_retry_options;
3288 chip->setup_read_retry = nand_setup_read_retry_micron;
3292 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3294 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3297 struct nand_onfi_params *p = &chip->onfi_params;
3301 /* Try ONFI for unknown chip or LP */
3302 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3303 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3304 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3308 * ONFI must be probed in 8-bit mode or with NAND_BUSWIDTH_AUTO, not
3309 * with NAND_BUSWIDTH_16
3311 if (chip->options & NAND_BUSWIDTH_16) {
3312 pr_err("ONFI cannot be probed in 16-bit mode; aborting\n");
3316 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3317 for (i = 0; i < 3; i++) {
3318 for (j = 0; j < sizeof(*p); j++)
3319 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3320 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3321 le16_to_cpu(p->crc)) {
3327 pr_err("Could not find valid ONFI parameter page; aborting\n");
3332 val = le16_to_cpu(p->revision);
3334 chip->onfi_version = 23;
3335 else if (val & (1 << 4))
3336 chip->onfi_version = 22;
3337 else if (val & (1 << 3))
3338 chip->onfi_version = 21;
3339 else if (val & (1 << 2))
3340 chip->onfi_version = 20;
3341 else if (val & (1 << 1))
3342 chip->onfi_version = 10;
3344 if (!chip->onfi_version) {
3345 pr_info("unsupported ONFI version: %d\n", val);
3349 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3350 sanitize_string(p->model, sizeof(p->model));
3352 mtd->name = p->model;
3354 mtd->writesize = le32_to_cpu(p->byte_per_page);
3357 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3358 * (don't ask me who thought of this...). MTD assumes that these
3359 * dimensions will be power-of-2, so just truncate the remaining area.
3361 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3362 mtd->erasesize *= mtd->writesize;
3364 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3366 /* See erasesize comment */
3367 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3368 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3369 chip->bits_per_cell = p->bits_per_cell;
3371 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3372 *busw = NAND_BUSWIDTH_16;
3376 if (p->ecc_bits != 0xff) {
3377 chip->ecc_strength_ds = p->ecc_bits;
3378 chip->ecc_step_ds = 512;
3379 } else if (chip->onfi_version >= 21 &&
3380 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3383 * The nand_flash_detect_ext_param_page() uses the
3384 * Change Read Column command which maybe not supported
3385 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3386 * now. We do not replace user supplied command function.
3388 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3389 chip->cmdfunc = nand_command_lp;
3391 /* The Extended Parameter Page is supported since ONFI 2.1. */
3392 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3393 pr_warn("Failed to detect ONFI extended param page\n");
3395 pr_warn("Could not retrieve ONFI ECC requirements\n");
3398 if (p->jedec_id == NAND_MFR_MICRON)
3399 nand_onfi_detect_micron(chip, p);
3404 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3412 * nand_id_has_period - Check if an ID string has a given wraparound period
3413 * @id_data: the ID string
3414 * @arrlen: the length of the @id_data array
3415 * @period: the period of repitition
3417 * Check if an ID string is repeated within a given sequence of bytes at
3418 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3419 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3420 * if the repetition has a period of @period; otherwise, returns zero.
3422 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3425 for (i = 0; i < period; i++)
3426 for (j = i + period; j < arrlen; j += period)
3427 if (id_data[i] != id_data[j])
3433 * nand_id_len - Get the length of an ID string returned by CMD_READID
3434 * @id_data: the ID string
3435 * @arrlen: the length of the @id_data array
3437 * Returns the length of the ID string, according to known wraparound/trailing
3438 * zero patterns. If no pattern exists, returns the length of the array.
3440 static int nand_id_len(u8 *id_data, int arrlen)
3442 int last_nonzero, period;
3444 /* Find last non-zero byte */
3445 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3446 if (id_data[last_nonzero])
3450 if (last_nonzero < 0)
3453 /* Calculate wraparound period */
3454 for (period = 1; period < arrlen; period++)
3455 if (nand_id_has_period(id_data, arrlen, period))
3458 /* There's a repeated pattern */
3459 if (period < arrlen)
3462 /* There are trailing zeros */
3463 if (last_nonzero < arrlen - 1)
3464 return last_nonzero + 1;
3466 /* No pattern detected */
3470 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3471 static int nand_get_bits_per_cell(u8 cellinfo)
3475 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3476 bits >>= NAND_CI_CELLTYPE_SHIFT;
3481 * Many new NAND share similar device ID codes, which represent the size of the
3482 * chip. The rest of the parameters must be decoded according to generic or
3483 * manufacturer-specific "extended ID" decoding patterns.
3485 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3486 u8 id_data[8], int *busw)
3489 /* The 3rd id byte holds MLC / multichip data */
3490 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3491 /* The 4th id byte is the important one */
3494 id_len = nand_id_len(id_data, 8);
3497 * Field definitions are in the following datasheets:
3498 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3499 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3500 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3502 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3503 * ID to decide what to do.
3505 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3506 !nand_is_slc(chip) && id_data[5] != 0x00) {
3508 mtd->writesize = 2048 << (extid & 0x03);
3511 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3531 default: /* Other cases are "reserved" (unknown) */
3532 mtd->oobsize = 1024;
3536 /* Calc blocksize */
3537 mtd->erasesize = (128 * 1024) <<
3538 (((extid >> 1) & 0x04) | (extid & 0x03));
3540 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3541 !nand_is_slc(chip)) {
3545 mtd->writesize = 2048 << (extid & 0x03);
3548 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3572 /* Calc blocksize */
3573 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3575 mtd->erasesize = (128 * 1024) << tmp;
3576 else if (tmp == 0x03)
3577 mtd->erasesize = 768 * 1024;
3579 mtd->erasesize = (64 * 1024) << tmp;
3583 mtd->writesize = 1024 << (extid & 0x03);
3586 mtd->oobsize = (8 << (extid & 0x01)) *
3587 (mtd->writesize >> 9);
3589 /* Calc blocksize. Blocksize is multiples of 64KiB */
3590 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3592 /* Get buswidth information */
3593 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3596 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3597 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3599 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3601 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3603 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3604 nand_is_slc(chip) &&
3605 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3606 !(id_data[4] & 0x80) /* !BENAND */) {
3607 mtd->oobsize = 32 * mtd->writesize >> 9;
3614 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3615 * decodes a matching ID table entry and assigns the MTD size parameters for
3618 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3619 struct nand_flash_dev *type, u8 id_data[8],
3622 int maf_id = id_data[0];
3624 mtd->erasesize = type->erasesize;
3625 mtd->writesize = type->pagesize;
3626 mtd->oobsize = mtd->writesize / 32;
3627 *busw = type->options & NAND_BUSWIDTH_16;
3629 /* All legacy ID NAND are small-page, SLC */
3630 chip->bits_per_cell = 1;
3633 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3634 * some Spansion chips have erasesize that conflicts with size
3635 * listed in nand_ids table.
3636 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3638 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3639 && id_data[6] == 0x00 && id_data[7] == 0x00
3640 && mtd->writesize == 512) {
3641 mtd->erasesize = 128 * 1024;
3642 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3647 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3648 * heuristic patterns using various detected parameters (e.g., manufacturer,
3649 * page size, cell-type information).
3651 static void nand_decode_bbm_options(struct mtd_info *mtd,
3652 struct nand_chip *chip, u8 id_data[8])
3654 int maf_id = id_data[0];
3656 /* Set the bad block position */
3657 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3658 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3660 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3663 * Bad block marker is stored in the last page of each block on Samsung
3664 * and Hynix MLC devices; stored in first two pages of each block on
3665 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3666 * AMD/Spansion, and Macronix. All others scan only the first page.
3668 if (!nand_is_slc(chip) &&
3669 (maf_id == NAND_MFR_SAMSUNG ||
3670 maf_id == NAND_MFR_HYNIX))
3671 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3672 else if ((nand_is_slc(chip) &&
3673 (maf_id == NAND_MFR_SAMSUNG ||
3674 maf_id == NAND_MFR_HYNIX ||
3675 maf_id == NAND_MFR_TOSHIBA ||
3676 maf_id == NAND_MFR_AMD ||
3677 maf_id == NAND_MFR_MACRONIX)) ||
3678 (mtd->writesize == 2048 &&
3679 maf_id == NAND_MFR_MICRON))
3680 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3683 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3685 return type->id_len;
3688 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3689 struct nand_flash_dev *type, u8 *id_data, int *busw)
3692 if (!strncmp(type->id, id_data, type->id_len)) {
3694 if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) {
3696 mtd->writesize = type->pagesize;
3697 mtd->erasesize = type->erasesize;
3698 mtd->oobsize = type->oobsize;
3700 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3701 chip->chipsize = (uint64_t)type->chipsize << 20;
3702 chip->options |= type->options;
3703 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3704 chip->ecc_step_ds = NAND_ECC_STEP(type);
3706 *busw = type->options & NAND_BUSWIDTH_16;
3709 mtd->name = type->name;
3717 * Get the flash and manufacturer id and lookup if the type is supported.
3719 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3720 struct nand_chip *chip,
3722 int *maf_id, int *dev_id,
3723 struct nand_flash_dev *type)
3728 /* Select the device */
3729 chip->select_chip(mtd, 0);
3732 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3735 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3737 /* Send the command for reading device ID */
3738 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3740 /* Read manufacturer and device IDs */
3741 *maf_id = chip->read_byte(mtd);
3742 *dev_id = chip->read_byte(mtd);
3745 * Try again to make sure, as some systems the bus-hold or other
3746 * interface concerns can cause random data which looks like a
3747 * possibly credible NAND flash to appear. If the two results do
3748 * not match, ignore the device completely.
3751 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3753 /* Read entire ID string */
3754 for (i = 0; i < 8; i++)
3755 id_data[i] = chip->read_byte(mtd);
3757 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3758 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3759 *maf_id, *dev_id, id_data[0], id_data[1]);
3760 return ERR_PTR(-ENODEV);
3764 type = nand_flash_ids;
3766 for (; type->name != NULL; type++) {
3767 if (is_full_id_nand(type)) {
3768 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3770 } else if (*dev_id == type->dev_id) {
3775 chip->onfi_version = 0;
3776 if (!type->name || !type->pagesize) {
3777 /* Check is chip is ONFI compliant */
3778 if (nand_flash_detect_onfi(mtd, chip, &busw))
3783 return ERR_PTR(-ENODEV);
3786 mtd->name = type->name;
3788 chip->chipsize = (uint64_t)type->chipsize << 20;
3790 if (!type->pagesize && chip->init_size) {
3791 /* Set the pagesize, oobsize, erasesize by the driver */
3792 busw = chip->init_size(mtd, chip, id_data);
3793 } else if (!type->pagesize) {
3794 /* Decode parameters from extended ID */
3795 nand_decode_ext_id(mtd, chip, id_data, &busw);
3797 nand_decode_id(mtd, chip, type, id_data, &busw);
3799 /* Get chip options */
3800 chip->options |= type->options;
3803 * Check if chip is not a Samsung device. Do not clear the
3804 * options for chips which do not have an extended id.
3806 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3807 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3810 /* Try to identify manufacturer */
3811 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3812 if (nand_manuf_ids[maf_idx].id == *maf_id)
3816 if (chip->options & NAND_BUSWIDTH_AUTO) {
3817 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3818 chip->options |= busw;
3819 nand_set_defaults(chip, busw);
3820 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3822 * Check, if buswidth is correct. Hardware drivers should set
3825 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3827 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3828 pr_warn("bus width %d instead %d bit\n",
3829 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3831 return ERR_PTR(-EINVAL);
3834 nand_decode_bbm_options(mtd, chip, id_data);
3836 /* Calculate the address shift from the page size */
3837 chip->page_shift = ffs(mtd->writesize) - 1;
3838 /* Convert chipsize to number of pages per chip -1 */
3839 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3841 chip->bbt_erase_shift = chip->phys_erase_shift =
3842 ffs(mtd->erasesize) - 1;
3843 if (chip->chipsize & 0xffffffff)
3844 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3846 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3847 chip->chip_shift += 32 - 1;
3850 chip->badblockbits = 8;
3851 chip->erase_cmd = single_erase_cmd;
3853 /* Do not replace user supplied command function! */
3854 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3855 chip->cmdfunc = nand_command_lp;
3857 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3859 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3860 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3861 chip->onfi_version ? chip->onfi_params.model : type->name);
3863 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, type->name);
3865 pr_info("%dMiB, %s, page size: %d, OOB size: %d\n",
3866 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3867 mtd->writesize, mtd->oobsize);
3872 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3873 * @mtd: MTD device structure
3874 * @maxchips: number of chips to scan for
3875 * @table: alternative NAND ID table
3877 * This is the first phase of the normal nand_scan() function. It reads the
3878 * flash ID and sets up MTD fields accordingly.
3880 * The mtd->owner field must be set to the module of the caller.
3882 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3883 struct nand_flash_dev *table)
3885 int i, busw, nand_maf_id, nand_dev_id;
3886 struct nand_chip *chip = mtd->priv;
3887 struct nand_flash_dev *type;
3889 /* Get buswidth to select the correct functions */
3890 busw = chip->options & NAND_BUSWIDTH_16;
3891 /* Set the default functions */
3892 nand_set_defaults(chip, busw);
3894 /* Read the flash type */
3895 type = nand_get_flash_type(mtd, chip, busw,
3896 &nand_maf_id, &nand_dev_id, table);
3899 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3900 pr_warn("No NAND device found\n");
3901 chip->select_chip(mtd, -1);
3902 return PTR_ERR(type);
3905 chip->select_chip(mtd, -1);
3907 /* Check for a chip array */
3908 for (i = 1; i < maxchips; i++) {
3909 chip->select_chip(mtd, i);
3910 /* See comment in nand_get_flash_type for reset */
3911 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3912 /* Send the command for reading device ID */
3913 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3914 /* Read manufacturer and device IDs */
3915 if (nand_maf_id != chip->read_byte(mtd) ||
3916 nand_dev_id != chip->read_byte(mtd)) {
3917 chip->select_chip(mtd, -1);
3920 chip->select_chip(mtd, -1);
3925 pr_info("%d chips detected\n", i);
3928 /* Store the number of chips and calc total size for mtd */
3930 mtd->size = i * chip->chipsize;
3934 EXPORT_SYMBOL(nand_scan_ident);
3938 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3939 * @mtd: MTD device structure
3941 * This is the second phase of the normal nand_scan() function. It fills out
3942 * all the uninitialized function pointers with the defaults and scans for a
3943 * bad block table if appropriate.
3945 int nand_scan_tail(struct mtd_info *mtd)
3948 struct nand_chip *chip = mtd->priv;
3949 struct nand_ecc_ctrl *ecc = &chip->ecc;
3951 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3952 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3953 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3955 if (!(chip->options & NAND_OWN_BUFFERS))
3956 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3960 /* Set the internal oob buffer location, just after the page data */
3961 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3964 * If no default placement scheme is given, select an appropriate one.
3966 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
3967 switch (mtd->oobsize) {
3969 ecc->layout = &nand_oob_8;
3972 ecc->layout = &nand_oob_16;
3975 ecc->layout = &nand_oob_64;
3978 ecc->layout = &nand_oob_128;
3981 pr_warn("No oob scheme defined for oobsize %d\n",
3987 if (!chip->write_page)
3988 chip->write_page = nand_write_page;
3991 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3992 * selected and we have 256 byte pagesize fallback to software ECC
3995 switch (ecc->mode) {
3996 case NAND_ECC_HW_OOB_FIRST:
3997 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3998 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
3999 pr_warn("No ECC functions supplied; "
4000 "hardware ECC not possible\n");
4003 if (!ecc->read_page)
4004 ecc->read_page = nand_read_page_hwecc_oob_first;
4007 /* Use standard hwecc read page function? */
4008 if (!ecc->read_page)
4009 ecc->read_page = nand_read_page_hwecc;
4010 if (!ecc->write_page)
4011 ecc->write_page = nand_write_page_hwecc;
4012 if (!ecc->read_page_raw)
4013 ecc->read_page_raw = nand_read_page_raw;
4014 if (!ecc->write_page_raw)
4015 ecc->write_page_raw = nand_write_page_raw;
4017 ecc->read_oob = nand_read_oob_std;
4018 if (!ecc->write_oob)
4019 ecc->write_oob = nand_write_oob_std;
4020 if (!ecc->read_subpage)
4021 ecc->read_subpage = nand_read_subpage;
4022 if (!ecc->write_subpage)
4023 ecc->write_subpage = nand_write_subpage_hwecc;
4025 case NAND_ECC_HW_SYNDROME:
4026 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
4028 ecc->read_page == nand_read_page_hwecc ||
4030 ecc->write_page == nand_write_page_hwecc)) {
4031 pr_warn("No ECC functions supplied; "
4032 "hardware ECC not possible\n");
4035 /* Use standard syndrome read/write page function? */
4036 if (!ecc->read_page)
4037 ecc->read_page = nand_read_page_syndrome;
4038 if (!ecc->write_page)
4039 ecc->write_page = nand_write_page_syndrome;
4040 if (!ecc->read_page_raw)
4041 ecc->read_page_raw = nand_read_page_raw_syndrome;
4042 if (!ecc->write_page_raw)
4043 ecc->write_page_raw = nand_write_page_raw_syndrome;
4045 ecc->read_oob = nand_read_oob_syndrome;
4046 if (!ecc->write_oob)
4047 ecc->write_oob = nand_write_oob_syndrome;
4049 if (mtd->writesize >= ecc->size) {
4050 if (!ecc->strength) {
4051 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4056 pr_warn("%d byte HW ECC not possible on "
4057 "%d byte page size, fallback to SW ECC\n",
4058 ecc->size, mtd->writesize);
4059 ecc->mode = NAND_ECC_SOFT;
4062 ecc->calculate = nand_calculate_ecc;
4063 ecc->correct = nand_correct_data;
4064 ecc->read_page = nand_read_page_swecc;
4065 ecc->read_subpage = nand_read_subpage;
4066 ecc->write_page = nand_write_page_swecc;
4067 ecc->read_page_raw = nand_read_page_raw;
4068 ecc->write_page_raw = nand_write_page_raw;
4069 ecc->read_oob = nand_read_oob_std;
4070 ecc->write_oob = nand_write_oob_std;
4077 case NAND_ECC_SOFT_BCH:
4078 if (!mtd_nand_has_bch()) {
4079 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
4082 ecc->calculate = nand_bch_calculate_ecc;
4083 ecc->correct = nand_bch_correct_data;
4084 ecc->read_page = nand_read_page_swecc;
4085 ecc->read_subpage = nand_read_subpage;
4086 ecc->write_page = nand_write_page_swecc;
4087 ecc->read_page_raw = nand_read_page_raw;
4088 ecc->write_page_raw = nand_write_page_raw;
4089 ecc->read_oob = nand_read_oob_std;
4090 ecc->write_oob = nand_write_oob_std;
4092 * Board driver should supply ecc.size and ecc.bytes values to
4093 * select how many bits are correctable; see nand_bch_init()
4094 * for details. Otherwise, default to 4 bits for large page
4097 if (!ecc->size && (mtd->oobsize >= 64)) {
4101 ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
4104 pr_warn("BCH ECC initialization failed!\n");
4107 ecc->strength = ecc->bytes * 8 / fls(8 * ecc->size);
4111 pr_warn("NAND_ECC_NONE selected by board driver. "
4112 "This is not recommended!\n");
4113 ecc->read_page = nand_read_page_raw;
4114 ecc->write_page = nand_write_page_raw;
4115 ecc->read_oob = nand_read_oob_std;
4116 ecc->read_page_raw = nand_read_page_raw;
4117 ecc->write_page_raw = nand_write_page_raw;
4118 ecc->write_oob = nand_write_oob_std;
4119 ecc->size = mtd->writesize;
4125 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
4129 /* For many systems, the standard OOB write also works for raw */
4130 if (!ecc->read_oob_raw)
4131 ecc->read_oob_raw = ecc->read_oob;
4132 if (!ecc->write_oob_raw)
4133 ecc->write_oob_raw = ecc->write_oob;
4136 * The number of bytes available for a client to place data into
4137 * the out of band area.
4139 ecc->layout->oobavail = 0;
4140 for (i = 0; ecc->layout->oobfree[i].length
4141 && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
4142 ecc->layout->oobavail += ecc->layout->oobfree[i].length;
4143 mtd->oobavail = ecc->layout->oobavail;
4146 * Set the number of read / write steps for one page depending on ECC
4149 ecc->steps = mtd->writesize / ecc->size;
4150 if (ecc->steps * ecc->size != mtd->writesize) {
4151 pr_warn("Invalid ECC parameters\n");
4154 ecc->total = ecc->steps * ecc->bytes;
4156 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4157 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
4158 switch (ecc->steps) {
4160 mtd->subpage_sft = 1;
4165 mtd->subpage_sft = 2;
4169 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4171 /* Initialize state */
4172 chip->state = FL_READY;
4174 /* Invalidate the pagebuffer reference */
4177 /* Large page NAND with SOFT_ECC should support subpage reads */
4178 if ((ecc->mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
4179 chip->options |= NAND_SUBPAGE_READ;
4181 /* Fill in remaining MTD driver data */
4182 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
4183 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4185 mtd->_erase = nand_erase;
4188 mtd->_unpoint = NULL;
4190 mtd->_read = nand_read;
4191 mtd->_write = nand_write;
4192 mtd->_panic_write = panic_nand_write;
4193 mtd->_read_oob = nand_read_oob;
4194 mtd->_write_oob = nand_write_oob;
4195 mtd->_sync = nand_sync;
4197 mtd->_unlock = NULL;
4199 mtd->_suspend = nand_suspend;
4200 mtd->_resume = nand_resume;
4202 mtd->_block_isbad = nand_block_isbad;
4203 mtd->_block_markbad = nand_block_markbad;
4204 mtd->writebufsize = mtd->writesize;
4206 /* propagate ecc info to mtd_info */
4207 mtd->ecclayout = ecc->layout;
4208 mtd->ecc_strength = ecc->strength;
4209 mtd->ecc_step_size = ecc->size;
4211 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4212 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4215 if (!mtd->bitflip_threshold)
4216 mtd->bitflip_threshold = mtd->ecc_strength;
4218 /* Check, if we should skip the bad block table scan */
4219 if (chip->options & NAND_SKIP_BBTSCAN)
4222 /* Build bad block table */
4223 return chip->scan_bbt(mtd);
4225 EXPORT_SYMBOL(nand_scan_tail);
4228 * is_module_text_address() isn't exported, and it's mostly a pointless
4229 * test if this is a module _anyway_ -- they'd have to try _really_ hard
4230 * to call us from in-kernel code if the core NAND support is modular.
4233 #define caller_is_module() (1)
4235 #define caller_is_module() \
4236 is_module_text_address((unsigned long)__builtin_return_address(0))
4240 * nand_scan - [NAND Interface] Scan for the NAND device
4241 * @mtd: MTD device structure
4242 * @maxchips: number of chips to scan for
4244 * This fills out all the uninitialized function pointers with the defaults.
4245 * The flash ID is read and the mtd/chip structures are filled with the
4246 * appropriate values. The mtd->owner field must be set to the module of the
4249 int nand_scan(struct mtd_info *mtd, int maxchips)
4253 /* Many callers got this wrong, so check for it for a while... */
4254 if (!mtd->owner && caller_is_module()) {
4255 pr_crit("%s called with NULL mtd->owner!\n", __func__);
4259 ret = nand_scan_ident(mtd, maxchips, NULL);
4261 ret = nand_scan_tail(mtd);
4264 EXPORT_SYMBOL(nand_scan);
4268 * nand_release - [NAND Interface] Free resources held by the NAND device
4269 * @mtd: MTD device structure
4271 void nand_release(struct mtd_info *mtd)
4273 struct nand_chip *chip = mtd->priv;
4275 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
4276 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4278 mtd_device_unregister(mtd);
4280 /* Free bad block table memory */
4282 if (!(chip->options & NAND_OWN_BUFFERS))
4283 kfree(chip->buffers);
4285 /* Free bad block descriptor memory */
4286 if (chip->badblock_pattern && chip->badblock_pattern->options
4287 & NAND_BBT_DYNAMICSTRUCT)
4288 kfree(chip->badblock_pattern);
4290 EXPORT_SYMBOL_GPL(nand_release);
4292 static int __init nand_base_init(void)
4294 led_trigger_register_simple("nand-disk", &nand_led_trigger);
4298 static void __exit nand_base_exit(void)
4300 led_trigger_unregister_simple(nand_led_trigger);
4304 module_init(nand_base_init);
4305 module_exit(nand_base_exit);
4307 MODULE_LICENSE("GPL");
4308 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4309 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4310 MODULE_DESCRIPTION("Generic NAND flash driver code");