5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/tech/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
28 * This program is free software; you can redistribute it and/or modify
29 * it under the terms of the GNU General Public License version 2 as
30 * published by the Free Software Foundation.
36 #include <linux/module.h>
37 #include <linux/delay.h>
38 #include <linux/errno.h>
39 #include <linux/err.h>
40 #include <linux/sched.h>
41 #include <linux/slab.h>
42 #include <linux/types.h>
43 #include <linux/mtd/mtd.h>
44 #include <linux/mtd/nand.h>
45 #include <linux/mtd/nand_ecc.h>
46 #include <linux/mtd/compatmac.h>
47 #include <linux/interrupt.h>
48 #include <linux/bitops.h>
49 #include <linux/leds.h>
52 #ifdef CONFIG_MTD_PARTITIONS
53 #include <linux/mtd/partitions.h>
60 #define ENOTSUPP 524 /* Operation is not supported */
62 #if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
66 #include <linux/err.h>
67 #include <linux/mtd/compat.h>
68 #include <linux/mtd/mtd.h>
69 #include <linux/mtd/nand.h>
70 #include <linux/mtd/nand_ecc.h>
73 #include <asm/errno.h>
75 #ifdef CONFIG_JFFS2_NAND
76 #include <jffs2/jffs2.h>
79 /* Define default oob placement schemes for large and small page devices */
80 static struct nand_ecclayout nand_oob_8 = {
90 static struct nand_ecclayout nand_oob_16 = {
92 .eccpos = {0, 1, 2, 3, 6, 7},
98 static struct nand_ecclayout nand_oob_64 = {
101 40, 41, 42, 43, 44, 45, 46, 47,
102 48, 49, 50, 51, 52, 53, 54, 55,
103 56, 57, 58, 59, 60, 61, 62, 63},
109 static struct nand_ecclayout nand_oob_128 = {
112 80, 81, 82, 83, 84, 85, 86, 87,
113 88, 89, 90, 91, 92, 93, 94, 95,
114 96, 97, 98, 99, 100, 101, 102, 103,
115 104, 105, 106, 107, 108, 109, 110, 111,
116 112, 113, 114, 115, 116, 117, 118, 119,
117 120, 121, 122, 123, 124, 125, 126, 127},
124 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
127 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
128 struct mtd_oob_ops *ops);
130 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
133 * For devices which display every fart in the system on a seperate LED. Is
134 * compiled away when LED support is disabled.
138 DEFINE_LED_TRIGGER(nand_led_trigger);
142 * nand_release_device - [GENERIC] release chip
143 * @mtd: MTD device structure
145 * Deselect, release chip lock and wake up anyone waiting on the device
149 static void nand_release_device(struct mtd_info *mtd)
151 struct nand_chip *chip = mtd->priv;
153 /* De-select the NAND device */
154 chip->select_chip(mtd, -1);
156 /* Release the controller and the chip */
157 spin_lock(&chip->controller->lock);
158 chip->controller->active = NULL;
159 chip->state = FL_READY;
160 wake_up(&chip->controller->wq);
161 spin_unlock(&chip->controller->lock);
164 static void nand_release_device (struct mtd_info *mtd)
166 struct nand_chip *this = mtd->priv;
167 this->select_chip(mtd, -1); /* De-select the NAND device */
172 * nand_read_byte - [DEFAULT] read one byte from the chip
173 * @mtd: MTD device structure
175 * Default read function for 8bit buswith
177 static uint8_t nand_read_byte(struct mtd_info *mtd)
179 struct nand_chip *chip = mtd->priv;
180 return readb(chip->IO_ADDR_R);
184 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
185 * @mtd: MTD device structure
187 * Default read function for 16bit buswith with
188 * endianess conversion
190 static uint8_t nand_read_byte16(struct mtd_info *mtd)
192 struct nand_chip *chip = mtd->priv;
193 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
197 * nand_read_word - [DEFAULT] read one word from the chip
198 * @mtd: MTD device structure
200 * Default read function for 16bit buswith without
201 * endianess conversion
203 static u16 nand_read_word(struct mtd_info *mtd)
205 struct nand_chip *chip = mtd->priv;
206 return readw(chip->IO_ADDR_R);
210 * nand_select_chip - [DEFAULT] control CE line
211 * @mtd: MTD device structure
212 * @chipnr: chipnumber to select, -1 for deselect
214 * Default select function for 1 chip devices.
216 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
218 struct nand_chip *chip = mtd->priv;
222 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
233 * nand_write_buf - [DEFAULT] write buffer to chip
234 * @mtd: MTD device structure
236 * @len: number of bytes to write
238 * Default write function for 8bit buswith
240 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
243 struct nand_chip *chip = mtd->priv;
245 for (i = 0; i < len; i++)
246 writeb(buf[i], chip->IO_ADDR_W);
250 * nand_read_buf - [DEFAULT] read chip data into buffer
251 * @mtd: MTD device structure
252 * @buf: buffer to store date
253 * @len: number of bytes to read
255 * Default read function for 8bit buswith
257 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
260 struct nand_chip *chip = mtd->priv;
262 for (i = 0; i < len; i++)
263 buf[i] = readb(chip->IO_ADDR_R);
267 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
268 * @mtd: MTD device structure
269 * @buf: buffer containing the data to compare
270 * @len: number of bytes to compare
272 * Default verify function for 8bit buswith
274 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
277 struct nand_chip *chip = mtd->priv;
279 for (i = 0; i < len; i++)
280 if (buf[i] != readb(chip->IO_ADDR_R))
286 * nand_write_buf16 - [DEFAULT] write buffer to chip
287 * @mtd: MTD device structure
289 * @len: number of bytes to write
291 * Default write function for 16bit buswith
293 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
296 struct nand_chip *chip = mtd->priv;
297 u16 *p = (u16 *) buf;
300 for (i = 0; i < len; i++)
301 writew(p[i], chip->IO_ADDR_W);
306 * nand_read_buf16 - [DEFAULT] read chip data into buffer
307 * @mtd: MTD device structure
308 * @buf: buffer to store date
309 * @len: number of bytes to read
311 * Default read function for 16bit buswith
313 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
316 struct nand_chip *chip = mtd->priv;
317 u16 *p = (u16 *) buf;
320 for (i = 0; i < len; i++)
321 p[i] = readw(chip->IO_ADDR_R);
325 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
326 * @mtd: MTD device structure
327 * @buf: buffer containing the data to compare
328 * @len: number of bytes to compare
330 * Default verify function for 16bit buswith
332 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
335 struct nand_chip *chip = mtd->priv;
336 u16 *p = (u16 *) buf;
339 for (i = 0; i < len; i++)
340 if (p[i] != readw(chip->IO_ADDR_R))
347 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
348 * @mtd: MTD device structure
349 * @ofs: offset from device start
350 * @getchip: 0, if the chip is already selected
352 * Check, if the block is bad.
354 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
356 int page, chipnr, res = 0;
357 struct nand_chip *chip = mtd->priv;
360 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
363 chipnr = (int)(ofs >> chip->chip_shift);
365 nand_get_device(chip, mtd, FL_READING);
367 /* Select the NAND device */
368 chip->select_chip(mtd, chipnr);
371 if (chip->options & NAND_BUSWIDTH_16) {
372 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
374 bad = cpu_to_le16(chip->read_word(mtd));
375 if (chip->badblockpos & 0x1)
377 if ((bad & 0xFF) != 0xff)
380 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
381 if (chip->read_byte(mtd) != 0xff)
386 nand_release_device(mtd);
392 * nand_default_block_markbad - [DEFAULT] mark a block bad
393 * @mtd: MTD device structure
394 * @ofs: offset from device start
396 * This is the default implementation, which can be overridden by
397 * a hardware specific driver.
399 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
401 struct nand_chip *chip = mtd->priv;
402 uint8_t buf[2] = { 0, 0 };
405 /* Get block number */
406 block = (int)(ofs >> chip->bbt_erase_shift);
408 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
410 /* Do we have a flash based bad block table ? */
411 if (chip->options & NAND_USE_FLASH_BBT)
412 ret = nand_update_bbt(mtd, ofs);
414 /* We write two bytes, so we dont have to mess with 16 bit
418 chip->ops.len = chip->ops.ooblen = 2;
419 chip->ops.datbuf = NULL;
420 chip->ops.oobbuf = buf;
421 chip->ops.ooboffs = chip->badblockpos & ~0x01;
423 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
426 mtd->ecc_stats.badblocks++;
431 * nand_check_wp - [GENERIC] check if the chip is write protected
432 * @mtd: MTD device structure
433 * Check, if the device is write protected
435 * The function expects, that the device is already selected
437 static int nand_check_wp(struct mtd_info *mtd)
439 struct nand_chip *chip = mtd->priv;
440 /* Check the WP bit */
441 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
442 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
446 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
447 * @mtd: MTD device structure
448 * @ofs: offset from device start
449 * @getchip: 0, if the chip is already selected
450 * @allowbbt: 1, if its allowed to access the bbt area
452 * Check, if the block is bad. Either by reading the bad block table or
453 * calling of the scan function.
455 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
458 struct nand_chip *chip = mtd->priv;
460 if (!(chip->options & NAND_BBT_SCANNED)) {
462 chip->options |= NAND_BBT_SCANNED;
466 return chip->block_bad(mtd, ofs, getchip);
468 /* Return info from the table */
469 return nand_isbad_bbt(mtd, ofs, allowbbt);
473 * Wait for the ready pin, after a command
474 * The timeout is catched later.
478 void nand_wait_ready(struct mtd_info *mtd)
480 struct nand_chip *chip = mtd->priv;
481 unsigned long timeo = jiffies + 2;
483 led_trigger_event(nand_led_trigger, LED_FULL);
484 /* wait until command is processed or timeout occures */
486 if (chip->dev_ready(mtd))
488 touch_softlockup_watchdog();
489 } while (time_before(jiffies, timeo));
490 led_trigger_event(nand_led_trigger, LED_OFF);
492 EXPORT_SYMBOL_GPL(nand_wait_ready);
494 void nand_wait_ready(struct mtd_info *mtd)
496 struct nand_chip *chip = mtd->priv;
497 u32 timeo = (CFG_HZ * 20) / 1000;
501 /* wait until command is processed or timeout occures */
502 while (get_timer(0) < timeo) {
504 if (chip->dev_ready(mtd))
511 * nand_command - [DEFAULT] Send command to NAND device
512 * @mtd: MTD device structure
513 * @command: the command to be sent
514 * @column: the column address for this command, -1 if none
515 * @page_addr: the page address for this command, -1 if none
517 * Send command to NAND device. This function is used for small page
518 * devices (256/512 Bytes per page)
520 static void nand_command(struct mtd_info *mtd, unsigned int command,
521 int column, int page_addr)
523 register struct nand_chip *chip = mtd->priv;
524 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
527 * Write out the command to the device.
529 if (command == NAND_CMD_SEQIN) {
532 if (column >= mtd->writesize) {
534 column -= mtd->writesize;
535 readcmd = NAND_CMD_READOOB;
536 } else if (column < 256) {
537 /* First 256 bytes --> READ0 */
538 readcmd = NAND_CMD_READ0;
541 readcmd = NAND_CMD_READ1;
543 chip->cmd_ctrl(mtd, readcmd, ctrl);
544 ctrl &= ~NAND_CTRL_CHANGE;
546 chip->cmd_ctrl(mtd, command, ctrl);
549 * Address cycle, when necessary
551 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
552 /* Serially input address */
554 /* Adjust columns for 16 bit buswidth */
555 if (chip->options & NAND_BUSWIDTH_16)
557 chip->cmd_ctrl(mtd, column, ctrl);
558 ctrl &= ~NAND_CTRL_CHANGE;
560 if (page_addr != -1) {
561 chip->cmd_ctrl(mtd, page_addr, ctrl);
562 ctrl &= ~NAND_CTRL_CHANGE;
563 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
564 /* One more address cycle for devices > 32MiB */
565 if (chip->chipsize > (32 << 20))
566 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
568 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
571 * program and erase have their own busy handlers
572 * status and sequential in needs no delay
576 case NAND_CMD_PAGEPROG:
577 case NAND_CMD_ERASE1:
578 case NAND_CMD_ERASE2:
580 case NAND_CMD_STATUS:
586 udelay(chip->chip_delay);
587 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
588 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
590 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
591 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
594 /* This applies to read commands */
597 * If we don't have access to the busy pin, we apply the given
600 if (!chip->dev_ready) {
601 udelay(chip->chip_delay);
605 /* Apply this short delay always to ensure that we do wait tWB in
606 * any case on any machine. */
609 nand_wait_ready(mtd);
613 * nand_command_lp - [DEFAULT] Send command to NAND large page device
614 * @mtd: MTD device structure
615 * @command: the command to be sent
616 * @column: the column address for this command, -1 if none
617 * @page_addr: the page address for this command, -1 if none
619 * Send command to NAND device. This is the version for the new large page
620 * devices We dont have the separate regions as we have in the small page
621 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
623 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
624 int column, int page_addr)
626 register struct nand_chip *chip = mtd->priv;
628 /* Emulate NAND_CMD_READOOB */
629 if (command == NAND_CMD_READOOB) {
630 column += mtd->writesize;
631 command = NAND_CMD_READ0;
634 /* Command latch cycle */
635 chip->cmd_ctrl(mtd, command & 0xff,
636 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
638 if (column != -1 || page_addr != -1) {
639 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
641 /* Serially input address */
643 /* Adjust columns for 16 bit buswidth */
644 if (chip->options & NAND_BUSWIDTH_16)
646 chip->cmd_ctrl(mtd, column, ctrl);
647 ctrl &= ~NAND_CTRL_CHANGE;
648 chip->cmd_ctrl(mtd, column >> 8, ctrl);
650 if (page_addr != -1) {
651 chip->cmd_ctrl(mtd, page_addr, ctrl);
652 chip->cmd_ctrl(mtd, page_addr >> 8,
653 NAND_NCE | NAND_ALE);
654 /* One more address cycle for devices > 128MiB */
655 if (chip->chipsize > (128 << 20))
656 chip->cmd_ctrl(mtd, page_addr >> 16,
657 NAND_NCE | NAND_ALE);
660 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
663 * program and erase have their own busy handlers
664 * status, sequential in, and deplete1 need no delay
668 case NAND_CMD_CACHEDPROG:
669 case NAND_CMD_PAGEPROG:
670 case NAND_CMD_ERASE1:
671 case NAND_CMD_ERASE2:
674 case NAND_CMD_STATUS:
675 case NAND_CMD_DEPLETE1:
679 * read error status commands require only a short delay
681 case NAND_CMD_STATUS_ERROR:
682 case NAND_CMD_STATUS_ERROR0:
683 case NAND_CMD_STATUS_ERROR1:
684 case NAND_CMD_STATUS_ERROR2:
685 case NAND_CMD_STATUS_ERROR3:
686 udelay(chip->chip_delay);
692 udelay(chip->chip_delay);
693 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
694 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
695 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
696 NAND_NCE | NAND_CTRL_CHANGE);
697 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
700 case NAND_CMD_RNDOUT:
701 /* No ready / busy check necessary */
702 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
703 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
704 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
705 NAND_NCE | NAND_CTRL_CHANGE);
709 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
710 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
711 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
712 NAND_NCE | NAND_CTRL_CHANGE);
714 /* This applies to read commands */
717 * If we don't have access to the busy pin, we apply the given
720 if (!chip->dev_ready) {
721 udelay(chip->chip_delay);
726 /* Apply this short delay always to ensure that we do wait tWB in
727 * any case on any machine. */
730 nand_wait_ready(mtd);
734 * nand_get_device - [GENERIC] Get chip for selected access
735 * @chip: the nand chip descriptor
736 * @mtd: MTD device structure
737 * @new_state: the state which is requested
739 * Get the device and lock it for exclusive access
744 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
746 spinlock_t *lock = &chip->controller->lock;
747 wait_queue_head_t *wq = &chip->controller->wq;
748 DECLARE_WAITQUEUE(wait, current);
752 /* Hardware controller shared among independend devices */
753 /* Hardware controller shared among independend devices */
754 if (!chip->controller->active)
755 chip->controller->active = chip;
757 if (chip->controller->active == chip && chip->state == FL_READY) {
758 chip->state = new_state;
762 if (new_state == FL_PM_SUSPENDED) {
764 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
766 set_current_state(TASK_UNINTERRUPTIBLE);
767 add_wait_queue(wq, &wait);
770 remove_wait_queue(wq, &wait);
774 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
781 * nand_wait - [DEFAULT] wait until the command is done
782 * @mtd: MTD device structure
783 * @chip: NAND chip structure
785 * Wait for command done. This applies to erase and program only
786 * Erase can take up to 400ms and program up to 20ms according to
787 * general NAND and SmartMedia specs
791 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
794 unsigned long timeo = jiffies;
795 int status, state = chip->state;
797 if (state == FL_ERASING)
798 timeo += (HZ * 400) / 1000;
800 timeo += (HZ * 20) / 1000;
802 led_trigger_event(nand_led_trigger, LED_FULL);
804 /* Apply this short delay always to ensure that we do wait tWB in
805 * any case on any machine. */
808 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
809 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
811 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
813 while (time_before(jiffies, timeo)) {
814 if (chip->dev_ready) {
815 if (chip->dev_ready(mtd))
818 if (chip->read_byte(mtd) & NAND_STATUS_READY)
823 led_trigger_event(nand_led_trigger, LED_OFF);
825 status = (int)chip->read_byte(mtd);
829 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
832 int state = this->state;
834 if (state == FL_ERASING)
835 timeo = (CFG_HZ * 400) / 1000;
837 timeo = (CFG_HZ * 20) / 1000;
839 if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
840 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
842 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
847 if (get_timer(0) > timeo) {
852 if (this->dev_ready) {
853 if (this->dev_ready(mtd))
856 if (this->read_byte(mtd) & NAND_STATUS_READY)
860 #ifdef PPCHAMELON_NAND_TIMER_HACK
862 while (get_timer(0) < 10);
863 #endif /* PPCHAMELON_NAND_TIMER_HACK */
865 return this->read_byte(mtd);
870 * nand_read_page_raw - [Intern] read raw page data without ecc
871 * @mtd: mtd info structure
872 * @chip: nand chip info structure
873 * @buf: buffer to store read data
875 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
878 chip->read_buf(mtd, buf, mtd->writesize);
879 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
884 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
885 * @mtd: mtd info structure
886 * @chip: nand chip info structure
887 * @buf: buffer to store read data
889 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
892 int i, eccsize = chip->ecc.size;
893 int eccbytes = chip->ecc.bytes;
894 int eccsteps = chip->ecc.steps;
896 uint8_t *ecc_calc = chip->buffers->ecccalc;
897 uint8_t *ecc_code = chip->buffers->ecccode;
898 uint32_t *eccpos = chip->ecc.layout->eccpos;
900 chip->ecc.read_page_raw(mtd, chip, buf);
902 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
903 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
905 for (i = 0; i < chip->ecc.total; i++)
906 ecc_code[i] = chip->oob_poi[eccpos[i]];
908 eccsteps = chip->ecc.steps;
911 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
914 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
916 mtd->ecc_stats.failed++;
918 mtd->ecc_stats.corrected += stat;
924 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
925 * @mtd: mtd info structure
926 * @chip: nand chip info structure
927 * @buf: buffer to store read data
929 * Not for syndrome calculating ecc controllers which need a special oob layout
931 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
934 int i, eccsize = chip->ecc.size;
935 int eccbytes = chip->ecc.bytes;
936 int eccsteps = chip->ecc.steps;
938 uint8_t *ecc_calc = chip->buffers->ecccalc;
939 uint8_t *ecc_code = chip->buffers->ecccode;
940 uint32_t *eccpos = chip->ecc.layout->eccpos;
942 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
943 chip->ecc.hwctl(mtd, NAND_ECC_READ);
944 chip->read_buf(mtd, p, eccsize);
945 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
947 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
949 for (i = 0; i < chip->ecc.total; i++)
950 ecc_code[i] = chip->oob_poi[eccpos[i]];
952 eccsteps = chip->ecc.steps;
955 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
958 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
960 mtd->ecc_stats.failed++;
962 mtd->ecc_stats.corrected += stat;
968 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
969 * @mtd: mtd info structure
970 * @chip: nand chip info structure
971 * @buf: buffer to store read data
973 * The hw generator calculates the error syndrome automatically. Therefor
974 * we need a special oob layout and handling.
976 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
979 int i, eccsize = chip->ecc.size;
980 int eccbytes = chip->ecc.bytes;
981 int eccsteps = chip->ecc.steps;
983 uint8_t *oob = chip->oob_poi;
985 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
988 chip->ecc.hwctl(mtd, NAND_ECC_READ);
989 chip->read_buf(mtd, p, eccsize);
991 if (chip->ecc.prepad) {
992 chip->read_buf(mtd, oob, chip->ecc.prepad);
993 oob += chip->ecc.prepad;
996 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
997 chip->read_buf(mtd, oob, eccbytes);
998 stat = chip->ecc.correct(mtd, p, oob, NULL);
1001 mtd->ecc_stats.failed++;
1003 mtd->ecc_stats.corrected += stat;
1007 if (chip->ecc.postpad) {
1008 chip->read_buf(mtd, oob, chip->ecc.postpad);
1009 oob += chip->ecc.postpad;
1013 /* Calculate remaining oob bytes */
1014 i = mtd->oobsize - (oob - chip->oob_poi);
1016 chip->read_buf(mtd, oob, i);
1022 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1023 * @chip: nand chip structure
1024 * @oob: oob destination address
1025 * @ops: oob ops structure
1026 * @len: size of oob to transfer
1028 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1029 struct mtd_oob_ops *ops, size_t len)
1035 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1038 case MTD_OOB_AUTO: {
1039 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1040 uint32_t boffs = 0, roffs = ops->ooboffs;
1043 for(; free->length && len; free++, len -= bytes) {
1044 /* Read request not from offset 0 ? */
1045 if (unlikely(roffs)) {
1046 if (roffs >= free->length) {
1047 roffs -= free->length;
1050 boffs = free->offset + roffs;
1051 bytes = min_t(size_t, len,
1052 (free->length - roffs));
1055 bytes = min_t(size_t, len, free->length);
1056 boffs = free->offset;
1058 memcpy(oob, chip->oob_poi + boffs, bytes);
1070 * nand_do_read_ops - [Internal] Read data with ECC
1072 * @mtd: MTD device structure
1073 * @from: offset to read from
1074 * @ops: oob ops structure
1076 * Internal function. Called with chip held.
1078 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1079 struct mtd_oob_ops *ops)
1081 int chipnr, page, realpage, col, bytes, aligned;
1082 struct nand_chip *chip = mtd->priv;
1083 struct mtd_ecc_stats stats;
1084 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1087 uint32_t readlen = ops->len;
1088 uint32_t oobreadlen = ops->ooblen;
1089 uint8_t *bufpoi, *oob, *buf;
1091 stats = mtd->ecc_stats;
1093 chipnr = (int)(from >> chip->chip_shift);
1094 chip->select_chip(mtd, chipnr);
1096 realpage = (int)(from >> chip->page_shift);
1097 page = realpage & chip->pagemask;
1099 col = (int)(from & (mtd->writesize - 1));
1105 bytes = min(mtd->writesize - col, readlen);
1106 aligned = (bytes == mtd->writesize);
1108 /* Is the current page in the buffer ? */
1109 if (realpage != chip->pagebuf || oob) {
1110 bufpoi = aligned ? buf : chip->buffers->databuf;
1112 if (likely(sndcmd)) {
1113 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1117 /* Now read the page into the buffer */
1118 if (unlikely(ops->mode == MTD_OOB_RAW))
1119 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi);
1121 ret = chip->ecc.read_page(mtd, chip, bufpoi);
1125 /* Transfer not aligned data */
1127 chip->pagebuf = realpage;
1128 memcpy(buf, chip->buffers->databuf + col, bytes);
1133 if (unlikely(oob)) {
1134 /* Raw mode does data:oob:data:oob */
1135 if (ops->mode != MTD_OOB_RAW) {
1136 int toread = min(oobreadlen,
1137 chip->ecc.layout->oobavail);
1139 oob = nand_transfer_oob(chip,
1141 oobreadlen -= toread;
1144 buf = nand_transfer_oob(chip,
1145 buf, ops, mtd->oobsize);
1148 if (!(chip->options & NAND_NO_READRDY)) {
1150 * Apply delay or wait for ready/busy pin. Do
1151 * this before the AUTOINCR check, so no
1152 * problems arise if a chip which does auto
1153 * increment is marked as NOAUTOINCR by the
1156 if (!chip->dev_ready)
1157 udelay(chip->chip_delay);
1159 nand_wait_ready(mtd);
1162 memcpy(buf, chip->buffers->databuf + col, bytes);
1171 /* For subsequent reads align to page boundary. */
1173 /* Increment page address */
1176 page = realpage & chip->pagemask;
1177 /* Check, if we cross a chip boundary */
1180 chip->select_chip(mtd, -1);
1181 chip->select_chip(mtd, chipnr);
1184 /* Check, if the chip supports auto page increment
1185 * or if we have hit a block boundary.
1187 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1191 ops->retlen = ops->len - (size_t) readlen;
1193 ops->oobretlen = ops->ooblen - oobreadlen;
1198 if (mtd->ecc_stats.failed - stats.failed)
1201 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1205 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1206 * @mtd: MTD device structure
1207 * @from: offset to read from
1208 * @len: number of bytes to read
1209 * @retlen: pointer to variable to store the number of read bytes
1210 * @buf: the databuffer to put data
1212 * Get hold of the chip and call nand_do_read
1214 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1215 size_t *retlen, uint8_t *buf)
1217 struct nand_chip *chip = mtd->priv;
1220 /* Do not allow reads past end of device */
1221 if ((from + len) > mtd->size)
1226 nand_get_device(chip, mtd, FL_READING);
1228 chip->ops.len = len;
1229 chip->ops.datbuf = buf;
1230 chip->ops.oobbuf = NULL;
1232 ret = nand_do_read_ops(mtd, from, &chip->ops);
1234 *retlen = chip->ops.retlen;
1236 nand_release_device(mtd);
1242 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1243 * @mtd: mtd info structure
1244 * @chip: nand chip info structure
1245 * @page: page number to read
1246 * @sndcmd: flag whether to issue read command or not
1248 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1249 int page, int sndcmd)
1252 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1255 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1260 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1262 * @mtd: mtd info structure
1263 * @chip: nand chip info structure
1264 * @page: page number to read
1265 * @sndcmd: flag whether to issue read command or not
1267 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1268 int page, int sndcmd)
1270 uint8_t *buf = chip->oob_poi;
1271 int length = mtd->oobsize;
1272 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1273 int eccsize = chip->ecc.size;
1274 uint8_t *bufpoi = buf;
1275 int i, toread, sndrnd = 0, pos;
1277 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1278 for (i = 0; i < chip->ecc.steps; i++) {
1280 pos = eccsize + i * (eccsize + chunk);
1281 if (mtd->writesize > 512)
1282 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1284 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1287 toread = min_t(int, length, chunk);
1288 chip->read_buf(mtd, bufpoi, toread);
1293 chip->read_buf(mtd, bufpoi, length);
1299 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1300 * @mtd: mtd info structure
1301 * @chip: nand chip info structure
1302 * @page: page number to write
1304 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1308 const uint8_t *buf = chip->oob_poi;
1309 int length = mtd->oobsize;
1311 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1312 chip->write_buf(mtd, buf, length);
1313 /* Send command to program the OOB data */
1314 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1316 status = chip->waitfunc(mtd, chip);
1318 return status & NAND_STATUS_FAIL ? -EIO : 0;
1322 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1323 * with syndrome - only for large page flash !
1324 * @mtd: mtd info structure
1325 * @chip: nand chip info structure
1326 * @page: page number to write
1328 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1329 struct nand_chip *chip, int page)
1331 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1332 int eccsize = chip->ecc.size, length = mtd->oobsize;
1333 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1334 const uint8_t *bufpoi = chip->oob_poi;
1337 * data-ecc-data-ecc ... ecc-oob
1339 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1341 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1342 pos = steps * (eccsize + chunk);
1347 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1348 for (i = 0; i < steps; i++) {
1350 if (mtd->writesize <= 512) {
1351 uint32_t fill = 0xFFFFFFFF;
1355 int num = min_t(int, len, 4);
1356 chip->write_buf(mtd, (uint8_t *)&fill,
1361 pos = eccsize + i * (eccsize + chunk);
1362 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1366 len = min_t(int, length, chunk);
1367 chip->write_buf(mtd, bufpoi, len);
1372 chip->write_buf(mtd, bufpoi, length);
1374 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1375 status = chip->waitfunc(mtd, chip);
1377 return status & NAND_STATUS_FAIL ? -EIO : 0;
1381 * nand_do_read_oob - [Intern] NAND read out-of-band
1382 * @mtd: MTD device structure
1383 * @from: offset to read from
1384 * @ops: oob operations description structure
1386 * NAND read out-of-band data from the spare area
1388 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1389 struct mtd_oob_ops *ops)
1391 int page, realpage, chipnr, sndcmd = 1;
1392 struct nand_chip *chip = mtd->priv;
1393 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1394 int readlen = ops->ooblen;
1396 uint8_t *buf = ops->oobbuf;
1398 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1399 (unsigned long long)from, readlen);
1401 if (ops->mode == MTD_OOB_AUTO)
1402 len = chip->ecc.layout->oobavail;
1406 if (unlikely(ops->ooboffs >= len)) {
1407 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1408 "Attempt to start read outside oob\n");
1412 /* Do not allow reads past end of device */
1413 if (unlikely(from >= mtd->size ||
1414 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1415 (from >> chip->page_shift)) * len)) {
1416 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1417 "Attempt read beyond end of device\n");
1421 chipnr = (int)(from >> chip->chip_shift);
1422 chip->select_chip(mtd, chipnr);
1424 /* Shift to get page */
1425 realpage = (int)(from >> chip->page_shift);
1426 page = realpage & chip->pagemask;
1429 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1431 len = min(len, readlen);
1432 buf = nand_transfer_oob(chip, buf, ops, len);
1434 if (!(chip->options & NAND_NO_READRDY)) {
1436 * Apply delay or wait for ready/busy pin. Do this
1437 * before the AUTOINCR check, so no problems arise if a
1438 * chip which does auto increment is marked as
1439 * NOAUTOINCR by the board driver.
1441 if (!chip->dev_ready)
1442 udelay(chip->chip_delay);
1444 nand_wait_ready(mtd);
1451 /* Increment page address */
1454 page = realpage & chip->pagemask;
1455 /* Check, if we cross a chip boundary */
1458 chip->select_chip(mtd, -1);
1459 chip->select_chip(mtd, chipnr);
1462 /* Check, if the chip supports auto page increment
1463 * or if we have hit a block boundary.
1465 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1469 ops->oobretlen = ops->ooblen;
1474 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1475 * @mtd: MTD device structure
1476 * @from: offset to read from
1477 * @ops: oob operation description structure
1479 * NAND read data and/or out-of-band data
1481 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1482 struct mtd_oob_ops *ops)
1484 struct nand_chip *chip = mtd->priv;
1485 int ret = -ENOTSUPP;
1489 /* Do not allow reads past end of device */
1490 if (ops->datbuf && (from + ops->len) > mtd->size) {
1491 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1492 "Attempt read beyond end of device\n");
1496 nand_get_device(chip, mtd, FL_READING);
1509 ret = nand_do_read_oob(mtd, from, ops);
1511 ret = nand_do_read_ops(mtd, from, ops);
1514 nand_release_device(mtd);
1520 * nand_write_page_raw - [Intern] raw page write function
1521 * @mtd: mtd info structure
1522 * @chip: nand chip info structure
1525 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1528 chip->write_buf(mtd, buf, mtd->writesize);
1529 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1533 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1534 * @mtd: mtd info structure
1535 * @chip: nand chip info structure
1538 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1541 int i, eccsize = chip->ecc.size;
1542 int eccbytes = chip->ecc.bytes;
1543 int eccsteps = chip->ecc.steps;
1544 uint8_t *ecc_calc = chip->buffers->ecccalc;
1545 const uint8_t *p = buf;
1546 uint32_t *eccpos = chip->ecc.layout->eccpos;
1548 /* Software ecc calculation */
1549 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1550 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1552 for (i = 0; i < chip->ecc.total; i++)
1553 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1555 chip->ecc.write_page_raw(mtd, chip, buf);
1559 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1560 * @mtd: mtd info structure
1561 * @chip: nand chip info structure
1564 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1567 int i, eccsize = chip->ecc.size;
1568 int eccbytes = chip->ecc.bytes;
1569 int eccsteps = chip->ecc.steps;
1570 uint8_t *ecc_calc = chip->buffers->ecccalc;
1571 const uint8_t *p = buf;
1572 uint32_t *eccpos = chip->ecc.layout->eccpos;
1574 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1575 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1576 chip->write_buf(mtd, p, eccsize);
1577 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1580 for (i = 0; i < chip->ecc.total; i++)
1581 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1583 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1587 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1588 * @mtd: mtd info structure
1589 * @chip: nand chip info structure
1592 * The hw generator calculates the error syndrome automatically. Therefor
1593 * we need a special oob layout and handling.
1595 static void nand_write_page_syndrome(struct mtd_info *mtd,
1596 struct nand_chip *chip, const uint8_t *buf)
1598 int i, eccsize = chip->ecc.size;
1599 int eccbytes = chip->ecc.bytes;
1600 int eccsteps = chip->ecc.steps;
1601 const uint8_t *p = buf;
1602 uint8_t *oob = chip->oob_poi;
1604 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1606 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1607 chip->write_buf(mtd, p, eccsize);
1609 if (chip->ecc.prepad) {
1610 chip->write_buf(mtd, oob, chip->ecc.prepad);
1611 oob += chip->ecc.prepad;
1614 chip->ecc.calculate(mtd, p, oob);
1615 chip->write_buf(mtd, oob, eccbytes);
1618 if (chip->ecc.postpad) {
1619 chip->write_buf(mtd, oob, chip->ecc.postpad);
1620 oob += chip->ecc.postpad;
1624 /* Calculate remaining oob bytes */
1625 i = mtd->oobsize - (oob - chip->oob_poi);
1627 chip->write_buf(mtd, oob, i);
1631 * nand_write_page - [REPLACEABLE] write one page
1632 * @mtd: MTD device structure
1633 * @chip: NAND chip descriptor
1634 * @buf: the data to write
1635 * @page: page number to write
1636 * @cached: cached programming
1637 * @raw: use _raw version of write_page
1639 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1640 const uint8_t *buf, int page, int cached, int raw)
1644 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1647 chip->ecc.write_page_raw(mtd, chip, buf);
1649 chip->ecc.write_page(mtd, chip, buf);
1652 * Cached progamming disabled for now, Not sure if its worth the
1653 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1657 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1659 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1660 status = chip->waitfunc(mtd, chip);
1662 * See if operation failed and additional status checks are
1665 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1666 status = chip->errstat(mtd, chip, FL_WRITING, status,
1669 if (status & NAND_STATUS_FAIL)
1672 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1673 status = chip->waitfunc(mtd, chip);
1676 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1677 /* Send command to read back the data */
1678 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1680 if (chip->verify_buf(mtd, buf, mtd->writesize))
1687 * nand_fill_oob - [Internal] Transfer client buffer to oob
1688 * @chip: nand chip structure
1689 * @oob: oob data buffer
1690 * @ops: oob ops structure
1692 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1693 struct mtd_oob_ops *ops)
1695 size_t len = ops->ooblen;
1701 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1704 case MTD_OOB_AUTO: {
1705 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1706 uint32_t boffs = 0, woffs = ops->ooboffs;
1709 for(; free->length && len; free++, len -= bytes) {
1710 /* Write request not from offset 0 ? */
1711 if (unlikely(woffs)) {
1712 if (woffs >= free->length) {
1713 woffs -= free->length;
1716 boffs = free->offset + woffs;
1717 bytes = min_t(size_t, len,
1718 (free->length - woffs));
1721 bytes = min_t(size_t, len, free->length);
1722 boffs = free->offset;
1724 memcpy(chip->oob_poi + boffs, oob, bytes);
1735 #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
1738 * nand_do_write_ops - [Internal] NAND write with ECC
1739 * @mtd: MTD device structure
1740 * @to: offset to write to
1741 * @ops: oob operations description structure
1743 * NAND write with ECC
1745 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1746 struct mtd_oob_ops *ops)
1748 int chipnr, realpage, page, blockmask, column;
1749 struct nand_chip *chip = mtd->priv;
1750 uint32_t writelen = ops->len;
1751 uint8_t *oob = ops->oobbuf;
1752 uint8_t *buf = ops->datbuf;
1759 /* reject writes, which are not page aligned */
1760 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1761 printk(KERN_NOTICE "nand_write: "
1762 "Attempt to write not page aligned data\n");
1766 column = to & (mtd->writesize - 1);
1767 subpage = column || (writelen & (mtd->writesize - 1));
1772 chipnr = (int)(to >> chip->chip_shift);
1773 chip->select_chip(mtd, chipnr);
1775 /* Check, if it is write protected */
1776 if (nand_check_wp(mtd)) {
1777 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1781 realpage = (int)(to >> chip->page_shift);
1782 page = realpage & chip->pagemask;
1783 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1785 /* Invalidate the page cache, when we write to the cached page */
1786 if (to <= (chip->pagebuf << chip->page_shift) &&
1787 (chip->pagebuf << chip->page_shift) < (to + ops->len))
1790 /* If we're not given explicit OOB data, let it be 0xFF */
1792 memset(chip->oob_poi, 0xff, mtd->oobsize);
1795 int bytes = mtd->writesize;
1796 int cached = writelen > bytes && page != blockmask;
1797 uint8_t *wbuf = buf;
1799 /* Partial page write ? */
1800 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1802 bytes = min_t(int, bytes - column, (int) writelen);
1804 memset(chip->buffers->databuf, 0xff, mtd->writesize);
1805 memcpy(&chip->buffers->databuf[column], buf, bytes);
1806 wbuf = chip->buffers->databuf;
1810 oob = nand_fill_oob(chip, oob, ops);
1812 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1813 (ops->mode == MTD_OOB_RAW));
1825 page = realpage & chip->pagemask;
1826 /* Check, if we cross a chip boundary */
1829 chip->select_chip(mtd, -1);
1830 chip->select_chip(mtd, chipnr);
1834 ops->retlen = ops->len - writelen;
1836 ops->oobretlen = ops->ooblen;
1841 * nand_write - [MTD Interface] NAND write with ECC
1842 * @mtd: MTD device structure
1843 * @to: offset to write to
1844 * @len: number of bytes to write
1845 * @retlen: pointer to variable to store the number of written bytes
1846 * @buf: the data to write
1848 * NAND write with ECC
1850 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1851 size_t *retlen, const uint8_t *buf)
1853 struct nand_chip *chip = mtd->priv;
1856 /* Do not allow reads past end of device */
1857 if ((to + len) > mtd->size)
1862 nand_get_device(chip, mtd, FL_WRITING);
1864 chip->ops.len = len;
1865 chip->ops.datbuf = (uint8_t *)buf;
1866 chip->ops.oobbuf = NULL;
1868 ret = nand_do_write_ops(mtd, to, &chip->ops);
1870 *retlen = chip->ops.retlen;
1872 nand_release_device(mtd);
1878 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1879 * @mtd: MTD device structure
1880 * @to: offset to write to
1881 * @ops: oob operation description structure
1883 * NAND write out-of-band
1885 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1886 struct mtd_oob_ops *ops)
1888 int chipnr, page, status, len;
1889 struct nand_chip *chip = mtd->priv;
1891 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1892 (unsigned int)to, (int)ops->ooblen);
1894 if (ops->mode == MTD_OOB_AUTO)
1895 len = chip->ecc.layout->oobavail;
1899 /* Do not allow write past end of page */
1900 if ((ops->ooboffs + ops->ooblen) > len) {
1901 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
1902 "Attempt to write past end of page\n");
1906 if (unlikely(ops->ooboffs >= len)) {
1907 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1908 "Attempt to start write outside oob\n");
1912 /* Do not allow reads past end of device */
1913 if (unlikely(to >= mtd->size ||
1914 ops->ooboffs + ops->ooblen >
1915 ((mtd->size >> chip->page_shift) -
1916 (to >> chip->page_shift)) * len)) {
1917 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1918 "Attempt write beyond end of device\n");
1922 chipnr = (int)(to >> chip->chip_shift);
1923 chip->select_chip(mtd, chipnr);
1925 /* Shift to get page */
1926 page = (int)(to >> chip->page_shift);
1929 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
1930 * of my DiskOnChip 2000 test units) will clear the whole data page too
1931 * if we don't do this. I have no clue why, but I seem to have 'fixed'
1932 * it in the doc2000 driver in August 1999. dwmw2.
1934 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1936 /* Check, if it is write protected */
1937 if (nand_check_wp(mtd))
1940 /* Invalidate the page cache, if we write to the cached page */
1941 if (page == chip->pagebuf)
1944 memset(chip->oob_poi, 0xff, mtd->oobsize);
1945 nand_fill_oob(chip, ops->oobbuf, ops);
1946 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1947 memset(chip->oob_poi, 0xff, mtd->oobsize);
1952 ops->oobretlen = ops->ooblen;
1958 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
1959 * @mtd: MTD device structure
1960 * @to: offset to write to
1961 * @ops: oob operation description structure
1963 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
1964 struct mtd_oob_ops *ops)
1966 struct nand_chip *chip = mtd->priv;
1967 int ret = -ENOTSUPP;
1971 /* Do not allow writes past end of device */
1972 if (ops->datbuf && (to + ops->len) > mtd->size) {
1973 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1974 "Attempt read beyond end of device\n");
1978 nand_get_device(chip, mtd, FL_WRITING);
1991 ret = nand_do_write_oob(mtd, to, ops);
1993 ret = nand_do_write_ops(mtd, to, ops);
1996 nand_release_device(mtd);
2001 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2002 * @mtd: MTD device structure
2003 * @page: the page address of the block which will be erased
2005 * Standard erase command for NAND chips
2007 static void single_erase_cmd(struct mtd_info *mtd, int page)
2009 struct nand_chip *chip = mtd->priv;
2010 /* Send commands to erase a block */
2011 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2012 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2016 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2017 * @mtd: MTD device structure
2018 * @page: the page address of the block which will be erased
2020 * AND multi block erase command function
2021 * Erase 4 consecutive blocks
2023 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2025 struct nand_chip *chip = mtd->priv;
2026 /* Send commands to erase a block */
2027 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2028 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2029 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2030 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2031 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2035 * nand_erase - [MTD Interface] erase block(s)
2036 * @mtd: MTD device structure
2037 * @instr: erase instruction
2039 * Erase one ore more blocks
2041 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2043 return nand_erase_nand(mtd, instr, 0);
2046 #define BBT_PAGE_MASK 0xffffff3f
2048 * nand_erase_nand - [Internal] erase block(s)
2049 * @mtd: MTD device structure
2050 * @instr: erase instruction
2051 * @allowbbt: allow erasing the bbt area
2053 * Erase one ore more blocks
2055 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2058 int page, len, status, pages_per_block, ret, chipnr;
2059 struct nand_chip *chip = mtd->priv;
2060 int rewrite_bbt[NAND_MAX_CHIPS]={0};
2061 unsigned int bbt_masked_page = 0xffffffff;
2063 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
2064 (unsigned int) instr->addr, (unsigned int) instr->len);
2066 /* Start address must align on block boundary */
2067 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2068 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2072 /* Length must align on block boundary */
2073 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2074 MTDDEBUG (MTD_DEBUG_LEVEL0,
2075 "nand_erase: Length not block aligned\n");
2079 /* Do not allow erase past end of device */
2080 if ((instr->len + instr->addr) > mtd->size) {
2081 MTDDEBUG (MTD_DEBUG_LEVEL0,
2082 "nand_erase: Erase past end of device\n");
2086 instr->fail_addr = 0xffffffff;
2088 /* Grab the lock and see if the device is available */
2089 nand_get_device(chip, mtd, FL_ERASING);
2091 /* Shift to get first page */
2092 page = (int)(instr->addr >> chip->page_shift);
2093 chipnr = (int)(instr->addr >> chip->chip_shift);
2095 /* Calculate pages in each block */
2096 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2098 /* Select the NAND device */
2099 chip->select_chip(mtd, chipnr);
2101 /* Check, if it is write protected */
2102 if (nand_check_wp(mtd)) {
2103 MTDDEBUG (MTD_DEBUG_LEVEL0,
2104 "nand_erase: Device is write protected!!!\n");
2105 instr->state = MTD_ERASE_FAILED;
2110 * If BBT requires refresh, set the BBT page mask to see if the BBT
2111 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2112 * can not be matched. This is also done when the bbt is actually
2113 * erased to avoid recusrsive updates
2115 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2116 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2118 /* Loop through the pages */
2121 instr->state = MTD_ERASING;
2125 * heck if we have a bad block, we do not erase bad blocks !
2127 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2128 chip->page_shift, 0, allowbbt)) {
2129 printk(KERN_WARNING "nand_erase: attempt to erase a "
2130 "bad block at page 0x%08x\n", page);
2131 instr->state = MTD_ERASE_FAILED;
2136 * Invalidate the page cache, if we erase the block which
2137 * contains the current cached page
2139 if (page <= chip->pagebuf && chip->pagebuf <
2140 (page + pages_per_block))
2143 chip->erase_cmd(mtd, page & chip->pagemask);
2145 status = chip->waitfunc(mtd, chip);
2148 * See if operation failed and additional status checks are
2151 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2152 status = chip->errstat(mtd, chip, FL_ERASING,
2155 /* See if block erase succeeded */
2156 if (status & NAND_STATUS_FAIL) {
2157 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
2158 "Failed erase, page 0x%08x\n", page);
2159 instr->state = MTD_ERASE_FAILED;
2160 instr->fail_addr = (page << chip->page_shift);
2165 * If BBT requires refresh, set the BBT rewrite flag to the
2168 if (bbt_masked_page != 0xffffffff &&
2169 (page & BBT_PAGE_MASK) == bbt_masked_page)
2170 rewrite_bbt[chipnr] = (page << chip->page_shift);
2172 /* Increment page address and decrement length */
2173 len -= (1 << chip->phys_erase_shift);
2174 page += pages_per_block;
2176 /* Check, if we cross a chip boundary */
2177 if (len && !(page & chip->pagemask)) {
2179 chip->select_chip(mtd, -1);
2180 chip->select_chip(mtd, chipnr);
2183 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2184 * page mask to see if this BBT should be rewritten
2186 if (bbt_masked_page != 0xffffffff &&
2187 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2188 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2192 instr->state = MTD_ERASE_DONE;
2196 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2197 /* Do call back function */
2199 mtd_erase_callback(instr);
2201 /* Deselect and wake up anyone waiting on the device */
2202 nand_release_device(mtd);
2205 * If BBT requires refresh and erase was successful, rewrite any
2206 * selected bad block tables
2208 if (bbt_masked_page == 0xffffffff || ret)
2211 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2212 if (!rewrite_bbt[chipnr])
2214 /* update the BBT for chip */
2215 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2216 "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2217 chip->bbt_td->pages[chipnr]);
2218 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2221 /* Return more or less happy */
2226 * nand_sync - [MTD Interface] sync
2227 * @mtd: MTD device structure
2229 * Sync is actually a wait for chip ready function
2231 static void nand_sync(struct mtd_info *mtd)
2233 struct nand_chip *chip = mtd->priv;
2235 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2237 /* Grab the lock and see if the device is available */
2238 nand_get_device(chip, mtd, FL_SYNCING);
2239 /* Release it and go back */
2240 nand_release_device(mtd);
2244 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2245 * @mtd: MTD device structure
2246 * @offs: offset relative to mtd start
2248 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2250 /* Check for invalid offset */
2251 if (offs > mtd->size)
2254 return nand_block_checkbad(mtd, offs, 1, 0);
2258 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2259 * @mtd: MTD device structure
2260 * @ofs: offset relative to mtd start
2262 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2264 struct nand_chip *chip = mtd->priv;
2267 if ((ret = nand_block_isbad(mtd, ofs))) {
2268 /* If it was bad already, return success and do nothing. */
2274 return chip->block_markbad(mtd, ofs);
2278 * nand_suspend - [MTD Interface] Suspend the NAND flash
2279 * @mtd: MTD device structure
2281 static int nand_suspend(struct mtd_info *mtd)
2283 struct nand_chip *chip = mtd->priv;
2285 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2289 * nand_resume - [MTD Interface] Resume the NAND flash
2290 * @mtd: MTD device structure
2292 static void nand_resume(struct mtd_info *mtd)
2294 struct nand_chip *chip = mtd->priv;
2296 if (chip->state == FL_PM_SUSPENDED)
2297 nand_release_device(mtd);
2299 printk(KERN_ERR "nand_resume() called for a chip which is not "
2300 "in suspended state\n");
2304 * Set default functions
2306 static void nand_set_defaults(struct nand_chip *chip, int busw)
2308 /* check for proper chip_delay setup, set 20us if not */
2309 if (!chip->chip_delay)
2310 chip->chip_delay = 20;
2312 /* check, if a user supplied command function given */
2313 if (chip->cmdfunc == NULL)
2314 chip->cmdfunc = nand_command;
2316 /* check, if a user supplied wait function given */
2317 if (chip->waitfunc == NULL)
2318 chip->waitfunc = nand_wait;
2320 if (!chip->select_chip)
2321 chip->select_chip = nand_select_chip;
2322 if (!chip->read_byte)
2323 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2324 if (!chip->read_word)
2325 chip->read_word = nand_read_word;
2326 if (!chip->block_bad)
2327 chip->block_bad = nand_block_bad;
2328 if (!chip->block_markbad)
2329 chip->block_markbad = nand_default_block_markbad;
2330 if (!chip->write_buf)
2331 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2332 if (!chip->read_buf)
2333 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2334 if (!chip->verify_buf)
2335 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2336 if (!chip->scan_bbt)
2337 chip->scan_bbt = nand_default_bbt;
2339 if (!chip->controller) {
2340 chip->controller = &chip->hwcontrol;
2342 /* XXX U-BOOT XXX */
2344 spin_lock_init(&chip->controller->lock);
2345 init_waitqueue_head(&chip->controller->wq);
2352 * Get the flash and manufacturer id and lookup if the type is supported
2354 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2355 struct nand_chip *chip,
2356 int busw, int *maf_id)
2358 struct nand_flash_dev *type = NULL;
2359 int i, dev_id, maf_idx;
2361 /* Select the device */
2362 chip->select_chip(mtd, 0);
2364 /* Send the command for reading device ID */
2365 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2367 /* Read manufacturer and device IDs */
2368 *maf_id = chip->read_byte(mtd);
2369 dev_id = chip->read_byte(mtd);
2371 /* Lookup the flash id */
2372 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2373 if (dev_id == nand_flash_ids[i].id) {
2374 type = &nand_flash_ids[i];
2380 return ERR_PTR(-ENODEV);
2383 mtd->name = type->name;
2385 chip->chipsize = type->chipsize << 20;
2387 /* Newer devices have all the information in additional id bytes */
2388 if (!type->pagesize) {
2390 /* The 3rd id byte holds MLC / multichip data */
2391 chip->cellinfo = chip->read_byte(mtd);
2392 /* The 4th id byte is the important one */
2393 extid = chip->read_byte(mtd);
2395 mtd->writesize = 1024 << (extid & 0x3);
2398 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2400 /* Calc blocksize. Blocksize is multiples of 64KiB */
2401 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2403 /* Get buswidth information */
2404 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2408 * Old devices have chip data hardcoded in the device id table
2410 mtd->erasesize = type->erasesize;
2411 mtd->writesize = type->pagesize;
2412 mtd->oobsize = mtd->writesize / 32;
2413 busw = type->options & NAND_BUSWIDTH_16;
2416 /* Try to identify manufacturer */
2417 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2418 if (nand_manuf_ids[maf_idx].id == *maf_id)
2423 * Check, if buswidth is correct. Hardware drivers should set
2426 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2427 printk(KERN_INFO "NAND device: Manufacturer ID:"
2428 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2429 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2430 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2431 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2433 return ERR_PTR(-EINVAL);
2436 /* Calculate the address shift from the page size */
2437 chip->page_shift = ffs(mtd->writesize) - 1;
2438 /* Convert chipsize to number of pages per chip -1. */
2439 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2441 chip->bbt_erase_shift = chip->phys_erase_shift =
2442 ffs(mtd->erasesize) - 1;
2443 chip->chip_shift = ffs(chip->chipsize) - 1;
2445 /* Set the bad block position */
2446 chip->badblockpos = mtd->writesize > 512 ?
2447 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2449 /* Get chip options, preserve non chip based options */
2450 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2451 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2454 * Set chip as a default. Board drivers can override it, if necessary
2456 chip->options |= NAND_NO_AUTOINCR;
2458 /* Check if chip is a not a samsung device. Do not clear the
2459 * options for chips which are not having an extended id.
2461 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2462 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2464 /* Check for AND chips with 4 page planes */
2465 if (chip->options & NAND_4PAGE_ARRAY)
2466 chip->erase_cmd = multi_erase_cmd;
2468 chip->erase_cmd = single_erase_cmd;
2470 /* Do not replace user supplied command function ! */
2471 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2472 chip->cmdfunc = nand_command_lp;
2474 MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2475 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2476 nand_manuf_ids[maf_idx].name, type->name);
2482 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2483 * @mtd: MTD device structure
2484 * @maxchips: Number of chips to scan for
2486 * This is the first phase of the normal nand_scan() function. It
2487 * reads the flash ID and sets up MTD fields accordingly.
2489 * The mtd->owner field must be set to the module of the caller.
2491 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2493 int i, busw, nand_maf_id;
2494 struct nand_chip *chip = mtd->priv;
2495 struct nand_flash_dev *type;
2497 /* Get buswidth to select the correct functions */
2498 busw = chip->options & NAND_BUSWIDTH_16;
2499 /* Set the default functions */
2500 nand_set_defaults(chip, busw);
2502 /* Read the flash type */
2503 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2506 printk(KERN_WARNING "No NAND device found!!!\n");
2507 chip->select_chip(mtd, -1);
2508 return PTR_ERR(type);
2511 /* Check for a chip array */
2512 for (i = 1; i < maxchips; i++) {
2513 chip->select_chip(mtd, i);
2514 /* Send the command for reading device ID */
2515 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2516 /* Read manufacturer and device IDs */
2517 if (nand_maf_id != chip->read_byte(mtd) ||
2518 type->id != chip->read_byte(mtd))
2522 printk(KERN_INFO "%d NAND chips detected\n", i);
2524 /* Store the number of chips and calc total size for mtd */
2526 mtd->size = i * chip->chipsize;
2533 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2534 * @mtd: MTD device structure
2535 * @maxchips: Number of chips to scan for
2537 * This is the second phase of the normal nand_scan() function. It
2538 * fills out all the uninitialized function pointers with the defaults
2539 * and scans for a bad block table if appropriate.
2541 int nand_scan_tail(struct mtd_info *mtd)
2544 struct nand_chip *chip = mtd->priv;
2546 if (!(chip->options & NAND_OWN_BUFFERS))
2547 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2551 /* Set the internal oob buffer location, just after the page data */
2552 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2555 * If no default placement scheme is given, select an appropriate one
2557 if (!chip->ecc.layout) {
2558 switch (mtd->oobsize) {
2560 chip->ecc.layout = &nand_oob_8;
2563 chip->ecc.layout = &nand_oob_16;
2566 chip->ecc.layout = &nand_oob_64;
2569 chip->ecc.layout = &nand_oob_128;
2572 printk(KERN_WARNING "No oob scheme defined for "
2573 "oobsize %d\n", mtd->oobsize);
2578 if (!chip->write_page)
2579 chip->write_page = nand_write_page;
2582 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2583 * selected and we have 256 byte pagesize fallback to software ECC
2585 if (!chip->ecc.read_page_raw)
2586 chip->ecc.read_page_raw = nand_read_page_raw;
2587 if (!chip->ecc.write_page_raw)
2588 chip->ecc.write_page_raw = nand_write_page_raw;
2590 switch (chip->ecc.mode) {
2592 /* Use standard hwecc read page function ? */
2593 if (!chip->ecc.read_page)
2594 chip->ecc.read_page = nand_read_page_hwecc;
2595 if (!chip->ecc.write_page)
2596 chip->ecc.write_page = nand_write_page_hwecc;
2597 if (!chip->ecc.read_oob)
2598 chip->ecc.read_oob = nand_read_oob_std;
2599 if (!chip->ecc.write_oob)
2600 chip->ecc.write_oob = nand_write_oob_std;
2602 case NAND_ECC_HW_SYNDROME:
2603 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2604 !chip->ecc.hwctl) &&
2605 (!chip->ecc.read_page ||
2606 chip->ecc.read_page == nand_read_page_hwecc ||
2607 !chip->ecc.write_page ||
2608 chip->ecc.write_page == nand_write_page_hwecc)) {
2609 printk(KERN_WARNING "No ECC functions supplied, "
2610 "Hardware ECC not possible\n");
2613 /* Use standard syndrome read/write page function ? */
2614 if (!chip->ecc.read_page)
2615 chip->ecc.read_page = nand_read_page_syndrome;
2616 if (!chip->ecc.write_page)
2617 chip->ecc.write_page = nand_write_page_syndrome;
2618 if (!chip->ecc.read_oob)
2619 chip->ecc.read_oob = nand_read_oob_syndrome;
2620 if (!chip->ecc.write_oob)
2621 chip->ecc.write_oob = nand_write_oob_syndrome;
2623 if (mtd->writesize >= chip->ecc.size)
2625 printk(KERN_WARNING "%d byte HW ECC not possible on "
2626 "%d byte page size, fallback to SW ECC\n",
2627 chip->ecc.size, mtd->writesize);
2628 chip->ecc.mode = NAND_ECC_SOFT;
2631 chip->ecc.calculate = nand_calculate_ecc;
2632 chip->ecc.correct = nand_correct_data;
2633 chip->ecc.read_page = nand_read_page_swecc;
2634 chip->ecc.write_page = nand_write_page_swecc;
2635 chip->ecc.read_oob = nand_read_oob_std;
2636 chip->ecc.write_oob = nand_write_oob_std;
2637 chip->ecc.size = 256;
2638 chip->ecc.bytes = 3;
2642 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2643 "This is not recommended !!\n");
2644 chip->ecc.read_page = nand_read_page_raw;
2645 chip->ecc.write_page = nand_write_page_raw;
2646 chip->ecc.read_oob = nand_read_oob_std;
2647 chip->ecc.write_oob = nand_write_oob_std;
2648 chip->ecc.size = mtd->writesize;
2649 chip->ecc.bytes = 0;
2653 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2659 * The number of bytes available for a client to place data into
2660 * the out of band area
2662 chip->ecc.layout->oobavail = 0;
2663 for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
2664 chip->ecc.layout->oobavail +=
2665 chip->ecc.layout->oobfree[i].length;
2666 mtd->oobavail = chip->ecc.layout->oobavail;
2669 * Set the number of read / write steps for one page depending on ECC
2672 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2673 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2674 printk(KERN_WARNING "Invalid ecc parameters\n");
2677 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2680 * Allow subpage writes up to ecc.steps. Not possible for MLC
2683 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2684 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2685 switch(chip->ecc.steps) {
2687 mtd->subpage_sft = 1;
2691 mtd->subpage_sft = 2;
2695 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2697 /* Initialize state */
2698 chip->state = FL_READY;
2700 /* De-select the device */
2701 chip->select_chip(mtd, -1);
2703 /* Invalidate the pagebuffer reference */
2706 /* Fill in remaining MTD driver data */
2707 mtd->type = MTD_NANDFLASH;
2708 mtd->flags = MTD_CAP_NANDFLASH;
2709 mtd->erase = nand_erase;
2711 mtd->unpoint = NULL;
2712 mtd->read = nand_read;
2713 mtd->write = nand_write;
2714 mtd->read_oob = nand_read_oob;
2715 mtd->write_oob = nand_write_oob;
2716 mtd->sync = nand_sync;
2719 mtd->suspend = nand_suspend;
2720 mtd->resume = nand_resume;
2721 mtd->block_isbad = nand_block_isbad;
2722 mtd->block_markbad = nand_block_markbad;
2724 /* propagate ecc.layout to mtd_info */
2725 mtd->ecclayout = chip->ecc.layout;
2727 /* Check, if we should skip the bad block table scan */
2728 if (chip->options & NAND_SKIP_BBTSCAN)
2729 chip->options |= NAND_BBT_SCANNED;
2734 /* module_text_address() isn't exported, and it's mostly a pointless
2735 test if this is a module _anyway_ -- they'd have to try _really_ hard
2736 to call us from in-kernel code if the core NAND support is modular. */
2738 #define caller_is_module() (1)
2740 #define caller_is_module() \
2741 module_text_address((unsigned long)__builtin_return_address(0))
2745 * nand_scan - [NAND Interface] Scan for the NAND device
2746 * @mtd: MTD device structure
2747 * @maxchips: Number of chips to scan for
2749 * This fills out all the uninitialized function pointers
2750 * with the defaults.
2751 * The flash ID is read and the mtd/chip structures are
2752 * filled with the appropriate values.
2753 * The mtd->owner field must be set to the module of the caller
2756 int nand_scan(struct mtd_info *mtd, int maxchips)
2760 /* Many callers got this wrong, so check for it for a while... */
2761 /* XXX U-BOOT XXX */
2763 if (!mtd->owner && caller_is_module()) {
2764 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2769 ret = nand_scan_ident(mtd, maxchips);
2771 ret = nand_scan_tail(mtd);
2776 * nand_release - [NAND Interface] Free resources held by the NAND device
2777 * @mtd: MTD device structure
2779 void nand_release(struct mtd_info *mtd)
2781 struct nand_chip *chip = mtd->priv;
2783 #ifdef CONFIG_MTD_PARTITIONS
2784 /* Deregister partitions */
2785 del_mtd_partitions(mtd);
2787 /* Deregister the device */
2788 /* XXX U-BOOT XXX */
2790 del_mtd_device(mtd);
2793 /* Free bad block table memory */
2795 if (!(chip->options & NAND_OWN_BUFFERS))
2796 kfree(chip->buffers);
2799 /* XXX U-BOOT XXX */
2801 EXPORT_SYMBOL_GPL(nand_scan);
2802 EXPORT_SYMBOL_GPL(nand_scan_ident);
2803 EXPORT_SYMBOL_GPL(nand_scan_tail);
2804 EXPORT_SYMBOL_GPL(nand_release);
2806 static int __init nand_base_init(void)
2808 led_trigger_register_simple("nand-disk", &nand_led_trigger);
2812 static void __exit nand_base_exit(void)
2814 led_trigger_unregister_simple(nand_led_trigger);
2817 module_init(nand_base_init);
2818 module_exit(nand_base_exit);
2820 MODULE_LICENSE("GPL");
2821 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2822 MODULE_DESCRIPTION("Generic NAND flash driver code");