5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
37 #include <linux/module.h>
38 #include <linux/delay.h>
39 #include <linux/errno.h>
40 #include <linux/err.h>
41 #include <linux/sched.h>
42 #include <linux/slab.h>
43 #include <linux/types.h>
44 #include <linux/mtd/mtd.h>
45 #include <linux/mtd/nand.h>
46 #include <linux/mtd/nand_ecc.h>
47 #include <linux/mtd/compatmac.h>
48 #include <linux/interrupt.h>
49 #include <linux/bitops.h>
50 #include <linux/leds.h>
53 #ifdef CONFIG_MTD_PARTITIONS
54 #include <linux/mtd/partitions.h>
61 #define ENOTSUPP 524 /* Operation is not supported */
65 #include <linux/err.h>
66 #include <linux/mtd/compat.h>
67 #include <linux/mtd/mtd.h>
68 #include <linux/mtd/nand.h>
69 #include <linux/mtd/nand_ecc.h>
71 #ifdef CONFIG_MTD_PARTITIONS
72 #include <linux/mtd/partitions.h>
76 #include <asm/errno.h>
78 #ifdef CONFIG_JFFS2_NAND
79 #include <jffs2/jffs2.h>
83 * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
84 * a flash. NAND flash is initialized prior to interrupts so standard timers
85 * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
86 * which is greater than (max NAND reset time / NAND status read time).
87 * A conservative default of 200000 (500 us / 25 ns) is used as a default.
89 #ifndef CONFIG_SYS_NAND_RESET_CNT
90 #define CONFIG_SYS_NAND_RESET_CNT 200000
93 /* Define default oob placement schemes for large and small page devices */
94 static struct nand_ecclayout nand_oob_8 = {
104 static struct nand_ecclayout nand_oob_16 = {
106 .eccpos = {0, 1, 2, 3, 6, 7},
112 static struct nand_ecclayout nand_oob_64 = {
115 40, 41, 42, 43, 44, 45, 46, 47,
116 48, 49, 50, 51, 52, 53, 54, 55,
117 56, 57, 58, 59, 60, 61, 62, 63},
123 static struct nand_ecclayout nand_oob_128 = {
126 80, 81, 82, 83, 84, 85, 86, 87,
127 88, 89, 90, 91, 92, 93, 94, 95,
128 96, 97, 98, 99, 100, 101, 102, 103,
129 104, 105, 106, 107, 108, 109, 110, 111,
130 112, 113, 114, 115, 116, 117, 118, 119,
131 120, 121, 122, 123, 124, 125, 126, 127},
138 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
141 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
142 struct mtd_oob_ops *ops);
144 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
147 * For devices which display every fart in the system on a separate LED. Is
148 * compiled away when LED support is disabled.
152 DEFINE_LED_TRIGGER(nand_led_trigger);
156 * nand_release_device - [GENERIC] release chip
157 * @mtd: MTD device structure
159 * Deselect, release chip lock and wake up anyone waiting on the device
163 static void nand_release_device(struct mtd_info *mtd)
165 struct nand_chip *chip = mtd->priv;
167 /* De-select the NAND device */
168 chip->select_chip(mtd, -1);
170 /* Release the controller and the chip */
171 spin_lock(&chip->controller->lock);
172 chip->controller->active = NULL;
173 chip->state = FL_READY;
174 wake_up(&chip->controller->wq);
175 spin_unlock(&chip->controller->lock);
178 static void nand_release_device (struct mtd_info *mtd)
180 struct nand_chip *this = mtd->priv;
181 this->select_chip(mtd, -1); /* De-select the NAND device */
186 * nand_read_byte - [DEFAULT] read one byte from the chip
187 * @mtd: MTD device structure
189 * Default read function for 8bit buswith
191 static uint8_t nand_read_byte(struct mtd_info *mtd)
193 struct nand_chip *chip = mtd->priv;
194 return readb(chip->IO_ADDR_R);
198 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
199 * @mtd: MTD device structure
201 * Default read function for 16bit buswith with
202 * endianess conversion
204 static uint8_t nand_read_byte16(struct mtd_info *mtd)
206 struct nand_chip *chip = mtd->priv;
207 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
211 * nand_read_word - [DEFAULT] read one word from the chip
212 * @mtd: MTD device structure
214 * Default read function for 16bit buswith without
215 * endianess conversion
217 static u16 nand_read_word(struct mtd_info *mtd)
219 struct nand_chip *chip = mtd->priv;
220 return readw(chip->IO_ADDR_R);
224 * nand_select_chip - [DEFAULT] control CE line
225 * @mtd: MTD device structure
226 * @chipnr: chipnumber to select, -1 for deselect
228 * Default select function for 1 chip devices.
230 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
232 struct nand_chip *chip = mtd->priv;
236 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
247 * nand_write_buf - [DEFAULT] write buffer to chip
248 * @mtd: MTD device structure
250 * @len: number of bytes to write
252 * Default write function for 8bit buswith
254 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
257 struct nand_chip *chip = mtd->priv;
259 for (i = 0; i < len; i++)
260 writeb(buf[i], chip->IO_ADDR_W);
264 * nand_read_buf - [DEFAULT] read chip data into buffer
265 * @mtd: MTD device structure
266 * @buf: buffer to store date
267 * @len: number of bytes to read
269 * Default read function for 8bit buswith
271 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
274 struct nand_chip *chip = mtd->priv;
276 for (i = 0; i < len; i++)
277 buf[i] = readb(chip->IO_ADDR_R);
281 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
282 * @mtd: MTD device structure
283 * @buf: buffer containing the data to compare
284 * @len: number of bytes to compare
286 * Default verify function for 8bit buswith
288 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
291 struct nand_chip *chip = mtd->priv;
293 for (i = 0; i < len; i++)
294 if (buf[i] != readb(chip->IO_ADDR_R))
300 * nand_write_buf16 - [DEFAULT] write buffer to chip
301 * @mtd: MTD device structure
303 * @len: number of bytes to write
305 * Default write function for 16bit buswith
307 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
310 struct nand_chip *chip = mtd->priv;
311 u16 *p = (u16 *) buf;
314 for (i = 0; i < len; i++)
315 writew(p[i], chip->IO_ADDR_W);
320 * nand_read_buf16 - [DEFAULT] read chip data into buffer
321 * @mtd: MTD device structure
322 * @buf: buffer to store date
323 * @len: number of bytes to read
325 * Default read function for 16bit buswith
327 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
330 struct nand_chip *chip = mtd->priv;
331 u16 *p = (u16 *) buf;
334 for (i = 0; i < len; i++)
335 p[i] = readw(chip->IO_ADDR_R);
339 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
340 * @mtd: MTD device structure
341 * @buf: buffer containing the data to compare
342 * @len: number of bytes to compare
344 * Default verify function for 16bit buswith
346 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
349 struct nand_chip *chip = mtd->priv;
350 u16 *p = (u16 *) buf;
353 for (i = 0; i < len; i++)
354 if (p[i] != readw(chip->IO_ADDR_R))
361 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
362 * @mtd: MTD device structure
363 * @ofs: offset from device start
364 * @getchip: 0, if the chip is already selected
366 * Check, if the block is bad.
368 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
370 int page, chipnr, res = 0;
371 struct nand_chip *chip = mtd->priv;
374 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
377 chipnr = (int)(ofs >> chip->chip_shift);
379 nand_get_device(chip, mtd, FL_READING);
381 /* Select the NAND device */
382 chip->select_chip(mtd, chipnr);
385 if (chip->options & NAND_BUSWIDTH_16) {
386 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
388 bad = cpu_to_le16(chip->read_word(mtd));
389 if (chip->badblockpos & 0x1)
391 if ((bad & 0xFF) != 0xff)
394 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
395 if (chip->read_byte(mtd) != 0xff)
400 nand_release_device(mtd);
406 * nand_default_block_markbad - [DEFAULT] mark a block bad
407 * @mtd: MTD device structure
408 * @ofs: offset from device start
410 * This is the default implementation, which can be overridden by
411 * a hardware specific driver.
413 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
415 struct nand_chip *chip = mtd->priv;
416 uint8_t buf[2] = { 0, 0 };
419 /* Get block number */
420 block = (int)(ofs >> chip->bbt_erase_shift);
422 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
424 /* Do we have a flash based bad block table ? */
425 if (chip->options & NAND_USE_FLASH_BBT)
426 ret = nand_update_bbt(mtd, ofs);
428 /* We write two bytes, so we dont have to mess with 16 bit
431 nand_get_device(chip, mtd, FL_WRITING);
433 chip->ops.len = chip->ops.ooblen = 2;
434 chip->ops.datbuf = NULL;
435 chip->ops.oobbuf = buf;
436 chip->ops.ooboffs = chip->badblockpos & ~0x01;
438 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
439 nand_release_device(mtd);
442 mtd->ecc_stats.badblocks++;
448 * nand_check_wp - [GENERIC] check if the chip is write protected
449 * @mtd: MTD device structure
450 * Check, if the device is write protected
452 * The function expects, that the device is already selected
454 static int nand_check_wp(struct mtd_info *mtd)
456 struct nand_chip *chip = mtd->priv;
457 /* Check the WP bit */
458 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
459 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
463 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
464 * @mtd: MTD device structure
465 * @ofs: offset from device start
466 * @getchip: 0, if the chip is already selected
467 * @allowbbt: 1, if its allowed to access the bbt area
469 * Check, if the block is bad. Either by reading the bad block table or
470 * calling of the scan function.
472 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
475 struct nand_chip *chip = mtd->priv;
477 if (!(chip->options & NAND_BBT_SCANNED)) {
478 chip->options |= NAND_BBT_SCANNED;
483 return chip->block_bad(mtd, ofs, getchip);
485 /* Return info from the table */
486 return nand_isbad_bbt(mtd, ofs, allowbbt);
490 * Wait for the ready pin, after a command
491 * The timeout is catched later.
495 void nand_wait_ready(struct mtd_info *mtd)
497 struct nand_chip *chip = mtd->priv;
498 unsigned long timeo = jiffies + 2;
500 led_trigger_event(nand_led_trigger, LED_FULL);
501 /* wait until command is processed or timeout occures */
503 if (chip->dev_ready(mtd))
505 touch_softlockup_watchdog();
506 } while (time_before(jiffies, timeo));
507 led_trigger_event(nand_led_trigger, LED_OFF);
509 EXPORT_SYMBOL_GPL(nand_wait_ready);
511 void nand_wait_ready(struct mtd_info *mtd)
513 struct nand_chip *chip = mtd->priv;
514 u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
518 /* wait until command is processed or timeout occures */
519 while (get_timer(0) < timeo) {
521 if (chip->dev_ready(mtd))
528 * nand_command - [DEFAULT] Send command to NAND device
529 * @mtd: MTD device structure
530 * @command: the command to be sent
531 * @column: the column address for this command, -1 if none
532 * @page_addr: the page address for this command, -1 if none
534 * Send command to NAND device. This function is used for small page
535 * devices (256/512 Bytes per page)
537 static void nand_command(struct mtd_info *mtd, unsigned int command,
538 int column, int page_addr)
540 register struct nand_chip *chip = mtd->priv;
541 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
542 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
545 * Write out the command to the device.
547 if (command == NAND_CMD_SEQIN) {
550 if (column >= mtd->writesize) {
552 column -= mtd->writesize;
553 readcmd = NAND_CMD_READOOB;
554 } else if (column < 256) {
555 /* First 256 bytes --> READ0 */
556 readcmd = NAND_CMD_READ0;
559 readcmd = NAND_CMD_READ1;
561 chip->cmd_ctrl(mtd, readcmd, ctrl);
562 ctrl &= ~NAND_CTRL_CHANGE;
564 chip->cmd_ctrl(mtd, command, ctrl);
567 * Address cycle, when necessary
569 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
570 /* Serially input address */
572 /* Adjust columns for 16 bit buswidth */
573 if (chip->options & NAND_BUSWIDTH_16)
575 chip->cmd_ctrl(mtd, column, ctrl);
576 ctrl &= ~NAND_CTRL_CHANGE;
578 if (page_addr != -1) {
579 chip->cmd_ctrl(mtd, page_addr, ctrl);
580 ctrl &= ~NAND_CTRL_CHANGE;
581 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
582 /* One more address cycle for devices > 32MiB */
583 if (chip->chipsize > (32 << 20))
584 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
586 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
589 * program and erase have their own busy handlers
590 * status and sequential in needs no delay
594 case NAND_CMD_PAGEPROG:
595 case NAND_CMD_ERASE1:
596 case NAND_CMD_ERASE2:
598 case NAND_CMD_STATUS:
604 udelay(chip->chip_delay);
605 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
606 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
608 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
609 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
613 /* This applies to read commands */
616 * If we don't have access to the busy pin, we apply the given
619 if (!chip->dev_ready) {
620 udelay(chip->chip_delay);
624 /* Apply this short delay always to ensure that we do wait tWB in
625 * any case on any machine. */
628 nand_wait_ready(mtd);
632 * nand_command_lp - [DEFAULT] Send command to NAND large page device
633 * @mtd: MTD device structure
634 * @command: the command to be sent
635 * @column: the column address for this command, -1 if none
636 * @page_addr: the page address for this command, -1 if none
638 * Send command to NAND device. This is the version for the new large page
639 * devices We dont have the separate regions as we have in the small page
640 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
642 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
643 int column, int page_addr)
645 register struct nand_chip *chip = mtd->priv;
646 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
648 /* Emulate NAND_CMD_READOOB */
649 if (command == NAND_CMD_READOOB) {
650 column += mtd->writesize;
651 command = NAND_CMD_READ0;
654 /* Command latch cycle */
655 chip->cmd_ctrl(mtd, command & 0xff,
656 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
658 if (column != -1 || page_addr != -1) {
659 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
661 /* Serially input address */
663 /* Adjust columns for 16 bit buswidth */
664 if (chip->options & NAND_BUSWIDTH_16)
666 chip->cmd_ctrl(mtd, column, ctrl);
667 ctrl &= ~NAND_CTRL_CHANGE;
668 chip->cmd_ctrl(mtd, column >> 8, ctrl);
670 if (page_addr != -1) {
671 chip->cmd_ctrl(mtd, page_addr, ctrl);
672 chip->cmd_ctrl(mtd, page_addr >> 8,
673 NAND_NCE | NAND_ALE);
674 /* One more address cycle for devices > 128MiB */
675 if (chip->chipsize > (128 << 20))
676 chip->cmd_ctrl(mtd, page_addr >> 16,
677 NAND_NCE | NAND_ALE);
680 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
683 * program and erase have their own busy handlers
684 * status, sequential in, and deplete1 need no delay
688 case NAND_CMD_CACHEDPROG:
689 case NAND_CMD_PAGEPROG:
690 case NAND_CMD_ERASE1:
691 case NAND_CMD_ERASE2:
694 case NAND_CMD_STATUS:
695 case NAND_CMD_DEPLETE1:
699 * read error status commands require only a short delay
701 case NAND_CMD_STATUS_ERROR:
702 case NAND_CMD_STATUS_ERROR0:
703 case NAND_CMD_STATUS_ERROR1:
704 case NAND_CMD_STATUS_ERROR2:
705 case NAND_CMD_STATUS_ERROR3:
706 udelay(chip->chip_delay);
712 udelay(chip->chip_delay);
713 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
714 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
715 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
716 NAND_NCE | NAND_CTRL_CHANGE);
717 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
721 case NAND_CMD_RNDOUT:
722 /* No ready / busy check necessary */
723 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
724 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
725 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
726 NAND_NCE | NAND_CTRL_CHANGE);
730 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
731 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
732 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
733 NAND_NCE | NAND_CTRL_CHANGE);
735 /* This applies to read commands */
738 * If we don't have access to the busy pin, we apply the given
741 if (!chip->dev_ready) {
742 udelay(chip->chip_delay);
747 /* Apply this short delay always to ensure that we do wait tWB in
748 * any case on any machine. */
751 nand_wait_ready(mtd);
755 * nand_get_device - [GENERIC] Get chip for selected access
756 * @chip: the nand chip descriptor
757 * @mtd: MTD device structure
758 * @new_state: the state which is requested
760 * Get the device and lock it for exclusive access
765 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
767 spinlock_t *lock = &chip->controller->lock;
768 wait_queue_head_t *wq = &chip->controller->wq;
769 DECLARE_WAITQUEUE(wait, current);
773 /* Hardware controller shared among independend devices */
774 /* Hardware controller shared among independend devices */
775 if (!chip->controller->active)
776 chip->controller->active = chip;
778 if (chip->controller->active == chip && chip->state == FL_READY) {
779 chip->state = new_state;
783 if (new_state == FL_PM_SUSPENDED) {
785 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
787 set_current_state(TASK_UNINTERRUPTIBLE);
788 add_wait_queue(wq, &wait);
791 remove_wait_queue(wq, &wait);
795 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
797 this->state = new_state;
803 * nand_wait - [DEFAULT] wait until the command is done
804 * @mtd: MTD device structure
805 * @chip: NAND chip structure
807 * Wait for command done. This applies to erase and program only
808 * Erase can take up to 400ms and program up to 20ms according to
809 * general NAND and SmartMedia specs
813 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
816 unsigned long timeo = jiffies;
817 int status, state = chip->state;
819 if (state == FL_ERASING)
820 timeo += (HZ * 400) / 1000;
822 timeo += (HZ * 20) / 1000;
824 led_trigger_event(nand_led_trigger, LED_FULL);
826 /* Apply this short delay always to ensure that we do wait tWB in
827 * any case on any machine. */
830 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
831 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
833 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
835 while (time_before(jiffies, timeo)) {
836 if (chip->dev_ready) {
837 if (chip->dev_ready(mtd))
840 if (chip->read_byte(mtd) & NAND_STATUS_READY)
845 led_trigger_event(nand_led_trigger, LED_OFF);
847 status = (int)chip->read_byte(mtd);
851 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
854 int state = this->state;
856 if (state == FL_ERASING)
857 timeo = (CONFIG_SYS_HZ * 400) / 1000;
859 timeo = (CONFIG_SYS_HZ * 20) / 1000;
861 if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
862 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
864 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
869 if (get_timer(0) > timeo) {
874 if (this->dev_ready) {
875 if (this->dev_ready(mtd))
878 if (this->read_byte(mtd) & NAND_STATUS_READY)
882 #ifdef PPCHAMELON_NAND_TIMER_HACK
884 while (get_timer(0) < 10);
885 #endif /* PPCHAMELON_NAND_TIMER_HACK */
887 return this->read_byte(mtd);
892 * nand_read_page_raw - [Intern] read raw page data without ecc
893 * @mtd: mtd info structure
894 * @chip: nand chip info structure
895 * @buf: buffer to store read data
896 * @page: page number to read
898 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
899 uint8_t *buf, int page)
901 chip->read_buf(mtd, buf, mtd->writesize);
902 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
907 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
908 * @mtd: mtd info structure
909 * @chip: nand chip info structure
910 * @buf: buffer to store read data
911 * @page: page number to read
913 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
914 uint8_t *buf, int page)
916 int i, eccsize = chip->ecc.size;
917 int eccbytes = chip->ecc.bytes;
918 int eccsteps = chip->ecc.steps;
920 uint8_t *ecc_calc = chip->buffers->ecccalc;
921 uint8_t *ecc_code = chip->buffers->ecccode;
922 uint32_t *eccpos = chip->ecc.layout->eccpos;
924 chip->ecc.read_page_raw(mtd, chip, buf, page);
926 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
927 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
929 for (i = 0; i < chip->ecc.total; i++)
930 ecc_code[i] = chip->oob_poi[eccpos[i]];
932 eccsteps = chip->ecc.steps;
935 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
938 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
940 mtd->ecc_stats.failed++;
942 mtd->ecc_stats.corrected += stat;
948 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
949 * @mtd: mtd info structure
950 * @chip: nand chip info structure
951 * @data_offs: offset of requested data within the page
952 * @readlen: data length
953 * @bufpoi: buffer to store read data
955 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
957 int start_step, end_step, num_steps;
958 uint32_t *eccpos = chip->ecc.layout->eccpos;
960 int data_col_addr, i, gaps = 0;
961 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
962 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
964 /* Column address wihin the page aligned to ECC size (256bytes). */
965 start_step = data_offs / chip->ecc.size;
966 end_step = (data_offs + readlen - 1) / chip->ecc.size;
967 num_steps = end_step - start_step + 1;
969 /* Data size aligned to ECC ecc.size*/
970 datafrag_len = num_steps * chip->ecc.size;
971 eccfrag_len = num_steps * chip->ecc.bytes;
973 data_col_addr = start_step * chip->ecc.size;
974 /* If we read not a page aligned data */
975 if (data_col_addr != 0)
976 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
978 p = bufpoi + data_col_addr;
979 chip->read_buf(mtd, p, datafrag_len);
982 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
983 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
985 /* The performance is faster if to position offsets
986 according to ecc.pos. Let make sure here that
987 there are no gaps in ecc positions */
988 for (i = 0; i < eccfrag_len - 1; i++) {
989 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
990 eccpos[i + start_step * chip->ecc.bytes + 1]) {
996 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
997 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
999 /* send the command to read the particular ecc bytes */
1000 /* take care about buswidth alignment in read_buf */
1001 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
1002 aligned_len = eccfrag_len;
1003 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
1005 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
1008 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
1009 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1012 for (i = 0; i < eccfrag_len; i++)
1013 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
1015 p = bufpoi + data_col_addr;
1016 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1019 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1021 mtd->ecc_stats.failed++;
1023 mtd->ecc_stats.corrected += stat;
1029 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
1030 * @mtd: mtd info structure
1031 * @chip: nand chip info structure
1032 * @buf: buffer to store read data
1033 * @page: page number to read
1035 * Not for syndrome calculating ecc controllers which need a special oob layout
1037 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1038 uint8_t *buf, int page)
1040 int i, eccsize = chip->ecc.size;
1041 int eccbytes = chip->ecc.bytes;
1042 int eccsteps = chip->ecc.steps;
1044 uint8_t *ecc_calc = chip->buffers->ecccalc;
1045 uint8_t *ecc_code = chip->buffers->ecccode;
1046 uint32_t *eccpos = chip->ecc.layout->eccpos;
1048 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1049 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1050 chip->read_buf(mtd, p, eccsize);
1051 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1053 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1055 for (i = 0; i < chip->ecc.total; i++)
1056 ecc_code[i] = chip->oob_poi[eccpos[i]];
1058 eccsteps = chip->ecc.steps;
1061 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1064 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1066 mtd->ecc_stats.failed++;
1068 mtd->ecc_stats.corrected += stat;
1074 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1075 * @mtd: mtd info structure
1076 * @chip: nand chip info structure
1077 * @buf: buffer to store read data
1078 * @page: page number to read
1080 * Hardware ECC for large page chips, require OOB to be read first.
1081 * For this ECC mode, the write_page method is re-used from ECC_HW.
1082 * These methods read/write ECC from the OOB area, unlike the
1083 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1084 * "infix ECC" scheme and reads/writes ECC from the data area, by
1085 * overwriting the NAND manufacturer bad block markings.
1087 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1088 struct nand_chip *chip, uint8_t *buf, int page)
1090 int i, eccsize = chip->ecc.size;
1091 int eccbytes = chip->ecc.bytes;
1092 int eccsteps = chip->ecc.steps;
1094 uint8_t *ecc_code = chip->buffers->ecccode;
1095 uint32_t *eccpos = chip->ecc.layout->eccpos;
1096 uint8_t *ecc_calc = chip->buffers->ecccalc;
1098 /* Read the OOB area first */
1099 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1100 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1101 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1103 for (i = 0; i < chip->ecc.total; i++)
1104 ecc_code[i] = chip->oob_poi[eccpos[i]];
1106 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1109 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1110 chip->read_buf(mtd, p, eccsize);
1111 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1113 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1115 mtd->ecc_stats.failed++;
1117 mtd->ecc_stats.corrected += stat;
1123 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1124 * @mtd: mtd info structure
1125 * @chip: nand chip info structure
1126 * @buf: buffer to store read data
1127 * @page: page number to read
1129 * The hw generator calculates the error syndrome automatically. Therefor
1130 * we need a special oob layout and handling.
1132 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1133 uint8_t *buf, int page)
1135 int i, eccsize = chip->ecc.size;
1136 int eccbytes = chip->ecc.bytes;
1137 int eccsteps = chip->ecc.steps;
1139 uint8_t *oob = chip->oob_poi;
1141 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1144 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1145 chip->read_buf(mtd, p, eccsize);
1147 if (chip->ecc.prepad) {
1148 chip->read_buf(mtd, oob, chip->ecc.prepad);
1149 oob += chip->ecc.prepad;
1152 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1153 chip->read_buf(mtd, oob, eccbytes);
1154 stat = chip->ecc.correct(mtd, p, oob, NULL);
1157 mtd->ecc_stats.failed++;
1159 mtd->ecc_stats.corrected += stat;
1163 if (chip->ecc.postpad) {
1164 chip->read_buf(mtd, oob, chip->ecc.postpad);
1165 oob += chip->ecc.postpad;
1169 /* Calculate remaining oob bytes */
1170 i = mtd->oobsize - (oob - chip->oob_poi);
1172 chip->read_buf(mtd, oob, i);
1178 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1179 * @chip: nand chip structure
1180 * @oob: oob destination address
1181 * @ops: oob ops structure
1182 * @len: size of oob to transfer
1184 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1185 struct mtd_oob_ops *ops, size_t len)
1191 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1194 case MTD_OOB_AUTO: {
1195 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1196 uint32_t boffs = 0, roffs = ops->ooboffs;
1199 for(; free->length && len; free++, len -= bytes) {
1200 /* Read request not from offset 0 ? */
1201 if (unlikely(roffs)) {
1202 if (roffs >= free->length) {
1203 roffs -= free->length;
1206 boffs = free->offset + roffs;
1207 bytes = min_t(size_t, len,
1208 (free->length - roffs));
1211 bytes = min_t(size_t, len, free->length);
1212 boffs = free->offset;
1214 memcpy(oob, chip->oob_poi + boffs, bytes);
1226 * nand_do_read_ops - [Internal] Read data with ECC
1228 * @mtd: MTD device structure
1229 * @from: offset to read from
1230 * @ops: oob ops structure
1232 * Internal function. Called with chip held.
1234 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1235 struct mtd_oob_ops *ops)
1237 int chipnr, page, realpage, col, bytes, aligned;
1238 struct nand_chip *chip = mtd->priv;
1239 struct mtd_ecc_stats stats;
1240 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1243 uint32_t readlen = ops->len;
1244 uint32_t oobreadlen = ops->ooblen;
1245 uint8_t *bufpoi, *oob, *buf;
1247 stats = mtd->ecc_stats;
1249 chipnr = (int)(from >> chip->chip_shift);
1250 chip->select_chip(mtd, chipnr);
1252 realpage = (int)(from >> chip->page_shift);
1253 page = realpage & chip->pagemask;
1255 col = (int)(from & (mtd->writesize - 1));
1261 bytes = min(mtd->writesize - col, readlen);
1262 aligned = (bytes == mtd->writesize);
1264 /* Is the current page in the buffer ? */
1265 if (realpage != chip->pagebuf || oob) {
1266 bufpoi = aligned ? buf : chip->buffers->databuf;
1268 if (likely(sndcmd)) {
1269 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1273 /* Now read the page into the buffer */
1274 if (unlikely(ops->mode == MTD_OOB_RAW))
1275 ret = chip->ecc.read_page_raw(mtd, chip,
1277 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1278 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1280 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1285 /* Transfer not aligned data */
1287 if (!NAND_SUBPAGE_READ(chip) && !oob)
1288 chip->pagebuf = realpage;
1289 memcpy(buf, chip->buffers->databuf + col, bytes);
1294 if (unlikely(oob)) {
1295 /* Raw mode does data:oob:data:oob */
1296 if (ops->mode != MTD_OOB_RAW) {
1297 int toread = min(oobreadlen,
1298 chip->ecc.layout->oobavail);
1300 oob = nand_transfer_oob(chip,
1302 oobreadlen -= toread;
1305 buf = nand_transfer_oob(chip,
1306 buf, ops, mtd->oobsize);
1309 if (!(chip->options & NAND_NO_READRDY)) {
1311 * Apply delay or wait for ready/busy pin. Do
1312 * this before the AUTOINCR check, so no
1313 * problems arise if a chip which does auto
1314 * increment is marked as NOAUTOINCR by the
1317 if (!chip->dev_ready)
1318 udelay(chip->chip_delay);
1320 nand_wait_ready(mtd);
1323 memcpy(buf, chip->buffers->databuf + col, bytes);
1332 /* For subsequent reads align to page boundary. */
1334 /* Increment page address */
1337 page = realpage & chip->pagemask;
1338 /* Check, if we cross a chip boundary */
1341 chip->select_chip(mtd, -1);
1342 chip->select_chip(mtd, chipnr);
1345 /* Check, if the chip supports auto page increment
1346 * or if we have hit a block boundary.
1348 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1352 ops->retlen = ops->len - (size_t) readlen;
1354 ops->oobretlen = ops->ooblen - oobreadlen;
1359 if (mtd->ecc_stats.failed - stats.failed)
1362 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1366 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1367 * @mtd: MTD device structure
1368 * @from: offset to read from
1369 * @len: number of bytes to read
1370 * @retlen: pointer to variable to store the number of read bytes
1371 * @buf: the databuffer to put data
1373 * Get hold of the chip and call nand_do_read
1375 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1376 size_t *retlen, uint8_t *buf)
1378 struct nand_chip *chip = mtd->priv;
1381 /* Do not allow reads past end of device */
1382 if ((from + len) > mtd->size)
1387 nand_get_device(chip, mtd, FL_READING);
1389 chip->ops.len = len;
1390 chip->ops.datbuf = buf;
1391 chip->ops.oobbuf = NULL;
1393 ret = nand_do_read_ops(mtd, from, &chip->ops);
1395 *retlen = chip->ops.retlen;
1397 nand_release_device(mtd);
1403 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1404 * @mtd: mtd info structure
1405 * @chip: nand chip info structure
1406 * @page: page number to read
1407 * @sndcmd: flag whether to issue read command or not
1409 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1410 int page, int sndcmd)
1413 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1416 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1421 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1423 * @mtd: mtd info structure
1424 * @chip: nand chip info structure
1425 * @page: page number to read
1426 * @sndcmd: flag whether to issue read command or not
1428 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1429 int page, int sndcmd)
1431 uint8_t *buf = chip->oob_poi;
1432 int length = mtd->oobsize;
1433 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1434 int eccsize = chip->ecc.size;
1435 uint8_t *bufpoi = buf;
1436 int i, toread, sndrnd = 0, pos;
1438 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1439 for (i = 0; i < chip->ecc.steps; i++) {
1441 pos = eccsize + i * (eccsize + chunk);
1442 if (mtd->writesize > 512)
1443 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1445 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1448 toread = min_t(int, length, chunk);
1449 chip->read_buf(mtd, bufpoi, toread);
1454 chip->read_buf(mtd, bufpoi, length);
1460 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1461 * @mtd: mtd info structure
1462 * @chip: nand chip info structure
1463 * @page: page number to write
1465 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1469 const uint8_t *buf = chip->oob_poi;
1470 int length = mtd->oobsize;
1472 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1473 chip->write_buf(mtd, buf, length);
1474 /* Send command to program the OOB data */
1475 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1477 status = chip->waitfunc(mtd, chip);
1479 return status & NAND_STATUS_FAIL ? -EIO : 0;
1483 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1484 * with syndrome - only for large page flash !
1485 * @mtd: mtd info structure
1486 * @chip: nand chip info structure
1487 * @page: page number to write
1489 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1490 struct nand_chip *chip, int page)
1492 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1493 int eccsize = chip->ecc.size, length = mtd->oobsize;
1494 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1495 const uint8_t *bufpoi = chip->oob_poi;
1498 * data-ecc-data-ecc ... ecc-oob
1500 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1502 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1503 pos = steps * (eccsize + chunk);
1508 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1509 for (i = 0; i < steps; i++) {
1511 if (mtd->writesize <= 512) {
1512 uint32_t fill = 0xFFFFFFFF;
1516 int num = min_t(int, len, 4);
1517 chip->write_buf(mtd, (uint8_t *)&fill,
1522 pos = eccsize + i * (eccsize + chunk);
1523 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1527 len = min_t(int, length, chunk);
1528 chip->write_buf(mtd, bufpoi, len);
1533 chip->write_buf(mtd, bufpoi, length);
1535 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1536 status = chip->waitfunc(mtd, chip);
1538 return status & NAND_STATUS_FAIL ? -EIO : 0;
1542 * nand_do_read_oob - [Intern] NAND read out-of-band
1543 * @mtd: MTD device structure
1544 * @from: offset to read from
1545 * @ops: oob operations description structure
1547 * NAND read out-of-band data from the spare area
1549 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1550 struct mtd_oob_ops *ops)
1552 int page, realpage, chipnr, sndcmd = 1;
1553 struct nand_chip *chip = mtd->priv;
1554 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1555 int readlen = ops->ooblen;
1557 uint8_t *buf = ops->oobbuf;
1559 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1560 (unsigned long long)from, readlen);
1562 if (ops->mode == MTD_OOB_AUTO)
1563 len = chip->ecc.layout->oobavail;
1567 if (unlikely(ops->ooboffs >= len)) {
1568 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1569 "Attempt to start read outside oob\n");
1573 /* Do not allow reads past end of device */
1574 if (unlikely(from >= mtd->size ||
1575 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1576 (from >> chip->page_shift)) * len)) {
1577 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1578 "Attempt read beyond end of device\n");
1582 chipnr = (int)(from >> chip->chip_shift);
1583 chip->select_chip(mtd, chipnr);
1585 /* Shift to get page */
1586 realpage = (int)(from >> chip->page_shift);
1587 page = realpage & chip->pagemask;
1590 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1592 len = min(len, readlen);
1593 buf = nand_transfer_oob(chip, buf, ops, len);
1595 if (!(chip->options & NAND_NO_READRDY)) {
1597 * Apply delay or wait for ready/busy pin. Do this
1598 * before the AUTOINCR check, so no problems arise if a
1599 * chip which does auto increment is marked as
1600 * NOAUTOINCR by the board driver.
1602 if (!chip->dev_ready)
1603 udelay(chip->chip_delay);
1605 nand_wait_ready(mtd);
1612 /* Increment page address */
1615 page = realpage & chip->pagemask;
1616 /* Check, if we cross a chip boundary */
1619 chip->select_chip(mtd, -1);
1620 chip->select_chip(mtd, chipnr);
1623 /* Check, if the chip supports auto page increment
1624 * or if we have hit a block boundary.
1626 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1630 ops->oobretlen = ops->ooblen;
1635 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1636 * @mtd: MTD device structure
1637 * @from: offset to read from
1638 * @ops: oob operation description structure
1640 * NAND read data and/or out-of-band data
1642 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1643 struct mtd_oob_ops *ops)
1645 struct nand_chip *chip = mtd->priv;
1646 int ret = -ENOTSUPP;
1650 /* Do not allow reads past end of device */
1651 if (ops->datbuf && (from + ops->len) > mtd->size) {
1652 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1653 "Attempt read beyond end of device\n");
1657 nand_get_device(chip, mtd, FL_READING);
1670 ret = nand_do_read_oob(mtd, from, ops);
1672 ret = nand_do_read_ops(mtd, from, ops);
1675 nand_release_device(mtd);
1681 * nand_write_page_raw - [Intern] raw page write function
1682 * @mtd: mtd info structure
1683 * @chip: nand chip info structure
1686 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1689 chip->write_buf(mtd, buf, mtd->writesize);
1690 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1694 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1695 * @mtd: mtd info structure
1696 * @chip: nand chip info structure
1699 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1702 int i, eccsize = chip->ecc.size;
1703 int eccbytes = chip->ecc.bytes;
1704 int eccsteps = chip->ecc.steps;
1705 uint8_t *ecc_calc = chip->buffers->ecccalc;
1706 const uint8_t *p = buf;
1707 uint32_t *eccpos = chip->ecc.layout->eccpos;
1709 /* Software ecc calculation */
1710 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1711 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1713 for (i = 0; i < chip->ecc.total; i++)
1714 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1716 chip->ecc.write_page_raw(mtd, chip, buf);
1720 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1721 * @mtd: mtd info structure
1722 * @chip: nand chip info structure
1725 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1728 int i, eccsize = chip->ecc.size;
1729 int eccbytes = chip->ecc.bytes;
1730 int eccsteps = chip->ecc.steps;
1731 uint8_t *ecc_calc = chip->buffers->ecccalc;
1732 const uint8_t *p = buf;
1733 uint32_t *eccpos = chip->ecc.layout->eccpos;
1735 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1736 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1737 chip->write_buf(mtd, p, eccsize);
1738 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1741 for (i = 0; i < chip->ecc.total; i++)
1742 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1744 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1748 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1749 * @mtd: mtd info structure
1750 * @chip: nand chip info structure
1753 * The hw generator calculates the error syndrome automatically. Therefor
1754 * we need a special oob layout and handling.
1756 static void nand_write_page_syndrome(struct mtd_info *mtd,
1757 struct nand_chip *chip, const uint8_t *buf)
1759 int i, eccsize = chip->ecc.size;
1760 int eccbytes = chip->ecc.bytes;
1761 int eccsteps = chip->ecc.steps;
1762 const uint8_t *p = buf;
1763 uint8_t *oob = chip->oob_poi;
1765 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1767 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1768 chip->write_buf(mtd, p, eccsize);
1770 if (chip->ecc.prepad) {
1771 chip->write_buf(mtd, oob, chip->ecc.prepad);
1772 oob += chip->ecc.prepad;
1775 chip->ecc.calculate(mtd, p, oob);
1776 chip->write_buf(mtd, oob, eccbytes);
1779 if (chip->ecc.postpad) {
1780 chip->write_buf(mtd, oob, chip->ecc.postpad);
1781 oob += chip->ecc.postpad;
1785 /* Calculate remaining oob bytes */
1786 i = mtd->oobsize - (oob - chip->oob_poi);
1788 chip->write_buf(mtd, oob, i);
1792 * nand_write_page - [REPLACEABLE] write one page
1793 * @mtd: MTD device structure
1794 * @chip: NAND chip descriptor
1795 * @buf: the data to write
1796 * @page: page number to write
1797 * @cached: cached programming
1798 * @raw: use _raw version of write_page
1800 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1801 const uint8_t *buf, int page, int cached, int raw)
1805 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1808 chip->ecc.write_page_raw(mtd, chip, buf);
1810 chip->ecc.write_page(mtd, chip, buf);
1813 * Cached progamming disabled for now, Not sure if its worth the
1814 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1818 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1820 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1821 status = chip->waitfunc(mtd, chip);
1823 * See if operation failed and additional status checks are
1826 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1827 status = chip->errstat(mtd, chip, FL_WRITING, status,
1830 if (status & NAND_STATUS_FAIL)
1833 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1834 status = chip->waitfunc(mtd, chip);
1837 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1838 /* Send command to read back the data */
1839 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1841 if (chip->verify_buf(mtd, buf, mtd->writesize))
1848 * nand_fill_oob - [Internal] Transfer client buffer to oob
1849 * @chip: nand chip structure
1850 * @oob: oob data buffer
1851 * @ops: oob ops structure
1853 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1854 struct mtd_oob_ops *ops)
1856 size_t len = ops->ooblen;
1862 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1865 case MTD_OOB_AUTO: {
1866 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1867 uint32_t boffs = 0, woffs = ops->ooboffs;
1870 for(; free->length && len; free++, len -= bytes) {
1871 /* Write request not from offset 0 ? */
1872 if (unlikely(woffs)) {
1873 if (woffs >= free->length) {
1874 woffs -= free->length;
1877 boffs = free->offset + woffs;
1878 bytes = min_t(size_t, len,
1879 (free->length - woffs));
1882 bytes = min_t(size_t, len, free->length);
1883 boffs = free->offset;
1885 memcpy(chip->oob_poi + boffs, oob, bytes);
1896 #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
1899 * nand_do_write_ops - [Internal] NAND write with ECC
1900 * @mtd: MTD device structure
1901 * @to: offset to write to
1902 * @ops: oob operations description structure
1904 * NAND write with ECC
1906 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1907 struct mtd_oob_ops *ops)
1909 int chipnr, realpage, page, blockmask, column;
1910 struct nand_chip *chip = mtd->priv;
1911 uint32_t writelen = ops->len;
1912 uint8_t *oob = ops->oobbuf;
1913 uint8_t *buf = ops->datbuf;
1920 /* reject writes, which are not page aligned */
1921 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1922 printk(KERN_NOTICE "nand_write: "
1923 "Attempt to write not page aligned data\n");
1927 column = to & (mtd->writesize - 1);
1928 subpage = column || (writelen & (mtd->writesize - 1));
1933 chipnr = (int)(to >> chip->chip_shift);
1934 chip->select_chip(mtd, chipnr);
1936 /* Check, if it is write protected */
1937 if (nand_check_wp(mtd)) {
1938 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1942 realpage = (int)(to >> chip->page_shift);
1943 page = realpage & chip->pagemask;
1944 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1946 /* Invalidate the page cache, when we write to the cached page */
1947 if (to <= (chip->pagebuf << chip->page_shift) &&
1948 (chip->pagebuf << chip->page_shift) < (to + ops->len))
1951 /* If we're not given explicit OOB data, let it be 0xFF */
1953 memset(chip->oob_poi, 0xff, mtd->oobsize);
1956 int bytes = mtd->writesize;
1957 int cached = writelen > bytes && page != blockmask;
1958 uint8_t *wbuf = buf;
1960 /* Partial page write ? */
1961 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1963 bytes = min_t(int, bytes - column, (int) writelen);
1965 memset(chip->buffers->databuf, 0xff, mtd->writesize);
1966 memcpy(&chip->buffers->databuf[column], buf, bytes);
1967 wbuf = chip->buffers->databuf;
1971 oob = nand_fill_oob(chip, oob, ops);
1973 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1974 (ops->mode == MTD_OOB_RAW));
1986 page = realpage & chip->pagemask;
1987 /* Check, if we cross a chip boundary */
1990 chip->select_chip(mtd, -1);
1991 chip->select_chip(mtd, chipnr);
1995 ops->retlen = ops->len - writelen;
1997 ops->oobretlen = ops->ooblen;
2002 * nand_write - [MTD Interface] NAND write with ECC
2003 * @mtd: MTD device structure
2004 * @to: offset to write to
2005 * @len: number of bytes to write
2006 * @retlen: pointer to variable to store the number of written bytes
2007 * @buf: the data to write
2009 * NAND write with ECC
2011 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2012 size_t *retlen, const uint8_t *buf)
2014 struct nand_chip *chip = mtd->priv;
2017 /* Do not allow reads past end of device */
2018 if ((to + len) > mtd->size)
2023 nand_get_device(chip, mtd, FL_WRITING);
2025 chip->ops.len = len;
2026 chip->ops.datbuf = (uint8_t *)buf;
2027 chip->ops.oobbuf = NULL;
2029 ret = nand_do_write_ops(mtd, to, &chip->ops);
2031 *retlen = chip->ops.retlen;
2033 nand_release_device(mtd);
2039 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2040 * @mtd: MTD device structure
2041 * @to: offset to write to
2042 * @ops: oob operation description structure
2044 * NAND write out-of-band
2046 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2047 struct mtd_oob_ops *ops)
2049 int chipnr, page, status, len;
2050 struct nand_chip *chip = mtd->priv;
2052 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
2053 (unsigned int)to, (int)ops->ooblen);
2055 if (ops->mode == MTD_OOB_AUTO)
2056 len = chip->ecc.layout->oobavail;
2060 /* Do not allow write past end of page */
2061 if ((ops->ooboffs + ops->ooblen) > len) {
2062 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
2063 "Attempt to write past end of page\n");
2067 if (unlikely(ops->ooboffs >= len)) {
2068 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2069 "Attempt to start write outside oob\n");
2073 /* Do not allow reads past end of device */
2074 if (unlikely(to >= mtd->size ||
2075 ops->ooboffs + ops->ooblen >
2076 ((mtd->size >> chip->page_shift) -
2077 (to >> chip->page_shift)) * len)) {
2078 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2079 "Attempt write beyond end of device\n");
2083 chipnr = (int)(to >> chip->chip_shift);
2084 chip->select_chip(mtd, chipnr);
2086 /* Shift to get page */
2087 page = (int)(to >> chip->page_shift);
2090 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2091 * of my DiskOnChip 2000 test units) will clear the whole data page too
2092 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2093 * it in the doc2000 driver in August 1999. dwmw2.
2095 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2097 /* Check, if it is write protected */
2098 if (nand_check_wp(mtd))
2101 /* Invalidate the page cache, if we write to the cached page */
2102 if (page == chip->pagebuf)
2105 memset(chip->oob_poi, 0xff, mtd->oobsize);
2106 nand_fill_oob(chip, ops->oobbuf, ops);
2107 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2108 memset(chip->oob_poi, 0xff, mtd->oobsize);
2113 ops->oobretlen = ops->ooblen;
2119 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2120 * @mtd: MTD device structure
2121 * @to: offset to write to
2122 * @ops: oob operation description structure
2124 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2125 struct mtd_oob_ops *ops)
2127 struct nand_chip *chip = mtd->priv;
2128 int ret = -ENOTSUPP;
2132 /* Do not allow writes past end of device */
2133 if (ops->datbuf && (to + ops->len) > mtd->size) {
2134 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
2135 "Attempt read beyond end of device\n");
2139 nand_get_device(chip, mtd, FL_WRITING);
2152 ret = nand_do_write_oob(mtd, to, ops);
2154 ret = nand_do_write_ops(mtd, to, ops);
2157 nand_release_device(mtd);
2162 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2163 * @mtd: MTD device structure
2164 * @page: the page address of the block which will be erased
2166 * Standard erase command for NAND chips
2168 static void single_erase_cmd(struct mtd_info *mtd, int page)
2170 struct nand_chip *chip = mtd->priv;
2171 /* Send commands to erase a block */
2172 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2173 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2177 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2178 * @mtd: MTD device structure
2179 * @page: the page address of the block which will be erased
2181 * AND multi block erase command function
2182 * Erase 4 consecutive blocks
2184 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2186 struct nand_chip *chip = mtd->priv;
2187 /* Send commands to erase a block */
2188 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2189 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2190 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2191 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2192 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2196 * nand_erase - [MTD Interface] erase block(s)
2197 * @mtd: MTD device structure
2198 * @instr: erase instruction
2200 * Erase one ore more blocks
2202 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2204 return nand_erase_nand(mtd, instr, 0);
2207 #define BBT_PAGE_MASK 0xffffff3f
2209 * nand_erase_nand - [Internal] erase block(s)
2210 * @mtd: MTD device structure
2211 * @instr: erase instruction
2212 * @allowbbt: allow erasing the bbt area
2214 * Erase one ore more blocks
2216 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2219 int page, status, pages_per_block, ret, chipnr;
2220 struct nand_chip *chip = mtd->priv;
2221 loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0};
2222 unsigned int bbt_masked_page = 0xffffffff;
2225 MTDDEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%012llx, "
2226 "len = %llu\n", (unsigned long long) instr->addr,
2227 (unsigned long long) instr->len);
2229 /* Start address must align on block boundary */
2230 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2231 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2235 /* Length must align on block boundary */
2236 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2237 MTDDEBUG (MTD_DEBUG_LEVEL0,
2238 "nand_erase: Length not block aligned\n");
2242 /* Do not allow erase past end of device */
2243 if ((instr->len + instr->addr) > mtd->size) {
2244 MTDDEBUG (MTD_DEBUG_LEVEL0,
2245 "nand_erase: Erase past end of device\n");
2249 instr->fail_addr = 0xffffffff;
2251 /* Grab the lock and see if the device is available */
2252 nand_get_device(chip, mtd, FL_ERASING);
2254 /* Shift to get first page */
2255 page = (int)(instr->addr >> chip->page_shift);
2256 chipnr = (int)(instr->addr >> chip->chip_shift);
2258 /* Calculate pages in each block */
2259 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2261 /* Select the NAND device */
2262 chip->select_chip(mtd, chipnr);
2264 /* Check, if it is write protected */
2265 if (nand_check_wp(mtd)) {
2266 MTDDEBUG (MTD_DEBUG_LEVEL0,
2267 "nand_erase: Device is write protected!!!\n");
2268 instr->state = MTD_ERASE_FAILED;
2273 * If BBT requires refresh, set the BBT page mask to see if the BBT
2274 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2275 * can not be matched. This is also done when the bbt is actually
2276 * erased to avoid recusrsive updates
2278 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2279 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2281 /* Loop through the pages */
2284 instr->state = MTD_ERASING;
2288 * heck if we have a bad block, we do not erase bad blocks !
2290 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2291 chip->page_shift, 0, allowbbt)) {
2292 printk(KERN_WARNING "nand_erase: attempt to erase a "
2293 "bad block at page 0x%08x\n", page);
2294 instr->state = MTD_ERASE_FAILED;
2299 * Invalidate the page cache, if we erase the block which
2300 * contains the current cached page
2302 if (page <= chip->pagebuf && chip->pagebuf <
2303 (page + pages_per_block))
2306 chip->erase_cmd(mtd, page & chip->pagemask);
2308 status = chip->waitfunc(mtd, chip);
2311 * See if operation failed and additional status checks are
2314 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2315 status = chip->errstat(mtd, chip, FL_ERASING,
2318 /* See if block erase succeeded */
2319 if (status & NAND_STATUS_FAIL) {
2320 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
2321 "Failed erase, page 0x%08x\n", page);
2322 instr->state = MTD_ERASE_FAILED;
2323 instr->fail_addr = ((loff_t)page << chip->page_shift);
2328 * If BBT requires refresh, set the BBT rewrite flag to the
2331 if (bbt_masked_page != 0xffffffff &&
2332 (page & BBT_PAGE_MASK) == bbt_masked_page)
2333 rewrite_bbt[chipnr] =
2334 ((loff_t)page << chip->page_shift);
2336 /* Increment page address and decrement length */
2337 len -= (1 << chip->phys_erase_shift);
2338 page += pages_per_block;
2340 /* Check, if we cross a chip boundary */
2341 if (len && !(page & chip->pagemask)) {
2343 chip->select_chip(mtd, -1);
2344 chip->select_chip(mtd, chipnr);
2347 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2348 * page mask to see if this BBT should be rewritten
2350 if (bbt_masked_page != 0xffffffff &&
2351 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2352 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2356 instr->state = MTD_ERASE_DONE;
2360 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2362 /* Deselect and wake up anyone waiting on the device */
2363 nand_release_device(mtd);
2365 /* Do call back function */
2367 mtd_erase_callback(instr);
2370 * If BBT requires refresh and erase was successful, rewrite any
2371 * selected bad block tables
2373 if (bbt_masked_page == 0xffffffff || ret)
2376 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2377 if (!rewrite_bbt[chipnr])
2379 /* update the BBT for chip */
2380 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2381 "(%d:0x%0llx 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2382 chip->bbt_td->pages[chipnr]);
2383 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2386 /* Return more or less happy */
2391 * nand_sync - [MTD Interface] sync
2392 * @mtd: MTD device structure
2394 * Sync is actually a wait for chip ready function
2396 static void nand_sync(struct mtd_info *mtd)
2398 struct nand_chip *chip = mtd->priv;
2400 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2402 /* Grab the lock and see if the device is available */
2403 nand_get_device(chip, mtd, FL_SYNCING);
2404 /* Release it and go back */
2405 nand_release_device(mtd);
2409 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2410 * @mtd: MTD device structure
2411 * @offs: offset relative to mtd start
2413 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2415 /* Check for invalid offset */
2416 if (offs > mtd->size)
2419 return nand_block_checkbad(mtd, offs, 1, 0);
2423 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2424 * @mtd: MTD device structure
2425 * @ofs: offset relative to mtd start
2427 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2429 struct nand_chip *chip = mtd->priv;
2432 if ((ret = nand_block_isbad(mtd, ofs))) {
2433 /* If it was bad already, return success and do nothing. */
2439 return chip->block_markbad(mtd, ofs);
2443 * nand_suspend - [MTD Interface] Suspend the NAND flash
2444 * @mtd: MTD device structure
2446 static int nand_suspend(struct mtd_info *mtd)
2448 struct nand_chip *chip = mtd->priv;
2450 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2454 * nand_resume - [MTD Interface] Resume the NAND flash
2455 * @mtd: MTD device structure
2457 static void nand_resume(struct mtd_info *mtd)
2459 struct nand_chip *chip = mtd->priv;
2461 if (chip->state == FL_PM_SUSPENDED)
2462 nand_release_device(mtd);
2464 printk(KERN_ERR "nand_resume() called for a chip which is not "
2465 "in suspended state\n");
2469 * Set default functions
2471 static void nand_set_defaults(struct nand_chip *chip, int busw)
2473 /* check for proper chip_delay setup, set 20us if not */
2474 if (!chip->chip_delay)
2475 chip->chip_delay = 20;
2477 /* check, if a user supplied command function given */
2478 if (chip->cmdfunc == NULL)
2479 chip->cmdfunc = nand_command;
2481 /* check, if a user supplied wait function given */
2482 if (chip->waitfunc == NULL)
2483 chip->waitfunc = nand_wait;
2485 if (!chip->select_chip)
2486 chip->select_chip = nand_select_chip;
2487 if (!chip->read_byte)
2488 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2489 if (!chip->read_word)
2490 chip->read_word = nand_read_word;
2491 if (!chip->block_bad)
2492 chip->block_bad = nand_block_bad;
2493 if (!chip->block_markbad)
2494 chip->block_markbad = nand_default_block_markbad;
2495 if (!chip->write_buf)
2496 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2497 if (!chip->read_buf)
2498 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2499 if (!chip->verify_buf)
2500 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2501 if (!chip->scan_bbt)
2502 chip->scan_bbt = nand_default_bbt;
2504 if (!chip->controller) {
2505 chip->controller = &chip->hwcontrol;
2507 /* XXX U-BOOT XXX */
2509 spin_lock_init(&chip->controller->lock);
2510 init_waitqueue_head(&chip->controller->wq);
2517 * Get the flash and manufacturer id and lookup if the type is supported
2519 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2520 struct nand_chip *chip,
2521 int busw, int *maf_id)
2523 struct nand_flash_dev *type = NULL;
2524 int i, dev_id, maf_idx;
2525 int tmp_id, tmp_manf;
2527 /* Select the device */
2528 chip->select_chip(mtd, 0);
2531 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2534 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2536 /* Send the command for reading device ID */
2537 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2539 /* Read manufacturer and device IDs */
2540 *maf_id = chip->read_byte(mtd);
2541 dev_id = chip->read_byte(mtd);
2543 /* Try again to make sure, as some systems the bus-hold or other
2544 * interface concerns can cause random data which looks like a
2545 * possibly credible NAND flash to appear. If the two results do
2546 * not match, ignore the device completely.
2549 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2551 /* Read manufacturer and device IDs */
2553 tmp_manf = chip->read_byte(mtd);
2554 tmp_id = chip->read_byte(mtd);
2556 if (tmp_manf != *maf_id || tmp_id != dev_id) {
2557 printk(KERN_INFO "%s: second ID read did not match "
2558 "%02x,%02x against %02x,%02x\n", __func__,
2559 *maf_id, dev_id, tmp_manf, tmp_id);
2560 return ERR_PTR(-ENODEV);
2563 /* Lookup the flash id */
2564 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2565 if (dev_id == nand_flash_ids[i].id) {
2566 type = &nand_flash_ids[i];
2572 return ERR_PTR(-ENODEV);
2575 mtd->name = type->name;
2577 chip->chipsize = (uint64_t)type->chipsize << 20;
2579 /* Newer devices have all the information in additional id bytes */
2580 if (!type->pagesize) {
2582 /* The 3rd id byte holds MLC / multichip data */
2583 chip->cellinfo = chip->read_byte(mtd);
2584 /* The 4th id byte is the important one */
2585 extid = chip->read_byte(mtd);
2587 mtd->writesize = 1024 << (extid & 0x3);
2590 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2592 /* Calc blocksize. Blocksize is multiples of 64KiB */
2593 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2595 /* Get buswidth information */
2596 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2600 * Old devices have chip data hardcoded in the device id table
2602 mtd->erasesize = type->erasesize;
2603 mtd->writesize = type->pagesize;
2604 mtd->oobsize = mtd->writesize / 32;
2605 busw = type->options & NAND_BUSWIDTH_16;
2608 /* Try to identify manufacturer */
2609 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2610 if (nand_manuf_ids[maf_idx].id == *maf_id)
2615 * Check, if buswidth is correct. Hardware drivers should set
2618 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2619 printk(KERN_INFO "NAND device: Manufacturer ID:"
2620 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2621 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2622 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2623 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2625 return ERR_PTR(-EINVAL);
2628 /* Calculate the address shift from the page size */
2629 chip->page_shift = ffs(mtd->writesize) - 1;
2630 /* Convert chipsize to number of pages per chip -1. */
2631 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2633 chip->bbt_erase_shift = chip->phys_erase_shift =
2634 ffs(mtd->erasesize) - 1;
2635 if (chip->chipsize & 0xffffffff)
2636 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2638 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 31;
2640 /* Set the bad block position */
2641 chip->badblockpos = mtd->writesize > 512 ?
2642 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2644 /* Get chip options, preserve non chip based options */
2645 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2646 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2649 * Set chip as a default. Board drivers can override it, if necessary
2651 chip->options |= NAND_NO_AUTOINCR;
2653 /* Check if chip is a not a samsung device. Do not clear the
2654 * options for chips which are not having an extended id.
2656 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2657 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2659 /* Check for AND chips with 4 page planes */
2660 if (chip->options & NAND_4PAGE_ARRAY)
2661 chip->erase_cmd = multi_erase_cmd;
2663 chip->erase_cmd = single_erase_cmd;
2665 /* Do not replace user supplied command function ! */
2666 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2667 chip->cmdfunc = nand_command_lp;
2669 MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2670 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2671 nand_manuf_ids[maf_idx].name, type->name);
2677 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2678 * @mtd: MTD device structure
2679 * @maxchips: Number of chips to scan for
2681 * This is the first phase of the normal nand_scan() function. It
2682 * reads the flash ID and sets up MTD fields accordingly.
2684 * The mtd->owner field must be set to the module of the caller.
2686 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2688 int i, busw, nand_maf_id;
2689 struct nand_chip *chip = mtd->priv;
2690 struct nand_flash_dev *type;
2692 /* Get buswidth to select the correct functions */
2693 busw = chip->options & NAND_BUSWIDTH_16;
2694 /* Set the default functions */
2695 nand_set_defaults(chip, busw);
2697 /* Read the flash type */
2698 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2701 #ifndef CONFIG_SYS_NAND_QUIET_TEST
2702 printk(KERN_WARNING "No NAND device found!!!\n");
2704 chip->select_chip(mtd, -1);
2705 return PTR_ERR(type);
2708 /* Check for a chip array */
2709 for (i = 1; i < maxchips; i++) {
2710 chip->select_chip(mtd, i);
2711 /* See comment in nand_get_flash_type for reset */
2712 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2713 /* Send the command for reading device ID */
2714 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2715 /* Read manufacturer and device IDs */
2716 if (nand_maf_id != chip->read_byte(mtd) ||
2717 type->id != chip->read_byte(mtd))
2722 printk(KERN_INFO "%d NAND chips detected\n", i);
2725 /* Store the number of chips and calc total size for mtd */
2727 mtd->size = i * chip->chipsize;
2734 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2735 * @mtd: MTD device structure
2737 * This is the second phase of the normal nand_scan() function. It
2738 * fills out all the uninitialized function pointers with the defaults
2739 * and scans for a bad block table if appropriate.
2741 int nand_scan_tail(struct mtd_info *mtd)
2744 struct nand_chip *chip = mtd->priv;
2746 if (!(chip->options & NAND_OWN_BUFFERS))
2747 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2751 /* Set the internal oob buffer location, just after the page data */
2752 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2755 * If no default placement scheme is given, select an appropriate one
2757 if (!chip->ecc.layout) {
2758 switch (mtd->oobsize) {
2760 chip->ecc.layout = &nand_oob_8;
2763 chip->ecc.layout = &nand_oob_16;
2766 chip->ecc.layout = &nand_oob_64;
2769 chip->ecc.layout = &nand_oob_128;
2772 printk(KERN_WARNING "No oob scheme defined for "
2773 "oobsize %d\n", mtd->oobsize);
2777 if (!chip->write_page)
2778 chip->write_page = nand_write_page;
2781 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2782 * selected and we have 256 byte pagesize fallback to software ECC
2784 if (!chip->ecc.read_page_raw)
2785 chip->ecc.read_page_raw = nand_read_page_raw;
2786 if (!chip->ecc.write_page_raw)
2787 chip->ecc.write_page_raw = nand_write_page_raw;
2789 switch (chip->ecc.mode) {
2790 case NAND_ECC_HW_OOB_FIRST:
2791 /* Similar to NAND_ECC_HW, but a separate read_page handle */
2792 if (!chip->ecc.calculate || !chip->ecc.correct ||
2794 printk(KERN_WARNING "No ECC functions supplied, "
2795 "Hardware ECC not possible\n");
2798 if (!chip->ecc.read_page)
2799 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
2802 /* Use standard hwecc read page function ? */
2803 if (!chip->ecc.read_page)
2804 chip->ecc.read_page = nand_read_page_hwecc;
2805 if (!chip->ecc.write_page)
2806 chip->ecc.write_page = nand_write_page_hwecc;
2807 if (!chip->ecc.read_oob)
2808 chip->ecc.read_oob = nand_read_oob_std;
2809 if (!chip->ecc.write_oob)
2810 chip->ecc.write_oob = nand_write_oob_std;
2812 case NAND_ECC_HW_SYNDROME:
2813 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2814 !chip->ecc.hwctl) &&
2815 (!chip->ecc.read_page ||
2816 chip->ecc.read_page == nand_read_page_hwecc ||
2817 !chip->ecc.write_page ||
2818 chip->ecc.write_page == nand_write_page_hwecc)) {
2819 printk(KERN_WARNING "No ECC functions supplied, "
2820 "Hardware ECC not possible\n");
2823 /* Use standard syndrome read/write page function ? */
2824 if (!chip->ecc.read_page)
2825 chip->ecc.read_page = nand_read_page_syndrome;
2826 if (!chip->ecc.write_page)
2827 chip->ecc.write_page = nand_write_page_syndrome;
2828 if (!chip->ecc.read_oob)
2829 chip->ecc.read_oob = nand_read_oob_syndrome;
2830 if (!chip->ecc.write_oob)
2831 chip->ecc.write_oob = nand_write_oob_syndrome;
2833 if (mtd->writesize >= chip->ecc.size)
2835 printk(KERN_WARNING "%d byte HW ECC not possible on "
2836 "%d byte page size, fallback to SW ECC\n",
2837 chip->ecc.size, mtd->writesize);
2838 chip->ecc.mode = NAND_ECC_SOFT;
2841 chip->ecc.calculate = nand_calculate_ecc;
2842 chip->ecc.correct = nand_correct_data;
2843 chip->ecc.read_page = nand_read_page_swecc;
2844 chip->ecc.read_subpage = nand_read_subpage;
2845 chip->ecc.write_page = nand_write_page_swecc;
2846 chip->ecc.read_oob = nand_read_oob_std;
2847 chip->ecc.write_oob = nand_write_oob_std;
2848 chip->ecc.size = 256;
2849 chip->ecc.bytes = 3;
2853 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2854 "This is not recommended !!\n");
2855 chip->ecc.read_page = nand_read_page_raw;
2856 chip->ecc.write_page = nand_write_page_raw;
2857 chip->ecc.read_oob = nand_read_oob_std;
2858 chip->ecc.write_oob = nand_write_oob_std;
2859 chip->ecc.size = mtd->writesize;
2860 chip->ecc.bytes = 0;
2864 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2870 * The number of bytes available for a client to place data into
2871 * the out of band area
2873 chip->ecc.layout->oobavail = 0;
2874 for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
2875 chip->ecc.layout->oobavail +=
2876 chip->ecc.layout->oobfree[i].length;
2877 mtd->oobavail = chip->ecc.layout->oobavail;
2880 * Set the number of read / write steps for one page depending on ECC
2883 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2884 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2885 printk(KERN_WARNING "Invalid ecc parameters\n");
2888 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2891 * Allow subpage writes up to ecc.steps. Not possible for MLC
2894 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2895 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2896 switch(chip->ecc.steps) {
2898 mtd->subpage_sft = 1;
2903 mtd->subpage_sft = 2;
2907 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2909 /* Initialize state */
2910 chip->state = FL_READY;
2912 /* De-select the device */
2913 chip->select_chip(mtd, -1);
2915 /* Invalidate the pagebuffer reference */
2918 /* Fill in remaining MTD driver data */
2919 mtd->type = MTD_NANDFLASH;
2920 mtd->flags = MTD_CAP_NANDFLASH;
2921 mtd->erase = nand_erase;
2923 mtd->unpoint = NULL;
2924 mtd->read = nand_read;
2925 mtd->write = nand_write;
2926 mtd->read_oob = nand_read_oob;
2927 mtd->write_oob = nand_write_oob;
2928 mtd->sync = nand_sync;
2931 mtd->suspend = nand_suspend;
2932 mtd->resume = nand_resume;
2933 mtd->block_isbad = nand_block_isbad;
2934 mtd->block_markbad = nand_block_markbad;
2936 /* propagate ecc.layout to mtd_info */
2937 mtd->ecclayout = chip->ecc.layout;
2939 /* Check, if we should skip the bad block table scan */
2940 if (chip->options & NAND_SKIP_BBTSCAN)
2941 chip->options |= NAND_BBT_SCANNED;
2946 /* module_text_address() isn't exported, and it's mostly a pointless
2947 test if this is a module _anyway_ -- they'd have to try _really_ hard
2948 to call us from in-kernel code if the core NAND support is modular. */
2950 #define caller_is_module() (1)
2952 #define caller_is_module() \
2953 module_text_address((unsigned long)__builtin_return_address(0))
2957 * nand_scan - [NAND Interface] Scan for the NAND device
2958 * @mtd: MTD device structure
2959 * @maxchips: Number of chips to scan for
2961 * This fills out all the uninitialized function pointers
2962 * with the defaults.
2963 * The flash ID is read and the mtd/chip structures are
2964 * filled with the appropriate values.
2965 * The mtd->owner field must be set to the module of the caller
2968 int nand_scan(struct mtd_info *mtd, int maxchips)
2972 /* Many callers got this wrong, so check for it for a while... */
2973 /* XXX U-BOOT XXX */
2975 if (!mtd->owner && caller_is_module()) {
2976 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2981 ret = nand_scan_ident(mtd, maxchips);
2983 ret = nand_scan_tail(mtd);
2988 * nand_release - [NAND Interface] Free resources held by the NAND device
2989 * @mtd: MTD device structure
2991 void nand_release(struct mtd_info *mtd)
2993 struct nand_chip *chip = mtd->priv;
2995 #ifdef CONFIG_MTD_PARTITIONS
2996 /* Deregister partitions */
2997 del_mtd_partitions(mtd);
2999 /* Deregister the device */
3000 /* XXX U-BOOT XXX */
3002 del_mtd_device(mtd);
3005 /* Free bad block table memory */
3007 if (!(chip->options & NAND_OWN_BUFFERS))
3008 kfree(chip->buffers);
3011 /* XXX U-BOOT XXX */
3013 EXPORT_SYMBOL_GPL(nand_scan);
3014 EXPORT_SYMBOL_GPL(nand_scan_ident);
3015 EXPORT_SYMBOL_GPL(nand_scan_tail);
3016 EXPORT_SYMBOL_GPL(nand_release);
3018 static int __init nand_base_init(void)
3020 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3024 static void __exit nand_base_exit(void)
3026 led_trigger_unregister_simple(nand_led_trigger);
3029 module_init(nand_base_init);
3030 module_exit(nand_base_exit);
3032 MODULE_LICENSE("GPL");
3033 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
3034 MODULE_DESCRIPTION("Generic NAND flash driver code");