5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/tech/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
28 * This program is free software; you can redistribute it and/or modify
29 * it under the terms of the GNU General Public License version 2 as
30 * published by the Free Software Foundation.
36 #include <linux/module.h>
37 #include <linux/delay.h>
38 #include <linux/errno.h>
39 #include <linux/err.h>
40 #include <linux/sched.h>
41 #include <linux/slab.h>
42 #include <linux/types.h>
43 #include <linux/mtd/mtd.h>
44 #include <linux/mtd/nand.h>
45 #include <linux/mtd/nand_ecc.h>
46 #include <linux/mtd/compatmac.h>
47 #include <linux/interrupt.h>
48 #include <linux/bitops.h>
49 #include <linux/leds.h>
52 #ifdef CONFIG_MTD_PARTITIONS
53 #include <linux/mtd/partitions.h>
60 #define ENOTSUPP 524 /* Operation is not supported */
62 #if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
66 #include <linux/err.h>
67 #include <linux/mtd/compat.h>
68 #include <linux/mtd/mtd.h>
69 #include <linux/mtd/nand.h>
70 #include <linux/mtd/nand_ecc.h>
73 #include <asm/errno.h>
75 #ifdef CONFIG_JFFS2_NAND
76 #include <jffs2/jffs2.h>
79 /* Define default oob placement schemes for large and small page devices */
80 static struct nand_ecclayout nand_oob_8 = {
90 static struct nand_ecclayout nand_oob_16 = {
92 .eccpos = {0, 1, 2, 3, 6, 7},
98 static struct nand_ecclayout nand_oob_64 = {
101 40, 41, 42, 43, 44, 45, 46, 47,
102 48, 49, 50, 51, 52, 53, 54, 55,
103 56, 57, 58, 59, 60, 61, 62, 63},
109 static struct nand_ecclayout nand_oob_128 = {
112 80, 81, 82, 83, 84, 85, 86, 87,
113 88, 89, 90, 91, 92, 93, 94, 95,
114 96, 97, 98, 99, 100, 101, 102, 103,
115 104, 105, 106, 107, 108, 109, 110, 111,
116 112, 113, 114, 115, 116, 117, 118, 119,
117 120, 121, 122, 123, 124, 125, 126, 127},
124 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
127 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
128 struct mtd_oob_ops *ops);
130 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
133 * For devices which display every fart in the system on a seperate LED. Is
134 * compiled away when LED support is disabled.
138 DEFINE_LED_TRIGGER(nand_led_trigger);
142 * nand_release_device - [GENERIC] release chip
143 * @mtd: MTD device structure
145 * Deselect, release chip lock and wake up anyone waiting on the device
149 static void nand_release_device(struct mtd_info *mtd)
151 struct nand_chip *chip = mtd->priv;
153 /* De-select the NAND device */
154 chip->select_chip(mtd, -1);
156 /* Release the controller and the chip */
157 spin_lock(&chip->controller->lock);
158 chip->controller->active = NULL;
159 chip->state = FL_READY;
160 wake_up(&chip->controller->wq);
161 spin_unlock(&chip->controller->lock);
164 static void nand_release_device (struct mtd_info *mtd)
166 struct nand_chip *this = mtd->priv;
167 this->select_chip(mtd, -1); /* De-select the NAND device */
172 * nand_read_byte - [DEFAULT] read one byte from the chip
173 * @mtd: MTD device structure
175 * Default read function for 8bit buswith
177 static uint8_t nand_read_byte(struct mtd_info *mtd)
179 struct nand_chip *chip = mtd->priv;
180 return readb(chip->IO_ADDR_R);
184 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
185 * @mtd: MTD device structure
187 * Default read function for 16bit buswith with
188 * endianess conversion
190 static uint8_t nand_read_byte16(struct mtd_info *mtd)
192 struct nand_chip *chip = mtd->priv;
193 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
197 * nand_read_word - [DEFAULT] read one word from the chip
198 * @mtd: MTD device structure
200 * Default read function for 16bit buswith without
201 * endianess conversion
203 static u16 nand_read_word(struct mtd_info *mtd)
205 struct nand_chip *chip = mtd->priv;
206 return readw(chip->IO_ADDR_R);
210 * nand_select_chip - [DEFAULT] control CE line
211 * @mtd: MTD device structure
212 * @chipnr: chipnumber to select, -1 for deselect
214 * Default select function for 1 chip devices.
216 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
218 struct nand_chip *chip = mtd->priv;
222 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
233 * nand_write_buf - [DEFAULT] write buffer to chip
234 * @mtd: MTD device structure
236 * @len: number of bytes to write
238 * Default write function for 8bit buswith
240 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
243 struct nand_chip *chip = mtd->priv;
245 for (i = 0; i < len; i++)
246 writeb(buf[i], chip->IO_ADDR_W);
250 * nand_read_buf - [DEFAULT] read chip data into buffer
251 * @mtd: MTD device structure
252 * @buf: buffer to store date
253 * @len: number of bytes to read
255 * Default read function for 8bit buswith
257 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
260 struct nand_chip *chip = mtd->priv;
262 for (i = 0; i < len; i++)
263 buf[i] = readb(chip->IO_ADDR_R);
267 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
268 * @mtd: MTD device structure
269 * @buf: buffer containing the data to compare
270 * @len: number of bytes to compare
272 * Default verify function for 8bit buswith
274 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
277 struct nand_chip *chip = mtd->priv;
279 for (i = 0; i < len; i++)
280 if (buf[i] != readb(chip->IO_ADDR_R))
286 * nand_write_buf16 - [DEFAULT] write buffer to chip
287 * @mtd: MTD device structure
289 * @len: number of bytes to write
291 * Default write function for 16bit buswith
293 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
296 struct nand_chip *chip = mtd->priv;
297 u16 *p = (u16 *) buf;
300 for (i = 0; i < len; i++)
301 writew(p[i], chip->IO_ADDR_W);
306 * nand_read_buf16 - [DEFAULT] read chip data into buffer
307 * @mtd: MTD device structure
308 * @buf: buffer to store date
309 * @len: number of bytes to read
311 * Default read function for 16bit buswith
313 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
316 struct nand_chip *chip = mtd->priv;
317 u16 *p = (u16 *) buf;
320 for (i = 0; i < len; i++)
321 p[i] = readw(chip->IO_ADDR_R);
325 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
326 * @mtd: MTD device structure
327 * @buf: buffer containing the data to compare
328 * @len: number of bytes to compare
330 * Default verify function for 16bit buswith
332 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
335 struct nand_chip *chip = mtd->priv;
336 u16 *p = (u16 *) buf;
339 for (i = 0; i < len; i++)
340 if (p[i] != readw(chip->IO_ADDR_R))
347 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
348 * @mtd: MTD device structure
349 * @ofs: offset from device start
350 * @getchip: 0, if the chip is already selected
352 * Check, if the block is bad.
354 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
356 int page, chipnr, res = 0;
357 struct nand_chip *chip = mtd->priv;
360 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
363 chipnr = (int)(ofs >> chip->chip_shift);
365 nand_get_device(chip, mtd, FL_READING);
367 /* Select the NAND device */
368 chip->select_chip(mtd, chipnr);
371 if (chip->options & NAND_BUSWIDTH_16) {
372 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
374 bad = cpu_to_le16(chip->read_word(mtd));
375 if (chip->badblockpos & 0x1)
377 if ((bad & 0xFF) != 0xff)
380 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
381 if (chip->read_byte(mtd) != 0xff)
386 nand_release_device(mtd);
392 * nand_default_block_markbad - [DEFAULT] mark a block bad
393 * @mtd: MTD device structure
394 * @ofs: offset from device start
396 * This is the default implementation, which can be overridden by
397 * a hardware specific driver.
399 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
401 struct nand_chip *chip = mtd->priv;
402 uint8_t buf[2] = { 0, 0 };
405 /* Get block number */
406 block = (int)(ofs >> chip->bbt_erase_shift);
408 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
410 /* Do we have a flash based bad block table ? */
411 if (chip->options & NAND_USE_FLASH_BBT)
412 ret = nand_update_bbt(mtd, ofs);
414 /* We write two bytes, so we dont have to mess with 16 bit
418 chip->ops.len = chip->ops.ooblen = 2;
419 chip->ops.datbuf = NULL;
420 chip->ops.oobbuf = buf;
421 chip->ops.ooboffs = chip->badblockpos & ~0x01;
423 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
426 mtd->ecc_stats.badblocks++;
431 * nand_check_wp - [GENERIC] check if the chip is write protected
432 * @mtd: MTD device structure
433 * Check, if the device is write protected
435 * The function expects, that the device is already selected
437 static int nand_check_wp(struct mtd_info *mtd)
439 struct nand_chip *chip = mtd->priv;
440 /* Check the WP bit */
441 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
442 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
446 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
447 * @mtd: MTD device structure
448 * @ofs: offset from device start
449 * @getchip: 0, if the chip is already selected
450 * @allowbbt: 1, if its allowed to access the bbt area
452 * Check, if the block is bad. Either by reading the bad block table or
453 * calling of the scan function.
455 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
458 struct nand_chip *chip = mtd->priv;
461 return chip->block_bad(mtd, ofs, getchip);
463 /* Return info from the table */
464 return nand_isbad_bbt(mtd, ofs, allowbbt);
468 * Wait for the ready pin, after a command
469 * The timeout is catched later.
473 void nand_wait_ready(struct mtd_info *mtd)
475 struct nand_chip *chip = mtd->priv;
476 unsigned long timeo = jiffies + 2;
478 led_trigger_event(nand_led_trigger, LED_FULL);
479 /* wait until command is processed or timeout occures */
481 if (chip->dev_ready(mtd))
483 touch_softlockup_watchdog();
484 } while (time_before(jiffies, timeo));
485 led_trigger_event(nand_led_trigger, LED_OFF);
487 EXPORT_SYMBOL_GPL(nand_wait_ready);
489 void nand_wait_ready(struct mtd_info *mtd)
491 struct nand_chip *chip = mtd->priv;
492 nand_wait(mtd, chip);
497 * nand_command - [DEFAULT] Send command to NAND device
498 * @mtd: MTD device structure
499 * @command: the command to be sent
500 * @column: the column address for this command, -1 if none
501 * @page_addr: the page address for this command, -1 if none
503 * Send command to NAND device. This function is used for small page
504 * devices (256/512 Bytes per page)
506 static void nand_command(struct mtd_info *mtd, unsigned int command,
507 int column, int page_addr)
509 register struct nand_chip *chip = mtd->priv;
510 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
513 * Write out the command to the device.
515 if (command == NAND_CMD_SEQIN) {
518 if (column >= mtd->writesize) {
520 column -= mtd->writesize;
521 readcmd = NAND_CMD_READOOB;
522 } else if (column < 256) {
523 /* First 256 bytes --> READ0 */
524 readcmd = NAND_CMD_READ0;
527 readcmd = NAND_CMD_READ1;
529 chip->cmd_ctrl(mtd, readcmd, ctrl);
530 ctrl &= ~NAND_CTRL_CHANGE;
532 chip->cmd_ctrl(mtd, command, ctrl);
535 * Address cycle, when necessary
537 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
538 /* Serially input address */
540 /* Adjust columns for 16 bit buswidth */
541 if (chip->options & NAND_BUSWIDTH_16)
543 chip->cmd_ctrl(mtd, column, ctrl);
544 ctrl &= ~NAND_CTRL_CHANGE;
546 if (page_addr != -1) {
547 chip->cmd_ctrl(mtd, page_addr, ctrl);
548 ctrl &= ~NAND_CTRL_CHANGE;
549 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
550 /* One more address cycle for devices > 32MiB */
551 if (chip->chipsize > (32 << 20))
552 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
554 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
557 * program and erase have their own busy handlers
558 * status and sequential in needs no delay
562 case NAND_CMD_PAGEPROG:
563 case NAND_CMD_ERASE1:
564 case NAND_CMD_ERASE2:
566 case NAND_CMD_STATUS:
572 udelay(chip->chip_delay);
573 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
574 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
576 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
577 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
580 /* This applies to read commands */
583 * If we don't have access to the busy pin, we apply the given
586 if (!chip->dev_ready) {
587 udelay(chip->chip_delay);
591 /* Apply this short delay always to ensure that we do wait tWB in
592 * any case on any machine. */
595 nand_wait_ready(mtd);
599 * nand_command_lp - [DEFAULT] Send command to NAND large page device
600 * @mtd: MTD device structure
601 * @command: the command to be sent
602 * @column: the column address for this command, -1 if none
603 * @page_addr: the page address for this command, -1 if none
605 * Send command to NAND device. This is the version for the new large page
606 * devices We dont have the separate regions as we have in the small page
607 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
609 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
610 int column, int page_addr)
612 register struct nand_chip *chip = mtd->priv;
614 /* Emulate NAND_CMD_READOOB */
615 if (command == NAND_CMD_READOOB) {
616 column += mtd->writesize;
617 command = NAND_CMD_READ0;
620 /* Command latch cycle */
621 chip->cmd_ctrl(mtd, command & 0xff,
622 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
624 if (column != -1 || page_addr != -1) {
625 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
627 /* Serially input address */
629 /* Adjust columns for 16 bit buswidth */
630 if (chip->options & NAND_BUSWIDTH_16)
632 chip->cmd_ctrl(mtd, column, ctrl);
633 ctrl &= ~NAND_CTRL_CHANGE;
634 chip->cmd_ctrl(mtd, column >> 8, ctrl);
636 if (page_addr != -1) {
637 chip->cmd_ctrl(mtd, page_addr, ctrl);
638 chip->cmd_ctrl(mtd, page_addr >> 8,
639 NAND_NCE | NAND_ALE);
640 /* One more address cycle for devices > 128MiB */
641 if (chip->chipsize > (128 << 20))
642 chip->cmd_ctrl(mtd, page_addr >> 16,
643 NAND_NCE | NAND_ALE);
646 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
649 * program and erase have their own busy handlers
650 * status, sequential in, and deplete1 need no delay
654 case NAND_CMD_CACHEDPROG:
655 case NAND_CMD_PAGEPROG:
656 case NAND_CMD_ERASE1:
657 case NAND_CMD_ERASE2:
660 case NAND_CMD_STATUS:
661 case NAND_CMD_DEPLETE1:
665 * read error status commands require only a short delay
667 case NAND_CMD_STATUS_ERROR:
668 case NAND_CMD_STATUS_ERROR0:
669 case NAND_CMD_STATUS_ERROR1:
670 case NAND_CMD_STATUS_ERROR2:
671 case NAND_CMD_STATUS_ERROR3:
672 udelay(chip->chip_delay);
678 udelay(chip->chip_delay);
679 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
680 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
681 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
682 NAND_NCE | NAND_CTRL_CHANGE);
683 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
686 case NAND_CMD_RNDOUT:
687 /* No ready / busy check necessary */
688 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
689 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
690 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
691 NAND_NCE | NAND_CTRL_CHANGE);
695 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
696 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
697 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
698 NAND_NCE | NAND_CTRL_CHANGE);
700 /* This applies to read commands */
703 * If we don't have access to the busy pin, we apply the given
706 if (!chip->dev_ready) {
707 udelay(chip->chip_delay);
712 /* Apply this short delay always to ensure that we do wait tWB in
713 * any case on any machine. */
716 nand_wait_ready(mtd);
720 * nand_get_device - [GENERIC] Get chip for selected access
721 * @chip: the nand chip descriptor
722 * @mtd: MTD device structure
723 * @new_state: the state which is requested
725 * Get the device and lock it for exclusive access
730 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
732 spinlock_t *lock = &chip->controller->lock;
733 wait_queue_head_t *wq = &chip->controller->wq;
734 DECLARE_WAITQUEUE(wait, current);
738 /* Hardware controller shared among independend devices */
739 /* Hardware controller shared among independend devices */
740 if (!chip->controller->active)
741 chip->controller->active = chip;
743 if (chip->controller->active == chip && chip->state == FL_READY) {
744 chip->state = new_state;
748 if (new_state == FL_PM_SUSPENDED) {
750 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
752 set_current_state(TASK_UNINTERRUPTIBLE);
753 add_wait_queue(wq, &wait);
756 remove_wait_queue(wq, &wait);
760 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
767 * nand_wait - [DEFAULT] wait until the command is done
768 * @mtd: MTD device structure
769 * @chip: NAND chip structure
771 * Wait for command done. This applies to erase and program only
772 * Erase can take up to 400ms and program up to 20ms according to
773 * general NAND and SmartMedia specs
777 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
780 unsigned long timeo = jiffies;
781 int status, state = chip->state;
783 if (state == FL_ERASING)
784 timeo += (HZ * 400) / 1000;
786 timeo += (HZ * 20) / 1000;
788 led_trigger_event(nand_led_trigger, LED_FULL);
790 /* Apply this short delay always to ensure that we do wait tWB in
791 * any case on any machine. */
794 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
795 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
797 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
799 while (time_before(jiffies, timeo)) {
800 if (chip->dev_ready) {
801 if (chip->dev_ready(mtd))
804 if (chip->read_byte(mtd) & NAND_STATUS_READY)
809 led_trigger_event(nand_led_trigger, LED_OFF);
811 status = (int)chip->read_byte(mtd);
815 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
818 int state = this->state;
820 if (state == FL_ERASING)
821 timeo = (CFG_HZ * 400) / 1000;
823 timeo = (CFG_HZ * 20) / 1000;
825 if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
826 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
828 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
833 if (get_timer(0) > timeo) {
838 if (this->dev_ready) {
839 if (this->dev_ready(mtd))
842 if (this->read_byte(mtd) & NAND_STATUS_READY)
846 #ifdef PPCHAMELON_NAND_TIMER_HACK
848 while (get_timer(0) < 10);
849 #endif /* PPCHAMELON_NAND_TIMER_HACK */
851 return this->read_byte(mtd);
856 * nand_read_page_raw - [Intern] read raw page data without ecc
857 * @mtd: mtd info structure
858 * @chip: nand chip info structure
859 * @buf: buffer to store read data
861 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
864 chip->read_buf(mtd, buf, mtd->writesize);
865 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
870 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
871 * @mtd: mtd info structure
872 * @chip: nand chip info structure
873 * @buf: buffer to store read data
875 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
878 int i, eccsize = chip->ecc.size;
879 int eccbytes = chip->ecc.bytes;
880 int eccsteps = chip->ecc.steps;
882 uint8_t *ecc_calc = chip->buffers->ecccalc;
883 uint8_t *ecc_code = chip->buffers->ecccode;
884 uint32_t *eccpos = chip->ecc.layout->eccpos;
886 chip->ecc.read_page_raw(mtd, chip, buf);
888 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
889 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
891 for (i = 0; i < chip->ecc.total; i++)
892 ecc_code[i] = chip->oob_poi[eccpos[i]];
894 eccsteps = chip->ecc.steps;
897 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
900 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
902 mtd->ecc_stats.failed++;
904 mtd->ecc_stats.corrected += stat;
910 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
911 * @mtd: mtd info structure
912 * @chip: nand chip info structure
913 * @buf: buffer to store read data
915 * Not for syndrome calculating ecc controllers which need a special oob layout
917 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
920 int i, eccsize = chip->ecc.size;
921 int eccbytes = chip->ecc.bytes;
922 int eccsteps = chip->ecc.steps;
924 uint8_t *ecc_calc = chip->buffers->ecccalc;
925 uint8_t *ecc_code = chip->buffers->ecccode;
926 uint32_t *eccpos = chip->ecc.layout->eccpos;
928 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
929 chip->ecc.hwctl(mtd, NAND_ECC_READ);
930 chip->read_buf(mtd, p, eccsize);
931 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
933 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
935 for (i = 0; i < chip->ecc.total; i++)
936 ecc_code[i] = chip->oob_poi[eccpos[i]];
938 eccsteps = chip->ecc.steps;
941 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
944 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
946 mtd->ecc_stats.failed++;
948 mtd->ecc_stats.corrected += stat;
954 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
955 * @mtd: mtd info structure
956 * @chip: nand chip info structure
957 * @buf: buffer to store read data
959 * The hw generator calculates the error syndrome automatically. Therefor
960 * we need a special oob layout and handling.
962 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
965 int i, eccsize = chip->ecc.size;
966 int eccbytes = chip->ecc.bytes;
967 int eccsteps = chip->ecc.steps;
969 uint8_t *oob = chip->oob_poi;
971 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
974 chip->ecc.hwctl(mtd, NAND_ECC_READ);
975 chip->read_buf(mtd, p, eccsize);
977 if (chip->ecc.prepad) {
978 chip->read_buf(mtd, oob, chip->ecc.prepad);
979 oob += chip->ecc.prepad;
982 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
983 chip->read_buf(mtd, oob, eccbytes);
984 stat = chip->ecc.correct(mtd, p, oob, NULL);
987 mtd->ecc_stats.failed++;
989 mtd->ecc_stats.corrected += stat;
993 if (chip->ecc.postpad) {
994 chip->read_buf(mtd, oob, chip->ecc.postpad);
995 oob += chip->ecc.postpad;
999 /* Calculate remaining oob bytes */
1000 i = mtd->oobsize - (oob - chip->oob_poi);
1002 chip->read_buf(mtd, oob, i);
1008 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1009 * @chip: nand chip structure
1010 * @oob: oob destination address
1011 * @ops: oob ops structure
1012 * @len: size of oob to transfer
1014 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1015 struct mtd_oob_ops *ops, size_t len)
1021 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1024 case MTD_OOB_AUTO: {
1025 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1026 uint32_t boffs = 0, roffs = ops->ooboffs;
1029 for(; free->length && len; free++, len -= bytes) {
1030 /* Read request not from offset 0 ? */
1031 if (unlikely(roffs)) {
1032 if (roffs >= free->length) {
1033 roffs -= free->length;
1036 boffs = free->offset + roffs;
1037 bytes = min_t(size_t, len,
1038 (free->length - roffs));
1041 bytes = min_t(size_t, len, free->length);
1042 boffs = free->offset;
1044 memcpy(oob, chip->oob_poi + boffs, bytes);
1056 * nand_do_read_ops - [Internal] Read data with ECC
1058 * @mtd: MTD device structure
1059 * @from: offset to read from
1060 * @ops: oob ops structure
1062 * Internal function. Called with chip held.
1064 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1065 struct mtd_oob_ops *ops)
1067 int chipnr, page, realpage, col, bytes, aligned;
1068 struct nand_chip *chip = mtd->priv;
1069 struct mtd_ecc_stats stats;
1070 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1073 uint32_t readlen = ops->len;
1074 uint32_t oobreadlen = ops->ooblen;
1075 uint8_t *bufpoi, *oob, *buf;
1077 stats = mtd->ecc_stats;
1079 chipnr = (int)(from >> chip->chip_shift);
1080 chip->select_chip(mtd, chipnr);
1082 realpage = (int)(from >> chip->page_shift);
1083 page = realpage & chip->pagemask;
1085 col = (int)(from & (mtd->writesize - 1));
1091 bytes = min(mtd->writesize - col, readlen);
1092 aligned = (bytes == mtd->writesize);
1094 /* Is the current page in the buffer ? */
1095 if (realpage != chip->pagebuf || oob) {
1096 bufpoi = aligned ? buf : chip->buffers->databuf;
1098 if (likely(sndcmd)) {
1099 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1103 /* Now read the page into the buffer */
1104 if (unlikely(ops->mode == MTD_OOB_RAW))
1105 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi);
1107 ret = chip->ecc.read_page(mtd, chip, bufpoi);
1111 /* Transfer not aligned data */
1113 chip->pagebuf = realpage;
1114 memcpy(buf, chip->buffers->databuf + col, bytes);
1119 if (unlikely(oob)) {
1120 /* Raw mode does data:oob:data:oob */
1121 if (ops->mode != MTD_OOB_RAW) {
1122 int toread = min(oobreadlen,
1123 chip->ecc.layout->oobavail);
1125 oob = nand_transfer_oob(chip,
1127 oobreadlen -= toread;
1130 buf = nand_transfer_oob(chip,
1131 buf, ops, mtd->oobsize);
1134 if (!(chip->options & NAND_NO_READRDY)) {
1136 * Apply delay or wait for ready/busy pin. Do
1137 * this before the AUTOINCR check, so no
1138 * problems arise if a chip which does auto
1139 * increment is marked as NOAUTOINCR by the
1142 if (!chip->dev_ready)
1143 udelay(chip->chip_delay);
1145 nand_wait_ready(mtd);
1148 memcpy(buf, chip->buffers->databuf + col, bytes);
1157 /* For subsequent reads align to page boundary. */
1159 /* Increment page address */
1162 page = realpage & chip->pagemask;
1163 /* Check, if we cross a chip boundary */
1166 chip->select_chip(mtd, -1);
1167 chip->select_chip(mtd, chipnr);
1170 /* Check, if the chip supports auto page increment
1171 * or if we have hit a block boundary.
1173 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1177 ops->retlen = ops->len - (size_t) readlen;
1179 ops->oobretlen = ops->ooblen - oobreadlen;
1184 if (mtd->ecc_stats.failed - stats.failed)
1187 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1191 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1192 * @mtd: MTD device structure
1193 * @from: offset to read from
1194 * @len: number of bytes to read
1195 * @retlen: pointer to variable to store the number of read bytes
1196 * @buf: the databuffer to put data
1198 * Get hold of the chip and call nand_do_read
1200 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1201 size_t *retlen, uint8_t *buf)
1203 struct nand_chip *chip = mtd->priv;
1206 /* Do not allow reads past end of device */
1207 if ((from + len) > mtd->size)
1212 nand_get_device(chip, mtd, FL_READING);
1214 chip->ops.len = len;
1215 chip->ops.datbuf = buf;
1216 chip->ops.oobbuf = NULL;
1218 ret = nand_do_read_ops(mtd, from, &chip->ops);
1220 *retlen = chip->ops.retlen;
1222 nand_release_device(mtd);
1228 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1229 * @mtd: mtd info structure
1230 * @chip: nand chip info structure
1231 * @page: page number to read
1232 * @sndcmd: flag whether to issue read command or not
1234 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1235 int page, int sndcmd)
1238 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1241 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1246 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1248 * @mtd: mtd info structure
1249 * @chip: nand chip info structure
1250 * @page: page number to read
1251 * @sndcmd: flag whether to issue read command or not
1253 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1254 int page, int sndcmd)
1256 uint8_t *buf = chip->oob_poi;
1257 int length = mtd->oobsize;
1258 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1259 int eccsize = chip->ecc.size;
1260 uint8_t *bufpoi = buf;
1261 int i, toread, sndrnd = 0, pos;
1263 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1264 for (i = 0; i < chip->ecc.steps; i++) {
1266 pos = eccsize + i * (eccsize + chunk);
1267 if (mtd->writesize > 512)
1268 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1270 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1273 toread = min_t(int, length, chunk);
1274 chip->read_buf(mtd, bufpoi, toread);
1279 chip->read_buf(mtd, bufpoi, length);
1285 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1286 * @mtd: mtd info structure
1287 * @chip: nand chip info structure
1288 * @page: page number to write
1290 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1294 const uint8_t *buf = chip->oob_poi;
1295 int length = mtd->oobsize;
1297 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1298 chip->write_buf(mtd, buf, length);
1299 /* Send command to program the OOB data */
1300 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1302 status = chip->waitfunc(mtd, chip);
1304 return status & NAND_STATUS_FAIL ? -EIO : 0;
1308 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1309 * with syndrome - only for large page flash !
1310 * @mtd: mtd info structure
1311 * @chip: nand chip info structure
1312 * @page: page number to write
1314 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1315 struct nand_chip *chip, int page)
1317 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1318 int eccsize = chip->ecc.size, length = mtd->oobsize;
1319 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1320 const uint8_t *bufpoi = chip->oob_poi;
1323 * data-ecc-data-ecc ... ecc-oob
1325 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1327 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1328 pos = steps * (eccsize + chunk);
1333 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1334 for (i = 0; i < steps; i++) {
1336 if (mtd->writesize <= 512) {
1337 uint32_t fill = 0xFFFFFFFF;
1341 int num = min_t(int, len, 4);
1342 chip->write_buf(mtd, (uint8_t *)&fill,
1347 pos = eccsize + i * (eccsize + chunk);
1348 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1352 len = min_t(int, length, chunk);
1353 chip->write_buf(mtd, bufpoi, len);
1358 chip->write_buf(mtd, bufpoi, length);
1360 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1361 status = chip->waitfunc(mtd, chip);
1363 return status & NAND_STATUS_FAIL ? -EIO : 0;
1367 * nand_do_read_oob - [Intern] NAND read out-of-band
1368 * @mtd: MTD device structure
1369 * @from: offset to read from
1370 * @ops: oob operations description structure
1372 * NAND read out-of-band data from the spare area
1374 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1375 struct mtd_oob_ops *ops)
1377 int page, realpage, chipnr, sndcmd = 1;
1378 struct nand_chip *chip = mtd->priv;
1379 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1380 int readlen = ops->ooblen;
1382 uint8_t *buf = ops->oobbuf;
1384 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1385 (unsigned long long)from, readlen);
1387 if (ops->mode == MTD_OOB_AUTO)
1388 len = chip->ecc.layout->oobavail;
1392 if (unlikely(ops->ooboffs >= len)) {
1393 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1394 "Attempt to start read outside oob\n");
1398 /* Do not allow reads past end of device */
1399 if (unlikely(from >= mtd->size ||
1400 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1401 (from >> chip->page_shift)) * len)) {
1402 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1403 "Attempt read beyond end of device\n");
1407 chipnr = (int)(from >> chip->chip_shift);
1408 chip->select_chip(mtd, chipnr);
1410 /* Shift to get page */
1411 realpage = (int)(from >> chip->page_shift);
1412 page = realpage & chip->pagemask;
1415 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1417 len = min(len, readlen);
1418 buf = nand_transfer_oob(chip, buf, ops, len);
1420 if (!(chip->options & NAND_NO_READRDY)) {
1422 * Apply delay or wait for ready/busy pin. Do this
1423 * before the AUTOINCR check, so no problems arise if a
1424 * chip which does auto increment is marked as
1425 * NOAUTOINCR by the board driver.
1427 if (!chip->dev_ready)
1428 udelay(chip->chip_delay);
1430 nand_wait_ready(mtd);
1437 /* Increment page address */
1440 page = realpage & chip->pagemask;
1441 /* Check, if we cross a chip boundary */
1444 chip->select_chip(mtd, -1);
1445 chip->select_chip(mtd, chipnr);
1448 /* Check, if the chip supports auto page increment
1449 * or if we have hit a block boundary.
1451 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1455 ops->oobretlen = ops->ooblen;
1460 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1461 * @mtd: MTD device structure
1462 * @from: offset to read from
1463 * @ops: oob operation description structure
1465 * NAND read data and/or out-of-band data
1467 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1468 struct mtd_oob_ops *ops)
1470 struct nand_chip *chip = mtd->priv;
1471 int ret = -ENOTSUPP;
1475 /* Do not allow reads past end of device */
1476 if (ops->datbuf && (from + ops->len) > mtd->size) {
1477 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1478 "Attempt read beyond end of device\n");
1482 nand_get_device(chip, mtd, FL_READING);
1495 ret = nand_do_read_oob(mtd, from, ops);
1497 ret = nand_do_read_ops(mtd, from, ops);
1500 nand_release_device(mtd);
1506 * nand_write_page_raw - [Intern] raw page write function
1507 * @mtd: mtd info structure
1508 * @chip: nand chip info structure
1511 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1514 chip->write_buf(mtd, buf, mtd->writesize);
1515 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1519 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1520 * @mtd: mtd info structure
1521 * @chip: nand chip info structure
1524 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1527 int i, eccsize = chip->ecc.size;
1528 int eccbytes = chip->ecc.bytes;
1529 int eccsteps = chip->ecc.steps;
1530 uint8_t *ecc_calc = chip->buffers->ecccalc;
1531 const uint8_t *p = buf;
1532 uint32_t *eccpos = chip->ecc.layout->eccpos;
1534 /* Software ecc calculation */
1535 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1536 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1538 for (i = 0; i < chip->ecc.total; i++)
1539 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1541 chip->ecc.write_page_raw(mtd, chip, buf);
1545 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1546 * @mtd: mtd info structure
1547 * @chip: nand chip info structure
1550 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1553 int i, eccsize = chip->ecc.size;
1554 int eccbytes = chip->ecc.bytes;
1555 int eccsteps = chip->ecc.steps;
1556 uint8_t *ecc_calc = chip->buffers->ecccalc;
1557 const uint8_t *p = buf;
1558 uint32_t *eccpos = chip->ecc.layout->eccpos;
1560 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1561 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1562 chip->write_buf(mtd, p, eccsize);
1563 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1566 for (i = 0; i < chip->ecc.total; i++)
1567 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1569 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1573 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1574 * @mtd: mtd info structure
1575 * @chip: nand chip info structure
1578 * The hw generator calculates the error syndrome automatically. Therefor
1579 * we need a special oob layout and handling.
1581 static void nand_write_page_syndrome(struct mtd_info *mtd,
1582 struct nand_chip *chip, const uint8_t *buf)
1584 int i, eccsize = chip->ecc.size;
1585 int eccbytes = chip->ecc.bytes;
1586 int eccsteps = chip->ecc.steps;
1587 const uint8_t *p = buf;
1588 uint8_t *oob = chip->oob_poi;
1590 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1592 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1593 chip->write_buf(mtd, p, eccsize);
1595 if (chip->ecc.prepad) {
1596 chip->write_buf(mtd, oob, chip->ecc.prepad);
1597 oob += chip->ecc.prepad;
1600 chip->ecc.calculate(mtd, p, oob);
1601 chip->write_buf(mtd, oob, eccbytes);
1604 if (chip->ecc.postpad) {
1605 chip->write_buf(mtd, oob, chip->ecc.postpad);
1606 oob += chip->ecc.postpad;
1610 /* Calculate remaining oob bytes */
1611 i = mtd->oobsize - (oob - chip->oob_poi);
1613 chip->write_buf(mtd, oob, i);
1617 * nand_write_page - [REPLACEABLE] write one page
1618 * @mtd: MTD device structure
1619 * @chip: NAND chip descriptor
1620 * @buf: the data to write
1621 * @page: page number to write
1622 * @cached: cached programming
1623 * @raw: use _raw version of write_page
1625 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1626 const uint8_t *buf, int page, int cached, int raw)
1630 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1633 chip->ecc.write_page_raw(mtd, chip, buf);
1635 chip->ecc.write_page(mtd, chip, buf);
1638 * Cached progamming disabled for now, Not sure if its worth the
1639 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1643 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1645 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1646 status = chip->waitfunc(mtd, chip);
1648 * See if operation failed and additional status checks are
1651 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1652 status = chip->errstat(mtd, chip, FL_WRITING, status,
1655 if (status & NAND_STATUS_FAIL)
1658 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1659 status = chip->waitfunc(mtd, chip);
1662 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1663 /* Send command to read back the data */
1664 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1666 if (chip->verify_buf(mtd, buf, mtd->writesize))
1673 * nand_fill_oob - [Internal] Transfer client buffer to oob
1674 * @chip: nand chip structure
1675 * @oob: oob data buffer
1676 * @ops: oob ops structure
1678 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1679 struct mtd_oob_ops *ops)
1681 size_t len = ops->ooblen;
1687 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1690 case MTD_OOB_AUTO: {
1691 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1692 uint32_t boffs = 0, woffs = ops->ooboffs;
1695 for(; free->length && len; free++, len -= bytes) {
1696 /* Write request not from offset 0 ? */
1697 if (unlikely(woffs)) {
1698 if (woffs >= free->length) {
1699 woffs -= free->length;
1702 boffs = free->offset + woffs;
1703 bytes = min_t(size_t, len,
1704 (free->length - woffs));
1707 bytes = min_t(size_t, len, free->length);
1708 boffs = free->offset;
1710 memcpy(chip->oob_poi + boffs, oob, bytes);
1721 #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
1724 * nand_do_write_ops - [Internal] NAND write with ECC
1725 * @mtd: MTD device structure
1726 * @to: offset to write to
1727 * @ops: oob operations description structure
1729 * NAND write with ECC
1731 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1732 struct mtd_oob_ops *ops)
1734 int chipnr, realpage, page, blockmask, column;
1735 struct nand_chip *chip = mtd->priv;
1736 uint32_t writelen = ops->len;
1737 uint8_t *oob = ops->oobbuf;
1738 uint8_t *buf = ops->datbuf;
1745 /* reject writes, which are not page aligned */
1746 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1747 printk(KERN_NOTICE "nand_write: "
1748 "Attempt to write not page aligned data\n");
1752 column = to & (mtd->writesize - 1);
1753 subpage = column || (writelen & (mtd->writesize - 1));
1758 chipnr = (int)(to >> chip->chip_shift);
1759 chip->select_chip(mtd, chipnr);
1761 /* Check, if it is write protected */
1762 if (nand_check_wp(mtd)) {
1763 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1767 realpage = (int)(to >> chip->page_shift);
1768 page = realpage & chip->pagemask;
1769 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1771 /* Invalidate the page cache, when we write to the cached page */
1772 if (to <= (chip->pagebuf << chip->page_shift) &&
1773 (chip->pagebuf << chip->page_shift) < (to + ops->len))
1776 /* If we're not given explicit OOB data, let it be 0xFF */
1778 memset(chip->oob_poi, 0xff, mtd->oobsize);
1781 int bytes = mtd->writesize;
1782 int cached = writelen > bytes && page != blockmask;
1783 uint8_t *wbuf = buf;
1785 /* Partial page write ? */
1786 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1788 bytes = min_t(int, bytes - column, (int) writelen);
1790 memset(chip->buffers->databuf, 0xff, mtd->writesize);
1791 memcpy(&chip->buffers->databuf[column], buf, bytes);
1792 wbuf = chip->buffers->databuf;
1796 oob = nand_fill_oob(chip, oob, ops);
1798 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1799 (ops->mode == MTD_OOB_RAW));
1811 page = realpage & chip->pagemask;
1812 /* Check, if we cross a chip boundary */
1815 chip->select_chip(mtd, -1);
1816 chip->select_chip(mtd, chipnr);
1820 ops->retlen = ops->len - writelen;
1822 ops->oobretlen = ops->ooblen;
1827 * nand_write - [MTD Interface] NAND write with ECC
1828 * @mtd: MTD device structure
1829 * @to: offset to write to
1830 * @len: number of bytes to write
1831 * @retlen: pointer to variable to store the number of written bytes
1832 * @buf: the data to write
1834 * NAND write with ECC
1836 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1837 size_t *retlen, const uint8_t *buf)
1839 struct nand_chip *chip = mtd->priv;
1842 /* Do not allow reads past end of device */
1843 if ((to + len) > mtd->size)
1848 nand_get_device(chip, mtd, FL_WRITING);
1850 chip->ops.len = len;
1851 chip->ops.datbuf = (uint8_t *)buf;
1852 chip->ops.oobbuf = NULL;
1854 ret = nand_do_write_ops(mtd, to, &chip->ops);
1856 *retlen = chip->ops.retlen;
1858 nand_release_device(mtd);
1864 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1865 * @mtd: MTD device structure
1866 * @to: offset to write to
1867 * @ops: oob operation description structure
1869 * NAND write out-of-band
1871 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1872 struct mtd_oob_ops *ops)
1874 int chipnr, page, status, len;
1875 struct nand_chip *chip = mtd->priv;
1877 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1878 (unsigned int)to, (int)ops->ooblen);
1880 if (ops->mode == MTD_OOB_AUTO)
1881 len = chip->ecc.layout->oobavail;
1885 /* Do not allow write past end of page */
1886 if ((ops->ooboffs + ops->ooblen) > len) {
1887 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
1888 "Attempt to write past end of page\n");
1892 if (unlikely(ops->ooboffs >= len)) {
1893 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1894 "Attempt to start write outside oob\n");
1898 /* Do not allow reads past end of device */
1899 if (unlikely(to >= mtd->size ||
1900 ops->ooboffs + ops->ooblen >
1901 ((mtd->size >> chip->page_shift) -
1902 (to >> chip->page_shift)) * len)) {
1903 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1904 "Attempt write beyond end of device\n");
1908 chipnr = (int)(to >> chip->chip_shift);
1909 chip->select_chip(mtd, chipnr);
1911 /* Shift to get page */
1912 page = (int)(to >> chip->page_shift);
1915 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
1916 * of my DiskOnChip 2000 test units) will clear the whole data page too
1917 * if we don't do this. I have no clue why, but I seem to have 'fixed'
1918 * it in the doc2000 driver in August 1999. dwmw2.
1920 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1922 /* Check, if it is write protected */
1923 if (nand_check_wp(mtd))
1926 /* Invalidate the page cache, if we write to the cached page */
1927 if (page == chip->pagebuf)
1930 memset(chip->oob_poi, 0xff, mtd->oobsize);
1931 nand_fill_oob(chip, ops->oobbuf, ops);
1932 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1933 memset(chip->oob_poi, 0xff, mtd->oobsize);
1938 ops->oobretlen = ops->ooblen;
1944 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
1945 * @mtd: MTD device structure
1946 * @to: offset to write to
1947 * @ops: oob operation description structure
1949 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
1950 struct mtd_oob_ops *ops)
1952 struct nand_chip *chip = mtd->priv;
1953 int ret = -ENOTSUPP;
1957 /* Do not allow writes past end of device */
1958 if (ops->datbuf && (to + ops->len) > mtd->size) {
1959 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1960 "Attempt read beyond end of device\n");
1964 nand_get_device(chip, mtd, FL_WRITING);
1977 ret = nand_do_write_oob(mtd, to, ops);
1979 ret = nand_do_write_ops(mtd, to, ops);
1982 nand_release_device(mtd);
1987 * single_erease_cmd - [GENERIC] NAND standard block erase command function
1988 * @mtd: MTD device structure
1989 * @page: the page address of the block which will be erased
1991 * Standard erase command for NAND chips
1993 static void single_erase_cmd(struct mtd_info *mtd, int page)
1995 struct nand_chip *chip = mtd->priv;
1996 /* Send commands to erase a block */
1997 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
1998 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2002 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2003 * @mtd: MTD device structure
2004 * @page: the page address of the block which will be erased
2006 * AND multi block erase command function
2007 * Erase 4 consecutive blocks
2009 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2011 struct nand_chip *chip = mtd->priv;
2012 /* Send commands to erase a block */
2013 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2014 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2015 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2016 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2017 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2021 * nand_erase - [MTD Interface] erase block(s)
2022 * @mtd: MTD device structure
2023 * @instr: erase instruction
2025 * Erase one ore more blocks
2027 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2029 return nand_erase_nand(mtd, instr, 0);
2032 #define BBT_PAGE_MASK 0xffffff3f
2034 * nand_erase_nand - [Internal] erase block(s)
2035 * @mtd: MTD device structure
2036 * @instr: erase instruction
2037 * @allowbbt: allow erasing the bbt area
2039 * Erase one ore more blocks
2041 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2044 int page, len, status, pages_per_block, ret, chipnr;
2045 struct nand_chip *chip = mtd->priv;
2046 int rewrite_bbt[NAND_MAX_CHIPS]={0};
2047 unsigned int bbt_masked_page = 0xffffffff;
2049 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
2050 (unsigned int) instr->addr, (unsigned int) instr->len);
2052 /* Start address must align on block boundary */
2053 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2054 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2058 /* Length must align on block boundary */
2059 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2060 MTDDEBUG (MTD_DEBUG_LEVEL0,
2061 "nand_erase: Length not block aligned\n");
2065 /* Do not allow erase past end of device */
2066 if ((instr->len + instr->addr) > mtd->size) {
2067 MTDDEBUG (MTD_DEBUG_LEVEL0,
2068 "nand_erase: Erase past end of device\n");
2072 instr->fail_addr = 0xffffffff;
2074 /* Grab the lock and see if the device is available */
2075 nand_get_device(chip, mtd, FL_ERASING);
2077 /* Shift to get first page */
2078 page = (int)(instr->addr >> chip->page_shift);
2079 chipnr = (int)(instr->addr >> chip->chip_shift);
2081 /* Calculate pages in each block */
2082 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2084 /* Select the NAND device */
2085 chip->select_chip(mtd, chipnr);
2087 /* Check, if it is write protected */
2088 if (nand_check_wp(mtd)) {
2089 MTDDEBUG (MTD_DEBUG_LEVEL0,
2090 "nand_erase: Device is write protected!!!\n");
2091 instr->state = MTD_ERASE_FAILED;
2096 * If BBT requires refresh, set the BBT page mask to see if the BBT
2097 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2098 * can not be matched. This is also done when the bbt is actually
2099 * erased to avoid recusrsive updates
2101 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2102 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2104 /* Loop through the pages */
2107 instr->state = MTD_ERASING;
2111 * heck if we have a bad block, we do not erase bad blocks !
2113 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2114 chip->page_shift, 0, allowbbt)) {
2115 printk(KERN_WARNING "nand_erase: attempt to erase a "
2116 "bad block at page 0x%08x\n", page);
2117 instr->state = MTD_ERASE_FAILED;
2122 * Invalidate the page cache, if we erase the block which
2123 * contains the current cached page
2125 if (page <= chip->pagebuf && chip->pagebuf <
2126 (page + pages_per_block))
2129 chip->erase_cmd(mtd, page & chip->pagemask);
2131 status = chip->waitfunc(mtd, chip);
2134 * See if operation failed and additional status checks are
2137 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2138 status = chip->errstat(mtd, chip, FL_ERASING,
2141 /* See if block erase succeeded */
2142 if (status & NAND_STATUS_FAIL) {
2143 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
2144 "Failed erase, page 0x%08x\n", page);
2145 instr->state = MTD_ERASE_FAILED;
2146 instr->fail_addr = (page << chip->page_shift);
2151 * If BBT requires refresh, set the BBT rewrite flag to the
2154 if (bbt_masked_page != 0xffffffff &&
2155 (page & BBT_PAGE_MASK) == bbt_masked_page)
2156 rewrite_bbt[chipnr] = (page << chip->page_shift);
2158 /* Increment page address and decrement length */
2159 len -= (1 << chip->phys_erase_shift);
2160 page += pages_per_block;
2162 /* Check, if we cross a chip boundary */
2163 if (len && !(page & chip->pagemask)) {
2165 chip->select_chip(mtd, -1);
2166 chip->select_chip(mtd, chipnr);
2169 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2170 * page mask to see if this BBT should be rewritten
2172 if (bbt_masked_page != 0xffffffff &&
2173 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2174 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2178 instr->state = MTD_ERASE_DONE;
2182 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2183 /* Do call back function */
2185 mtd_erase_callback(instr);
2187 /* Deselect and wake up anyone waiting on the device */
2188 nand_release_device(mtd);
2191 * If BBT requires refresh and erase was successful, rewrite any
2192 * selected bad block tables
2194 if (bbt_masked_page == 0xffffffff || ret)
2197 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2198 if (!rewrite_bbt[chipnr])
2200 /* update the BBT for chip */
2201 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2202 "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2203 chip->bbt_td->pages[chipnr]);
2204 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2207 /* Return more or less happy */
2212 * nand_sync - [MTD Interface] sync
2213 * @mtd: MTD device structure
2215 * Sync is actually a wait for chip ready function
2217 static void nand_sync(struct mtd_info *mtd)
2219 struct nand_chip *chip = mtd->priv;
2221 MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2223 /* Grab the lock and see if the device is available */
2224 nand_get_device(chip, mtd, FL_SYNCING);
2225 /* Release it and go back */
2226 nand_release_device(mtd);
2230 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2231 * @mtd: MTD device structure
2232 * @offs: offset relative to mtd start
2234 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2236 /* Check for invalid offset */
2237 if (offs > mtd->size)
2240 return nand_block_checkbad(mtd, offs, 1, 0);
2244 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2245 * @mtd: MTD device structure
2246 * @ofs: offset relative to mtd start
2248 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2250 struct nand_chip *chip = mtd->priv;
2253 if ((ret = nand_block_isbad(mtd, ofs))) {
2254 /* If it was bad already, return success and do nothing. */
2260 return chip->block_markbad(mtd, ofs);
2264 * nand_suspend - [MTD Interface] Suspend the NAND flash
2265 * @mtd: MTD device structure
2267 static int nand_suspend(struct mtd_info *mtd)
2269 struct nand_chip *chip = mtd->priv;
2271 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2275 * nand_resume - [MTD Interface] Resume the NAND flash
2276 * @mtd: MTD device structure
2278 static void nand_resume(struct mtd_info *mtd)
2280 struct nand_chip *chip = mtd->priv;
2282 if (chip->state == FL_PM_SUSPENDED)
2283 nand_release_device(mtd);
2285 printk(KERN_ERR "nand_resume() called for a chip which is not "
2286 "in suspended state\n");
2290 * Set default functions
2292 static void nand_set_defaults(struct nand_chip *chip, int busw)
2294 /* check for proper chip_delay setup, set 20us if not */
2295 if (!chip->chip_delay)
2296 chip->chip_delay = 20;
2298 /* check, if a user supplied command function given */
2299 if (chip->cmdfunc == NULL)
2300 chip->cmdfunc = nand_command;
2302 /* check, if a user supplied wait function given */
2303 if (chip->waitfunc == NULL)
2304 chip->waitfunc = nand_wait;
2306 if (!chip->select_chip)
2307 chip->select_chip = nand_select_chip;
2308 if (!chip->read_byte)
2309 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2310 if (!chip->read_word)
2311 chip->read_word = nand_read_word;
2312 if (!chip->block_bad)
2313 chip->block_bad = nand_block_bad;
2314 if (!chip->block_markbad)
2315 chip->block_markbad = nand_default_block_markbad;
2316 if (!chip->write_buf)
2317 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2318 if (!chip->read_buf)
2319 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2320 if (!chip->verify_buf)
2321 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2322 if (!chip->scan_bbt)
2323 chip->scan_bbt = nand_default_bbt;
2325 if (!chip->controller) {
2326 chip->controller = &chip->hwcontrol;
2328 /* XXX U-BOOT XXX */
2330 spin_lock_init(&chip->controller->lock);
2331 init_waitqueue_head(&chip->controller->wq);
2338 * Get the flash and manufacturer id and lookup if the type is supported
2340 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2341 struct nand_chip *chip,
2342 int busw, int *maf_id)
2344 struct nand_flash_dev *type = NULL;
2345 int i, dev_id, maf_idx;
2347 /* Select the device */
2348 chip->select_chip(mtd, 0);
2350 /* Send the command for reading device ID */
2351 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2353 /* Read manufacturer and device IDs */
2354 *maf_id = chip->read_byte(mtd);
2355 dev_id = chip->read_byte(mtd);
2357 /* Lookup the flash id */
2358 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2359 if (dev_id == nand_flash_ids[i].id) {
2360 type = &nand_flash_ids[i];
2366 return ERR_PTR(-ENODEV);
2369 mtd->name = type->name;
2371 chip->chipsize = type->chipsize << 20;
2373 /* Newer devices have all the information in additional id bytes */
2374 if (!type->pagesize) {
2376 /* The 3rd id byte holds MLC / multichip data */
2377 chip->cellinfo = chip->read_byte(mtd);
2378 /* The 4th id byte is the important one */
2379 extid = chip->read_byte(mtd);
2381 mtd->writesize = 1024 << (extid & 0x3);
2384 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2386 /* Calc blocksize. Blocksize is multiples of 64KiB */
2387 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2389 /* Get buswidth information */
2390 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2394 * Old devices have chip data hardcoded in the device id table
2396 mtd->erasesize = type->erasesize;
2397 mtd->writesize = type->pagesize;
2398 mtd->oobsize = mtd->writesize / 32;
2399 busw = type->options & NAND_BUSWIDTH_16;
2402 /* Try to identify manufacturer */
2403 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2404 if (nand_manuf_ids[maf_idx].id == *maf_id)
2409 * Check, if buswidth is correct. Hardware drivers should set
2412 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2413 printk(KERN_INFO "NAND device: Manufacturer ID:"
2414 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2415 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2416 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2417 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2419 return ERR_PTR(-EINVAL);
2422 /* Calculate the address shift from the page size */
2423 chip->page_shift = ffs(mtd->writesize) - 1;
2424 /* Convert chipsize to number of pages per chip -1. */
2425 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2427 chip->bbt_erase_shift = chip->phys_erase_shift =
2428 ffs(mtd->erasesize) - 1;
2429 chip->chip_shift = ffs(chip->chipsize) - 1;
2431 /* Set the bad block position */
2432 chip->badblockpos = mtd->writesize > 512 ?
2433 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2435 /* Get chip options, preserve non chip based options */
2436 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2437 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2440 * Set chip as a default. Board drivers can override it, if necessary
2442 chip->options |= NAND_NO_AUTOINCR;
2444 /* Check if chip is a not a samsung device. Do not clear the
2445 * options for chips which are not having an extended id.
2447 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2448 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2450 /* Check for AND chips with 4 page planes */
2451 if (chip->options & NAND_4PAGE_ARRAY)
2452 chip->erase_cmd = multi_erase_cmd;
2454 chip->erase_cmd = single_erase_cmd;
2456 /* Do not replace user supplied command function ! */
2457 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2458 chip->cmdfunc = nand_command_lp;
2460 printk(KERN_INFO "NAND device: Manufacturer ID:"
2461 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2462 nand_manuf_ids[maf_idx].name, type->name);
2468 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2469 * @mtd: MTD device structure
2470 * @maxchips: Number of chips to scan for
2472 * This is the first phase of the normal nand_scan() function. It
2473 * reads the flash ID and sets up MTD fields accordingly.
2475 * The mtd->owner field must be set to the module of the caller.
2477 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2479 int i, busw, nand_maf_id;
2480 struct nand_chip *chip = mtd->priv;
2481 struct nand_flash_dev *type;
2483 /* Get buswidth to select the correct functions */
2484 busw = chip->options & NAND_BUSWIDTH_16;
2485 /* Set the default functions */
2486 nand_set_defaults(chip, busw);
2488 /* Read the flash type */
2489 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2492 printk(KERN_WARNING "No NAND device found!!!\n");
2493 chip->select_chip(mtd, -1);
2494 return PTR_ERR(type);
2497 /* Check for a chip array */
2498 for (i = 1; i < maxchips; i++) {
2499 chip->select_chip(mtd, i);
2500 /* Send the command for reading device ID */
2501 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2502 /* Read manufacturer and device IDs */
2503 if (nand_maf_id != chip->read_byte(mtd) ||
2504 type->id != chip->read_byte(mtd))
2508 printk(KERN_INFO "%d NAND chips detected\n", i);
2510 /* Store the number of chips and calc total size for mtd */
2512 mtd->size = i * chip->chipsize;
2519 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2520 * @mtd: MTD device structure
2521 * @maxchips: Number of chips to scan for
2523 * This is the second phase of the normal nand_scan() function. It
2524 * fills out all the uninitialized function pointers with the defaults
2525 * and scans for a bad block table if appropriate.
2527 int nand_scan_tail(struct mtd_info *mtd)
2530 struct nand_chip *chip = mtd->priv;
2532 if (!(chip->options & NAND_OWN_BUFFERS))
2533 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2537 /* Set the internal oob buffer location, just after the page data */
2538 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2541 * If no default placement scheme is given, select an appropriate one
2543 if (!chip->ecc.layout) {
2544 switch (mtd->oobsize) {
2546 chip->ecc.layout = &nand_oob_8;
2549 chip->ecc.layout = &nand_oob_16;
2552 chip->ecc.layout = &nand_oob_64;
2555 chip->ecc.layout = &nand_oob_128;
2558 printk(KERN_WARNING "No oob scheme defined for "
2559 "oobsize %d\n", mtd->oobsize);
2564 if (!chip->write_page)
2565 chip->write_page = nand_write_page;
2568 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2569 * selected and we have 256 byte pagesize fallback to software ECC
2571 if (!chip->ecc.read_page_raw)
2572 chip->ecc.read_page_raw = nand_read_page_raw;
2573 if (!chip->ecc.write_page_raw)
2574 chip->ecc.write_page_raw = nand_write_page_raw;
2576 switch (chip->ecc.mode) {
2578 /* Use standard hwecc read page function ? */
2579 if (!chip->ecc.read_page)
2580 chip->ecc.read_page = nand_read_page_hwecc;
2581 if (!chip->ecc.write_page)
2582 chip->ecc.write_page = nand_write_page_hwecc;
2583 if (!chip->ecc.read_oob)
2584 chip->ecc.read_oob = nand_read_oob_std;
2585 if (!chip->ecc.write_oob)
2586 chip->ecc.write_oob = nand_write_oob_std;
2588 case NAND_ECC_HW_SYNDROME:
2589 if (!chip->ecc.calculate || !chip->ecc.correct ||
2591 printk(KERN_WARNING "No ECC functions supplied, "
2592 "Hardware ECC not possible\n");
2595 /* Use standard syndrome read/write page function ? */
2596 if (!chip->ecc.read_page)
2597 chip->ecc.read_page = nand_read_page_syndrome;
2598 if (!chip->ecc.write_page)
2599 chip->ecc.write_page = nand_write_page_syndrome;
2600 if (!chip->ecc.read_oob)
2601 chip->ecc.read_oob = nand_read_oob_syndrome;
2602 if (!chip->ecc.write_oob)
2603 chip->ecc.write_oob = nand_write_oob_syndrome;
2605 if (mtd->writesize >= chip->ecc.size)
2607 printk(KERN_WARNING "%d byte HW ECC not possible on "
2608 "%d byte page size, fallback to SW ECC\n",
2609 chip->ecc.size, mtd->writesize);
2610 chip->ecc.mode = NAND_ECC_SOFT;
2613 chip->ecc.calculate = nand_calculate_ecc;
2614 chip->ecc.correct = nand_correct_data;
2615 chip->ecc.read_page = nand_read_page_swecc;
2616 chip->ecc.write_page = nand_write_page_swecc;
2617 chip->ecc.read_oob = nand_read_oob_std;
2618 chip->ecc.write_oob = nand_write_oob_std;
2619 chip->ecc.size = 256;
2620 chip->ecc.bytes = 3;
2624 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2625 "This is not recommended !!\n");
2626 chip->ecc.read_page = nand_read_page_raw;
2627 chip->ecc.write_page = nand_write_page_raw;
2628 chip->ecc.read_oob = nand_read_oob_std;
2629 chip->ecc.write_oob = nand_write_oob_std;
2630 chip->ecc.size = mtd->writesize;
2631 chip->ecc.bytes = 0;
2635 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2641 * The number of bytes available for a client to place data into
2642 * the out of band area
2644 chip->ecc.layout->oobavail = 0;
2645 for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
2646 chip->ecc.layout->oobavail +=
2647 chip->ecc.layout->oobfree[i].length;
2648 mtd->oobavail = chip->ecc.layout->oobavail;
2651 * Set the number of read / write steps for one page depending on ECC
2654 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2655 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2656 printk(KERN_WARNING "Invalid ecc parameters\n");
2659 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2662 * Allow subpage writes up to ecc.steps. Not possible for MLC
2665 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2666 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2667 switch(chip->ecc.steps) {
2669 mtd->subpage_sft = 1;
2673 mtd->subpage_sft = 2;
2677 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2679 /* Initialize state */
2680 chip->state = FL_READY;
2682 /* De-select the device */
2683 chip->select_chip(mtd, -1);
2685 /* Invalidate the pagebuffer reference */
2688 /* Fill in remaining MTD driver data */
2689 mtd->type = MTD_NANDFLASH;
2690 mtd->flags = MTD_CAP_NANDFLASH;
2691 mtd->erase = nand_erase;
2693 mtd->unpoint = NULL;
2694 mtd->read = nand_read;
2695 mtd->write = nand_write;
2696 mtd->read_oob = nand_read_oob;
2697 mtd->write_oob = nand_write_oob;
2698 mtd->sync = nand_sync;
2701 mtd->suspend = nand_suspend;
2702 mtd->resume = nand_resume;
2703 mtd->block_isbad = nand_block_isbad;
2704 mtd->block_markbad = nand_block_markbad;
2706 /* propagate ecc.layout to mtd_info */
2707 mtd->ecclayout = chip->ecc.layout;
2709 /* Check, if we should skip the bad block table scan */
2710 if (chip->options & NAND_SKIP_BBTSCAN)
2713 /* Build bad block table */
2714 return chip->scan_bbt(mtd);
2717 /* module_text_address() isn't exported, and it's mostly a pointless
2718 test if this is a module _anyway_ -- they'd have to try _really_ hard
2719 to call us from in-kernel code if the core NAND support is modular. */
2721 #define caller_is_module() (1)
2723 #define caller_is_module() \
2724 module_text_address((unsigned long)__builtin_return_address(0))
2728 * nand_scan - [NAND Interface] Scan for the NAND device
2729 * @mtd: MTD device structure
2730 * @maxchips: Number of chips to scan for
2732 * This fills out all the uninitialized function pointers
2733 * with the defaults.
2734 * The flash ID is read and the mtd/chip structures are
2735 * filled with the appropriate values.
2736 * The mtd->owner field must be set to the module of the caller
2739 int nand_scan(struct mtd_info *mtd, int maxchips)
2743 /* Many callers got this wrong, so check for it for a while... */
2744 /* XXX U-BOOT XXX */
2746 if (!mtd->owner && caller_is_module()) {
2747 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2752 ret = nand_scan_ident(mtd, maxchips);
2754 ret = nand_scan_tail(mtd);
2759 * nand_release - [NAND Interface] Free resources held by the NAND device
2760 * @mtd: MTD device structure
2762 void nand_release(struct mtd_info *mtd)
2764 struct nand_chip *chip = mtd->priv;
2766 #ifdef CONFIG_MTD_PARTITIONS
2767 /* Deregister partitions */
2768 del_mtd_partitions(mtd);
2770 /* Deregister the device */
2771 /* XXX U-BOOT XXX */
2773 del_mtd_device(mtd);
2776 /* Free bad block table memory */
2778 if (!(chip->options & NAND_OWN_BUFFERS))
2779 kfree(chip->buffers);
2782 /* XXX U-BOOT XXX */
2784 EXPORT_SYMBOL_GPL(nand_scan);
2785 EXPORT_SYMBOL_GPL(nand_scan_ident);
2786 EXPORT_SYMBOL_GPL(nand_scan_tail);
2787 EXPORT_SYMBOL_GPL(nand_release);
2789 static int __init nand_base_init(void)
2791 led_trigger_register_simple("nand-disk", &nand_led_trigger);
2795 static void __exit nand_base_exit(void)
2797 led_trigger_unregister_simple(nand_led_trigger);
2800 module_init(nand_base_init);
2801 module_exit(nand_base_exit);
2803 MODULE_LICENSE("GPL");
2804 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2805 MODULE_DESCRIPTION("Generic NAND flash driver code");