2 * (C) Copyright 2006 OpenMoko, Inc.
3 * Author: Harald Welte <laforge@openmoko.org>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #define DEBUGN(x, args ...) {}
33 #define __REGb(x) (*(volatile unsigned char *)(x))
34 #define __REGi(x) (*(volatile unsigned int *)(x))
36 #define NF_BASE 0x4e000000
37 #define NFCONF __REGi(NF_BASE + 0x0)
38 #define NFCMD __REGb(NF_BASE + 0x4)
39 #define NFADDR __REGb(NF_BASE + 0x8)
40 #define NFDATA __REGb(NF_BASE + 0xc)
41 #define NFSTAT __REGb(NF_BASE + 0x10)
42 #define NFECC0 __REGb(NF_BASE + 0x14)
43 #define NFECC1 __REGb(NF_BASE + 0x15)
44 #define NFECC2 __REGb(NF_BASE + 0x16)
46 #define S3C2410_NFCONF_EN (1<<15)
47 #define S3C2410_NFCONF_512BYTE (1<<14)
48 #define S3C2410_NFCONF_4STEP (1<<13)
49 #define S3C2410_NFCONF_INITECC (1<<12)
50 #define S3C2410_NFCONF_nFCE (1<<11)
51 #define S3C2410_NFCONF_TACLS(x) ((x)<<8)
52 #define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
53 #define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
55 #define S3C2410_ADDR_NALE 4
56 #define S3C2410_ADDR_NCLE 8
58 static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
60 struct nand_chip *chip = mtd->priv;
62 DEBUGN("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl);
64 if (ctrl & NAND_CTRL_CHANGE) {
65 ulong IO_ADDR_W = NF_BASE;
67 if (!(ctrl & NAND_CLE))
68 IO_ADDR_W |= S3C2410_ADDR_NCLE;
69 if (!(ctrl & NAND_ALE))
70 IO_ADDR_W |= S3C2410_ADDR_NALE;
72 chip->IO_ADDR_W = (void *)IO_ADDR_W;
75 NFCONF &= ~S3C2410_NFCONF_nFCE;
77 NFCONF |= S3C2410_NFCONF_nFCE;
80 if (cmd != NAND_CMD_NONE)
81 writeb(cmd, chip->IO_ADDR_W);
84 static int s3c2410_dev_ready(struct mtd_info *mtd)
86 DEBUGN("dev_ready\n");
87 return (NFSTAT & 0x01);
90 #ifdef CONFIG_S3C2410_NAND_HWECC
91 void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
93 DEBUGN("s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode);
94 NFCONF |= S3C2410_NFCONF_INITECC;
97 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
100 ecc_code[0] = NFECC0;
101 ecc_code[1] = NFECC1;
102 ecc_code[2] = NFECC2;
103 DEBUGN("s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",
104 mtd , ecc_code[0], ecc_code[1], ecc_code[2]);
109 static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
110 u_char *read_ecc, u_char *calc_ecc)
112 if (read_ecc[0] == calc_ecc[0] &&
113 read_ecc[1] == calc_ecc[1] &&
114 read_ecc[2] == calc_ecc[2])
117 printf("s3c2410_nand_correct_data: not implemented\n");
122 int board_nand_init(struct nand_chip *nand)
125 u_int8_t tacls, twrph0, twrph1;
126 S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
128 DEBUGN("board_nand_init()\n");
130 clk_power->CLKCON |= (1 << 4);
132 /* initialize hardware */
133 twrph0 = 3; twrph1 = 0; tacls = 0;
135 cfg = S3C2410_NFCONF_EN;
136 cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
137 cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
138 cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
142 /* initialize nand_chip data structure */
143 nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)0x4e00000c;
145 /* read_buf and write_buf are default */
146 /* read_byte and write_byte are default */
148 /* hwcontrol always must be implemented */
149 nand->cmd_ctrl = s3c2410_hwcontrol;
151 nand->dev_ready = s3c2410_dev_ready;
153 #ifdef CONFIG_S3C2410_NAND_HWECC
154 nand->ecc.hwctl = s3c2410_nand_enable_hwecc;
155 nand->ecc.calculate = s3c2410_nand_calculate_ecc;
156 nand->ecc.correct = s3c2410_nand_correct_data;
157 nand->ecc.mode = NAND_ECC_HW3_512;
159 nand->ecc.mode = NAND_ECC_SOFT;
162 #ifdef CONFIG_S3C2410_NAND_BBT
163 nand->options = NAND_USE_FLASH_BBT;
168 DEBUGN("end of nand_init\n");