2 * Copyright (c) 2014-2015, Antmicro Ltd <www.antmicro.com>
3 * Copyright (c) 2015, AW-SOM Technologies <www.aw-som.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/clock.h>
13 #include <linux/ctype.h>
16 #define NFC_CTL 0x00000000
17 #define NFC_ST 0x00000004
18 #define NFC_INT 0x00000008
19 #define NFC_TIMING_CTL 0x0000000C
20 #define NFC_TIMING_CFG 0x00000010
21 #define NFC_ADDR_LOW 0x00000014
22 #define NFC_ADDR_HIGH 0x00000018
23 #define NFC_SECTOR_NUM 0x0000001C
24 #define NFC_CNT 0x00000020
25 #define NFC_CMD 0x00000024
26 #define NFC_RCMD_SET 0x00000028
27 #define NFC_WCMD_SET 0x0000002C
28 #define NFC_IO_DATA 0x00000030
29 #define NFC_ECC_CTL 0x00000034
30 #define NFC_ECC_ST 0x00000038
31 #define NFC_DEBUG 0x0000003C
32 #define NFC_ECC_CNT0 0x00000040
33 #define NFC_ECC_CNT1 0x00000044
34 #define NFC_ECC_CNT2 0x00000048
35 #define NFC_ECC_CNT3 0x0000004C
36 #define NFC_USER_DATA_BASE 0x00000050
37 #define NFC_EFNAND_STATUS 0x00000090
38 #define NFC_SPARE_AREA 0x000000A0
39 #define NFC_PATTERN_ID 0x000000A4
40 #define NFC_RAM0_BASE 0x00000400
41 #define NFC_RAM1_BASE 0x00000800
43 #define NFC_CTL_EN (1 << 0)
44 #define NFC_CTL_RESET (1 << 1)
45 #define NFC_CTL_RAM_METHOD (1 << 14)
46 #define NFC_CTL_PAGE_SIZE_MASK (0xf << 8)
47 #define NFC_CTL_PAGE_SIZE(a) ((fls(a) - 11) << 8)
50 #define NFC_ECC_EN (1 << 0)
51 #define NFC_ECC_PIPELINE (1 << 3)
52 #define NFC_ECC_EXCEPTION (1 << 4)
53 #define NFC_ECC_BLOCK_SIZE (1 << 5)
54 #define NFC_ECC_RANDOM_EN (1 << 9)
55 #define NFC_ECC_RANDOM_DIRECTION (1 << 10)
58 #define NFC_ADDR_NUM_OFFSET 16
59 #define NFC_SEND_ADDR (1 << 19)
60 #define NFC_ACCESS_DIR (1 << 20)
61 #define NFC_DATA_TRANS (1 << 21)
62 #define NFC_SEND_CMD1 (1 << 22)
63 #define NFC_WAIT_FLAG (1 << 23)
64 #define NFC_SEND_CMD2 (1 << 24)
65 #define NFC_SEQ (1 << 25)
66 #define NFC_DATA_SWAP_METHOD (1 << 26)
67 #define NFC_ROW_AUTO_INC (1 << 27)
68 #define NFC_SEND_CMD3 (1 << 28)
69 #define NFC_SEND_CMD4 (1 << 29)
70 #define NFC_RAW_CMD (0 << 30)
71 #define NFC_ECC_CMD (1 << 30)
72 #define NFC_PAGE_CMD (2 << 30)
74 #define NFC_ST_CMD_INT_FLAG (1 << 1)
75 #define NFC_ST_DMA_INT_FLAG (1 << 2)
76 #define NFC_ST_CMD_FIFO_STAT (1 << 3)
78 #define NFC_READ_CMD_OFFSET 0
79 #define NFC_RANDOM_READ_CMD0_OFFSET 8
80 #define NFC_RANDOM_READ_CMD1_OFFSET 16
82 #define NFC_CMD_RNDOUTSTART 0xE0
83 #define NFC_CMD_RNDOUT 0x05
84 #define NFC_CMD_READSTART 0x30
96 /* minimal "boot0" style NAND support for Allwinner A20 */
98 /* random seed used by linux */
99 const uint16_t random_seed[128] = {
100 0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
101 0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
102 0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
103 0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
104 0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
105 0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
106 0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
107 0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
108 0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
109 0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
110 0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
111 0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
112 0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
113 0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
114 0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
115 0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
118 #define DEFAULT_TIMEOUT_US 100000
120 static int check_value_inner(int offset, int expected_bits,
121 int timeout_us, int negation)
124 int val = readl(offset) & expected_bits;
125 if (negation ? !val : val)
128 } while (--timeout_us);
133 static inline int check_value(int offset, int expected_bits,
136 return check_value_inner(offset, expected_bits, timeout_us, 0);
139 static inline int check_value_negated(int offset, int unexpected_bits,
142 return check_value_inner(offset, unexpected_bits, timeout_us, 1);
145 static int nand_wait_cmd_fifo_empty(void)
147 if (!check_value_negated(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_FIFO_STAT,
148 DEFAULT_TIMEOUT_US)) {
149 printf("nand: timeout waiting for empty cmd FIFO\n");
156 static int nand_wait_int(void)
158 if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_ST_CMD_INT_FLAG,
159 DEFAULT_TIMEOUT_US)) {
160 printf("nand: timeout waiting for interruption\n");
167 static int nand_exec_cmd(u32 cmd)
171 ret = nand_wait_cmd_fifo_empty();
175 writel(NFC_ST_CMD_INT_FLAG, SUNXI_NFC_BASE + NFC_ST);
176 writel(cmd, SUNXI_NFC_BASE + NFC_CMD);
178 return nand_wait_int();
187 val = readl(SUNXI_NFC_BASE + NFC_CTL);
188 /* enable and reset CTL */
189 writel(val | NFC_CTL_EN | NFC_CTL_RESET,
190 SUNXI_NFC_BASE + NFC_CTL);
192 if (!check_value_negated(SUNXI_NFC_BASE + NFC_CTL,
193 NFC_CTL_RESET, DEFAULT_TIMEOUT_US)) {
194 printf("Couldn't initialize nand\n");
198 nand_exec_cmd(NFC_SEND_CMD1 | NFC_WAIT_FLAG | NAND_CMD_RESET);
201 static void nand_apply_config(const struct nfc_config *conf)
205 nand_wait_cmd_fifo_empty();
207 val = readl(SUNXI_NFC_BASE + NFC_CTL);
208 val &= ~NFC_CTL_PAGE_SIZE_MASK;
209 writel(val | NFC_CTL_RAM_METHOD | NFC_CTL_PAGE_SIZE(conf->page_size),
210 SUNXI_NFC_BASE + NFC_CTL);
211 writel(conf->ecc_size, SUNXI_NFC_BASE + NFC_CNT);
212 writel(conf->page_size, SUNXI_NFC_BASE + NFC_SPARE_AREA);
215 static int nand_load_page(const struct nfc_config *conf, u32 offs)
217 int page = offs / conf->page_size;
219 writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET) |
220 (NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET) |
221 (NFC_CMD_READSTART << NFC_READ_CMD_OFFSET),
222 SUNXI_NFC_BASE + NFC_RCMD_SET);
223 writel(((page & 0xFFFF) << 16), SUNXI_NFC_BASE + NFC_ADDR_LOW);
224 writel((page >> 16) & 0xFF, SUNXI_NFC_BASE + NFC_ADDR_HIGH);
226 return nand_exec_cmd(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD |
227 NFC_SEND_ADDR | NFC_WAIT_FLAG |
228 ((conf->addr_cycles - 1) << NFC_ADDR_NUM_OFFSET));
231 static int nand_change_column(u16 column)
235 writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET) |
236 (NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET) |
237 (NFC_CMD_RNDOUTSTART << NFC_READ_CMD_OFFSET),
238 SUNXI_NFC_BASE + NFC_RCMD_SET);
239 writel(column, SUNXI_NFC_BASE + NFC_ADDR_LOW);
241 ret = nand_exec_cmd(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_RAW_CMD |
242 (1 << NFC_ADDR_NUM_OFFSET) | NFC_SEND_ADDR |
247 /* Ensure tCCS has passed before reading data */
253 static const int ecc_bytes[] = {32, 46, 54, 60, 74, 88, 102, 110, 116};
255 static int nand_read_page(const struct nfc_config *conf, u32 offs,
258 int nsectors = len / conf->ecc_size;
260 int oob_chunk_sz = ecc_bytes[conf->ecc_strength];
261 int page = offs / conf->page_size;
265 if (offs % conf->page_size || len % conf->ecc_size ||
266 len > conf->page_size || len < 0)
269 /* Choose correct seed if randomized */
271 rand_seed = random_seed[page % conf->nseeds];
273 /* Retrieve data from SRAM (PIO) */
274 for (i = 0; i < nsectors; i++) {
275 int data_off = i * conf->ecc_size;
276 int oob_off = conf->page_size + (i * oob_chunk_sz);
277 u8 *data = dest + data_off;
279 /* Clear ECC status and restart ECC engine */
280 writel(0, SUNXI_NFC_BASE + NFC_ECC_ST);
281 writel((rand_seed << 16) | (conf->ecc_strength << 12) |
282 (conf->randomize ? NFC_ECC_RANDOM_EN : 0) |
283 (conf->ecc_size == 512 ? NFC_ECC_BLOCK_SIZE : 0) |
284 NFC_ECC_EN | NFC_ECC_EXCEPTION,
285 SUNXI_NFC_BASE + NFC_ECC_CTL);
287 /* Move the data in SRAM */
288 nand_change_column(data_off);
289 writel(conf->ecc_size, SUNXI_NFC_BASE + NFC_CNT);
290 nand_exec_cmd(NFC_DATA_TRANS);
293 * Let the ECC engine consume the ECC bytes and possibly correct
296 nand_change_column(oob_off);
297 nand_exec_cmd(NFC_DATA_TRANS | NFC_ECC_CMD);
299 /* Get the ECC status */
300 ecc_st = readl(SUNXI_NFC_BASE + NFC_ECC_ST);
302 /* ECC error detected. */
307 * Return 1 if the first chunk is empty (needed for
308 * configuration detection).
310 if (!i && (ecc_st & 0x10000))
313 /* Retrieve the data from SRAM */
314 memcpy_fromio(data, SUNXI_NFC_BASE + NFC_RAM0_BASE,
317 /* Stop the ECC engine */
318 writel(readl(SUNXI_NFC_BASE + NFC_ECC_CTL) & ~NFC_ECC_EN,
319 SUNXI_NFC_BASE + NFC_ECC_CTL);
321 if (data_off + conf->ecc_size >= len)
328 static int nand_max_ecc_strength(struct nfc_config *conf)
330 int max_oobsize, max_ecc_bytes;
331 int nsectors = conf->page_size / conf->ecc_size;
335 * ECC strength is limited by the size of the OOB area which is
336 * correlated with the page size.
338 switch (conf->page_size) {
355 max_ecc_bytes = max_oobsize / nsectors;
357 for (i = 0; i < ARRAY_SIZE(ecc_bytes); i++) {
358 if (ecc_bytes[i] > max_ecc_bytes)
368 static int nand_detect_ecc_config(struct nfc_config *conf, u32 offs,
371 /* NAND with pages > 4k will likely require 1k sector size. */
372 int min_ecc_size = conf->page_size > 4096 ? 1024 : 512;
373 int page = offs / conf->page_size;
377 * In most cases, 1k sectors are preferred over 512b ones, start
378 * testing this config first.
380 for (conf->ecc_size = 1024; conf->ecc_size >= min_ecc_size;
381 conf->ecc_size >>= 1) {
382 int max_ecc_strength = nand_max_ecc_strength(conf);
384 nand_apply_config(conf);
387 * We are starting from the maximum ECC strength because
388 * most of the time NAND vendors provide an OOB area that
389 * barely meets the ECC requirements.
391 for (conf->ecc_strength = max_ecc_strength;
392 conf->ecc_strength >= 0;
393 conf->ecc_strength--) {
394 conf->randomize = false;
395 if (nand_change_column(0))
399 * Only read the first sector to speedup detection.
401 ret = nand_read_page(conf, offs, dest, conf->ecc_size);
404 } else if (ret > 0) {
406 * If page is empty we can't deduce anything
407 * about the ECC config => stop the detection.
412 conf->randomize = true;
413 conf->nseeds = ARRAY_SIZE(random_seed);
415 if (nand_change_column(0))
418 if (!nand_read_page(conf, offs, dest,
423 * Find the next ->nseeds value that would
424 * change the randomizer seed for the page
425 * we're trying to read.
427 while (conf->nseeds >= 16) {
428 int seed = page % conf->nseeds;
431 if (seed != page % conf->nseeds)
434 } while (conf->nseeds >= 16);
441 static int nand_detect_config(struct nfc_config *conf, u32 offs, void *dest)
447 * Modern NANDs are more likely than legacy ones, so we start testing
448 * with 5 address cycles.
450 for (conf->addr_cycles = 5;
451 conf->addr_cycles >= 4;
452 conf->addr_cycles--) {
453 int max_page_size = conf->addr_cycles == 4 ? 2048 : 16384;
456 * Ignoring 1k pages cause I'm not even sure this case exist
459 for (conf->page_size = 2048; conf->page_size <= max_page_size;
460 conf->page_size <<= 1) {
461 if (nand_load_page(conf, offs))
464 if (!nand_detect_ecc_config(conf, offs, dest)) {
474 static int nand_read_buffer(struct nfc_config *conf, uint32_t offs,
475 unsigned int size, void *dest)
477 int first_seed = 0, page, ret;
479 size = ALIGN(size, conf->page_size);
480 page = offs / conf->page_size;
482 first_seed = page % conf->nseeds;
484 for (; size; size -= conf->page_size) {
485 if (nand_load_page(conf, offs))
488 ret = nand_read_page(conf, offs, dest, conf->page_size);
490 * The ->nseeds value should be equal to the number of pages
491 * in an eraseblock. Since we don't know this information in
492 * advance we might have picked a wrong value.
494 if (ret < 0 && conf->randomize) {
495 int cur_seed = page % conf->nseeds;
498 * We already tried all the seed values => we are
499 * facing a real corruption.
501 if (cur_seed < first_seed)
504 /* Try to adjust ->nseeds and read the page again... */
505 conf->nseeds = cur_seed;
507 if (nand_change_column(0))
510 /* ... it still fails => it's a real corruption. */
511 if (nand_read_page(conf, offs, dest, conf->page_size))
513 } else if (ret && conf->randomize) {
514 memset(dest, 0xff, conf->page_size);
518 offs += conf->page_size;
519 dest += conf->page_size;
525 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
527 static struct nfc_config conf = { };
530 ret = nand_detect_config(&conf, offs, dest);
534 return nand_read_buffer(&conf, offs, size, dest);
537 void nand_deselect(void)
539 struct sunxi_ccm_reg *const ccm =
540 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
542 clrbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
543 #ifdef CONFIG_MACH_SUN9I
544 clrbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
546 clrbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
548 clrbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);