2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
4 * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
5 * (C) Copyright 2006 DENX Software Engineering
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/clock.h>
30 #include <asm/arch/funcmux.h>
31 #include <asm/arch-tegra/clk_rst.h>
32 #include <asm/errno.h>
35 #include "tegra_nand.h"
37 DECLARE_GLOBAL_DATA_PTR;
39 #define NAND_CMD_TIMEOUT_MS 10
41 #define SKIPPED_SPARE_BYTES 4
43 /* ECC bytes to be generated for tag data */
44 #define TAG_ECC_BYTES 4
46 /* 64 byte oob block info for large page (== 2KB) device
48 * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
54 * Yaffs2 will use 16 tag bytes.
56 static struct nand_ecclayout eccoob = {
59 4, 5, 6, 7, 8, 9, 10, 11, 12,
60 13, 14, 15, 16, 17, 18, 19, 20, 21,
61 22, 23, 24, 25, 26, 27, 28, 29, 30,
62 31, 32, 33, 34, 35, 36, 37, 38, 39,
75 ECC_TAG_ERROR = 1 << 0,
76 ECC_DATA_ERROR = 1 << 1
79 /* Timing parameters */
81 FDT_NAND_MAX_TRP_TREA,
83 FDT_NAND_MAX_TCR_TAR_TRR,
85 FDT_NAND_MAX_TCS_TCH_TALS_TALH,
94 /* Information about an attached NAND chip */
96 struct nand_ctlr *reg;
97 int enabled; /* 1 to enable, 0 to disable */
98 struct fdt_gpio_state wp_gpio; /* write-protect GPIO */
99 s32 width; /* bit width, normally 8 */
100 u32 timing[FDT_NAND_TIMING_COUNT];
104 struct nand_ctlr *reg;
107 * When running in PIO mode to get READ ID bytes from register
108 * RESP_0, we need this variable as an index to know which byte in
109 * register RESP_0 should be read.
110 * Because common code in nand_base.c invokes read_byte function two
111 * times for NAND_CMD_READID.
112 * And our controller returns 4 bytes at once in register RESP_0.
115 struct fdt_nand config;
118 static struct nand_drv nand_ctrl;
119 static struct mtd_info *our_mtd;
120 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
122 #ifdef CONFIG_SYS_DCACHE_OFF
123 static inline void dma_prepare(void *start, unsigned long length,
129 * Prepare for a DMA transaction
131 * For a write we flush out our data. For a read we invalidate, since we
132 * need to do this before we read from the buffer after the DMA has
133 * completed, so may as well do it now.
135 * @param start Start address for DMA buffer (should be cache-aligned)
136 * @param length Length of DMA buffer in bytes
137 * @param is_writing 0 if reading, non-zero if writing
139 static void dma_prepare(void *start, unsigned long length, int is_writing)
141 unsigned long addr = (unsigned long)start;
143 length = ALIGN(length, ARCH_DMA_MINALIGN);
145 flush_dcache_range(addr, addr + length);
147 invalidate_dcache_range(addr, addr + length);
152 * Wait for command completion
154 * @param reg nand_ctlr structure
156 * 1 - Command completed
159 static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
165 for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) {
166 if ((readl(®->command) & CMD_GO) ||
167 !(readl(®->status) & STATUS_RBSY0) ||
168 !(readl(®->isr) & ISR_IS_CMD_DONE)) {
172 reg_val = readl(®->dma_mst_ctrl);
174 * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE
175 * is set, that means DMA engine is running.
177 * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE
178 * is cleared, indicating DMA transfer completion.
180 running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE |
181 DMA_MST_CTRL_EN_B_ENABLE);
182 if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE))
190 * Read one byte from the chip
192 * @param mtd MTD device structure
195 * Read function for 8bit bus-width
197 static uint8_t read_byte(struct mtd_info *mtd)
199 struct nand_chip *chip = mtd->priv;
201 struct nand_drv *info;
203 info = (struct nand_drv *)chip->priv;
205 /* In PIO mode, only 4 bytes can be transferred with single CMD_GO. */
206 if (info->pio_byte_index > 3) {
207 info->pio_byte_index = 0;
208 writel(CMD_GO | CMD_PIO
210 &info->reg->command);
211 if (!nand_waitfor_cmd_completion(info->reg))
212 printf("Command timeout\n");
215 dword_read = readl(&info->reg->resp);
216 dword_read = dword_read >> (8 * info->pio_byte_index);
217 info->pio_byte_index++;
218 return (uint8_t)dword_read;
222 * Check NAND status to see if it is ready or not
224 * @param mtd MTD device structure
229 static int nand_dev_ready(struct mtd_info *mtd)
231 struct nand_chip *chip = mtd->priv;
233 struct nand_drv *info;
235 info = (struct nand_drv *)chip->priv;
237 reg_val = readl(&info->reg->status);
238 if (reg_val & STATUS_RBSY0)
244 /* Dummy implementation: we don't support multiple chips */
245 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
258 * Clear all interrupt status bits
260 * @param reg nand_ctlr structure
262 static void nand_clear_interrupt_status(struct nand_ctlr *reg)
266 /* Clear interrupt status */
267 reg_val = readl(®->isr);
268 writel(reg_val, ®->isr);
272 * Send command to NAND device
274 * @param mtd MTD device structure
275 * @param command the command to be sent
276 * @param column the column address for this command, -1 if none
277 * @param page_addr the page address for this command, -1 if none
279 static void nand_command(struct mtd_info *mtd, unsigned int command,
280 int column, int page_addr)
282 struct nand_chip *chip = mtd->priv;
283 struct nand_drv *info;
285 info = (struct nand_drv *)chip->priv;
288 * Write out the command to the device.
290 * Only command NAND_CMD_RESET or NAND_CMD_READID will come
291 * here before mtd->writesize is initialized.
294 /* Emulate NAND_CMD_READOOB */
295 if (command == NAND_CMD_READOOB) {
296 assert(mtd->writesize != 0);
297 column += mtd->writesize;
298 command = NAND_CMD_READ0;
301 /* Adjust columns for 16 bit bus-width */
302 if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
305 nand_clear_interrupt_status(info->reg);
307 /* Stop DMA engine, clear DMA completion status */
308 writel(DMA_MST_CTRL_EN_A_DISABLE
309 | DMA_MST_CTRL_EN_B_DISABLE
310 | DMA_MST_CTRL_IS_DMA_DONE,
311 &info->reg->dma_mst_ctrl);
314 * Program and erase have their own busy handlers
315 * status and sequential in needs no delay
318 case NAND_CMD_READID:
319 writel(NAND_CMD_READID, &info->reg->cmd_reg1);
320 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_PIO
322 ((4 - 1) << CMD_TRANS_SIZE_SHIFT)
324 &info->reg->command);
325 info->pio_byte_index = 0;
328 writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
329 writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
330 writel((page_addr << 16) | (column & 0xFFFF),
331 &info->reg->addr_reg1);
332 writel(page_addr >> 16, &info->reg->addr_reg2);
335 writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1);
336 writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2);
337 writel((page_addr << 16) | (column & 0xFFFF),
338 &info->reg->addr_reg1);
339 writel(page_addr >> 16,
340 &info->reg->addr_reg2);
342 case NAND_CMD_PAGEPROG:
344 case NAND_CMD_ERASE1:
345 writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1);
346 writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2);
347 writel(page_addr, &info->reg->addr_reg1);
348 writel(CMD_GO | CMD_CLE | CMD_ALE |
349 CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3,
350 &info->reg->command);
352 case NAND_CMD_ERASE2:
354 case NAND_CMD_STATUS:
355 writel(NAND_CMD_STATUS, &info->reg->cmd_reg1);
356 writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX
357 | ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
359 &info->reg->command);
360 info->pio_byte_index = 0;
363 writel(NAND_CMD_RESET, &info->reg->cmd_reg1);
364 writel(CMD_GO | CMD_CLE | CMD_CE0,
365 &info->reg->command);
367 case NAND_CMD_RNDOUT:
369 printf("%s: Unsupported command %d\n", __func__, command);
372 if (!nand_waitfor_cmd_completion(info->reg))
373 printf("Command 0x%02X timeout\n", command);
377 * Check whether the pointed buffer are all 0xff (blank).
379 * @param buf data buffer for blank check
380 * @param len length of the buffer in byte
385 static int blank_check(u8 *buf, int len)
389 for (i = 0; i < len; i++)
396 * After a DMA transfer for read, we call this function to see whether there
397 * is any uncorrectable error on the pointed data buffer or oob buffer.
399 * @param reg nand_ctlr structure
400 * @param databuf data buffer
401 * @param a_len data buffer length
402 * @param oobbuf oob buffer
403 * @param b_len oob buffer length
405 * ECC_OK - no ECC error or correctable ECC error
406 * ECC_TAG_ERROR - uncorrectable tag ECC error
407 * ECC_DATA_ERROR - uncorrectable data ECC error
408 * ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error
410 static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf,
411 int a_len, u8 *oobbuf, int b_len)
413 int return_val = ECC_OK;
416 if (!(readl(®->isr) & ISR_IS_ECC_ERR))
420 * Area A is used for the data block (databuf). Area B is used for
421 * the spare block (oobbuf)
423 reg_val = readl(®->dec_status);
424 if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) {
425 reg_val = readl(®->bch_dec_status_buf);
427 * If uncorrectable error occurs on data area, then see whether
428 * they are all FF. If all are FF, it's a blank page.
431 if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) &&
432 !blank_check(databuf, a_len))
433 return_val |= ECC_DATA_ERROR;
436 if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) {
437 reg_val = readl(®->bch_dec_status_buf);
439 * If uncorrectable error occurs on tag area, then see whether
440 * they are all FF. If all are FF, it's a blank page.
443 if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) &&
444 !blank_check(oobbuf, b_len))
445 return_val |= ECC_TAG_ERROR;
452 * Set GO bit to send command to device
454 * @param reg nand_ctlr structure
456 static void start_command(struct nand_ctlr *reg)
460 reg_val = readl(®->command);
462 writel(reg_val, ®->command);
466 * Clear command GO bit, DMA GO bit, and DMA completion status
468 * @param reg nand_ctlr structure
470 static void stop_command(struct nand_ctlr *reg)
473 writel(0, ®->command);
475 /* Stop DMA engine and clear DMA completion status */
476 writel(DMA_MST_CTRL_GO_DISABLE
477 | DMA_MST_CTRL_IS_DMA_DONE,
482 * Set up NAND bus width and page size
484 * @param info nand_info structure
485 * @param *reg_val address of reg_val
486 * @return 0 if ok, -1 on error
488 static int set_bus_width_page_size(struct fdt_nand *config,
491 if (config->width == 8)
492 *reg_val = CFG_BUS_WIDTH_8BIT;
493 else if (config->width == 16)
494 *reg_val = CFG_BUS_WIDTH_16BIT;
496 debug("%s: Unsupported bus width %d\n", __func__,
501 if (our_mtd->writesize == 512)
502 *reg_val |= CFG_PAGE_SIZE_512;
503 else if (our_mtd->writesize == 2048)
504 *reg_val |= CFG_PAGE_SIZE_2048;
505 else if (our_mtd->writesize == 4096)
506 *reg_val |= CFG_PAGE_SIZE_4096;
508 debug("%s: Unsupported page size %d\n", __func__,
517 * Page read/write function
519 * @param mtd mtd info structure
520 * @param chip nand chip info structure
521 * @param buf data buffer
522 * @param page page number
523 * @param with_ecc 1 to enable ECC, 0 to disable ECC
524 * @param is_writing 0 for read, 1 for write
525 * @return 0 when successfully completed
526 * -EIO when command timeout
528 static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
529 uint8_t *buf, int page, int with_ecc, int is_writing)
533 struct nand_oobfree *free = chip->ecc.layout->oobfree;
534 /* 4*128=512 (byte) is the value that our HW can support. */
535 ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128);
537 struct nand_drv *info;
538 struct fdt_nand *config;
540 if ((uintptr_t)buf & 0x03) {
541 printf("buf %p has to be 4-byte aligned\n", buf);
545 info = (struct nand_drv *)chip->priv;
546 config = &info->config;
547 if (set_bus_width_page_size(config, ®_val))
550 /* Need to be 4-byte aligned */
551 tag_ptr = (char *)tag_buf;
553 stop_command(info->reg);
555 writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
556 writel(virt_to_phys(buf), &info->reg->data_block_ptr);
559 writel(virt_to_phys(tag_ptr), &info->reg->tag_ptr);
561 memcpy(tag_ptr, chip->oob_poi + free->offset,
562 chip->ecc.layout->oobavail +
565 writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr);
568 /* Set ECC selection, configure ECC settings */
570 tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
571 reg_val |= (CFG_SKIP_SPARE_SEL_4
572 | CFG_SKIP_SPARE_ENABLE
573 | CFG_HW_ECC_CORRECTION_ENABLE
574 | CFG_ECC_EN_TAG_DISABLE
581 tag_size += SKIPPED_SPARE_BYTES;
582 dma_prepare(tag_ptr, tag_size, is_writing);
584 tag_size = mtd->oobsize;
585 reg_val |= (CFG_SKIP_SPARE_DISABLE
586 | CFG_HW_ECC_CORRECTION_DISABLE
587 | CFG_ECC_EN_TAG_DISABLE
590 dma_prepare(chip->oob_poi, tag_size, is_writing);
592 writel(reg_val, &info->reg->config);
594 dma_prepare(buf, 1 << chip->page_shift, is_writing);
596 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
598 writel(tag_size - 1, &info->reg->dma_cfg_b);
600 nand_clear_interrupt_status(info->reg);
602 reg_val = CMD_CLE | CMD_ALE
604 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
607 | (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT)
610 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
612 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
613 writel(reg_val, &info->reg->command);
615 /* Setup DMA engine */
616 reg_val = DMA_MST_CTRL_GO_ENABLE
617 | DMA_MST_CTRL_BURST_8WORDS
618 | DMA_MST_CTRL_EN_A_ENABLE
619 | DMA_MST_CTRL_EN_B_ENABLE;
622 reg_val |= DMA_MST_CTRL_DIR_READ;
624 reg_val |= DMA_MST_CTRL_DIR_WRITE;
626 writel(reg_val, &info->reg->dma_mst_ctrl);
628 start_command(info->reg);
630 if (!nand_waitfor_cmd_completion(info->reg)) {
632 printf("Read Page 0x%X timeout ", page);
634 printf("Write Page 0x%X timeout ", page);
638 printf("without ECC");
643 if (with_ecc && !is_writing) {
644 memcpy(chip->oob_poi, tag_ptr,
645 SKIPPED_SPARE_BYTES);
646 memcpy(chip->oob_poi + free->offset,
647 tag_ptr + SKIPPED_SPARE_BYTES,
648 chip->ecc.layout->oobavail);
649 reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf,
650 1 << chip->page_shift,
651 (u8 *)(tag_ptr + SKIPPED_SPARE_BYTES),
652 chip->ecc.layout->oobavail);
653 if (reg_val & ECC_TAG_ERROR)
654 printf("Read Page 0x%X tag ECC error\n", page);
655 if (reg_val & ECC_DATA_ERROR)
656 printf("Read Page 0x%X data ECC error\n",
658 if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR))
665 * Hardware ecc based page read function
667 * @param mtd mtd info structure
668 * @param chip nand chip info structure
669 * @param buf buffer to store read data
670 * @param page page number to read
671 * @return 0 when successfully completed
672 * -EIO when command timeout
674 static int nand_read_page_hwecc(struct mtd_info *mtd,
675 struct nand_chip *chip, uint8_t *buf, int page)
677 return nand_rw_page(mtd, chip, buf, page, 1, 0);
681 * Hardware ecc based page write function
683 * @param mtd mtd info structure
684 * @param chip nand chip info structure
685 * @param buf data buffer
687 static void nand_write_page_hwecc(struct mtd_info *mtd,
688 struct nand_chip *chip, const uint8_t *buf)
691 struct nand_drv *info;
693 info = (struct nand_drv *)chip->priv;
695 page = (readl(&info->reg->addr_reg1) >> 16) |
696 (readl(&info->reg->addr_reg2) << 16);
698 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
703 * Read raw page data without ecc
705 * @param mtd mtd info structure
706 * @param chip nand chip info structure
707 * @param buf buffer to store read data
708 * @param page page number to read
709 * @return 0 when successfully completed
710 * -EINVAL when chip->oob_poi is not double-word aligned
711 * -EIO when command timeout
713 static int nand_read_page_raw(struct mtd_info *mtd,
714 struct nand_chip *chip, uint8_t *buf, int page)
716 return nand_rw_page(mtd, chip, buf, page, 0, 0);
720 * Raw page write function
722 * @param mtd mtd info structure
723 * @param chip nand chip info structure
724 * @param buf data buffer
726 static void nand_write_page_raw(struct mtd_info *mtd,
727 struct nand_chip *chip, const uint8_t *buf)
730 struct nand_drv *info;
732 info = (struct nand_drv *)chip->priv;
733 page = (readl(&info->reg->addr_reg1) >> 16) |
734 (readl(&info->reg->addr_reg2) << 16);
736 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
740 * OOB data read/write function
742 * @param mtd mtd info structure
743 * @param chip nand chip info structure
744 * @param page page number to read
745 * @param with_ecc 1 to enable ECC, 0 to disable ECC
746 * @param is_writing 0 for read, 1 for write
747 * @return 0 when successfully completed
748 * -EINVAL when chip->oob_poi is not double-word aligned
749 * -EIO when command timeout
751 static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
752 int page, int with_ecc, int is_writing)
756 struct nand_oobfree *free = chip->ecc.layout->oobfree;
757 struct nand_drv *info;
759 if (((int)chip->oob_poi) & 0x03)
761 info = (struct nand_drv *)chip->priv;
762 if (set_bus_width_page_size(&info->config, ®_val))
765 stop_command(info->reg);
767 writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr);
769 /* Set ECC selection */
770 tag_size = mtd->oobsize;
772 reg_val |= CFG_ECC_EN_TAG_ENABLE;
774 reg_val |= (CFG_ECC_EN_TAG_DISABLE);
776 reg_val |= ((tag_size - 1) |
777 CFG_SKIP_SPARE_DISABLE |
778 CFG_HW_ECC_CORRECTION_DISABLE |
780 writel(reg_val, &info->reg->config);
782 dma_prepare(chip->oob_poi, tag_size, is_writing);
784 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
786 if (is_writing && with_ecc)
787 tag_size -= TAG_ECC_BYTES;
789 writel(tag_size - 1, &info->reg->dma_cfg_b);
791 nand_clear_interrupt_status(info->reg);
793 reg_val = CMD_CLE | CMD_ALE
795 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
799 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
801 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
802 writel(reg_val, &info->reg->command);
804 /* Setup DMA engine */
805 reg_val = DMA_MST_CTRL_GO_ENABLE
806 | DMA_MST_CTRL_BURST_8WORDS
807 | DMA_MST_CTRL_EN_B_ENABLE;
809 reg_val |= DMA_MST_CTRL_DIR_READ;
811 reg_val |= DMA_MST_CTRL_DIR_WRITE;
813 writel(reg_val, &info->reg->dma_mst_ctrl);
815 start_command(info->reg);
817 if (!nand_waitfor_cmd_completion(info->reg)) {
819 printf("Read OOB of Page 0x%X timeout\n", page);
821 printf("Write OOB of Page 0x%X timeout\n", page);
825 if (with_ecc && !is_writing) {
826 reg_val = (u32)check_ecc_error(info->reg, 0, 0,
827 (u8 *)(chip->oob_poi + free->offset),
828 chip->ecc.layout->oobavail);
829 if (reg_val & ECC_TAG_ERROR)
830 printf("Read OOB of Page 0x%X tag ECC error\n", page);
836 * OOB data read function
838 * @param mtd mtd info structure
839 * @param chip nand chip info structure
840 * @param page page number to read
841 * @param sndcmd flag whether to issue read command or not
842 * @return 1 - issue read command next time
845 static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
846 int page, int sndcmd)
849 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
852 nand_rw_oob(mtd, chip, page, 0, 0);
857 * OOB data write function
859 * @param mtd mtd info structure
860 * @param chip nand chip info structure
861 * @param page page number to write
862 * @return 0 when successfully completed
863 * -EINVAL when chip->oob_poi is not double-word aligned
864 * -EIO when command timeout
866 static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
869 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
871 return nand_rw_oob(mtd, chip, page, 0, 1);
875 * Set up NAND memory timings according to the provided parameters
877 * @param timing Timing parameters
878 * @param reg NAND controller register address
880 static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],
881 struct nand_ctlr *reg)
883 u32 reg_val, clk_rate, clk_period, time_val;
885 clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH,
886 CLOCK_ID_PERIPH) / 1000000;
887 clk_period = 1000 / clk_rate;
888 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
889 TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK;
890 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) <<
891 TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK;
892 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period;
894 reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) &
895 TIMING_TCR_TAR_TRR_CNT_MASK;
896 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) <<
897 TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK;
898 time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period;
900 reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) &
902 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) <<
903 TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK;
904 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) <<
905 TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK;
906 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) <<
907 TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK;
908 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
909 TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK;
910 writel(reg_val, ®->timing);
913 time_val = timing[FDT_NAND_TADL] / clk_period;
915 reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK;
916 writel(reg_val, ®->timing2);
920 * Decode NAND parameters from the device tree
922 * @param blob Device tree blob
923 * @param node Node containing "nand-flash" compatble node
924 * @return 0 if ok, -ve on error (FDT_ERR_...)
926 static int fdt_decode_nand(const void *blob, int node, struct fdt_nand *config)
930 config->reg = (struct nand_ctlr *)fdtdec_get_addr(blob, node, "reg");
931 config->enabled = fdtdec_get_is_enabled(blob, node);
932 config->width = fdtdec_get_int(blob, node, "nvidia,nand-width", 8);
933 err = fdtdec_decode_gpio(blob, node, "nvidia,wp-gpios",
937 err = fdtdec_get_int_array(blob, node, "nvidia,timing",
938 config->timing, FDT_NAND_TIMING_COUNT);
942 /* Now look up the controller and decode that */
943 node = fdt_next_node(blob, node, NULL);
951 * Board-specific NAND initialization
953 * @param nand nand chip info structure
954 * @return 0, after initialized, -1 on error
956 int tegra_nand_init(struct nand_chip *nand, int devnum)
958 struct nand_drv *info = &nand_ctrl;
959 struct fdt_nand *config = &info->config;
962 node = fdtdec_next_compatible(gd->fdt_blob, 0,
963 COMPAT_NVIDIA_TEGRA20_NAND);
966 if (fdt_decode_nand(gd->fdt_blob, node, config)) {
967 printf("Could not decode nand-flash in device tree\n");
970 if (!config->enabled)
972 info->reg = config->reg;
973 nand->ecc.mode = NAND_ECC_HW;
974 nand->ecc.layout = &eccoob;
976 nand->options = LP_OPTIONS;
977 nand->cmdfunc = nand_command;
978 nand->read_byte = read_byte;
979 nand->ecc.read_page = nand_read_page_hwecc;
980 nand->ecc.write_page = nand_write_page_hwecc;
981 nand->ecc.read_page_raw = nand_read_page_raw;
982 nand->ecc.write_page_raw = nand_write_page_raw;
983 nand->ecc.read_oob = nand_read_oob;
984 nand->ecc.write_oob = nand_write_oob;
985 nand->select_chip = nand_select_chip;
986 nand->dev_ready = nand_dev_ready;
987 nand->priv = &nand_ctrl;
989 /* Adjust controller clock rate */
990 clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000);
992 /* Adjust timing for NAND device */
993 setup_timing(config->timing, info->reg);
995 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
996 fdtdec_setup_gpio(&config->wp_gpio);
997 gpio_direction_output(config->wp_gpio.gpio, 1);
999 our_mtd = &nand_info[devnum];
1000 our_mtd->priv = nand;
1001 ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1005 nand->ecc.size = our_mtd->writesize;
1006 nand->ecc.bytes = our_mtd->oobsize;
1008 ret = nand_scan_tail(our_mtd);
1012 ret = nand_register(devnum);
1019 void board_nand_init(void)
1021 struct nand_chip *nand = &nand_chip[0];
1023 if (tegra_nand_init(nand, 0))
1024 puts("Tegra NAND init failed\n");