2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
4 * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
5 * (C) Copyright 2006 DENX Software Engineering
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/clock.h>
14 #include <asm/arch/funcmux.h>
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/errno.h>
19 #include "tegra_nand.h"
21 DECLARE_GLOBAL_DATA_PTR;
23 #define NAND_CMD_TIMEOUT_MS 10
25 #define SKIPPED_SPARE_BYTES 4
27 /* ECC bytes to be generated for tag data */
28 #define TAG_ECC_BYTES 4
30 /* 64 byte oob block info for large page (== 2KB) device
32 * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
38 * Yaffs2 will use 16 tag bytes.
40 static struct nand_ecclayout eccoob = {
43 4, 5, 6, 7, 8, 9, 10, 11, 12,
44 13, 14, 15, 16, 17, 18, 19, 20, 21,
45 22, 23, 24, 25, 26, 27, 28, 29, 30,
46 31, 32, 33, 34, 35, 36, 37, 38, 39,
59 ECC_TAG_ERROR = 1 << 0,
60 ECC_DATA_ERROR = 1 << 1
63 /* Timing parameters */
65 FDT_NAND_MAX_TRP_TREA,
67 FDT_NAND_MAX_TCR_TAR_TRR,
69 FDT_NAND_MAX_TCS_TCH_TALS_TALH,
78 /* Information about an attached NAND chip */
80 struct nand_ctlr *reg;
81 int enabled; /* 1 to enable, 0 to disable */
82 struct gpio_desc wp_gpio; /* write-protect GPIO */
83 s32 width; /* bit width, normally 8 */
84 u32 timing[FDT_NAND_TIMING_COUNT];
88 struct nand_ctlr *reg;
89 struct fdt_nand config;
92 static struct nand_drv nand_ctrl;
93 static struct mtd_info *our_mtd;
94 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
96 #ifdef CONFIG_SYS_DCACHE_OFF
97 static inline void dma_prepare(void *start, unsigned long length,
103 * Prepare for a DMA transaction
105 * For a write we flush out our data. For a read we invalidate, since we
106 * need to do this before we read from the buffer after the DMA has
107 * completed, so may as well do it now.
109 * @param start Start address for DMA buffer (should be cache-aligned)
110 * @param length Length of DMA buffer in bytes
111 * @param is_writing 0 if reading, non-zero if writing
113 static void dma_prepare(void *start, unsigned long length, int is_writing)
115 unsigned long addr = (unsigned long)start;
117 length = ALIGN(length, ARCH_DMA_MINALIGN);
119 flush_dcache_range(addr, addr + length);
121 invalidate_dcache_range(addr, addr + length);
126 * Wait for command completion
128 * @param reg nand_ctlr structure
130 * 1 - Command completed
133 static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
139 for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) {
140 if ((readl(®->command) & CMD_GO) ||
141 !(readl(®->status) & STATUS_RBSY0) ||
142 !(readl(®->isr) & ISR_IS_CMD_DONE)) {
146 reg_val = readl(®->dma_mst_ctrl);
148 * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE
149 * is set, that means DMA engine is running.
151 * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE
152 * is cleared, indicating DMA transfer completion.
154 running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE |
155 DMA_MST_CTRL_EN_B_ENABLE);
156 if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE))
164 * Read one byte from the chip
166 * @param mtd MTD device structure
169 * Read function for 8bit bus-width
171 static uint8_t read_byte(struct mtd_info *mtd)
173 struct nand_chip *chip = mtd->priv;
174 struct nand_drv *info;
176 info = (struct nand_drv *)chip->priv;
178 writel(CMD_GO | CMD_PIO | CMD_RX | CMD_CE0 | CMD_A_VALID,
179 &info->reg->command);
180 if (!nand_waitfor_cmd_completion(info->reg))
181 printf("Command timeout\n");
183 return (uint8_t)readl(&info->reg->resp);
187 * Read len bytes from the chip into a buffer
189 * @param mtd MTD device structure
190 * @param buf buffer to store data to
191 * @param len number of bytes to read
193 * Read function for 8bit bus-width
195 static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
199 struct nand_chip *chip = mtd->priv;
200 struct nand_drv *info = (struct nand_drv *)chip->priv;
202 for (i = 0; i < len; i += 4) {
203 s = (len - i) > 4 ? 4 : len - i;
204 writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 |
205 ((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO,
206 &info->reg->command);
207 if (!nand_waitfor_cmd_completion(info->reg))
208 puts("Command timeout during read_buf\n");
209 reg = readl(&info->reg->resp);
210 memcpy(buf + i, ®, s);
215 * Check NAND status to see if it is ready or not
217 * @param mtd MTD device structure
222 static int nand_dev_ready(struct mtd_info *mtd)
224 struct nand_chip *chip = mtd->priv;
226 struct nand_drv *info;
228 info = (struct nand_drv *)chip->priv;
230 reg_val = readl(&info->reg->status);
231 if (reg_val & STATUS_RBSY0)
237 /* Dummy implementation: we don't support multiple chips */
238 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
251 * Clear all interrupt status bits
253 * @param reg nand_ctlr structure
255 static void nand_clear_interrupt_status(struct nand_ctlr *reg)
259 /* Clear interrupt status */
260 reg_val = readl(®->isr);
261 writel(reg_val, ®->isr);
265 * Send command to NAND device
267 * @param mtd MTD device structure
268 * @param command the command to be sent
269 * @param column the column address for this command, -1 if none
270 * @param page_addr the page address for this command, -1 if none
272 static void nand_command(struct mtd_info *mtd, unsigned int command,
273 int column, int page_addr)
275 struct nand_chip *chip = mtd->priv;
276 struct nand_drv *info;
278 info = (struct nand_drv *)chip->priv;
281 * Write out the command to the device.
283 * Only command NAND_CMD_RESET or NAND_CMD_READID will come
284 * here before mtd->writesize is initialized.
287 /* Emulate NAND_CMD_READOOB */
288 if (command == NAND_CMD_READOOB) {
289 assert(mtd->writesize != 0);
290 column += mtd->writesize;
291 command = NAND_CMD_READ0;
294 /* Adjust columns for 16 bit bus-width */
295 if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
298 nand_clear_interrupt_status(info->reg);
300 /* Stop DMA engine, clear DMA completion status */
301 writel(DMA_MST_CTRL_EN_A_DISABLE
302 | DMA_MST_CTRL_EN_B_DISABLE
303 | DMA_MST_CTRL_IS_DMA_DONE,
304 &info->reg->dma_mst_ctrl);
307 * Program and erase have their own busy handlers
308 * status and sequential in needs no delay
311 case NAND_CMD_READID:
312 writel(NAND_CMD_READID, &info->reg->cmd_reg1);
313 writel(column & 0xFF, &info->reg->addr_reg1);
314 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
315 &info->reg->command);
318 writel(NAND_CMD_PARAM, &info->reg->cmd_reg1);
319 writel(column & 0xFF, &info->reg->addr_reg1);
320 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
321 &info->reg->command);
324 writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
325 writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
326 writel((page_addr << 16) | (column & 0xFFFF),
327 &info->reg->addr_reg1);
328 writel(page_addr >> 16, &info->reg->addr_reg2);
331 writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1);
332 writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2);
333 writel((page_addr << 16) | (column & 0xFFFF),
334 &info->reg->addr_reg1);
335 writel(page_addr >> 16,
336 &info->reg->addr_reg2);
338 case NAND_CMD_PAGEPROG:
340 case NAND_CMD_ERASE1:
341 writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1);
342 writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2);
343 writel(page_addr, &info->reg->addr_reg1);
344 writel(CMD_GO | CMD_CLE | CMD_ALE |
345 CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3,
346 &info->reg->command);
348 case NAND_CMD_ERASE2:
350 case NAND_CMD_STATUS:
351 writel(NAND_CMD_STATUS, &info->reg->cmd_reg1);
352 writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX
353 | ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
355 &info->reg->command);
358 writel(NAND_CMD_RESET, &info->reg->cmd_reg1);
359 writel(CMD_GO | CMD_CLE | CMD_CE0,
360 &info->reg->command);
362 case NAND_CMD_RNDOUT:
364 printf("%s: Unsupported command %d\n", __func__, command);
367 if (!nand_waitfor_cmd_completion(info->reg))
368 printf("Command 0x%02X timeout\n", command);
372 * Check whether the pointed buffer are all 0xff (blank).
374 * @param buf data buffer for blank check
375 * @param len length of the buffer in byte
380 static int blank_check(u8 *buf, int len)
384 for (i = 0; i < len; i++)
391 * After a DMA transfer for read, we call this function to see whether there
392 * is any uncorrectable error on the pointed data buffer or oob buffer.
394 * @param reg nand_ctlr structure
395 * @param databuf data buffer
396 * @param a_len data buffer length
397 * @param oobbuf oob buffer
398 * @param b_len oob buffer length
400 * ECC_OK - no ECC error or correctable ECC error
401 * ECC_TAG_ERROR - uncorrectable tag ECC error
402 * ECC_DATA_ERROR - uncorrectable data ECC error
403 * ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error
405 static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf,
406 int a_len, u8 *oobbuf, int b_len)
408 int return_val = ECC_OK;
411 if (!(readl(®->isr) & ISR_IS_ECC_ERR))
415 * Area A is used for the data block (databuf). Area B is used for
416 * the spare block (oobbuf)
418 reg_val = readl(®->dec_status);
419 if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) {
420 reg_val = readl(®->bch_dec_status_buf);
422 * If uncorrectable error occurs on data area, then see whether
423 * they are all FF. If all are FF, it's a blank page.
426 if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) &&
427 !blank_check(databuf, a_len))
428 return_val |= ECC_DATA_ERROR;
431 if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) {
432 reg_val = readl(®->bch_dec_status_buf);
434 * If uncorrectable error occurs on tag area, then see whether
435 * they are all FF. If all are FF, it's a blank page.
438 if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) &&
439 !blank_check(oobbuf, b_len))
440 return_val |= ECC_TAG_ERROR;
447 * Set GO bit to send command to device
449 * @param reg nand_ctlr structure
451 static void start_command(struct nand_ctlr *reg)
455 reg_val = readl(®->command);
457 writel(reg_val, ®->command);
461 * Clear command GO bit, DMA GO bit, and DMA completion status
463 * @param reg nand_ctlr structure
465 static void stop_command(struct nand_ctlr *reg)
468 writel(0, ®->command);
470 /* Stop DMA engine and clear DMA completion status */
471 writel(DMA_MST_CTRL_GO_DISABLE
472 | DMA_MST_CTRL_IS_DMA_DONE,
477 * Set up NAND bus width and page size
479 * @param info nand_info structure
480 * @param *reg_val address of reg_val
481 * @return 0 if ok, -1 on error
483 static int set_bus_width_page_size(struct fdt_nand *config,
486 if (config->width == 8)
487 *reg_val = CFG_BUS_WIDTH_8BIT;
488 else if (config->width == 16)
489 *reg_val = CFG_BUS_WIDTH_16BIT;
491 debug("%s: Unsupported bus width %d\n", __func__,
496 if (our_mtd->writesize == 512)
497 *reg_val |= CFG_PAGE_SIZE_512;
498 else if (our_mtd->writesize == 2048)
499 *reg_val |= CFG_PAGE_SIZE_2048;
500 else if (our_mtd->writesize == 4096)
501 *reg_val |= CFG_PAGE_SIZE_4096;
503 debug("%s: Unsupported page size %d\n", __func__,
512 * Page read/write function
514 * @param mtd mtd info structure
515 * @param chip nand chip info structure
516 * @param buf data buffer
517 * @param page page number
518 * @param with_ecc 1 to enable ECC, 0 to disable ECC
519 * @param is_writing 0 for read, 1 for write
520 * @return 0 when successfully completed
521 * -EIO when command timeout
523 static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
524 uint8_t *buf, int page, int with_ecc, int is_writing)
528 struct nand_oobfree *free = chip->ecc.layout->oobfree;
529 /* 4*128=512 (byte) is the value that our HW can support. */
530 ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128);
532 struct nand_drv *info;
533 struct fdt_nand *config;
535 if ((uintptr_t)buf & 0x03) {
536 printf("buf %p has to be 4-byte aligned\n", buf);
540 info = (struct nand_drv *)chip->priv;
541 config = &info->config;
542 if (set_bus_width_page_size(config, ®_val))
545 /* Need to be 4-byte aligned */
546 tag_ptr = (char *)tag_buf;
548 stop_command(info->reg);
550 writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
551 writel(virt_to_phys(buf), &info->reg->data_block_ptr);
554 writel(virt_to_phys(tag_ptr), &info->reg->tag_ptr);
556 memcpy(tag_ptr, chip->oob_poi + free->offset,
557 chip->ecc.layout->oobavail +
560 writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr);
563 /* Set ECC selection, configure ECC settings */
565 tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
566 reg_val |= (CFG_SKIP_SPARE_SEL_4
567 | CFG_SKIP_SPARE_ENABLE
568 | CFG_HW_ECC_CORRECTION_ENABLE
569 | CFG_ECC_EN_TAG_DISABLE
576 tag_size += SKIPPED_SPARE_BYTES;
577 dma_prepare(tag_ptr, tag_size, is_writing);
579 tag_size = mtd->oobsize;
580 reg_val |= (CFG_SKIP_SPARE_DISABLE
581 | CFG_HW_ECC_CORRECTION_DISABLE
582 | CFG_ECC_EN_TAG_DISABLE
585 dma_prepare(chip->oob_poi, tag_size, is_writing);
587 writel(reg_val, &info->reg->config);
589 dma_prepare(buf, 1 << chip->page_shift, is_writing);
591 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
593 writel(tag_size - 1, &info->reg->dma_cfg_b);
595 nand_clear_interrupt_status(info->reg);
597 reg_val = CMD_CLE | CMD_ALE
599 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
602 | (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT)
605 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
607 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
608 writel(reg_val, &info->reg->command);
610 /* Setup DMA engine */
611 reg_val = DMA_MST_CTRL_GO_ENABLE
612 | DMA_MST_CTRL_BURST_8WORDS
613 | DMA_MST_CTRL_EN_A_ENABLE
614 | DMA_MST_CTRL_EN_B_ENABLE;
617 reg_val |= DMA_MST_CTRL_DIR_READ;
619 reg_val |= DMA_MST_CTRL_DIR_WRITE;
621 writel(reg_val, &info->reg->dma_mst_ctrl);
623 start_command(info->reg);
625 if (!nand_waitfor_cmd_completion(info->reg)) {
627 printf("Read Page 0x%X timeout ", page);
629 printf("Write Page 0x%X timeout ", page);
633 printf("without ECC");
638 if (with_ecc && !is_writing) {
639 memcpy(chip->oob_poi, tag_ptr,
640 SKIPPED_SPARE_BYTES);
641 memcpy(chip->oob_poi + free->offset,
642 tag_ptr + SKIPPED_SPARE_BYTES,
643 chip->ecc.layout->oobavail);
644 reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf,
645 1 << chip->page_shift,
646 (u8 *)(tag_ptr + SKIPPED_SPARE_BYTES),
647 chip->ecc.layout->oobavail);
648 if (reg_val & ECC_TAG_ERROR)
649 printf("Read Page 0x%X tag ECC error\n", page);
650 if (reg_val & ECC_DATA_ERROR)
651 printf("Read Page 0x%X data ECC error\n",
653 if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR))
660 * Hardware ecc based page read function
662 * @param mtd mtd info structure
663 * @param chip nand chip info structure
664 * @param buf buffer to store read data
665 * @param page page number to read
666 * @return 0 when successfully completed
667 * -EIO when command timeout
669 static int nand_read_page_hwecc(struct mtd_info *mtd,
670 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
672 return nand_rw_page(mtd, chip, buf, page, 1, 0);
676 * Hardware ecc based page write function
678 * @param mtd mtd info structure
679 * @param chip nand chip info structure
680 * @param buf data buffer
682 static int nand_write_page_hwecc(struct mtd_info *mtd,
683 struct nand_chip *chip, const uint8_t *buf, int oob_required)
686 struct nand_drv *info;
688 info = (struct nand_drv *)chip->priv;
690 page = (readl(&info->reg->addr_reg1) >> 16) |
691 (readl(&info->reg->addr_reg2) << 16);
693 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
699 * Read raw page data without ecc
701 * @param mtd mtd info structure
702 * @param chip nand chip info structure
703 * @param buf buffer to store read data
704 * @param page page number to read
705 * @return 0 when successfully completed
706 * -EINVAL when chip->oob_poi is not double-word aligned
707 * -EIO when command timeout
709 static int nand_read_page_raw(struct mtd_info *mtd,
710 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
712 return nand_rw_page(mtd, chip, buf, page, 0, 0);
716 * Raw page write function
718 * @param mtd mtd info structure
719 * @param chip nand chip info structure
720 * @param buf data buffer
722 static int nand_write_page_raw(struct mtd_info *mtd,
723 struct nand_chip *chip, const uint8_t *buf, int oob_required)
726 struct nand_drv *info;
728 info = (struct nand_drv *)chip->priv;
729 page = (readl(&info->reg->addr_reg1) >> 16) |
730 (readl(&info->reg->addr_reg2) << 16);
732 nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
737 * OOB data read/write function
739 * @param mtd mtd info structure
740 * @param chip nand chip info structure
741 * @param page page number to read
742 * @param with_ecc 1 to enable ECC, 0 to disable ECC
743 * @param is_writing 0 for read, 1 for write
744 * @return 0 when successfully completed
745 * -EINVAL when chip->oob_poi is not double-word aligned
746 * -EIO when command timeout
748 static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
749 int page, int with_ecc, int is_writing)
753 struct nand_oobfree *free = chip->ecc.layout->oobfree;
754 struct nand_drv *info;
756 if (((int)chip->oob_poi) & 0x03)
758 info = (struct nand_drv *)chip->priv;
759 if (set_bus_width_page_size(&info->config, ®_val))
762 stop_command(info->reg);
764 writel(virt_to_phys(chip->oob_poi), &info->reg->tag_ptr);
766 /* Set ECC selection */
767 tag_size = mtd->oobsize;
769 reg_val |= CFG_ECC_EN_TAG_ENABLE;
771 reg_val |= (CFG_ECC_EN_TAG_DISABLE);
773 reg_val |= ((tag_size - 1) |
774 CFG_SKIP_SPARE_DISABLE |
775 CFG_HW_ECC_CORRECTION_DISABLE |
777 writel(reg_val, &info->reg->config);
779 dma_prepare(chip->oob_poi, tag_size, is_writing);
781 writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
783 if (is_writing && with_ecc)
784 tag_size -= TAG_ECC_BYTES;
786 writel(tag_size - 1, &info->reg->dma_cfg_b);
788 nand_clear_interrupt_status(info->reg);
790 reg_val = CMD_CLE | CMD_ALE
792 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
796 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
798 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
799 writel(reg_val, &info->reg->command);
801 /* Setup DMA engine */
802 reg_val = DMA_MST_CTRL_GO_ENABLE
803 | DMA_MST_CTRL_BURST_8WORDS
804 | DMA_MST_CTRL_EN_B_ENABLE;
806 reg_val |= DMA_MST_CTRL_DIR_READ;
808 reg_val |= DMA_MST_CTRL_DIR_WRITE;
810 writel(reg_val, &info->reg->dma_mst_ctrl);
812 start_command(info->reg);
814 if (!nand_waitfor_cmd_completion(info->reg)) {
816 printf("Read OOB of Page 0x%X timeout\n", page);
818 printf("Write OOB of Page 0x%X timeout\n", page);
822 if (with_ecc && !is_writing) {
823 reg_val = (u32)check_ecc_error(info->reg, 0, 0,
824 (u8 *)(chip->oob_poi + free->offset),
825 chip->ecc.layout->oobavail);
826 if (reg_val & ECC_TAG_ERROR)
827 printf("Read OOB of Page 0x%X tag ECC error\n", page);
833 * OOB data read function
835 * @param mtd mtd info structure
836 * @param chip nand chip info structure
837 * @param page page number to read
839 static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
842 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
843 nand_rw_oob(mtd, chip, page, 0, 0);
848 * OOB data write function
850 * @param mtd mtd info structure
851 * @param chip nand chip info structure
852 * @param page page number to write
853 * @return 0 when successfully completed
854 * -EINVAL when chip->oob_poi is not double-word aligned
855 * -EIO when command timeout
857 static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
860 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
862 return nand_rw_oob(mtd, chip, page, 0, 1);
866 * Set up NAND memory timings according to the provided parameters
868 * @param timing Timing parameters
869 * @param reg NAND controller register address
871 static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],
872 struct nand_ctlr *reg)
874 u32 reg_val, clk_rate, clk_period, time_val;
876 clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH,
877 CLOCK_ID_PERIPH) / 1000000;
878 clk_period = 1000 / clk_rate;
879 reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
880 TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK;
881 reg_val |= ((timing[FDT_NAND_TWB] / clk_period) <<
882 TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK;
883 time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period;
885 reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) &
886 TIMING_TCR_TAR_TRR_CNT_MASK;
887 reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) <<
888 TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK;
889 time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period;
891 reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) &
893 reg_val |= ((timing[FDT_NAND_TWH] / clk_period) <<
894 TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK;
895 reg_val |= ((timing[FDT_NAND_TWP] / clk_period) <<
896 TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK;
897 reg_val |= ((timing[FDT_NAND_TRH] / clk_period) <<
898 TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK;
899 reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
900 TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK;
901 writel(reg_val, ®->timing);
904 time_val = timing[FDT_NAND_TADL] / clk_period;
906 reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK;
907 writel(reg_val, ®->timing2);
911 * Decode NAND parameters from the device tree
913 * @param blob Device tree blob
914 * @param node Node containing "nand-flash" compatble node
915 * @return 0 if ok, -ve on error (FDT_ERR_...)
917 static int fdt_decode_nand(const void *blob, int node, struct fdt_nand *config)
921 config->reg = (struct nand_ctlr *)fdtdec_get_addr(blob, node, "reg");
922 config->enabled = fdtdec_get_is_enabled(blob, node);
923 config->width = fdtdec_get_int(blob, node, "nvidia,nand-width", 8);
924 err = gpio_request_by_name_nodev(blob, node, "nvidia,wp-gpios", 0,
925 &config->wp_gpio, GPIOD_IS_OUT);
928 err = fdtdec_get_int_array(blob, node, "nvidia,timing",
929 config->timing, FDT_NAND_TIMING_COUNT);
933 /* Now look up the controller and decode that */
934 node = fdt_next_node(blob, node, NULL);
942 * Board-specific NAND initialization
944 * @param nand nand chip info structure
945 * @return 0, after initialized, -1 on error
947 int tegra_nand_init(struct nand_chip *nand, int devnum)
949 struct nand_drv *info = &nand_ctrl;
950 struct fdt_nand *config = &info->config;
953 node = fdtdec_next_compatible(gd->fdt_blob, 0,
954 COMPAT_NVIDIA_TEGRA20_NAND);
957 if (fdt_decode_nand(gd->fdt_blob, node, config)) {
958 printf("Could not decode nand-flash in device tree\n");
961 if (!config->enabled)
963 info->reg = config->reg;
964 nand->ecc.mode = NAND_ECC_HW;
965 nand->ecc.layout = &eccoob;
967 nand->options = LP_OPTIONS;
968 nand->cmdfunc = nand_command;
969 nand->read_byte = read_byte;
970 nand->read_buf = read_buf;
971 nand->ecc.read_page = nand_read_page_hwecc;
972 nand->ecc.write_page = nand_write_page_hwecc;
973 nand->ecc.read_page_raw = nand_read_page_raw;
974 nand->ecc.write_page_raw = nand_write_page_raw;
975 nand->ecc.read_oob = nand_read_oob;
976 nand->ecc.write_oob = nand_write_oob;
977 nand->ecc.strength = 1;
978 nand->select_chip = nand_select_chip;
979 nand->dev_ready = nand_dev_ready;
980 nand->priv = &nand_ctrl;
982 /* Adjust controller clock rate */
983 clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000);
985 /* Adjust timing for NAND device */
986 setup_timing(config->timing, info->reg);
988 dm_gpio_set_value(&config->wp_gpio, 1);
990 our_mtd = &nand_info[devnum];
991 our_mtd->priv = nand;
992 ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
996 nand->ecc.size = our_mtd->writesize;
997 nand->ecc.bytes = our_mtd->oobsize;
999 ret = nand_scan_tail(our_mtd);
1003 ret = nand_register(devnum);
1010 void board_nand_init(void)
1012 struct nand_chip *nand = &nand_chip[0];
1014 if (tegra_nand_init(nand, 0))
1015 puts("Tegra NAND init failed\n");