2 * Copyright 2009-2014 Freescale Semiconductor, Inc. and others
4 * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver.
5 * Ported to U-Boot by Stefan Agner
6 * Based on RFC driver posted on Kernel Mailing list by Bill Pringlemeir
7 * Jason ported to M54418TWR and MVFA5.
8 * Authors: Stefan Agner <stefan.agner@toradex.com>
9 * Bill Pringlemeir <bpringlemeir@nbsps.com>
10 * Shaohui Xie <b21989@freescale.com>
11 * Jason Jin <Jason.jin@freescale.com>
13 * Based on original driver mpc5121_nfc.c.
15 * This is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
21 * - Untested on MPC5125 and M54418.
24 * - Only 2K page w. 64+OOB and hardware ECC.
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/nand.h>
32 #include <linux/mtd/partitions.h>
38 /* Register Offsets */
39 #define NFC_FLASH_CMD1 0x3F00
40 #define NFC_FLASH_CMD2 0x3F04
41 #define NFC_COL_ADDR 0x3F08
42 #define NFC_ROW_ADDR 0x3F0c
43 #define NFC_ROW_ADDR_INC 0x3F14
44 #define NFC_FLASH_STATUS1 0x3F18
45 #define NFC_FLASH_STATUS2 0x3F1c
46 #define NFC_CACHE_SWAP 0x3F28
47 #define NFC_SECTOR_SIZE 0x3F2c
48 #define NFC_FLASH_CONFIG 0x3F30
49 #define NFC_IRQ_STATUS 0x3F38
51 /* Addresses for NFC MAIN RAM BUFFER areas */
52 #define NFC_MAIN_AREA(n) ((n) * 0x1000)
54 #define PAGE_2K 0x0800
58 * NFC_CMD2[CODE] values. See section:
59 * - 31.4.7 Flash Command Code Description, Vybrid manual
60 * - 23.8.6 Flash Command Sequencer, MPC5125 manual
62 * Briefly these are bitmasks of controller cycles.
64 #define READ_PAGE_CMD_CODE 0x7EE0
65 #define READ_ONFI_PARAM_CMD_CODE 0x4860
66 #define PROGRAM_PAGE_CMD_CODE 0x7FC0
67 #define ERASE_CMD_CODE 0x4EC0
68 #define READ_ID_CMD_CODE 0x4804
69 #define RESET_CMD_CODE 0x4040
70 #define STATUS_READ_CMD_CODE 0x4068
72 /* NFC ECC mode define */
77 /*** Register Mask and bit definitions */
79 /* NFC_FLASH_CMD1 Field */
80 #define CMD_BYTE2_MASK 0xFF000000
81 #define CMD_BYTE2_SHIFT 24
83 /* NFC_FLASH_CM2 Field */
84 #define CMD_BYTE1_MASK 0xFF000000
85 #define CMD_BYTE1_SHIFT 24
86 #define CMD_CODE_MASK 0x00FFFF00
87 #define CMD_CODE_SHIFT 8
88 #define BUFNO_MASK 0x00000006
90 #define START_BIT (1<<0)
92 /* NFC_COL_ADDR Field */
93 #define COL_ADDR_MASK 0x0000FFFF
94 #define COL_ADDR_SHIFT 0
96 /* NFC_ROW_ADDR Field */
97 #define ROW_ADDR_MASK 0x00FFFFFF
98 #define ROW_ADDR_SHIFT 0
99 #define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000
100 #define ROW_ADDR_CHIP_SEL_RB_SHIFT 28
101 #define ROW_ADDR_CHIP_SEL_MASK 0x0F000000
102 #define ROW_ADDR_CHIP_SEL_SHIFT 24
104 /* NFC_FLASH_STATUS2 Field */
105 #define STATUS_BYTE1_MASK 0x000000FF
107 /* NFC_FLASH_CONFIG Field */
108 #define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000
109 #define CONFIG_ECC_SRAM_ADDR_SHIFT 22
110 #define CONFIG_ECC_SRAM_REQ_BIT (1<<21)
111 #define CONFIG_DMA_REQ_BIT (1<<20)
112 #define CONFIG_ECC_MODE_MASK 0x000E0000
113 #define CONFIG_ECC_MODE_SHIFT 17
114 #define CONFIG_FAST_FLASH_BIT (1<<16)
115 #define CONFIG_16BIT (1<<7)
116 #define CONFIG_BOOT_MODE_BIT (1<<6)
117 #define CONFIG_ADDR_AUTO_INCR_BIT (1<<5)
118 #define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4)
119 #define CONFIG_PAGE_CNT_MASK 0xF
120 #define CONFIG_PAGE_CNT_SHIFT 0
122 /* NFC_IRQ_STATUS Field */
123 #define IDLE_IRQ_BIT (1<<29)
124 #define IDLE_EN_BIT (1<<20)
125 #define CMD_DONE_CLEAR_BIT (1<<18)
126 #define IDLE_CLEAR_BIT (1<<17)
128 #define NFC_TIMEOUT (1000)
130 /* ECC status placed at end of buffers. */
131 #define ECC_SRAM_ADDR ((PAGE_2K+256-8) >> 3)
132 #define ECC_STATUS_MASK 0x80
133 #define ECC_ERR_COUNT 0x3F
136 * ECC status is stored at NFC_CFG[ECCADD] +4 for little-endian
137 * and +7 for big-endian SOC.
146 struct mtd_info *mtd;
147 struct nand_chip chip;
150 /* Status and ID are in alternate locations. */
153 #define ALT_BUF_STAT 2
154 #define ALT_BUF_ONFI 3
158 #define mtd_to_nfc(_mtd) \
159 (struct vf610_nfc *)((struct nand_chip *)_mtd->priv)->priv
161 #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES)
162 #define ECC_HW_MODE ECC_45_BYTE
164 static struct nand_ecclayout vf610_nfc_ecc = {
166 .eccpos = {19, 20, 21, 22, 23,
167 24, 25, 26, 27, 28, 29, 30, 31,
168 32, 33, 34, 35, 36, 37, 38, 39,
169 40, 41, 42, 43, 44, 45, 46, 47,
170 48, 49, 50, 51, 52, 53, 54, 55,
171 56, 57, 58, 59, 60, 61, 62, 63},
176 #elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES)
177 #define ECC_HW_MODE ECC_60_BYTE
179 static struct nand_ecclayout vf610_nfc_ecc = {
181 .eccpos = { 4, 5, 6, 7, 8, 9, 10, 11,
182 12, 13, 14, 15, 16, 17, 18, 19,
183 20, 21, 22, 23, 24, 25, 26, 27,
184 28, 29, 30, 31, 32, 33, 34, 35,
185 36, 37, 38, 39, 40, 41, 42, 43,
186 44, 45, 46, 47, 48, 49, 50, 51,
187 52, 53, 54, 55, 56, 57, 58, 59,
195 static inline u32 vf610_nfc_read(struct mtd_info *mtd, uint reg)
197 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
199 return readl(nfc->regs + reg);
202 static inline void vf610_nfc_write(struct mtd_info *mtd, uint reg, u32 val)
204 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
206 writel(val, nfc->regs + reg);
209 static inline void vf610_nfc_set(struct mtd_info *mtd, uint reg, u32 bits)
211 vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) | bits);
214 static inline void vf610_nfc_clear(struct mtd_info *mtd, uint reg, u32 bits)
216 vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) & ~bits);
219 static inline void vf610_nfc_set_field(struct mtd_info *mtd, u32 reg,
220 u32 mask, u32 shift, u32 val)
222 vf610_nfc_write(mtd, reg,
223 (vf610_nfc_read(mtd, reg) & (~mask)) | val << shift);
226 static inline void vf610_nfc_memcpy(void *dst, const void *src, size_t n)
229 * Use this accessor for the interal SRAM buffers. On ARM we can
230 * treat the SRAM buffer as if its memory, hence use memcpy
235 /* Clear flags for upcoming command */
236 static inline void vf610_nfc_clear_status(void __iomem *regbase)
238 void __iomem *reg = regbase + NFC_IRQ_STATUS;
239 u32 tmp = __raw_readl(reg);
240 tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT;
241 __raw_writel(tmp, reg);
244 /* Wait for complete operation */
245 static inline void vf610_nfc_done(struct mtd_info *mtd)
247 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
251 * Barrier is needed after this write. This write need
252 * to be done before reading the next register the first
254 * vf610_nfc_set implicates such a barrier by using writel
255 * to write to the register.
257 vf610_nfc_set(mtd, NFC_FLASH_CMD2, START_BIT);
259 start = get_timer(0);
261 while (!(vf610_nfc_read(mtd, NFC_IRQ_STATUS) & IDLE_IRQ_BIT)) {
262 if (get_timer(start) > NFC_TIMEOUT) {
263 printf("Timeout while waiting for !BUSY.\n");
267 vf610_nfc_clear_status(nfc->regs);
270 static u8 vf610_nfc_get_id(struct mtd_info *mtd, int col)
275 flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS1);
276 return (flash_id >> (3-col)*8) & 0xff;
278 flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS2);
279 return flash_id >> 24;
283 static u8 vf610_nfc_get_status(struct mtd_info *mtd)
285 return vf610_nfc_read(mtd, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK;
289 static void vf610_nfc_send_command(void __iomem *regbase, u32 cmd_byte1,
292 void __iomem *reg = regbase + NFC_FLASH_CMD2;
294 vf610_nfc_clear_status(regbase);
296 tmp = __raw_readl(reg);
297 tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK);
298 tmp |= cmd_byte1 << CMD_BYTE1_SHIFT;
299 tmp |= cmd_code << CMD_CODE_SHIFT;
300 __raw_writel(tmp, reg);
304 static void vf610_nfc_send_commands(void __iomem *regbase, u32 cmd_byte1,
305 u32 cmd_byte2, u32 cmd_code)
307 void __iomem *reg = regbase + NFC_FLASH_CMD1;
309 vf610_nfc_send_command(regbase, cmd_byte1, cmd_code);
311 tmp = __raw_readl(reg);
312 tmp &= ~CMD_BYTE2_MASK;
313 tmp |= cmd_byte2 << CMD_BYTE2_SHIFT;
314 __raw_writel(tmp, reg);
317 static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
320 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
321 if (nfc->chip.options & NAND_BUSWIDTH_16)
323 vf610_nfc_set_field(mtd, NFC_COL_ADDR, COL_ADDR_MASK,
324 COL_ADDR_SHIFT, column);
327 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
328 ROW_ADDR_SHIFT, page);
331 static inline void vf610_nfc_ecc_mode(struct mtd_info *mtd, int ecc_mode)
333 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
334 CONFIG_ECC_MODE_MASK,
335 CONFIG_ECC_MODE_SHIFT, ecc_mode);
338 static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size)
340 __raw_writel(size, regbase + NFC_SECTOR_SIZE);
343 /* Send command to NAND chip */
344 static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
345 int column, int page)
347 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
348 int page_sz = nfc->chip.options & NAND_BUSWIDTH_16 ? 1 : 0;
350 nfc->column = max(column, 0);
355 /* Use valid column/page from preread... */
356 vf610_nfc_addr_cycle(mtd, column, page);
358 * SEQIN => data => PAGEPROG sequence is done by the controller
359 * hence we do not need to issue the command here...
362 case NAND_CMD_PAGEPROG:
363 page_sz += mtd->writesize + mtd->oobsize;
364 vf610_nfc_transfer_size(nfc->regs, page_sz);
365 vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN,
366 command, PROGRAM_PAGE_CMD_CODE);
367 vf610_nfc_ecc_mode(mtd, ECC_HW_MODE);
371 vf610_nfc_transfer_size(nfc->regs, 0);
372 vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE);
375 case NAND_CMD_READOOB:
376 page_sz += mtd->oobsize;
377 column = mtd->writesize;
378 vf610_nfc_transfer_size(nfc->regs, page_sz);
379 vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
380 NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
381 vf610_nfc_addr_cycle(mtd, column, page);
382 vf610_nfc_ecc_mode(mtd, ECC_BYPASS);
386 page_sz += mtd->writesize + mtd->oobsize;
388 vf610_nfc_transfer_size(nfc->regs, page_sz);
389 vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
390 NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
391 vf610_nfc_addr_cycle(mtd, column, page);
392 vf610_nfc_ecc_mode(mtd, ECC_HW_MODE);
396 nfc->alt_buf = ALT_BUF_ONFI;
397 vf610_nfc_transfer_size(nfc->regs, 768);
398 vf610_nfc_send_command(nfc->regs, NAND_CMD_PARAM,
399 READ_ONFI_PARAM_CMD_CODE);
400 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
401 ROW_ADDR_SHIFT, column);
402 vf610_nfc_ecc_mode(mtd, ECC_BYPASS);
405 case NAND_CMD_ERASE1:
406 vf610_nfc_transfer_size(nfc->regs, 0);
407 vf610_nfc_send_commands(nfc->regs, command,
408 NAND_CMD_ERASE2, ERASE_CMD_CODE);
409 vf610_nfc_addr_cycle(mtd, column, page);
412 case NAND_CMD_READID:
413 nfc->alt_buf = ALT_BUF_ID;
415 vf610_nfc_transfer_size(nfc->regs, 0);
416 vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE);
417 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
418 ROW_ADDR_SHIFT, column);
421 case NAND_CMD_STATUS:
422 nfc->alt_buf = ALT_BUF_STAT;
423 vf610_nfc_transfer_size(nfc->regs, 0);
424 vf610_nfc_send_command(nfc->regs, command,
425 STATUS_READ_CMD_CODE);
434 /* Read data from NFC buffers */
435 static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
437 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
438 uint c = nfc->column;
440 /* Alternate buffers are only supported through read_byte */
444 vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, len);
449 /* Write data to NFC buffers */
450 static void vf610_nfc_write_buf(struct mtd_info *mtd, const u_char *buf,
453 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
454 uint c = nfc->column;
457 l = min((uint)len, mtd->writesize + mtd->oobsize - c);
459 vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l);
462 /* Read byte from NFC buffers */
463 static u8 vf610_nfc_read_byte(struct mtd_info *mtd)
465 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
467 uint c = nfc->column;
469 switch (nfc->alt_buf) {
471 tmp = vf610_nfc_get_id(mtd, c);
474 tmp = vf610_nfc_get_status(mtd);
477 #ifdef __LITTLE_ENDIAN
478 /* Reverse byte since the controller uses big endianness */
479 c = nfc->column ^ 0x3;
480 tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c));
484 tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c));
491 /* Read word from NFC buffers */
492 static u16 vf610_nfc_read_word(struct mtd_info *mtd)
495 vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
499 /* If not provided, upper layers apply a fixed delay. */
500 static int vf610_nfc_dev_ready(struct mtd_info *mtd)
502 /* NFC handles R/B internally; always ready. */
507 * This function supports Vybrid only (MPC5125 would have full RB and four CS)
509 static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip)
512 u32 tmp = vf610_nfc_read(mtd, NFC_ROW_ADDR);
513 tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK);
514 tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT;
517 tmp |= 1 << ROW_ADDR_CHIP_SEL_SHIFT;
519 tmp |= 2 << ROW_ADDR_CHIP_SEL_SHIFT;
521 vf610_nfc_write(mtd, NFC_ROW_ADDR, tmp);
525 /* Count the number of 0's in buff upto max_bits */
526 static inline int count_written_bits(uint8_t *buff, int size, int max_bits)
528 uint32_t *buff32 = (uint32_t *)buff;
529 int k, written_bits = 0;
531 for (k = 0; k < (size / 4); k++) {
532 written_bits += hweight32(~buff32[k]);
533 if (written_bits > max_bits)
540 static inline int vf610_nfc_correct_data(struct mtd_info *mtd, u_char *dat)
542 struct vf610_nfc *nfc = mtd_to_nfc(mtd);
547 ecc_status = __raw_readb(nfc->regs + ECC_SRAM_ADDR * 8 + ECC_OFFSET);
548 ecc_count = ecc_status & ECC_ERR_COUNT;
549 if (!(ecc_status & ECC_STATUS_MASK))
552 /* If 'ecc_count' zero or less then buffer is all 0xff or erased. */
553 flip = count_written_bits(dat, nfc->chip.ecc.size, ecc_count);
556 if (flip > ecc_count && flip > (nfc->chip.ecc.strength / 2))
560 memset(dat, 0xff, nfc->chip.ecc.size);
565 static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
566 uint8_t *buf, int oob_required, int page)
568 int eccsize = chip->ecc.size;
573 vf610_nfc_read_buf(mtd, p, eccsize);
576 vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
578 stat = vf610_nfc_correct_data(mtd, p);
581 mtd->ecc_stats.failed++;
583 mtd->ecc_stats.corrected += stat;
589 * ECC will be calculated automatically
591 static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
592 const uint8_t *buf, int oob_required)
594 vf610_nfc_write_buf(mtd, buf, mtd->writesize);
596 vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
601 struct vf610_nfc_config {
607 static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
609 struct mtd_info *mtd = &nand_info[devnum];
610 struct nand_chip *chip;
611 struct vf610_nfc *nfc;
613 struct vf610_nfc_config cfg = {
615 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
623 nfc = malloc(sizeof(*nfc));
625 printf(KERN_ERR "%s: Memory exhausted!\n", __func__);
636 chip->options |= NAND_BUSWIDTH_16;
638 /* Use 8-bit mode during initialization */
639 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
641 /* Disable subpage writes as we do not provide ecc->hwctl */
642 chip->options |= NAND_NO_SUBPAGE_WRITE;
644 chip->dev_ready = vf610_nfc_dev_ready;
645 chip->cmdfunc = vf610_nfc_command;
646 chip->read_byte = vf610_nfc_read_byte;
647 chip->read_word = vf610_nfc_read_word;
648 chip->read_buf = vf610_nfc_read_buf;
649 chip->write_buf = vf610_nfc_write_buf;
650 chip->select_chip = vf610_nfc_select_chip;
652 /* Bad block options. */
654 chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB |
657 /* Set configuration register. */
658 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
659 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT);
660 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT);
661 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT);
662 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT);
664 /* Enable Idle IRQ */
665 vf610_nfc_set(mtd, NFC_IRQ_STATUS, IDLE_EN_BIT);
668 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
669 CONFIG_PAGE_CNT_SHIFT, 1);
671 /* Set ECC_STATUS offset */
672 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
673 CONFIG_ECC_SRAM_ADDR_MASK,
674 CONFIG_ECC_SRAM_ADDR_SHIFT, ECC_SRAM_ADDR);
676 /* first scan to find the device and get the page size */
677 if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) {
683 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
685 chip->ecc.mode = NAND_ECC_SOFT; /* default */
687 /* Single buffer only, max 256 OOB minus ECC status */
688 if (mtd->writesize + mtd->oobsize > PAGE_2K + 256 - 8) {
689 dev_err(nfc->dev, "Unsupported flash size\n");
694 if (cfg.hardware_ecc) {
695 if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
696 dev_err(nfc->dev, "Unsupported flash with hwecc\n");
701 /* Current HW ECC layouts only use 64 bytes of OOB */
702 if (mtd->oobsize > 64)
705 /* propagate ecc.layout to mtd_info */
706 mtd->ecclayout = chip->ecc.layout;
707 chip->ecc.read_page = vf610_nfc_read_page;
708 chip->ecc.write_page = vf610_nfc_write_page;
709 chip->ecc.mode = NAND_ECC_HW;
711 chip->ecc.size = PAGE_2K;
712 chip->ecc.layout = &vf610_nfc_ecc;
713 #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES)
714 chip->ecc.strength = 24;
715 chip->ecc.bytes = 45;
716 #elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES)
717 chip->ecc.strength = 32;
718 chip->ecc.bytes = 60;
721 /* Enable ECC_STATUS */
722 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);
725 /* second phase scan */
726 err = nand_scan_tail(mtd);
730 err = nand_register(devnum);
740 void board_nand_init(void)
742 int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE);
744 printf("VF610 NAND init failed (err %d)\n", err);