git.sur5r.net Git - u-boot/blob - drivers/mtd/nand/zynq_nand.c

   1 /*
   2  * (C) Copyright 2016 Xilinx, Inc.
   3  *
   4  * Xilinx Zynq NAND Flash Controller Driver
   5  * This driver is based on plat_nand.c and mxc_nand.c drivers
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <malloc.h>
  12 #include <asm/io.h>
  13 #include <linux/errno.h>
  14 #include <nand.h>
  15 #include <linux/mtd/mtd.h>
  16 #include <linux/mtd/nand.h>
  17 #include <linux/mtd/partitions.h>
  18 #include <linux/mtd/nand_ecc.h>
  19 #include <asm/arch/hardware.h>
  20
  21 /* The NAND flash driver defines */
  22 #define ZYNQ_NAND_CMD_PHASE             1
  23 #define ZYNQ_NAND_DATA_PHASE            2
  24 #define ZYNQ_NAND_ECC_SIZE              512
  25 #define ZYNQ_NAND_SET_OPMODE_8BIT       (0 << 0)
  26 #define ZYNQ_NAND_SET_OPMODE_16BIT      (1 << 0)
  27 #define ZYNQ_NAND_ECC_STATUS            (1 << 6)
  28 #define ZYNQ_MEMC_CLRCR_INT_CLR1        (1 << 4)
  29 #define ZYNQ_MEMC_SR_RAW_INT_ST1        (1 << 6)
  30 #define ZYNQ_MEMC_SR_INT_ST1            (1 << 4)
  31 #define ZYNQ_MEMC_NAND_ECC_MODE_MASK    0xC
  32
  33 /* Flash memory controller operating parameters */
  34 #define ZYNQ_NAND_CLR_CONFIG    ((0x1 << 1)  |  /* Disable interrupt */ \
  35                                 (0x1 << 4)   |  /* Clear interrupt */ \
  36                                 (0x1 << 6))     /* Disable ECC interrupt */
  37
  38 #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
  39
  40 /* Assuming 50MHz clock (20ns cycle time) and 3V operation */
  41 #define ZYNQ_NAND_SET_CYCLES    ((0x2 << 20) |  /* t_rr from nand_cycles */ \
  42                                 (0x2 << 17)  |  /* t_ar from nand_cycles */ \
  43                                 (0x1 << 14)  |  /* t_clr from nand_cycles */ \
  44                                 (0x3 << 11)  |  /* t_wp from nand_cycles */ \
  45                                 (0x2 << 8)   |  /* t_rea from nand_cycles */ \
  46                                 (0x5 << 4)   |  /* t_wc from nand_cycles */ \
  47                                 (0x5 << 0))     /* t_rc from nand_cycles */
  48 #endif
  49
  50
  51 #define ZYNQ_NAND_DIRECT_CMD    ((0x4 << 23) |  /* Chip 0 from interface 1 */ \
  52                                 (0x2 << 21))    /* UpdateRegs operation */
  53
  54 #define ZYNQ_NAND_ECC_CONFIG    ((0x1 << 2)  |  /* ECC available on APB */ \
  55                                 (0x1 << 4)   |  /* ECC read at end of page */ \
  56                                 (0x0 << 5))     /* No Jumping */
  57
  58 #define ZYNQ_NAND_ECC_CMD1      ((0x80)      |  /* Write command */ \
  59                                 (0x00 << 8)  |  /* Read command */ \
  60                                 (0x30 << 16) |  /* Read End command */ \
  61                                 (0x1 << 24))    /* Read End command calid */
  62
  63 #define ZYNQ_NAND_ECC_CMD2      ((0x85)      |  /* Write col change cmd */ \
  64                                 (0x05 << 8)  |  /* Read col change cmd */ \
  65                                 (0xE0 << 16) |  /* Read col change end cmd */ \
  66                                 (0x1 << 24))    /* Read col change
  67                                                         end cmd valid */
  68 /* AXI Address definitions */
  69 #define START_CMD_SHIFT                 3
  70 #define END_CMD_SHIFT                   11
  71 #define END_CMD_VALID_SHIFT             20
  72 #define ADDR_CYCLES_SHIFT               21
  73 #define CLEAR_CS_SHIFT                  21
  74 #define ECC_LAST_SHIFT                  10
  75 #define COMMAND_PHASE                   (0 << 19)
  76 #define DATA_PHASE                      (1 << 19)
  77 #define ONDIE_ECC_FEATURE_ADDR          0x90
  78 #define ONDIE_ECC_FEATURE_ENABLE        0x08
  79
  80 #define ZYNQ_NAND_ECC_LAST      (1 << ECC_LAST_SHIFT)   /* Set ECC_Last */
  81 #define ZYNQ_NAND_CLEAR_CS      (1 << CLEAR_CS_SHIFT)   /* Clear chip select */
  82
  83 /* ECC block registers bit position and bit mask */
  84 #define ZYNQ_NAND_ECC_BUSY      (1 << 6)        /* ECC block is busy */
  85 #define ZYNQ_NAND_ECC_MASK      0x00FFFFFF      /* ECC value mask */
  86
  87
  88 /* SMC register set */
  89 struct zynq_nand_smc_regs {
  90         u32 csr;                /* 0x00 */
  91         u32 reserved0[2];
  92         u32 cfr;                /* 0x0C */
  93         u32 dcr;                /* 0x10 */
  94         u32 scr;                /* 0x14 */
  95         u32 sor;                /* 0x18 */
  96         u32 reserved1[249];
  97         u32 esr;                /* 0x400 */
  98         u32 emcr;               /* 0x404 */
  99         u32 emcmd1r;            /* 0x408 */
 100         u32 emcmd2r;            /* 0x40C */
 101         u32 reserved2[2];
 102         u32 eval0r;             /* 0x418 */
 103 };
 104 #define zynq_nand_smc_base      ((struct zynq_nand_smc_regs __iomem *)\
 105                                 ZYNQ_SMC_BASEADDR)
 106
 107 /*
 108  * struct zynq_nand_info - Defines the NAND flash driver instance
 109  * @parts:              Pointer to the mtd_partition structure
 110  * @nand_base:          Virtual address of the NAND flash device
 111  * @end_cmd_pending:    End command is pending
 112  * @end_cmd:            End command
 113  */
 114 struct zynq_nand_info {
 115         void __iomem    *nand_base;
 116         u8              end_cmd_pending;
 117         u8              end_cmd;
 118 };
 119
 120 /*
 121  * struct zynq_nand_command_format - Defines NAND flash command format
 122  * @start_cmd:          First cycle command (Start command)
 123  * @end_cmd:            Second cycle command (Last command)
 124  * @addr_cycles:        Number of address cycles required to send the address
 125  * @end_cmd_valid:      The second cycle command is valid for cmd or data phase
 126  */
 127 struct zynq_nand_command_format {
 128         u8 start_cmd;
 129         u8 end_cmd;
 130         u8 addr_cycles;
 131         u8 end_cmd_valid;
 132 };
 133
 134 /*  The NAND flash operations command format */
 135 static const struct zynq_nand_command_format zynq_nand_commands[] = {
 136         {NAND_CMD_READ0, NAND_CMD_READSTART, 5, ZYNQ_NAND_CMD_PHASE},
 137         {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, ZYNQ_NAND_CMD_PHASE},
 138         {NAND_CMD_READID, NAND_CMD_NONE, 1, 0},
 139         {NAND_CMD_STATUS, NAND_CMD_NONE, 0, 0},
 140         {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, 5, ZYNQ_NAND_DATA_PHASE},
 141         {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, 0},
 142         {NAND_CMD_ERASE1, NAND_CMD_ERASE2, 3, ZYNQ_NAND_CMD_PHASE},
 143         {NAND_CMD_RESET, NAND_CMD_NONE, 0, 0},
 144         {NAND_CMD_PARAM, NAND_CMD_NONE, 1, 0},
 145         {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 0},
 146         {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0},
 147         {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0},
 148         /* Add all the flash commands supported by the flash device */
 149 };
 150
 151 /* Define default oob placement schemes for large and small page devices */
 152 static struct nand_ecclayout nand_oob_16 = {
 153         .eccbytes = 3,
 154         .eccpos = {0, 1, 2},
 155         .oobfree = {
 156                 { .offset = 8, .length = 8 }
 157         }
 158 };
 159
 160 static struct nand_ecclayout nand_oob_64 = {
 161         .eccbytes = 12,
 162         .eccpos = {
 163                    52, 53, 54, 55, 56, 57,
 164                    58, 59, 60, 61, 62, 63},
 165         .oobfree = {
 166                 { .offset = 2, .length = 50 }
 167         }
 168 };
 169
 170 static struct nand_ecclayout ondie_nand_oob_64 = {
 171         .eccbytes = 32,
 172
 173         .eccpos = {
 174                 8, 9, 10, 11, 12, 13, 14, 15,
 175                 24, 25, 26, 27, 28, 29, 30, 31,
 176                 40, 41, 42, 43, 44, 45, 46, 47,
 177                 56, 57, 58, 59, 60, 61, 62, 63
 178         },
 179
 180         .oobfree = {
 181                 { .offset = 4, .length = 4 },
 182                 { .offset = 20, .length = 4 },
 183                 { .offset = 36, .length = 4 },
 184                 { .offset = 52, .length = 4 }
 185         }
 186 };
 187
 188 /* bbt decriptors for chips with on-die ECC and
 189    chips with 64-byte OOB */
 190 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 191 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 192
 193 static struct nand_bbt_descr bbt_main_descr = {
 194         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 195                 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 196         .offs = 4,
 197         .len = 4,
 198         .veroffs = 20,
 199         .maxblocks = 4,
 200         .pattern = bbt_pattern
 201 };
 202
 203 static struct nand_bbt_descr bbt_mirror_descr = {
 204         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 205                 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 206         .offs = 4,
 207         .len = 4,
 208         .veroffs = 20,
 209         .maxblocks = 4,
 210         .pattern = mirror_pattern
 211 };
 212
 213 /*
 214  * zynq_nand_waitfor_ecc_completion - Wait for ECC completion
 215  *
 216  * returns: status for command completion, -1 for Timeout
 217  */
 218 static int zynq_nand_waitfor_ecc_completion(void)
 219 {
 220         unsigned long timeout;
 221         u32 status;
 222
 223         /* Wait max 10us */
 224         timeout = 10;
 225         status = readl(&zynq_nand_smc_base->esr);
 226         while (status & ZYNQ_NAND_ECC_BUSY) {
 227                 status = readl(&zynq_nand_smc_base->esr);
 228                 if (timeout == 0)
 229                         return -1;
 230                 timeout--;
 231                 udelay(1);
 232         }
 233
 234         return status;
 235 }
 236
 237 /*
 238  * zynq_nand_init_nand_flash - Initialize NAND controller
 239  * @option:     Device property flags
 240  *
 241  * This function initializes the NAND flash interface on the NAND controller.
 242  *
 243  * returns:     0 on success or error value on failure
 244  */
 245 static int zynq_nand_init_nand_flash(int option)
 246 {
 247         u32 status;
 248
 249         /* disable interrupts */
 250         writel(ZYNQ_NAND_CLR_CONFIG, &zynq_nand_smc_base->cfr);
 251 #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
 252         /* Initialize the NAND interface by setting cycles and operation mode */
 253         writel(ZYNQ_NAND_SET_CYCLES, &zynq_nand_smc_base->scr);
 254 #endif
 255         if (option & NAND_BUSWIDTH_16)
 256                 writel(ZYNQ_NAND_SET_OPMODE_16BIT, &zynq_nand_smc_base->sor);
 257         else
 258                 writel(ZYNQ_NAND_SET_OPMODE_8BIT, &zynq_nand_smc_base->sor);
 259
 260         writel(ZYNQ_NAND_DIRECT_CMD, &zynq_nand_smc_base->dcr);
 261
 262         /* Wait till the ECC operation is complete */
 263         status = zynq_nand_waitfor_ecc_completion();
 264         if (status < 0) {
 265                 printf("%s: Timeout\n", __func__);
 266                 return status;
 267         }
 268
 269         /* Set the command1 and command2 register */
 270         writel(ZYNQ_NAND_ECC_CMD1, &zynq_nand_smc_base->emcmd1r);
 271         writel(ZYNQ_NAND_ECC_CMD2, &zynq_nand_smc_base->emcmd2r);
 272
 273         return 0;
 274 }
 275
 276 /*
 277  * zynq_nand_calculate_hwecc - Calculate Hardware ECC
 278  * @mtd:        Pointer to the mtd_info structure
 279  * @data:       Pointer to the page data
 280  * @ecc_code:   Pointer to the ECC buffer where ECC data needs to be stored
 281  *
 282  * This function retrieves the Hardware ECC data from the controller and returns
 283  * ECC data back to the MTD subsystem.
 284  *
 285  * returns:     0 on success or error value on failure
 286  */
 287 static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data,
 288                 u8 *ecc_code)
 289 {
 290         u32 ecc_value = 0;
 291         u8 ecc_reg, ecc_byte;
 292         u32 ecc_status;
 293
 294         /* Wait till the ECC operation is complete */
 295         ecc_status = zynq_nand_waitfor_ecc_completion();
 296         if (ecc_status < 0) {
 297                 printf("%s: Timeout\n", __func__);
 298                 return ecc_status;
 299         }
 300
 301         for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) {
 302                 /* Read ECC value for each block */
 303                 ecc_value = readl(&zynq_nand_smc_base->eval0r + ecc_reg);
 304
 305                 /* Get the ecc status from ecc read value */
 306                 ecc_status = (ecc_value >> 24) & 0xFF;
 307
 308                 /* ECC value valid */
 309                 if (ecc_status & ZYNQ_NAND_ECC_STATUS) {
 310                         for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) {
 311                                 /* Copy ECC bytes to MTD buffer */
 312                                 *ecc_code = ecc_value & 0xFF;
 313                                 ecc_value = ecc_value >> 8;
 314                                 ecc_code++;
 315                         }
 316                 } else {
 317                         debug("%s: ecc status failed\n", __func__);
 318                 }
 319         }
 320
 321         return 0;
 322 }
 323
 324 /*
 325  * onehot - onehot function
 326  * @value:      value to check for onehot
 327  *
 328  * This function checks whether a value is onehot or not.
 329  * onehot is if and only if one bit is set.
 330  *
 331  * FIXME: Try to move this in common.h
 332  */
 333 static bool onehot(unsigned short value)
 334 {
 335         bool onehot;
 336
 337         onehot = value && !(value & (value - 1));
 338         return onehot;
 339 }
 340
 341 /*
 342  * zynq_nand_correct_data - ECC correction function
 343  * @mtd:        Pointer to the mtd_info structure
 344  * @buf:        Pointer to the page data
 345  * @read_ecc:   Pointer to the ECC value read from spare data area
 346  * @calc_ecc:   Pointer to the calculated ECC value
 347  *
 348  * This function corrects the ECC single bit errors & detects 2-bit errors.
 349  *
 350  * returns:     0 if no ECC errors found
 351  *              1 if single bit error found and corrected.
 352  *              -1 if multiple ECC errors found.
 353  */
 354 static int zynq_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
 355                         unsigned char *read_ecc, unsigned char *calc_ecc)
 356 {
 357         unsigned char bit_addr;
 358         unsigned int byte_addr;
 359         unsigned short ecc_odd, ecc_even;
 360         unsigned short read_ecc_lower, read_ecc_upper;
 361         unsigned short calc_ecc_lower, calc_ecc_upper;
 362
 363         read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff;
 364         read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff;
 365
 366         calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff;
 367         calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff;
 368
 369         ecc_odd = read_ecc_lower ^ calc_ecc_lower;
 370         ecc_even = read_ecc_upper ^ calc_ecc_upper;
 371
 372         if ((ecc_odd == 0) && (ecc_even == 0))
 373                 return 0;       /* no error */
 374
 375         if (ecc_odd == (~ecc_even & 0xfff)) {
 376                 /* bits [11:3] of error code is byte offset */
 377                 byte_addr = (ecc_odd >> 3) & 0x1ff;
 378                 /* bits [2:0] of error code is bit offset */
 379                 bit_addr = ecc_odd & 0x7;
 380                 /* Toggling error bit */
 381                 buf[byte_addr] ^= (1 << bit_addr);
 382                 return 1;
 383         }
 384
 385         if (onehot(ecc_odd | ecc_even))
 386                 return 1; /* one error in parity */
 387
 388         return -1; /* Uncorrectable error */
 389 }
 390
 391 /*
 392  * zynq_nand_read_oob - [REPLACABLE] the most common OOB data read function
 393  * @mtd:        mtd info structure
 394  * @chip:       nand chip info structure
 395  * @page:       page number to read
 396  * @sndcmd:     flag whether to issue read command or not
 397  */
 398 static int zynq_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 399                         int page)
 400 {
 401         unsigned long data_phase_addr = 0;
 402         int data_width = 4;
 403         u8 *p;
 404
 405         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 406
 407         p = chip->oob_poi;
 408         chip->read_buf(mtd, p, (mtd->oobsize - data_width));
 409         p += mtd->oobsize - data_width;
 410
 411         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 412         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 413         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 414         chip->read_buf(mtd, p, data_width);
 415
 416         return 0;
 417 }
 418
 419 /*
 420  * zynq_nand_write_oob - [REPLACABLE] the most common OOB data write function
 421  * @mtd:        mtd info structure
 422  * @chip:       nand chip info structure
 423  * @page:       page number to write
 424  */
 425 static int zynq_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
 426                              int page)
 427 {
 428         int status = 0, data_width = 4;
 429         const u8 *buf = chip->oob_poi;
 430         unsigned long data_phase_addr = 0;
 431
 432         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 433
 434         chip->write_buf(mtd, buf, (mtd->oobsize - data_width));
 435         buf += mtd->oobsize - data_width;
 436
 437         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 438         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 439         data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
 440         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 441         chip->write_buf(mtd, buf, data_width);
 442
 443         /* Send command to program the OOB data */
 444         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 445         status = chip->waitfunc(mtd, chip);
 446
 447         return status & NAND_STATUS_FAIL ? -EIO : 0;
 448 }
 449
 450 /*
 451  * zynq_nand_read_page_raw - [Intern] read raw page data without ecc
 452  * @mtd:        mtd info structure
 453  * @chip:       nand chip info structure
 454  * @buf:        buffer to store read data
 455  * @oob_required: must write chip->oob_poi to OOB
 456  * @page:       page number to read
 457  */
 458 static int zynq_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 459                                    u8 *buf,  int oob_required, int page)
 460 {
 461         unsigned long data_width = 4;
 462         unsigned long data_phase_addr = 0;
 463         u8 *p;
 464
 465         chip->read_buf(mtd, buf, mtd->writesize);
 466
 467         p = chip->oob_poi;
 468         chip->read_buf(mtd, p, (mtd->oobsize - data_width));
 469         p += (mtd->oobsize - data_width);
 470
 471         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 472         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 473         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 474
 475         chip->read_buf(mtd, p, data_width);
 476         return 0;
 477 }
 478
 479 static int zynq_nand_read_page_raw_nooob(struct mtd_info *mtd,
 480                 struct nand_chip *chip, u8 *buf, int oob_required, int page)
 481 {
 482         chip->read_buf(mtd, buf, mtd->writesize);
 483         return 0;
 484 }
 485
 486 static int zynq_nand_read_subpage_raw(struct mtd_info *mtd,
 487                                     struct nand_chip *chip, u32 data_offs,
 488                                     u32 readlen, u8 *buf, int page)
 489 {
 490         if (data_offs != 0) {
 491                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_offs, -1);
 492                 buf += data_offs;
 493         }
 494         chip->read_buf(mtd, buf, readlen);
 495
 496         return 0;
 497 }
 498
 499 /*
 500  * zynq_nand_write_page_raw - [Intern] raw page write function
 501  * @mtd:        mtd info structure
 502  * @chip:       nand chip info structure
 503  * @buf:        data buffer
 504  * @oob_required: must write chip->oob_poi to OOB
 505  */
 506 static int zynq_nand_write_page_raw(struct mtd_info *mtd,
 507         struct nand_chip *chip, const u8 *buf, int oob_required, int page)
 508 {
 509         unsigned long data_width = 4;
 510         unsigned long data_phase_addr = 0;
 511         u8 *p;
 512
 513         chip->write_buf(mtd, buf, mtd->writesize);
 514
 515         p = chip->oob_poi;
 516         chip->write_buf(mtd, p, (mtd->oobsize - data_width));
 517         p += (mtd->oobsize - data_width);
 518
 519         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 520         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 521         data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
 522         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 523
 524         chip->write_buf(mtd, p, data_width);
 525
 526         return 0;
 527 }
 528
 529 /*
 530  * nand_write_page_hwecc - Hardware ECC based page write function
 531  * @mtd:        Pointer to the mtd info structure
 532  * @chip:       Pointer to the NAND chip info structure
 533  * @buf:        Pointer to the data buffer
 534  * @oob_required: must write chip->oob_poi to OOB
 535  *
 536  * This functions writes data and hardware generated ECC values in to the page.
 537  */
 538 static int zynq_nand_write_page_hwecc(struct mtd_info *mtd,
 539         struct nand_chip *chip, const u8 *buf, int oob_required, int page)
 540 {
 541         int i, eccsteps, eccsize = chip->ecc.size;
 542         u8 *ecc_calc = chip->buffers->ecccalc;
 543         const u8 *p = buf;
 544         u32 *eccpos = chip->ecc.layout->eccpos;
 545         unsigned long data_phase_addr = 0;
 546         unsigned long data_width = 4;
 547         u8 *oob_ptr;
 548
 549         for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
 550                 chip->write_buf(mtd, p, eccsize);
 551                 p += eccsize;
 552         }
 553         chip->write_buf(mtd, p, (eccsize - data_width));
 554         p += eccsize - data_width;
 555
 556         /* Set ECC Last bit to 1 */
 557         data_phase_addr = (unsigned long) chip->IO_ADDR_W;
 558         data_phase_addr |= ZYNQ_NAND_ECC_LAST;
 559         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 560         chip->write_buf(mtd, p, data_width);
 561
 562         /* Wait for ECC to be calculated and read the error values */
 563         p = buf;
 564         chip->ecc.calculate(mtd, p, &ecc_calc[0]);
 565
 566         for (i = 0; i < chip->ecc.total; i++)
 567                 chip->oob_poi[eccpos[i]] = ~(ecc_calc[i]);
 568
 569         /* Clear ECC last bit */
 570         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 571         data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
 572         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 573
 574         /* Write the spare area with ECC bytes */
 575         oob_ptr = chip->oob_poi;
 576         chip->write_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
 577
 578         data_phase_addr = (unsigned long)chip->IO_ADDR_W;
 579         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 580         data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
 581         chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
 582         oob_ptr += (mtd->oobsize - data_width);
 583         chip->write_buf(mtd, oob_ptr, data_width);
 584
 585         return 0;
 586 }
 587
 588 /*
 589  * zynq_nand_write_page_swecc - [REPLACABLE] software ecc based page
 590  * write function
 591  * @mtd:        mtd info structure
 592  * @chip:       nand chip info structure
 593  * @buf:        data buffer
 594  * @oob_required: must write chip->oob_poi to OOB
 595  */
 596 static int zynq_nand_write_page_swecc(struct mtd_info *mtd,
 597         struct nand_chip *chip, const u8 *buf, int oob_required, int page)
 598 {
 599         int i, eccsize = chip->ecc.size;
 600         int eccbytes = chip->ecc.bytes;
 601         int eccsteps = chip->ecc.steps;
 602         u8 *ecc_calc = chip->buffers->ecccalc;
 603         const u8 *p = buf;
 604         u32 *eccpos = chip->ecc.layout->eccpos;
 605
 606         /* Software ecc calculation */
 607         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 608                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 609
 610         for (i = 0; i < chip->ecc.total; i++)
 611                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
 612
 613         return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
 614 }
 615
 616 /*
 617  * nand_read_page_hwecc - Hardware ECC based page read function
 618  * @mtd:        Pointer to the mtd info structure
 619  * @chip:       Pointer to the NAND chip info structure
 620  * @buf:        Pointer to the buffer to store read data
 621  * @oob_required: must write chip->oob_poi to OOB
 622  * @page:       page number to read
 623  *
 624  * This functions reads data and checks the data integrity by comparing hardware
 625  * generated ECC values and read ECC values from spare area.
 626  *
 627  * returns:     0 always and updates ECC operation status in to MTD structure
 628  */
 629 static int zynq_nand_read_page_hwecc(struct mtd_info *mtd,
 630         struct nand_chip *chip, u8 *buf, int oob_required, int page)
 631 {
 632         int i, stat, eccsteps, eccsize = chip->ecc.size;
 633         int eccbytes = chip->ecc.bytes;
 634         u8 *p = buf;
 635         u8 *ecc_calc = chip->buffers->ecccalc;
 636         u8 *ecc_code = chip->buffers->ecccode;
 637         u32 *eccpos = chip->ecc.layout->eccpos;
 638         unsigned long data_phase_addr = 0;
 639         unsigned long data_width = 4;
 640         u8 *oob_ptr;
 641
 642         for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
 643                 chip->read_buf(mtd, p, eccsize);
 644                 p += eccsize;
 645         }
 646         chip->read_buf(mtd, p, (eccsize - data_width));
 647         p += eccsize - data_width;
 648
 649         /* Set ECC Last bit to 1 */
 650         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 651         data_phase_addr |= ZYNQ_NAND_ECC_LAST;
 652         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 653         chip->read_buf(mtd, p, data_width);
 654
 655         /* Read the calculated ECC value */
 656         p = buf;
 657         chip->ecc.calculate(mtd, p, &ecc_calc[0]);
 658
 659         /* Clear ECC last bit */
 660         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 661         data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
 662         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 663
 664         /* Read the stored ECC value */
 665         oob_ptr = chip->oob_poi;
 666         chip->read_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
 667
 668         /* de-assert chip select */
 669         data_phase_addr = (unsigned long)chip->IO_ADDR_R;
 670         data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
 671         chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
 672
 673         oob_ptr += (mtd->oobsize - data_width);
 674         chip->read_buf(mtd, oob_ptr, data_width);
 675
 676         for (i = 0; i < chip->ecc.total; i++)
 677                 ecc_code[i] = ~(chip->oob_poi[eccpos[i]]);
 678
 679         eccsteps = chip->ecc.steps;
 680         p = buf;
 681
 682         /* Check ECC error for all blocks and correct if it is correctable */
 683         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 684                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 685                 if (stat < 0)
 686                         mtd->ecc_stats.failed++;
 687                 else
 688                         mtd->ecc_stats.corrected += stat;
 689         }
 690         return 0;
 691 }
 692
 693 /*
 694  * zynq_nand_read_page_swecc - [REPLACABLE] software ecc based page
 695  * read function
 696  * @mtd:        mtd info structure
 697  * @chip:       nand chip info structure
 698  * @buf:        buffer to store read data
 699  * @page:       page number to read
 700  */
 701 static int zynq_nand_read_page_swecc(struct mtd_info *mtd,
 702         struct nand_chip *chip, u8 *buf, int oob_required,  int page)
 703 {
 704         int i, eccsize = chip->ecc.size;
 705         int eccbytes = chip->ecc.bytes;
 706         int eccsteps = chip->ecc.steps;
 707         u8 *p = buf;
 708         u8 *ecc_calc = chip->buffers->ecccalc;
 709         u8 *ecc_code = chip->buffers->ecccode;
 710         u32 *eccpos = chip->ecc.layout->eccpos;
 711
 712         chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
 713
 714         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 715                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 716
 717         for (i = 0; i < chip->ecc.total; i++)
 718                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 719
 720         eccsteps = chip->ecc.steps;
 721         p = buf;
 722
 723         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 724                 int stat;
 725
 726                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 727                 if (stat < 0)
 728                         mtd->ecc_stats.failed++;
 729                 else
 730                         mtd->ecc_stats.corrected += stat;
 731         }
 732         return 0;
 733 }
 734
 735 /*
 736  * zynq_nand_select_chip - Select the flash device
 737  * @mtd:        Pointer to the mtd_info structure
 738  * @chip:       Chip number to be selected
 739  *
 740  * This function is empty as the NAND controller handles chip select line
 741  * internally based on the chip address passed in command and data phase.
 742  */
 743 static void zynq_nand_select_chip(struct mtd_info *mtd, int chip)
 744 {
 745         /* Not support multiple chips yet */
 746 }
 747
 748 /*
 749  * zynq_nand_cmd_function - Send command to NAND device
 750  * @mtd:        Pointer to the mtd_info structure
 751  * @command:    The command to be sent to the flash device
 752  * @column:     The column address for this command, -1 if none
 753  * @page_addr:  The page address for this command, -1 if none
 754  */
 755 static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
 756                                  int column, int page_addr)
 757 {
 758         struct nand_chip *chip = mtd->priv;
 759         const struct zynq_nand_command_format *curr_cmd = NULL;
 760         struct zynq_nand_info *xnand = (struct zynq_nand_info *)chip->priv;
 761         void *cmd_addr;
 762         unsigned long cmd_data = 0;
 763         unsigned long cmd_phase_addr = 0;
 764         unsigned long data_phase_addr = 0;
 765         u8 end_cmd = 0;
 766         u8 end_cmd_valid = 0;
 767         u32 index;
 768
 769         if (xnand->end_cmd_pending) {
 770                 /* Check for end command if this command request is same as the
 771                  * pending command then return
 772                  */
 773                 if (xnand->end_cmd == command) {
 774                         xnand->end_cmd = 0;
 775                         xnand->end_cmd_pending = 0;
 776                         return;
 777                 }
 778         }
 779
 780         /* Emulate NAND_CMD_READOOB for large page device */
 781         if ((mtd->writesize > ZYNQ_NAND_ECC_SIZE) &&
 782             (command == NAND_CMD_READOOB)) {
 783                 column += mtd->writesize;
 784                 command = NAND_CMD_READ0;
 785         }
 786
 787         /* Get the command format */
 788         for (index = 0; index < ARRAY_SIZE(zynq_nand_commands); index++)
 789                 if (command == zynq_nand_commands[index].start_cmd)
 790                         break;
 791
 792         if (index == ARRAY_SIZE(zynq_nand_commands)) {
 793                 printf("%s: Unsupported start cmd %02x\n", __func__, command);
 794                 return;
 795         }
 796         curr_cmd = &zynq_nand_commands[index];
 797
 798         /* Clear interrupt */
 799         writel(ZYNQ_MEMC_CLRCR_INT_CLR1, &zynq_nand_smc_base->cfr);
 800
 801         /* Get the command phase address */
 802         if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE)
 803                 end_cmd_valid = 1;
 804
 805         if (curr_cmd->end_cmd == NAND_CMD_NONE)
 806                 end_cmd = 0x0;
 807         else
 808                 end_cmd = curr_cmd->end_cmd;
 809
 810         cmd_phase_addr = (unsigned long)xnand->nand_base        |
 811                         (curr_cmd->addr_cycles << ADDR_CYCLES_SHIFT)    |
 812                         (end_cmd_valid << END_CMD_VALID_SHIFT)          |
 813                         (COMMAND_PHASE)                                 |
 814                         (end_cmd << END_CMD_SHIFT)                      |
 815                         (curr_cmd->start_cmd << START_CMD_SHIFT);
 816
 817         cmd_addr = (void __iomem *)cmd_phase_addr;
 818
 819         /* Get the data phase address */
 820         end_cmd_valid = 0;
 821
 822         data_phase_addr = (unsigned long)xnand->nand_base       |
 823                         (0x0 << CLEAR_CS_SHIFT)                         |
 824                         (end_cmd_valid << END_CMD_VALID_SHIFT)          |
 825                         (DATA_PHASE)                                    |
 826                         (end_cmd << END_CMD_SHIFT)                      |
 827                         (0x0 << ECC_LAST_SHIFT);
 828
 829         chip->IO_ADDR_R = (void  __iomem *)data_phase_addr;
 830         chip->IO_ADDR_W = chip->IO_ADDR_R;
 831
 832         /* Command phase AXI Read & Write */
 833         if (column != -1 && page_addr != -1) {
 834                 /* Adjust columns for 16 bit bus width */
 835                 if (chip->options & NAND_BUSWIDTH_16)
 836                         column >>= 1;
 837                 cmd_data = column;
 838                 if (mtd->writesize > ZYNQ_NAND_ECC_SIZE) {
 839                         cmd_data |= page_addr << 16;
 840                         /* Another address cycle for devices > 128MiB */
 841                         if (chip->chipsize > (128 << 20)) {
 842                                 writel(cmd_data, cmd_addr);
 843                                 cmd_data = (page_addr >> 16);
 844                         }
 845                 } else {
 846                         cmd_data |= page_addr << 8;
 847                 }
 848         } else if (page_addr != -1)  { /* Erase */
 849                 cmd_data = page_addr;
 850         } else if (column != -1) { /* Change read/write column, read id etc */
 851                 /* Adjust columns for 16 bit bus width */
 852                 if ((chip->options & NAND_BUSWIDTH_16) &&
 853                     ((command == NAND_CMD_READ0) ||
 854                      (command == NAND_CMD_SEQIN) ||
 855                      (command == NAND_CMD_RNDOUT) ||
 856                      (command == NAND_CMD_RNDIN)))
 857                         column >>= 1;
 858                 cmd_data = column;
 859         }
 860
 861         writel(cmd_data, cmd_addr);
 862
 863         if (curr_cmd->end_cmd_valid) {
 864                 xnand->end_cmd = curr_cmd->end_cmd;
 865                 xnand->end_cmd_pending = 1;
 866         }
 867
 868         ndelay(100);
 869
 870         if ((command == NAND_CMD_READ0) ||
 871             (command == NAND_CMD_RESET) ||
 872             (command == NAND_CMD_PARAM) ||
 873             (command == NAND_CMD_GET_FEATURES))
 874                 /* wait until command is processed */
 875                 nand_wait_ready(mtd);
 876 }
 877
 878 /*
 879  * zynq_nand_read_buf - read chip data into buffer
 880  * @mtd:        MTD device structure
 881  * @buf:        buffer to store date
 882  * @len:        number of bytes to read
 883  */
 884 static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 885 {
 886         struct nand_chip *chip = mtd->priv;
 887
 888         /* Make sure that buf is 32 bit aligned */
 889         if (((unsigned long)buf & 0x3) != 0) {
 890                 if (((unsigned long)buf & 0x1) != 0) {
 891                         if (len) {
 892                                 *buf = readb(chip->IO_ADDR_R);
 893                                 buf += 1;
 894                                 len--;
 895                         }
 896                 }
 897
 898                 if (((unsigned long)buf & 0x3) != 0) {
 899                         if (len >= 2) {
 900                                 *(u16 *)buf = readw(chip->IO_ADDR_R);
 901                                 buf += 2;
 902                                 len -= 2;
 903                         }
 904                 }
 905         }
 906
 907         /* copy aligned data */
 908         while (len >= 4) {
 909                 *(u32 *)buf = readl(chip->IO_ADDR_R);
 910                 buf += 4;
 911                 len -= 4;
 912         }
 913
 914         /* mop up any remaining bytes */
 915         if (len) {
 916                 if (len >= 2) {
 917                         *(u16 *)buf = readw(chip->IO_ADDR_R);
 918                         buf += 2;
 919                         len -= 2;
 920                 }
 921                 if (len)
 922                         *buf = readb(chip->IO_ADDR_R);
 923         }
 924 }
 925
 926 /*
 927  * zynq_nand_write_buf - write buffer to chip
 928  * @mtd:        MTD device structure
 929  * @buf:        data buffer
 930  * @len:        number of bytes to write
 931  */
 932 static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 933 {
 934         struct nand_chip *chip = mtd->priv;
 935         const u32 *nand = chip->IO_ADDR_W;
 936
 937         /* Make sure that buf is 32 bit aligned */
 938         if (((unsigned long)buf & 0x3) != 0) {
 939                 if (((unsigned long)buf & 0x1) != 0) {
 940                         if (len) {
 941                                 writeb(*buf, nand);
 942                                 buf += 1;
 943                                 len--;
 944                         }
 945                 }
 946
 947                 if (((unsigned long)buf & 0x3) != 0) {
 948                         if (len >= 2) {
 949                                 writew(*(u16 *)buf, nand);
 950                                 buf += 2;
 951                                 len -= 2;
 952                         }
 953                 }
 954         }
 955
 956         /* copy aligned data */
 957         while (len >= 4) {
 958                 writel(*(u32 *)buf, nand);
 959                 buf += 4;
 960                 len -= 4;
 961         }
 962
 963         /* mop up any remaining bytes */
 964         if (len) {
 965                 if (len >= 2) {
 966                         writew(*(u16 *)buf, nand);
 967                         buf += 2;
 968                         len -= 2;
 969                 }
 970
 971                 if (len)
 972                         writeb(*buf, nand);
 973         }
 974 }
 975
 976 /*
 977  * zynq_nand_device_ready - Check device ready/busy line
 978  * @mtd:        Pointer to the mtd_info structure
 979  *
 980  * returns:     0 on busy or 1 on ready state
 981  */
 982 static int zynq_nand_device_ready(struct mtd_info *mtd)
 983 {
 984         u32 csr_val;
 985
 986         csr_val = readl(&zynq_nand_smc_base->csr);
 987         /* Check the raw_int_status1 bit */
 988         if (csr_val & ZYNQ_MEMC_SR_RAW_INT_ST1) {
 989                 /* Clear the interrupt condition */
 990                 writel(ZYNQ_MEMC_SR_INT_ST1, &zynq_nand_smc_base->cfr);
 991                 return 1;
 992         }
 993
 994         return 0;
 995 }
 996
 997 int zynq_nand_init(struct nand_chip *nand_chip, int devnum)
 998 {
 999         struct zynq_nand_info *xnand;
1000         struct mtd_info *mtd;
1001         unsigned long ecc_page_size;
1002         u8 maf_id, dev_id, i;
1003         u8 get_feature[4];
1004         u8 set_feature[4] = {ONDIE_ECC_FEATURE_ENABLE, 0x00, 0x00, 0x00};
1005         unsigned long ecc_cfg;
1006         int ondie_ecc_enabled = 0;
1007         int err = -1;
1008
1009         xnand = calloc(1, sizeof(struct zynq_nand_info));
1010         if (!xnand) {
1011                 printf("%s: failed to allocate\n", __func__);
1012                 goto fail;
1013         }
1014
1015         xnand->nand_base = (void __iomem *)ZYNQ_NAND_BASEADDR;
1016         mtd = get_nand_dev_by_index(0);
1017
1018         nand_chip->priv = xnand;
1019         mtd->priv = nand_chip;
1020
1021         /* Set address of NAND IO lines */
1022         nand_chip->IO_ADDR_R = xnand->nand_base;
1023         nand_chip->IO_ADDR_W = xnand->nand_base;
1024
1025         /* Set the driver entry points for MTD */
1026         nand_chip->cmdfunc = zynq_nand_cmd_function;
1027         nand_chip->dev_ready = zynq_nand_device_ready;
1028         nand_chip->select_chip = zynq_nand_select_chip;
1029
1030         /* If we don't set this delay driver sets 20us by default */
1031         nand_chip->chip_delay = 30;
1032
1033         /* Buffer read/write routines */
1034         nand_chip->read_buf = zynq_nand_read_buf;
1035         nand_chip->write_buf = zynq_nand_write_buf;
1036
1037         nand_chip->bbt_options = NAND_BBT_USE_FLASH;
1038
1039         /* Initialize the NAND flash interface on NAND controller */
1040         if (zynq_nand_init_nand_flash(nand_chip->options) < 0) {
1041                 printf("%s: nand flash init failed\n", __func__);
1042                 goto fail;
1043         }
1044
1045         /* first scan to find the device and get the page size */
1046         if (nand_scan_ident(mtd, 1, NULL)) {
1047                 printf("%s: nand_scan_ident failed\n", __func__);
1048                 goto fail;
1049         }
1050         /* Send the command for reading device ID */
1051         nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1052         nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1053
1054         /* Read manufacturer and device IDs */
1055         maf_id = nand_chip->read_byte(mtd);
1056         dev_id = nand_chip->read_byte(mtd);
1057
1058         if ((maf_id == 0x2c) && ((dev_id == 0xf1) ||
1059                                  (dev_id == 0xa1) || (dev_id == 0xb1) ||
1060                                  (dev_id == 0xaa) || (dev_id == 0xba) ||
1061                                  (dev_id == 0xda) || (dev_id == 0xca) ||
1062                                  (dev_id == 0xac) || (dev_id == 0xbc) ||
1063                                  (dev_id == 0xdc) || (dev_id == 0xcc) ||
1064                                  (dev_id == 0xa3) || (dev_id == 0xb3) ||
1065                                  (dev_id == 0xd3) || (dev_id == 0xc3))) {
1066                 nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
1067                                                 ONDIE_ECC_FEATURE_ADDR, -1);
1068                 for (i = 0; i < 4; i++)
1069                         writeb(set_feature[i], nand_chip->IO_ADDR_W);
1070
1071                 /* Wait for 1us after writing data with SET_FEATURES command */
1072                 ndelay(1000);
1073
1074                 nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
1075                                                 ONDIE_ECC_FEATURE_ADDR, -1);
1076                 nand_chip->read_buf(mtd, get_feature, 4);
1077
1078                 if (get_feature[0] & ONDIE_ECC_FEATURE_ENABLE) {
1079                         debug("%s: OnDie ECC flash\n", __func__);
1080                         ondie_ecc_enabled = 1;
1081                 } else {
1082                         printf("%s: Unable to detect OnDie ECC\n", __func__);
1083                 }
1084         }
1085
1086         if (ondie_ecc_enabled) {
1087                 /* Bypass the controller ECC block */
1088                 ecc_cfg = readl(&zynq_nand_smc_base->emcr);
1089                 ecc_cfg &= ~ZYNQ_MEMC_NAND_ECC_MODE_MASK;
1090                 writel(ecc_cfg, &zynq_nand_smc_base->emcr);
1091
1092                 /* The software ECC routines won't work
1093                  * with the SMC controller
1094                  */
1095                 nand_chip->ecc.mode = NAND_ECC_HW;
1096                 nand_chip->ecc.strength = 1;
1097                 nand_chip->ecc.read_page = zynq_nand_read_page_raw_nooob;
1098                 nand_chip->ecc.read_subpage = zynq_nand_read_subpage_raw;
1099                 nand_chip->ecc.write_page = zynq_nand_write_page_raw;
1100                 nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
1101                 nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
1102                 nand_chip->ecc.read_oob = zynq_nand_read_oob;
1103                 nand_chip->ecc.write_oob = zynq_nand_write_oob;
1104                 nand_chip->ecc.size = mtd->writesize;
1105                 nand_chip->ecc.bytes = 0;
1106
1107                 /* NAND with on-die ECC supports subpage reads */
1108                 nand_chip->options |= NAND_SUBPAGE_READ;
1109
1110                 /* On-Die ECC spare bytes offset 8 is used for ECC codes */
1111                 if (ondie_ecc_enabled) {
1112                         nand_chip->ecc.layout = &ondie_nand_oob_64;
1113                         /* Use the BBT pattern descriptors */
1114                         nand_chip->bbt_td = &bbt_main_descr;
1115                         nand_chip->bbt_md = &bbt_mirror_descr;
1116                 }
1117         } else {
1118                 /* Hardware ECC generates 3 bytes ECC code for each 512 bytes */
1119                 nand_chip->ecc.mode = NAND_ECC_HW;
1120                 nand_chip->ecc.strength = 1;
1121                 nand_chip->ecc.size = ZYNQ_NAND_ECC_SIZE;
1122                 nand_chip->ecc.bytes = 3;
1123                 nand_chip->ecc.calculate = zynq_nand_calculate_hwecc;
1124                 nand_chip->ecc.correct = zynq_nand_correct_data;
1125                 nand_chip->ecc.hwctl = NULL;
1126                 nand_chip->ecc.read_page = zynq_nand_read_page_hwecc;
1127                 nand_chip->ecc.write_page = zynq_nand_write_page_hwecc;
1128                 nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
1129                 nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
1130                 nand_chip->ecc.read_oob = zynq_nand_read_oob;
1131                 nand_chip->ecc.write_oob = zynq_nand_write_oob;
1132
1133                 switch (mtd->writesize) {
1134                 case 512:
1135                         ecc_page_size = 0x1;
1136                         /* Set the ECC memory config register */
1137                         writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1138                                &zynq_nand_smc_base->emcr);
1139                         break;
1140                 case 1024:
1141                         ecc_page_size = 0x2;
1142                         /* Set the ECC memory config register */
1143                         writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1144                                &zynq_nand_smc_base->emcr);
1145                         break;
1146                 case 2048:
1147                         ecc_page_size = 0x3;
1148                         /* Set the ECC memory config register */
1149                         writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
1150                                &zynq_nand_smc_base->emcr);
1151                         break;
1152                 default:
1153                         nand_chip->ecc.mode = NAND_ECC_SOFT;
1154                         nand_chip->ecc.calculate = nand_calculate_ecc;
1155                         nand_chip->ecc.correct = nand_correct_data;
1156                         nand_chip->ecc.read_page = zynq_nand_read_page_swecc;
1157                         nand_chip->ecc.write_page = zynq_nand_write_page_swecc;
1158                         nand_chip->ecc.size = 256;
1159                         break;
1160                 }
1161
1162                 if (mtd->oobsize == 16)
1163                         nand_chip->ecc.layout = &nand_oob_16;
1164                 else if (mtd->oobsize == 64)
1165                         nand_chip->ecc.layout = &nand_oob_64;
1166                 else
1167                         printf("%s: No oob layout found\n", __func__);
1168         }
1169
1170         /* Second phase scan */
1171         if (nand_scan_tail(mtd)) {
1172                 printf("%s: nand_scan_tail failed\n", __func__);
1173                 goto fail;
1174         }
1175         if (nand_register(devnum, mtd))
1176                 goto fail;
1177         return 0;
1178 fail:
1179         free(xnand);
1180         return err;
1181 }
1182
1183 #ifdef CONFIG_SYS_NAND_SELF_INIT
1184 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1185
1186 void __weak board_nand_init(void)
1187 {
1188         struct nand_chip *nand = &nand_chip[0];
1189
1190         if (zynq_nand_init(nand, 0))
1191                 puts("ZYNQ NAND init failed\n");
1192 }
1193 #endif