3 * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
5 * SPDX-License-Identifier: GPL-2.0+
9 * Note: RAMTRON SPI FRAMs are ferroelectric, nonvolatile RAMs
10 * with an interface identical to SPI flash devices.
11 * However since they behave like RAM there are no delays or
12 * busy polls required. They can sustain read or write at the
13 * allowed SPI bus speed, which can be 40 MHz for some devices.
15 * Unfortunately some RAMTRON devices do not have a means of
16 * identifying them. They will leave the SO line undriven when
17 * the READ-ID command is issued. It is therefore mandatory
18 * that the MISO line has a proper pull-up, so that READ-ID
19 * will return a row of 0xff. This 0xff pseudo-id will cause
20 * probes by all vendor specific functions that are designed
21 * to handle it. If the MISO line is not pulled up, READ-ID
22 * could return any random noise, even mimicking another
25 * We use CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
26 * to define which device will be assumed after a simple status
27 * register verify. This method is prone to false positive
28 * detection and should therefore be the last to be tried.
29 * Enter it in the last position in the table in spi_flash.c!
31 * The define CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC both activates
32 * compilation of the special handler and defines the device
38 #include <spi_flash.h>
39 #include "spi_flash_internal.h"
42 * Properties of supported FRAMs
43 * Note: speed is currently not used because we have no method to deliver that
44 * value to the upper layers
46 struct ramtron_spi_fram_params {
47 u32 size; /* size in bytes */
48 u8 addr_len; /* number of address bytes */
49 u8 merge_cmd; /* some address bits are in the command byte */
50 u8 id1; /* device ID 1 (family, density) */
51 u8 id2; /* device ID 2 (sub, rev, rsvd) */
52 u32 speed; /* max. SPI clock in Hz */
53 const char *name; /* name for display and/or matching */
56 struct ramtron_spi_fram {
57 struct spi_flash flash;
58 const struct ramtron_spi_fram_params *params;
61 static inline struct ramtron_spi_fram *to_ramtron_spi_fram(struct spi_flash
64 return container_of(flash, struct ramtron_spi_fram, flash);
68 * table describing supported FRAM chips:
69 * chips without RDID command must have the values 0xff for id1 and id2
71 static const struct ramtron_spi_fram_params ramtron_spi_fram_table[] = {
126 #ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
139 static int ramtron_common(struct spi_flash *flash,
140 u32 offset, size_t len, void *buf, u8 command)
142 struct ramtron_spi_fram *sn = to_ramtron_spi_fram(flash);
147 if (sn->params->addr_len == 3 && sn->params->merge_cmd == 0) {
149 cmd[1] = offset >> 16;
150 cmd[2] = offset >> 8;
153 } else if (sn->params->addr_len == 2 && sn->params->merge_cmd == 0) {
155 cmd[1] = offset >> 8;
159 printf("SF: unsupported addr_len or merge_cmd\n");
164 ret = spi_claim_bus(flash->spi);
166 debug("SF: Unable to claim SPI bus\n");
170 if (command == CMD_PAGE_PROGRAM) {
172 ret = spi_flash_cmd_write_enable(flash);
174 debug("SF: Enabling Write failed\n");
179 /* do the transaction */
180 if (command == CMD_PAGE_PROGRAM)
181 ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, buf, len);
183 ret = spi_flash_cmd_read(flash->spi, cmd, cmd_len, buf, len);
185 debug("SF: Transaction failed\n");
188 /* release the bus */
189 spi_release_bus(flash->spi);
193 static int ramtron_read(struct spi_flash *flash,
194 u32 offset, size_t len, void *buf)
196 return ramtron_common(flash, offset, len, buf,
197 CMD_READ_ARRAY_SLOW);
200 static int ramtron_write(struct spi_flash *flash,
201 u32 offset, size_t len, const void *buf)
203 return ramtron_common(flash, offset, len, (void *)buf,
207 static int ramtron_erase(struct spi_flash *flash, u32 offset, size_t len)
209 debug("SF: Erase of RAMTRON FRAMs is pointless\n");
214 * nore: we are called here with idcode pointing to the first non-0x7f byte
217 struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode)
219 const struct ramtron_spi_fram_params *params;
220 struct ramtron_spi_fram *sn;
222 #ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
227 /* NOTE: the bus has been claimed before this function is called! */
230 /* JEDEC conformant RAMTRON id */
231 for (i = 0; i < ARRAY_SIZE(ramtron_spi_fram_table); i++) {
232 params = &ramtron_spi_fram_table[i];
233 if (idcode[1] == params->id1 && idcode[2] == params->id2)
237 #ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
240 * probably open MISO line, pulled up.
241 * We COULD have a non JEDEC conformant FRAM here,
242 * read the status register to verify
244 ret = spi_flash_cmd(spi, CMD_READ_STATUS, &sr, 1);
248 /* Bits 5,4,0 are fixed 0 for all devices */
249 if ((sr & 0x31) != 0x00)
251 /* now find the device */
252 for (i = 0; i < ARRAY_SIZE(ramtron_spi_fram_table); i++) {
253 params = &ramtron_spi_fram_table[i];
254 if (!strcmp(params->name, CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC))
257 debug("SF: Unsupported non-JEDEC RAMTRON device "
258 CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC "\n");
265 /* arriving here means no method has found a device we can handle */
266 debug("SF/ramtron: unsupported device id0=%02x id1=%02x id2=%02x\n",
267 idcode[0], idcode[1], idcode[2]);
271 sn = spi_flash_alloc(struct ramtron_spi_fram, spi, params->name);
273 debug("SF: Failed to allocate memory\n");
279 sn->flash.write = ramtron_write;
280 sn->flash.read = ramtron_read;
281 sn->flash.erase = ramtron_erase;
282 sn->flash.size = params->size;