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[u-boot] / drivers / mtd / spi / sf_internal.h
1 /*
2  * SPI flash internal definitions
3  *
4  * Copyright (C) 2008 Atmel Corporation
5  * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 #ifndef _SF_INTERNAL_H_
11 #define _SF_INTERNAL_H_
12
13 #define SPI_FLASH_3B_ADDR_LEN           3
14 #define SPI_FLASH_CMD_LEN               (1 + SPI_FLASH_3B_ADDR_LEN)
15 #define SPI_FLASH_16MB_BOUN             0x1000000
16
17 /* CFI Manufacture ID's */
18 #define SPI_FLASH_CFI_MFR_SPANSION      0x01
19 #define SPI_FLASH_CFI_MFR_STMICRO       0x20
20 #define SPI_FLASH_CFI_MFR_MACRONIX      0xc2
21 #define SPI_FLASH_CFI_MFR_WINBOND       0xef
22
23 /* SECT flags */
24 #define SECT_4K                         (1 << 1)
25 #define SECT_32K                        (1 << 2)
26 #define E_FSR                           (1 << 3)
27
28 /* Erase commands */
29 #define CMD_ERASE_4K                    0x20
30 #define CMD_ERASE_32K                   0x52
31 #define CMD_ERASE_CHIP                  0xc7
32 #define CMD_ERASE_64K                   0xd8
33
34 /* Write commands */
35 #define CMD_WRITE_STATUS                0x01
36 #define CMD_PAGE_PROGRAM                0x02
37 #define CMD_WRITE_DISABLE               0x04
38 #define CMD_READ_STATUS                 0x05
39 #define CMD_QUAD_PAGE_PROGRAM           0x32
40 #define CMD_READ_STATUS1                0x35
41 #define CMD_WRITE_ENABLE                0x06
42 #define CMD_READ_CONFIG                 0x35
43 #define CMD_FLAG_STATUS                 0x70
44
45 /* Read commands */
46 #define CMD_READ_ARRAY_SLOW             0x03
47 #define CMD_READ_ARRAY_FAST             0x0b
48 #define CMD_READ_DUAL_OUTPUT_FAST       0x3b
49 #define CMD_READ_DUAL_IO_FAST           0xbb
50 #define CMD_READ_QUAD_OUTPUT_FAST       0x6b
51 #define CMD_READ_QUAD_IO_FAST           0xeb
52 #define CMD_READ_ID                     0x9f
53
54 /* Bank addr access commands */
55 #ifdef CONFIG_SPI_FLASH_BAR
56 # define CMD_BANKADDR_BRWR              0x17
57 # define CMD_BANKADDR_BRRD              0x16
58 # define CMD_EXTNADDR_WREAR             0xC5
59 # define CMD_EXTNADDR_RDEAR             0xC8
60 #endif
61
62 /* Common status */
63 #define STATUS_WIP                      0x01
64 #define STATUS_QEB_WINSPAN              (1 << 1)
65 #define STATUS_QEB_MXIC                 (1 << 6)
66 #define STATUS_PEC                      0x80
67
68 /* Flash timeout values */
69 #define SPI_FLASH_PROG_TIMEOUT          (2 * CONFIG_SYS_HZ)
70 #define SPI_FLASH_PAGE_ERASE_TIMEOUT    (5 * CONFIG_SYS_HZ)
71 #define SPI_FLASH_SECTOR_ERASE_TIMEOUT  (10 * CONFIG_SYS_HZ)
72
73 /* SST specific */
74 #ifdef CONFIG_SPI_FLASH_SST
75 # define SST_WP                 0x01    /* Supports AAI word program */
76 # define CMD_SST_BP             0x02    /* Byte Program */
77 # define CMD_SST_AAI_WP         0xAD    /* Auto Address Incr Word Program */
78
79 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
80                 const void *buf);
81 #endif
82
83 /* Send a single-byte command to the device and read the response */
84 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
85
86 /*
87  * Send a multi-byte command to the device and read the response. Used
88  * for flash array reads, etc.
89  */
90 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
91                 size_t cmd_len, void *data, size_t data_len);
92
93 /*
94  * Send a multi-byte command to the device followed by (optional)
95  * data. Used for programming the flash array, etc.
96  */
97 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
98                 const void *data, size_t data_len);
99
100
101 /* Flash erase(sectors) operation, support all possible erase commands */
102 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
103
104 /* Read the status register */
105 int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs);
106
107 /* Program the status register */
108 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
109
110 /* Read the config register */
111 int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc);
112
113 /* Program the config register */
114 int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc);
115
116 /* Enable writing on the SPI flash */
117 static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
118 {
119         return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
120 }
121
122 /* Disable writing on the SPI flash */
123 static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
124 {
125         return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
126 }
127
128 /*
129  * Send the read status command to the device and wait for the wip
130  * (write-in-progress) bit to clear itself.
131  */
132 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout);
133
134 /*
135  * Used for spi_flash write operation
136  * - SPI claim
137  * - spi_flash_cmd_write_enable
138  * - spi_flash_cmd_write
139  * - spi_flash_cmd_wait_ready
140  * - SPI release
141  */
142 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
143                 size_t cmd_len, const void *buf, size_t buf_len);
144
145 /*
146  * Flash write operation, support all possible write commands.
147  * Write the requested data out breaking it up into multiple write
148  * commands as needed per the write size.
149  */
150 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
151                 size_t len, const void *buf);
152
153 /*
154  * Same as spi_flash_cmd_read() except it also claims/releases the SPI
155  * bus. Used as common part of the ->read() operation.
156  */
157 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
158                 size_t cmd_len, void *data, size_t data_len);
159
160 /* Flash read operation, support all possible read commands */
161 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
162                 size_t len, void *data);
163
164 #endif /* _SF_INTERNAL_H_ */