4 * Copyright (C) 2008 Atmel Corporation
5 * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
6 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <spi_flash.h>
18 #include "sf_internal.h"
20 DECLARE_GLOBAL_DATA_PTR;
23 * struct spi_flash_params - SPI/QSPI flash device params structure
25 * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
26 * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
27 * @ext_jedec: Device ext_jedec ID
28 * @sector_size: Sector size of this device
29 * @nr_sectors: No.of sectors on this device
30 * @e_rd_cmd: Enum list for read commands
31 * @flags: Importent param, for flash specific behaviour
33 struct spi_flash_params {
43 static const struct spi_flash_params spi_flash_params_table[] = {
44 #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
45 {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, 0, SECT_4K},
46 {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, 0, SECT_4K},
47 {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, 0, SECT_4K},
48 {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, 0, SECT_4K},
49 {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, 0, SECT_4K},
50 {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, 0, SECT_4K},
51 {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, 0, SECT_4K},
52 {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, 0, SECT_4K},
54 #ifdef CONFIG_SPI_FLASH_EON /* EON */
55 {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0, 0},
56 {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
57 {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0, 0},
58 {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0, 0},
60 #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
61 {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, 0, SECT_4K},
62 {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, 0, SECT_4K},
64 #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
65 {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0, 0},
66 {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0, 0},
67 {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0, 0},
68 {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0, 0},
69 {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0, 0},
70 {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0, 0},
71 {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, 0, 0},
72 {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, 0, 0},
73 {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, 0, 0},
74 {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, 0, 0},
76 #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
77 {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0, 0},
78 {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0, 0},
79 {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0, 0},
80 {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0, 0},
81 {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, 0, 0},
82 {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, 0, 0},
83 {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, 0, 0},
84 {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, 0, 0},
85 {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, 0, 0},
86 {"S25FL256S_256K", 0x010219, 0x4d00, 64 * 1024, 512, RD_FULL, WR_QPP},
87 {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP},
88 {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, 0, 0},
89 {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, 0, 0},
91 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
92 {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0, 0},
93 {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0, 0},
94 {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0, 0},
95 {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0, 0},
96 {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0, 0},
97 {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0, 0},
98 {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0, 0},
99 {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0, 0},
100 {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, 0, SECT_4K},
101 {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, 0, SECT_4K},
102 {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, 0, SECT_4K},
103 {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, 0, SECT_4K},
104 {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, 0, SECT_4K},
105 {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, 0, SECT_4K},
106 {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, 0, SECT_4K},
107 {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, 0, SECT_4K},
108 {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, 0, E_FSR | SECT_4K},
109 {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, 0, E_FSR | SECT_4K},
110 {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, 0, E_FSR | SECT_4K},
111 {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, 0, E_FSR | SECT_4K},
113 #ifdef CONFIG_SPI_FLASH_SST /* SST */
114 {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
115 {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
116 {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, 0, SECT_4K | SST_WP},
117 {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, 0, SECT_4K | SST_WP},
118 {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, 0, SECT_4K},
119 {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, 0, SECT_4K | SST_WP},
120 {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, 0, SECT_4K | SST_WP},
121 {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, 0, SECT_4K | SST_WP},
122 {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
123 {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
125 #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
126 {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0, 0},
127 {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0, 0},
128 {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0, 0},
129 {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, 0, SECT_4K},
130 {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, 0, SECT_4K},
131 {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, 0, SECT_4K},
132 {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
133 {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, 0, SECT_4K},
134 {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, 0, SECT_4K},
135 {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, 0, SECT_4K},
136 {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, 0, SECT_4K},
137 {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, 0, SECT_4K},
138 {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, 0, SECT_4K},
139 {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, 0, SECT_4K},
140 {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, 0, SECT_4K},
141 {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, 0, SECT_4K},
142 {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, 0, SECT_4K},
143 {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, 0, SECT_4K},
147 * Below paired flash devices has similar spi_flash params.
148 * (S25FL129P_64K, S25FL128S_64K)
149 * (W25Q80BL, W25Q80BV)
150 * (W25Q16CL, W25Q16DV)
151 * (W25Q32BV, W25Q32FV_SPI)
152 * (W25Q64CV, W25Q64FV_SPI)
153 * (W25Q128BV, W25Q128FV_SPI)
154 * (W25Q32DW, W25Q32FV_QPI)
155 * (W25Q64DW, W25Q64FV_QPI)
156 * (W25Q128FW, W25Q128FV_QPI)
160 /* Read commands array */
161 static u8 spi_read_cmds_array[] = {
163 CMD_READ_DUAL_OUTPUT_FAST,
164 CMD_READ_DUAL_IO_FAST,
165 CMD_READ_QUAD_OUTPUT_FAST,
168 static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
171 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
172 case SPI_FLASH_CFI_MFR_SPANSION:
173 case SPI_FLASH_CFI_MFR_WINBOND:
174 return spi_flash_set_qeb_winspan(flash);
176 #ifdef CONFIG_SPI_FLASH_STMICRO
177 case SPI_FLASH_CFI_MFR_STMICRO:
178 debug("SF: QEB is volatile for %02x flash\n", idcode0);
182 printf("SF: Need set QEB func for %02x flash\n", idcode0);
187 static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
190 const struct spi_flash_params *params;
191 struct spi_flash *flash;
194 u16 jedec = idcode[1] << 8 | idcode[2];
195 u16 ext_jedec = idcode[3] << 8 | idcode[4];
197 /* Get the flash id (jedec = manuf_id + dev_id, ext_jedec) */
198 for (i = 0; i < ARRAY_SIZE(spi_flash_params_table); i++) {
199 params = &spi_flash_params_table[i];
200 if ((params->jedec >> 16) == idcode[0]) {
201 if ((params->jedec & 0xFFFF) == jedec) {
202 if (params->ext_jedec == 0)
204 else if (params->ext_jedec == ext_jedec)
210 if (i == ARRAY_SIZE(spi_flash_params_table)) {
211 printf("SF: Unsupported flash IDs: ");
212 printf("manuf %02x, jedec %04x, ext_jedec %04x\n",
213 idcode[0], jedec, ext_jedec);
217 flash = malloc(sizeof(*flash));
219 debug("SF: Failed to allocate spi_flash\n");
222 memset(flash, '\0', sizeof(*flash));
224 /* Assign spi data */
226 flash->name = params->name;
227 flash->memory_map = spi->memory_map;
229 /* Assign spi_flash ops */
230 flash->write = spi_flash_cmd_write_ops;
231 #ifdef CONFIG_SPI_FLASH_SST
232 if (params->flags & SST_WP)
233 flash->write = sst_write_wp;
235 flash->erase = spi_flash_cmd_erase_ops;
236 flash->read = spi_flash_cmd_read_ops;
238 /* Compute the flash size */
239 flash->page_size = (ext_jedec == 0x4d00) ? 512 : 256;
240 flash->sector_size = params->sector_size;
241 flash->size = flash->sector_size * params->nr_sectors;
243 /* Compute erase sector and command */
244 if (params->flags & SECT_4K) {
245 flash->erase_cmd = CMD_ERASE_4K;
246 flash->erase_size = 4096;
247 } else if (params->flags & SECT_32K) {
248 flash->erase_cmd = CMD_ERASE_32K;
249 flash->erase_size = 32768;
251 flash->erase_cmd = CMD_ERASE_64K;
252 flash->erase_size = flash->sector_size;
255 /* Look for the fastest read cmd */
256 cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx);
258 cmd = spi_read_cmds_array[cmd - 1];
259 flash->read_cmd = cmd;
261 /* Go for for default supported read cmd */
262 flash->read_cmd = CMD_READ_ARRAY_FAST;
265 /* Not require to look for fastest only two write cmds yet */
266 if (params->flags & WR_QPP && flash->spi->op_mode_tx & SPI_OPM_TX_QPP)
267 flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
269 /* Go for default supported write cmd */
270 flash->write_cmd = CMD_PAGE_PROGRAM;
272 /* Set the quad enable bit - only for quad commands */
273 if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
274 (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
275 if (spi_flash_set_qeb(flash, idcode[0])) {
276 debug("SF: Fail to set QEB for %02x\n", idcode[0]);
281 /* Poll cmd seclection */
282 flash->poll_cmd = CMD_READ_STATUS;
283 #ifdef CONFIG_SPI_FLASH_STMICRO
284 if (params->flags & E_FSR)
285 flash->poll_cmd = CMD_FLAG_STATUS;
288 /* Configure the BAR - discover bank cmds and read current bank */
289 #ifdef CONFIG_SPI_FLASH_BAR
291 if (flash->size > SPI_FLASH_16MB_BOUN) {
292 flash->bank_read_cmd = (idcode[0] == 0x01) ?
293 CMD_BANKADDR_BRRD : CMD_EXTNADDR_RDEAR;
294 flash->bank_write_cmd = (idcode[0] == 0x01) ?
295 CMD_BANKADDR_BRWR : CMD_EXTNADDR_WREAR;
297 if (spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
299 debug("SF: fail to read bank addr register\n");
302 flash->bank_curr = curr_bank;
304 flash->bank_curr = curr_bank;
308 /* Flash powers up read-only, so clear BP# bits */
309 #if defined(CONFIG_SPI_FLASH_ATMEL) || \
310 defined(CONFIG_SPI_FLASH_MACRONIX) || \
311 defined(CONFIG_SPI_FLASH_SST)
312 spi_flash_cmd_write_status(flash, 0);
318 #ifdef CONFIG_OF_CONTROL
319 int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
325 /* If there is no node, do nothing */
326 node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
330 addr = fdtdec_get_addr_size(blob, node, "memory-map", &size);
331 if (addr == FDT_ADDR_T_NONE) {
332 debug("%s: Cannot decode address\n", __func__);
336 if (flash->size != size) {
337 debug("%s: Memory map must cover entire device\n", __func__);
340 flash->memory_map = map_sysmem(addr, size);
344 #endif /* CONFIG_OF_CONTROL */
346 static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi)
348 struct spi_flash *flash = NULL;
352 /* Setup spi_slave */
354 printf("SF: Failed to set up slave\n");
359 ret = spi_claim_bus(spi);
361 debug("SF: Failed to claim SPI bus: %d\n", ret);
365 /* Read the ID codes */
366 ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
368 printf("SF: Failed to get idcodes\n");
373 printf("SF: Got idcodes\n");
374 print_buffer(0, idcode, 1, sizeof(idcode), 0);
377 /* Validate params from spi_flash_params table */
378 flash = spi_flash_validate_params(spi, idcode);
382 #ifdef CONFIG_OF_CONTROL
383 if (spi_flash_decode_fdt(gd->fdt_blob, flash)) {
384 debug("SF: FDT decode error\n");
388 #ifndef CONFIG_SPL_BUILD
389 printf("SF: Detected %s with page size ", flash->name);
390 print_size(flash->page_size, ", erase size ");
391 print_size(flash->erase_size, ", total ");
392 print_size(flash->size, "");
393 if (flash->memory_map)
394 printf(", mapped at %p", flash->memory_map);
397 #ifndef CONFIG_SPI_FLASH_BAR
398 if (flash->size > SPI_FLASH_16MB_BOUN) {
399 puts("SF: Warning - Only lower 16MiB accessible,");
400 puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
404 /* Release spi bus */
405 spi_release_bus(spi);
410 spi_release_bus(spi);
416 struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
417 unsigned int max_hz, unsigned int spi_mode)
419 struct spi_slave *spi;
421 spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
422 return spi_flash_probe_slave(spi);
425 #ifdef CONFIG_OF_SPI_FLASH
426 struct spi_flash *spi_flash_probe_fdt(const void *blob, int slave_node,
429 struct spi_slave *spi;
431 spi = spi_setup_slave_fdt(blob, slave_node, spi_node);
432 return spi_flash_probe_slave(spi);
436 void spi_flash_free(struct spi_flash *flash)
438 spi_free_slave(flash->spi);