3 * Driver for NAND support, Rick Bronson
4 * borrowed heavily from:
5 * (c) 1999 Machine Vision Holdings, Inc.
6 * (c) 1999, 2000 David Woodhouse <dwmw2@infradead.org>
8 * Added 16-bit nand support
9 * (C) 2004 Texas Instruments
18 #ifdef CONFIG_SHOW_BOOT_PROGRESS
19 # include <status_led.h>
20 # define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
22 # define SHOW_BOOT_PROGRESS(arg)
25 #if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
27 #include <linux/mtd/nand_legacy.h>
28 #include <linux/mtd/nand_ids.h>
29 #include <jffs2/jffs2.h>
31 #ifdef CONFIG_OMAP1510
32 void archflashwp(void *archdata, int wp);
35 #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
40 /* ****************** WARNING *********************
41 * When ALLOW_ERASE_BAD_DEBUG is non-zero the erase command will
42 * erase (or at least attempt to erase) blocks that are marked
43 * bad. This can be very handy if you are _sure_ that the block
44 * is OK, say because you marked a good block bad to test bad
45 * block handling and you are done testing, or if you have
46 * accidentally marked blocks bad.
48 * Erasing factory marked bad blocks is a _bad_ idea. If the
49 * erase succeeds there is no reliable way to find them again,
50 * and attempting to program or erase bad blocks can affect
51 * the data in _other_ (good) blocks.
53 #define ALLOW_ERASE_BAD_DEBUG 0
55 #define CONFIG_MTD_NAND_ECC /* enable ECC */
56 #define CONFIG_MTD_NAND_ECC_JFFS2
58 /* bits for nand_legacy_rw() `cmd'; or together as needed */
59 #define NANDRW_READ 0x01
60 #define NANDRW_WRITE 0x00
61 #define NANDRW_JFFS2 0x02
62 #define NANDRW_JFFS2_SKIP 0x04
66 * Exported variables etc.
69 /* Definition of the out of band configuration structure */
70 struct nand_oob_config {
71 /* position of ECC bytes inside oob */
73 /* position of bad blk flag inside oob -1 = inactive */
75 /* position of ECC valid flag inside oob -1 = inactive */
77 } oob_config = { {0}, 0, 0};
79 struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE] = {{0}};
81 int curr_device = -1; /* Current NAND Device */
87 int nand_legacy_erase(struct nand_chip* nand, size_t ofs,
88 size_t len, int clean);
89 int nand_legacy_rw(struct nand_chip* nand, int cmd,
90 size_t start, size_t len,
91 size_t * retlen, u_char * buf);
92 void nand_print(struct nand_chip *nand);
93 void nand_print_bad(struct nand_chip *nand);
94 int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len,
95 size_t * retlen, u_char * buf);
96 int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,
97 size_t * retlen, const u_char * buf);
102 static int NanD_WaitReady(struct nand_chip *nand, int ale_wait);
103 static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len,
104 size_t * retlen, u_char *buf, u_char *ecc_code);
105 static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len,
106 size_t * retlen, const u_char * buf,
108 #ifdef CONFIG_MTD_NAND_ECC
109 static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc);
110 static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code);
116 * Function definitions
120 /* returns 0 if block containing pos is OK:
121 * valid erase block and
122 * not marked bad, or no bad mark position is specified
123 * returns 1 if marked bad or otherwise invalid
125 static int check_block (struct nand_chip *nand, unsigned long pos)
129 uint16_t oob_data16[6];
130 int page0 = pos & (-nand->erasesize);
131 int page1 = page0 + nand->oobblock;
132 int badpos = oob_config.badblock_pos;
134 if (pos >= nand->totlen)
138 return 0; /* no way to check, assume OK */
141 if (nand_read_oob(nand, (page0 + 0), 12, &retlen, (uint8_t *)oob_data16)
142 || (oob_data16[2] & 0xff00) != 0xff00)
144 if (nand_read_oob(nand, (page1 + 0), 12, &retlen, (uint8_t *)oob_data16)
145 || (oob_data16[2] & 0xff00) != 0xff00)
148 /* Note - bad block marker can be on first or second page */
149 if (nand_read_oob(nand, page0 + badpos, 1, &retlen, (unsigned char *)&oob_data)
151 || nand_read_oob (nand, page1 + badpos, 1, &retlen, (unsigned char *)&oob_data)
159 /* print bad blocks in NAND flash */
160 void nand_print_bad(struct nand_chip* nand)
164 for (pos = 0; pos < nand->totlen; pos += nand->erasesize) {
165 if (check_block(nand, pos))
166 printf(" 0x%8.8lx\n", pos);
171 /* cmd: 0: NANDRW_WRITE write, fail on bad block
172 * 1: NANDRW_READ read, fail on bad block
173 * 2: NANDRW_WRITE | NANDRW_JFFS2 write, skip bad blocks
174 * 3: NANDRW_READ | NANDRW_JFFS2 read, data all 0xff for bad blocks
175 * 7: NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP read, skip bad blocks
177 int nand_legacy_rw (struct nand_chip* nand, int cmd,
178 size_t start, size_t len,
179 size_t * retlen, u_char * buf)
181 int ret = 0, n, total = 0;
183 /* eblk (once set) is the start of the erase block containing the
184 * data being processed.
186 unsigned long eblk = ~0; /* force mismatch on first pass */
187 unsigned long erasesize = nand->erasesize;
190 if ((start & (-erasesize)) != eblk) {
191 /* have crossed into new erase block, deal with
192 * it if it is sure marked bad.
194 eblk = start & (-erasesize); /* start of block */
195 if (check_block(nand, eblk)) {
196 if (cmd == (NANDRW_READ | NANDRW_JFFS2)) {
198 start - eblk < erasesize) {
205 } else if (cmd == (NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP)) {
208 } else if (cmd == (NANDRW_WRITE | NANDRW_JFFS2)) {
218 /* The ECC will not be calculated correctly if
219 less than 512 is written or read */
220 /* Is request at least 512 bytes AND it starts on a proper boundry */
221 if((start != ROUND_DOWN(start, 0x200)) || (len < 0x200))
222 printf("Warning block writes should be at least 512 bytes and start on a 512 byte boundry\n");
224 if (cmd & NANDRW_READ) {
225 ret = nand_read_ecc(nand, start,
226 min(len, eblk + erasesize - start),
227 (size_t *)&n, (u_char*)buf, (u_char *)eccbuf);
229 ret = nand_write_ecc(nand, start,
230 min(len, eblk + erasesize - start),
231 (size_t *)&n, (u_char*)buf, (u_char *)eccbuf);
248 void nand_print(struct nand_chip *nand)
250 if (nand->numchips > 1) {
251 printf("%s at 0x%lx,\n"
252 "\t %d chips %s, size %d MB, \n"
253 "\t total size %ld MB, sector size %ld kB\n",
254 nand->name, nand->IO_ADDR, nand->numchips,
255 nand->chips_name, 1 << (nand->chipshift - 20),
256 nand->totlen >> 20, nand->erasesize >> 10);
259 printf("%s at 0x%lx (", nand->chips_name, nand->IO_ADDR);
260 print_size(nand->totlen, ", ");
261 print_size(nand->erasesize, " sector)\n");
265 /* ------------------------------------------------------------------------- */
267 static int NanD_WaitReady(struct nand_chip *nand, int ale_wait)
269 /* This is inline, to optimise the common case, where it's ready instantly */
272 #ifdef NAND_NO_RB /* in config file, shorter delays currently wrap accesses */
274 NAND_WAIT_READY(nand); /* do the worst case 25us wait */
277 #else /* has functional r/b signal */
278 NAND_WAIT_READY(nand);
283 /* NanD_Command: Send a flash command to the flash chip */
285 static inline int NanD_Command(struct nand_chip *nand, unsigned char command)
287 unsigned long nandptr = nand->IO_ADDR;
289 /* Assert the CLE (Command Latch Enable) line to the flash chip */
290 NAND_CTL_SETCLE(nandptr);
292 /* Send the command */
293 WRITE_NAND_COMMAND(command, nandptr);
295 /* Lower the CLE line */
296 NAND_CTL_CLRCLE(nandptr);
299 if(command == NAND_CMD_RESET){
301 NanD_Command(nand, NAND_CMD_STATUS);
303 ret_val = READ_NAND(nandptr);/* wait till ready */
304 } while((ret_val & 0x40) != 0x40);
307 return NanD_WaitReady(nand, 0);
310 /* NanD_Address: Set the current address for the flash chip */
312 static int NanD_Address(struct nand_chip *nand, int numbytes, unsigned long ofs)
314 unsigned long nandptr;
317 nandptr = nand->IO_ADDR;
319 /* Assert the ALE (Address Latch Enable) line to the flash chip */
320 NAND_CTL_SETALE(nandptr);
322 /* Send the address */
323 /* Devices with 256-byte page are addressed as:
324 * Column (bits 0-7), Page (bits 8-15, 16-23, 24-31)
325 * there is no device on the market with page256
326 * and more than 24 bits.
327 * Devices with 512-byte page are addressed as:
328 * Column (bits 0-7), Page (bits 9-16, 17-24, 25-31)
329 * 25-31 is sent only if the chip support it.
330 * bit 8 changes the read command to be sent
331 * (NAND_CMD_READ0 or NAND_CMD_READ1).
334 if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE)
335 WRITE_NAND_ADDRESS(ofs, nandptr);
337 ofs = ofs >> nand->page_shift;
339 if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE) {
340 for (i = 0; i < nand->pageadrlen; i++, ofs = ofs >> 8) {
341 WRITE_NAND_ADDRESS(ofs, nandptr);
345 /* Lower the ALE line */
346 NAND_CTL_CLRALE(nandptr);
348 /* Wait for the chip to respond */
349 return NanD_WaitReady(nand, 1);
352 /* NanD_SelectChip: Select a given flash chip within the current floor */
354 static inline int NanD_SelectChip(struct nand_chip *nand, int chip)
356 /* Wait for it to be ready */
357 return NanD_WaitReady(nand, 0);
360 /* NanD_IdentChip: Identify a given NAND chip given {floor,chip} */
362 static int NanD_IdentChip(struct nand_chip *nand, int floor, int chip)
366 NAND_ENABLE_CE(nand); /* set pin low */
368 if (NanD_Command(nand, NAND_CMD_RESET)) {
370 printf("NanD_Command (reset) for %d,%d returned true\n",
373 NAND_DISABLE_CE(nand); /* set pin high */
377 /* Read the NAND chip ID: 1. Send ReadID command */
378 if (NanD_Command(nand, NAND_CMD_READID)) {
380 printf("NanD_Command (ReadID) for %d,%d returned true\n",
383 NAND_DISABLE_CE(nand); /* set pin high */
387 /* Read the NAND chip ID: 2. Send address byte zero */
388 NanD_Address(nand, ADDR_COLUMN, 0);
390 /* Read the manufacturer and device id codes from the device */
392 mfr = READ_NAND(nand->IO_ADDR);
394 id = READ_NAND(nand->IO_ADDR);
396 NAND_DISABLE_CE(nand); /* set pin high */
399 printf("NanD_Command (ReadID) got %x %x\n", mfr, id);
401 if (mfr == 0xff || mfr == 0) {
402 /* No response - return failure */
406 /* Check it's the same as the first chip we identified.
407 * M-Systems say that any given nand_chip device should only
408 * contain _one_ type of flash part, although that's not a
409 * hardware restriction. */
411 if (nand->mfr == mfr && nand->id == id) {
412 return 1; /* This is another the same the first */
414 printf("Flash chip at floor %d, chip %d is different:\n",
419 /* Print and store the manufacturer and ID codes. */
420 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
421 if (mfr == nand_flash_ids[i].manufacture_id &&
422 id == nand_flash_ids[i].model_id) {
424 printf("Flash chip found:\n\t Manufacturer ID: 0x%2.2X, "
425 "Chip ID: 0x%2.2X (%s)\n", mfr, id,
426 nand_flash_ids[i].name);
432 nand_flash_ids[i].chipshift;
433 nand->page256 = nand_flash_ids[i].page256;
436 nand->oobblock = 256;
438 nand->page_shift = 8;
440 nand->oobblock = 512;
442 nand->page_shift = 9;
444 nand->pageadrlen = nand_flash_ids[i].pageadrlen;
445 nand->erasesize = nand_flash_ids[i].erasesize;
446 nand->chips_name = nand_flash_ids[i].name;
447 nand->bus16 = nand_flash_ids[i].bus16;
456 /* We haven't fully identified the chip. Print as much as we know. */
457 printf("Unknown flash chip found: %2.2X %2.2X\n",
464 /* NanD_ScanChips: Find all NAND chips present in a nand_chip, and identify them */
466 static void NanD_ScanChips(struct nand_chip *nand)
469 int numchips[NAND_MAX_FLOORS];
470 int maxchips = NAND_MAX_CHIPS;
478 /* For each floor, find the number of valid chips it contains */
479 for (floor = 0; floor < NAND_MAX_FLOORS; floor++) {
482 for (chip = 0; chip < maxchips && ret != 0; chip++) {
484 ret = NanD_IdentChip(nand, floor, chip);
492 /* If there are none at all that we recognise, bail */
493 if (!nand->numchips) {
495 puts ("No NAND flash chips recognised.\n");
500 /* Allocate an array to hold the information for each chip */
501 nand->chips = malloc(sizeof(struct Nand) * nand->numchips);
503 puts ("No memory for allocating chip info structures\n");
509 /* Fill out the chip array with {floor, chipno} for each
510 * detected chip in the device. */
511 for (floor = 0; floor < NAND_MAX_FLOORS; floor++) {
512 for (chip = 0; chip < numchips[floor]; chip++) {
513 nand->chips[ret].floor = floor;
514 nand->chips[ret].chip = chip;
515 nand->chips[ret].curadr = 0;
516 nand->chips[ret].curmode = 0x50;
521 /* Calculate and print the total size of the device */
522 nand->totlen = nand->numchips * (1 << nand->chipshift);
525 printf("%d flash chips found. Total nand_chip size: %ld MB\n",
526 nand->numchips, nand->totlen >> 20);
530 /* we need to be fast here, 1 us per read translates to 1 second per meg */
531 static void NanD_ReadBuf (struct nand_chip *nand, u_char * data_buf, int cntr)
533 unsigned long nandptr = nand->IO_ADDR;
535 NanD_Command (nand, NAND_CMD_READ0);
541 val = READ_NAND (nandptr);
542 *data_buf++ = val & 0xff;
543 *data_buf++ = val >> 8;
544 val = READ_NAND (nandptr);
545 *data_buf++ = val & 0xff;
546 *data_buf++ = val >> 8;
547 val = READ_NAND (nandptr);
548 *data_buf++ = val & 0xff;
549 *data_buf++ = val >> 8;
550 val = READ_NAND (nandptr);
551 *data_buf++ = val & 0xff;
552 *data_buf++ = val >> 8;
553 val = READ_NAND (nandptr);
554 *data_buf++ = val & 0xff;
555 *data_buf++ = val >> 8;
556 val = READ_NAND (nandptr);
557 *data_buf++ = val & 0xff;
558 *data_buf++ = val >> 8;
559 val = READ_NAND (nandptr);
560 *data_buf++ = val & 0xff;
561 *data_buf++ = val >> 8;
562 val = READ_NAND (nandptr);
563 *data_buf++ = val & 0xff;
564 *data_buf++ = val >> 8;
569 val = READ_NAND (nandptr);
570 *data_buf++ = val & 0xff;
571 *data_buf++ = val >> 8;
576 *data_buf++ = READ_NAND (nandptr);
577 *data_buf++ = READ_NAND (nandptr);
578 *data_buf++ = READ_NAND (nandptr);
579 *data_buf++ = READ_NAND (nandptr);
580 *data_buf++ = READ_NAND (nandptr);
581 *data_buf++ = READ_NAND (nandptr);
582 *data_buf++ = READ_NAND (nandptr);
583 *data_buf++ = READ_NAND (nandptr);
584 *data_buf++ = READ_NAND (nandptr);
585 *data_buf++ = READ_NAND (nandptr);
586 *data_buf++ = READ_NAND (nandptr);
587 *data_buf++ = READ_NAND (nandptr);
588 *data_buf++ = READ_NAND (nandptr);
589 *data_buf++ = READ_NAND (nandptr);
590 *data_buf++ = READ_NAND (nandptr);
591 *data_buf++ = READ_NAND (nandptr);
596 *data_buf++ = READ_NAND (nandptr);
605 static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len,
606 size_t * retlen, u_char *buf, u_char *ecc_code)
610 #ifdef CONFIG_MTD_NAND_ECC
617 /* Do not allow reads past end of device */
618 if ((start + len) > nand->totlen) {
619 printf ("%s: Attempt read beyond end of device %x %x %x\n",
620 __FUNCTION__, (uint) start, (uint) len, (uint) nand->totlen);
625 /* First we calculate the starting page */
626 /*page = shr(start, nand->page_shift);*/
627 page = start >> nand->page_shift;
629 /* Get raw starting column */
630 col = start & (nand->oobblock - 1);
632 /* Initialize return value */
635 /* Select the NAND device */
636 NAND_ENABLE_CE(nand); /* set pin low */
638 /* Loop until all data read */
639 while (*retlen < len) {
641 #ifdef CONFIG_MTD_NAND_ECC
642 /* Do we have this page in cache ? */
643 if (nand->cache_page == page)
645 /* Send the read command */
646 NanD_Command(nand, NAND_CMD_READ0);
648 NanD_Address(nand, ADDR_COLUMN_PAGE,
649 (page << nand->page_shift) + (col >> 1));
651 NanD_Address(nand, ADDR_COLUMN_PAGE,
652 (page << nand->page_shift) + col);
655 /* Read in a page + oob data */
656 NanD_ReadBuf(nand, nand->data_buf, nand->oobblock + nand->oobsize);
658 /* copy data into cache, for read out of cache and if ecc fails */
659 if (nand->data_cache) {
660 memcpy (nand->data_cache, nand->data_buf,
661 nand->oobblock + nand->oobsize);
664 /* Pick the ECC bytes out of the oob data */
665 for (j = 0; j < 6; j++) {
666 ecc_code[j] = nand->data_buf[(nand->oobblock + oob_config.ecc_pos[j])];
669 /* Calculate the ECC and verify it */
670 /* If block was not written with ECC, skip ECC */
671 if (oob_config.eccvalid_pos != -1 &&
672 (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0x0f) != 0x0f) {
674 nand_calculate_ecc (&nand->data_buf[0], &ecc_calc[0]);
675 switch (nand_correct_data (&nand->data_buf[0], &ecc_code[0], &ecc_calc[0])) {
677 printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page);
681 case 2: /* transfer ECC corrected data to cache */
682 if (nand->data_cache)
683 memcpy (nand->data_cache, nand->data_buf, 256);
688 if (oob_config.eccvalid_pos != -1 &&
689 nand->oobblock == 512 && (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0xf0) != 0xf0) {
691 nand_calculate_ecc (&nand->data_buf[256], &ecc_calc[3]);
692 switch (nand_correct_data (&nand->data_buf[256], &ecc_code[3], &ecc_calc[3])) {
694 printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page);
698 case 2: /* transfer ECC corrected data to cache */
699 if (nand->data_cache)
700 memcpy (&nand->data_cache[256], &nand->data_buf[256], 256);
705 /* Read the data from ECC data buffer into return buffer */
706 data_poi = (nand->data_cache) ? nand->data_cache : nand->data_buf;
708 if ((*retlen + (nand->oobblock - col)) >= len) {
709 memcpy (buf + *retlen, data_poi, len - *retlen);
712 memcpy (buf + *retlen, data_poi, nand->oobblock - col);
713 *retlen += nand->oobblock - col;
715 /* Set cache page address, invalidate, if ecc_failed */
716 nand->cache_page = (nand->data_cache && !ecc_failed) ? page : -1;
718 ecc_status += ecc_failed;
722 /* Send the read command */
723 NanD_Command(nand, NAND_CMD_READ0);
725 NanD_Address(nand, ADDR_COLUMN_PAGE,
726 (page << nand->page_shift) + (col >> 1));
728 NanD_Address(nand, ADDR_COLUMN_PAGE,
729 (page << nand->page_shift) + col);
732 /* Read the data directly into the return buffer */
733 if ((*retlen + (nand->oobblock - col)) >= len) {
734 NanD_ReadBuf(nand, buf + *retlen, len - *retlen);
739 NanD_ReadBuf(nand, buf + *retlen, nand->oobblock - col);
740 *retlen += nand->oobblock - col;
743 /* For subsequent reads align to page boundary. */
745 /* Increment page address */
749 /* De-select the NAND device */
750 NAND_DISABLE_CE(nand); /* set pin high */
753 * Return success, if no ECC failures, else -EIO
754 * fs driver will take care of that, because
755 * retlen == desired len and result == -EIO
757 return ecc_status ? -1 : 0;
761 * Nand_page_program function is used for write and writev !
763 static int nand_write_page (struct nand_chip *nand,
764 int page, int col, int last, u_char * ecc_code)
768 unsigned long nandptr = nand->IO_ADDR;
770 #ifdef CONFIG_MTD_NAND_ECC
771 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
772 int ecc_bytes = (nand->oobblock == 512) ? 6 : 3;
776 for (i = nand->oobblock; i < nand->oobblock + nand->oobsize; i++)
777 nand->data_buf[i] = 0xff;
779 #ifdef CONFIG_MTD_NAND_ECC
780 /* Zero out the ECC array */
781 for (i = 0; i < 6; i++)
784 /* Read back previous written data, if col > 0 */
786 NanD_Command (nand, NAND_CMD_READ0);
788 NanD_Address (nand, ADDR_COLUMN_PAGE,
789 (page << nand->page_shift) + (col >> 1));
791 NanD_Address (nand, ADDR_COLUMN_PAGE,
792 (page << nand->page_shift) + col);
798 for (i = 0; i < col; i += 2) {
799 val = READ_NAND (nandptr);
800 nand->data_buf[i] = val & 0xff;
801 nand->data_buf[i + 1] = val >> 8;
804 for (i = 0; i < col; i++)
805 nand->data_buf[i] = READ_NAND (nandptr);
809 /* Calculate and write the ECC if we have enough data */
810 if ((col < nand->eccsize) && (last >= nand->eccsize)) {
811 nand_calculate_ecc (&nand->data_buf[0], &(ecc_code[0]));
812 for (i = 0; i < 3; i++) {
813 nand->data_buf[(nand->oobblock +
814 oob_config.ecc_pos[i])] = ecc_code[i];
816 if (oob_config.eccvalid_pos != -1) {
817 nand->data_buf[nand->oobblock +
818 oob_config.eccvalid_pos] = 0xf0;
822 /* Calculate and write the second ECC if we have enough data */
823 if ((nand->oobblock == 512) && (last == nand->oobblock)) {
824 nand_calculate_ecc (&nand->data_buf[256], &(ecc_code[3]));
825 for (i = 3; i < 6; i++) {
826 nand->data_buf[(nand->oobblock +
827 oob_config.ecc_pos[i])] = ecc_code[i];
829 if (oob_config.eccvalid_pos != -1) {
830 nand->data_buf[nand->oobblock +
831 oob_config.eccvalid_pos] &= 0x0f;
835 /* Prepad for partial page programming !!! */
836 for (i = 0; i < col; i++)
837 nand->data_buf[i] = 0xff;
839 /* Postpad for partial page programming !!! oob is already padded */
840 for (i = last; i < nand->oobblock; i++)
841 nand->data_buf[i] = 0xff;
843 /* Send command to begin auto page programming */
844 NanD_Command (nand, NAND_CMD_READ0);
845 NanD_Command (nand, NAND_CMD_SEQIN);
847 NanD_Address (nand, ADDR_COLUMN_PAGE,
848 (page << nand->page_shift) + (col >> 1));
850 NanD_Address (nand, ADDR_COLUMN_PAGE,
851 (page << nand->page_shift) + col);
854 /* Write out complete page of data */
856 for (i = 0; i < (nand->oobblock + nand->oobsize); i += 2) {
857 WRITE_NAND (nand->data_buf[i] +
858 (nand->data_buf[i + 1] << 8),
862 for (i = 0; i < (nand->oobblock + nand->oobsize); i++)
863 WRITE_NAND (nand->data_buf[i], nand->IO_ADDR);
866 /* Send command to actually program the data */
867 NanD_Command (nand, NAND_CMD_PAGEPROG);
868 NanD_Command (nand, NAND_CMD_STATUS);
874 ret_val = READ_NAND (nandptr); /* wait till ready */
875 } while ((ret_val & 0x40) != 0x40);
878 /* See if device thinks it succeeded */
879 if (READ_NAND (nand->IO_ADDR) & 0x01) {
880 printf ("%s: Failed write, page 0x%08x, ", __FUNCTION__,
884 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
886 * The NAND device assumes that it is always writing to
887 * a cleanly erased page. Hence, it performs its internal
888 * write verification only on bits that transitioned from
889 * 1 to 0. The device does NOT verify the whole page on a
890 * byte by byte basis. It is possible that the page was
891 * not completely erased or the page is becoming unusable
892 * due to wear. The read with ECC would catch the error
893 * later when the ECC page check fails, but we would rather
894 * catch it early in the page write stage. Better to write
895 * no data than invalid data.
898 /* Send command to read back the page */
899 if (col < nand->eccsize)
900 NanD_Command (nand, NAND_CMD_READ0);
902 NanD_Command (nand, NAND_CMD_READ1);
904 NanD_Address (nand, ADDR_COLUMN_PAGE,
905 (page << nand->page_shift) + (col >> 1));
907 NanD_Address (nand, ADDR_COLUMN_PAGE,
908 (page << nand->page_shift) + col);
911 /* Loop through and verify the data */
913 for (i = col; i < last; i = +2) {
914 if ((nand->data_buf[i] +
915 (nand->data_buf[i + 1] << 8)) != READ_NAND (nand->IO_ADDR)) {
916 printf ("%s: Failed write verify, page 0x%08x ",
922 for (i = col; i < last; i++) {
923 if (nand->data_buf[i] != READ_NAND (nand->IO_ADDR)) {
924 printf ("%s: Failed write verify, page 0x%08x ",
931 #ifdef CONFIG_MTD_NAND_ECC
933 * We also want to check that the ECC bytes wrote
934 * correctly for the same reasons stated above.
936 NanD_Command (nand, NAND_CMD_READOOB);
938 NanD_Address (nand, ADDR_COLUMN_PAGE,
939 (page << nand->page_shift) + (col >> 1));
941 NanD_Address (nand, ADDR_COLUMN_PAGE,
942 (page << nand->page_shift) + col);
945 for (i = 0; i < nand->oobsize; i += 2) {
948 val = READ_NAND (nand->IO_ADDR);
949 nand->data_buf[i] = val & 0xff;
950 nand->data_buf[i + 1] = val >> 8;
953 for (i = 0; i < nand->oobsize; i++) {
954 nand->data_buf[i] = READ_NAND (nand->IO_ADDR);
957 for (i = 0; i < ecc_bytes; i++) {
958 if ((nand->data_buf[(oob_config.ecc_pos[i])] != ecc_code[i]) && ecc_code[i]) {
959 printf ("%s: Failed ECC write "
960 "verify, page 0x%08x, "
961 "%6i bytes were succesful\n",
962 __FUNCTION__, page, i);
966 #endif /* CONFIG_MTD_NAND_ECC */
967 #endif /* CONFIG_MTD_NAND_VERIFY_WRITE */
971 static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len,
972 size_t * retlen, const u_char * buf, u_char * ecc_code)
974 int i, page, col, cnt, ret = 0;
976 /* Do not allow write past end of device */
977 if ((to + len) > nand->totlen) {
978 printf ("%s: Attempt to write past end of page\n", __FUNCTION__);
982 /* Shift to get page */
983 page = ((int) to) >> nand->page_shift;
985 /* Get the starting column */
986 col = to & (nand->oobblock - 1);
988 /* Initialize return length value */
991 /* Select the NAND device */
992 #ifdef CONFIG_OMAP1510
999 NAND_ENABLE_CE(nand); /* set pin low */
1001 /* Check the WP bit */
1002 NanD_Command(nand, NAND_CMD_STATUS);
1003 if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
1004 printf ("%s: Device is write protected!!!\n", __FUNCTION__);
1009 /* Loop until all data is written */
1010 while (*retlen < len) {
1011 /* Invalidate cache, if we write to this page */
1012 if (nand->cache_page == page)
1013 nand->cache_page = -1;
1015 /* Write data into buffer */
1016 if ((col + len) >= nand->oobblock) {
1017 for (i = col, cnt = 0; i < nand->oobblock; i++, cnt++) {
1018 nand->data_buf[i] = buf[(*retlen + cnt)];
1021 for (i = col, cnt = 0; cnt < (len - *retlen); i++, cnt++) {
1022 nand->data_buf[i] = buf[(*retlen + cnt)];
1025 /* We use the same function for write and writev !) */
1026 ret = nand_write_page (nand, page, col, i, ecc_code);
1030 /* Next data start at page boundary */
1033 /* Update written bytes count */
1036 /* Increment page address */
1044 /* De-select the NAND device */
1045 NAND_DISABLE_CE(nand); /* set pin high */
1046 #ifdef CONFIG_OMAP1510
1056 /* read from the 16 bytes of oob data that correspond to a 512 byte
1057 * page or 2 256-byte pages.
1059 int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len,
1060 size_t * retlen, u_char * buf)
1063 struct Nand *mychip;
1066 mychip = &nand->chips[ofs >> nand->chipshift];
1068 /* update address for 2M x 8bit devices. OOB starts on the second */
1069 /* page to maintain compatibility with nand_read_ecc. */
1070 if (nand->page256) {
1077 NAND_ENABLE_CE(nand); /* set pin low */
1078 NanD_Command(nand, NAND_CMD_READOOB);
1080 NanD_Address(nand, ADDR_COLUMN_PAGE,
1081 ((ofs >> nand->page_shift) << nand->page_shift) +
1082 ((ofs & (nand->oobblock - 1)) >> 1));
1084 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
1087 /* treat crossing 8-byte OOB data for 2M x 8bit devices */
1088 /* Note: datasheet says it should automaticaly wrap to the */
1089 /* next OOB block, but it didn't work here. mf. */
1090 if (nand->page256 && ofs + len > (ofs | 0x7) + 1) {
1091 len256 = (ofs | 0x7) + 1 - ofs;
1092 NanD_ReadBuf(nand, buf, len256);
1094 NanD_Command(nand, NAND_CMD_READOOB);
1095 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff));
1098 NanD_ReadBuf(nand, &buf[len256], len - len256);
1101 /* Reading the full OOB data drops us off of the end of the page,
1102 * causing the flash device to go into busy mode, so we need
1103 * to wait until ready 11.4.1 and Toshiba TC58256FT nands */
1105 ret = NanD_WaitReady(nand, 1);
1106 NAND_DISABLE_CE(nand); /* set pin high */
1112 /* write to the 16 bytes of oob data that correspond to a 512 byte
1113 * page or 2 256-byte pages.
1115 int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,
1116 size_t * retlen, const u_char * buf)
1120 unsigned long nandptr = nand->IO_ADDR;
1123 printf("nand_write_oob(%lx, %d): %2.2X %2.2X %2.2X %2.2X ... %2.2X %2.2X .. %2.2X %2.2X\n",
1124 (long)ofs, len, buf[0], buf[1], buf[2], buf[3],
1125 buf[8], buf[9], buf[14],buf[15]);
1128 NAND_ENABLE_CE(nand); /* set pin low to enable chip */
1130 /* Reset the chip */
1131 NanD_Command(nand, NAND_CMD_RESET);
1133 /* issue the Read2 command to set the pointer to the Spare Data Area. */
1134 NanD_Command(nand, NAND_CMD_READOOB);
1136 NanD_Address(nand, ADDR_COLUMN_PAGE,
1137 ((ofs >> nand->page_shift) << nand->page_shift) +
1138 ((ofs & (nand->oobblock - 1)) >> 1));
1140 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
1143 /* update address for 2M x 8bit devices. OOB starts on the second */
1144 /* page to maintain compatibility with nand_read_ecc. */
1145 if (nand->page256) {
1152 /* issue the Serial Data In command to initial the Page Program process */
1153 NanD_Command(nand, NAND_CMD_SEQIN);
1155 NanD_Address(nand, ADDR_COLUMN_PAGE,
1156 ((ofs >> nand->page_shift) << nand->page_shift) +
1157 ((ofs & (nand->oobblock - 1)) >> 1));
1159 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
1162 /* treat crossing 8-byte OOB data for 2M x 8bit devices */
1163 /* Note: datasheet says it should automaticaly wrap to the */
1164 /* next OOB block, but it didn't work here. mf. */
1165 if (nand->page256 && ofs + len > (ofs | 0x7) + 1) {
1166 len256 = (ofs | 0x7) + 1 - ofs;
1167 for (i = 0; i < len256; i++)
1168 WRITE_NAND(buf[i], nandptr);
1170 NanD_Command(nand, NAND_CMD_PAGEPROG);
1171 NanD_Command(nand, NAND_CMD_STATUS);
1175 ret_val = READ_NAND(nandptr); /* wait till ready */
1176 } while ((ret_val & 0x40) != 0x40);
1179 if (READ_NAND(nandptr) & 1) {
1180 puts ("Error programming oob data\n");
1181 /* There was an error */
1182 NAND_DISABLE_CE(nand); /* set pin high */
1186 NanD_Command(nand, NAND_CMD_SEQIN);
1187 NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff));
1191 for (i = len256; i < len; i += 2) {
1192 WRITE_NAND(buf[i] + (buf[i+1] << 8), nandptr);
1195 for (i = len256; i < len; i++)
1196 WRITE_NAND(buf[i], nandptr);
1199 NanD_Command(nand, NAND_CMD_PAGEPROG);
1200 NanD_Command(nand, NAND_CMD_STATUS);
1204 ret_val = READ_NAND(nandptr); /* wait till ready */
1205 } while ((ret_val & 0x40) != 0x40);
1208 if (READ_NAND(nandptr) & 1) {
1209 puts ("Error programming oob data\n");
1210 /* There was an error */
1211 NAND_DISABLE_CE(nand); /* set pin high */
1216 NAND_DISABLE_CE(nand); /* set pin high */
1222 int nand_legacy_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean)
1224 /* This is defined as a structure so it will work on any system
1225 * using native endian jffs2 (the default).
1227 static struct jffs2_unknown_node clean_marker = {
1228 JFFS2_MAGIC_BITMASK,
1229 JFFS2_NODETYPE_CLEANMARKER,
1230 8 /* 8 bytes in this node */
1232 unsigned long nandptr;
1233 struct Nand *mychip;
1236 if (ofs & (nand->erasesize-1) || len & (nand->erasesize-1)) {
1237 printf ("Offset and size must be sector aligned, erasesize = %d\n",
1238 (int) nand->erasesize);
1242 nandptr = nand->IO_ADDR;
1244 /* Select the NAND device */
1245 #ifdef CONFIG_OMAP1510
1251 NAND_ENABLE_CE(nand); /* set pin low */
1253 /* Check the WP bit */
1254 NanD_Command(nand, NAND_CMD_STATUS);
1255 if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
1256 printf ("nand_write_ecc: Device is write protected!!!\n");
1261 /* Check the WP bit */
1262 NanD_Command(nand, NAND_CMD_STATUS);
1263 if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
1264 printf ("%s: Device is write protected!!!\n", __FUNCTION__);
1269 /* FIXME: Do nand in the background. Use timers or schedule_task() */
1271 /*mychip = &nand->chips[shr(ofs, nand->chipshift)];*/
1272 mychip = &nand->chips[ofs >> nand->chipshift];
1274 /* always check for bad block first, genuine bad blocks
1275 * should _never_ be erased.
1277 if (ALLOW_ERASE_BAD_DEBUG || !check_block(nand, ofs)) {
1278 /* Select the NAND device */
1279 NAND_ENABLE_CE(nand); /* set pin low */
1281 NanD_Command(nand, NAND_CMD_ERASE1);
1282 NanD_Address(nand, ADDR_PAGE, ofs);
1283 NanD_Command(nand, NAND_CMD_ERASE2);
1285 NanD_Command(nand, NAND_CMD_STATUS);
1290 ret_val = READ_NAND(nandptr); /* wait till ready */
1291 } while ((ret_val & 0x40) != 0x40);
1294 if (READ_NAND(nandptr) & 1) {
1295 printf ("%s: Error erasing at 0x%lx\n",
1296 __FUNCTION__, (long)ofs);
1297 /* There was an error */
1302 int n; /* return value not used */
1305 /* clean marker position and size depend
1306 * on the page size, since 256 byte pages
1307 * only have 8 bytes of oob data
1309 if (nand->page256) {
1310 p = NAND_JFFS2_OOB8_FSDAPOS;
1311 l = NAND_JFFS2_OOB8_FSDALEN;
1313 p = NAND_JFFS2_OOB16_FSDAPOS;
1314 l = NAND_JFFS2_OOB16_FSDALEN;
1317 ret = nand_write_oob(nand, ofs + p, l, (size_t *)&n,
1318 (u_char *)&clean_marker);
1319 /* quit here if write failed */
1324 ofs += nand->erasesize;
1325 len -= nand->erasesize;
1329 /* De-select the NAND device */
1330 NAND_DISABLE_CE(nand); /* set pin high */
1331 #ifdef CONFIG_OMAP1510
1342 static inline int nandcheck(unsigned long potential, unsigned long physadr)
1347 unsigned long nand_probe(unsigned long physadr)
1349 struct nand_chip *nand = NULL;
1350 int i = 0, ChipID = 1;
1352 #ifdef CONFIG_MTD_NAND_ECC_JFFS2
1353 oob_config.ecc_pos[0] = NAND_JFFS2_OOB_ECCPOS0;
1354 oob_config.ecc_pos[1] = NAND_JFFS2_OOB_ECCPOS1;
1355 oob_config.ecc_pos[2] = NAND_JFFS2_OOB_ECCPOS2;
1356 oob_config.ecc_pos[3] = NAND_JFFS2_OOB_ECCPOS3;
1357 oob_config.ecc_pos[4] = NAND_JFFS2_OOB_ECCPOS4;
1358 oob_config.ecc_pos[5] = NAND_JFFS2_OOB_ECCPOS5;
1359 oob_config.eccvalid_pos = 4;
1361 oob_config.ecc_pos[0] = NAND_NOOB_ECCPOS0;
1362 oob_config.ecc_pos[1] = NAND_NOOB_ECCPOS1;
1363 oob_config.ecc_pos[2] = NAND_NOOB_ECCPOS2;
1364 oob_config.ecc_pos[3] = NAND_NOOB_ECCPOS3;
1365 oob_config.ecc_pos[4] = NAND_NOOB_ECCPOS4;
1366 oob_config.ecc_pos[5] = NAND_NOOB_ECCPOS5;
1367 oob_config.eccvalid_pos = NAND_NOOB_ECCVPOS;
1369 oob_config.badblock_pos = 5;
1371 for (i=0; i<CFG_MAX_NAND_DEVICE; i++) {
1372 if (nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN) {
1373 nand = &nand_dev_desc[i];
1380 memset((char *)nand, 0, sizeof(struct nand_chip));
1382 nand->IO_ADDR = physadr;
1383 nand->cache_page = -1; /* init the cache page */
1384 NanD_ScanChips(nand);
1386 if (nand->totlen == 0) {
1387 /* no chips found, clean up and quit */
1388 memset((char *)nand, 0, sizeof(struct nand_chip));
1389 nand->ChipID = NAND_ChipID_UNKNOWN;
1393 nand->ChipID = ChipID;
1394 if (curr_device == -1)
1397 nand->data_buf = malloc (nand->oobblock + nand->oobsize);
1398 if (!nand->data_buf) {
1399 puts ("Cannot allocate memory for data structures.\n");
1403 return (nand->totlen);
1406 #ifdef CONFIG_MTD_NAND_ECC
1408 * Pre-calculated 256-way 1 byte column parity
1410 static const u_char nand_ecc_precalc_table[] = {
1411 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a,
1412 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00,
1413 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f,
1414 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
1415 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c,
1416 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
1417 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59,
1418 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
1419 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33,
1420 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
1421 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56,
1422 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
1423 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55,
1424 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
1425 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30,
1426 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
1427 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30,
1428 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
1429 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55,
1430 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
1431 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56,
1432 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
1433 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33,
1434 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
1435 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59,
1436 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
1437 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c,
1438 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
1439 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f,
1440 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
1441 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a,
1442 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00
1447 * Creates non-inverted ECC code from line parity
1449 static void nand_trans_result(u_char reg2, u_char reg3,
1452 u_char a, b, i, tmp1, tmp2;
1454 /* Initialize variables */
1458 /* Calculate first ECC byte */
1459 for (i = 0; i < 4; i++) {
1460 if (reg3 & a) /* LP15,13,11,9 --> ecc_code[0] */
1463 if (reg2 & a) /* LP14,12,10,8 --> ecc_code[0] */
1469 /* Calculate second ECC byte */
1471 for (i = 0; i < 4; i++) {
1472 if (reg3 & a) /* LP7,5,3,1 --> ecc_code[1] */
1475 if (reg2 & a) /* LP6,4,2,0 --> ecc_code[1] */
1481 /* Store two of the ECC bytes */
1487 * Calculate 3 byte ECC code for 256 byte block
1489 static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code)
1491 u_char idx, reg1, reg3;
1494 /* Initialize variables */
1496 ecc_code[0] = ecc_code[1] = ecc_code[2] = 0;
1498 /* Build up column parity */
1499 for(j = 0; j < 256; j++) {
1501 /* Get CP0 - CP5 from table */
1502 idx = nand_ecc_precalc_table[dat[j]];
1505 /* All bit XOR = 1 ? */
1511 /* Create non-inverted ECC code from line parity */
1512 nand_trans_result((reg1 & 0x40) ? ~reg3 : reg3, reg3, ecc_code);
1514 /* Calculate final ECC code */
1515 ecc_code[0] = ~ecc_code[0];
1516 ecc_code[1] = ~ecc_code[1];
1517 ecc_code[2] = ((~reg1) << 2) | 0x03;
1521 * Detect and correct a 1 bit error for 256 byte block
1523 static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc)
1525 u_char a, b, c, d1, d2, d3, add, bit, i;
1527 /* Do error detection */
1528 d1 = calc_ecc[0] ^ read_ecc[0];
1529 d2 = calc_ecc[1] ^ read_ecc[1];
1530 d3 = calc_ecc[2] ^ read_ecc[2];
1532 if ((d1 | d2 | d3) == 0) {
1536 a = (d1 ^ (d1 >> 1)) & 0x55;
1537 b = (d2 ^ (d2 >> 1)) & 0x55;
1538 c = (d3 ^ (d3 >> 1)) & 0x54;
1540 /* Found and will correct single bit error in the data */
1541 if ((a == 0x55) && (b == 0x55) && (c == 0x54)) {
1545 for (i=0; i<4; i++) {
1552 for (i=0; i<4; i++) {
1561 for (i=0; i<3; i++) {
1591 /* ECC Code Error Correction */
1592 read_ecc[0] = calc_ecc[0];
1593 read_ecc[1] = calc_ecc[1];
1594 read_ecc[2] = calc_ecc[2];
1598 /* Uncorrectable Error */
1604 /* Should never happen */
1610 #ifdef CONFIG_JFFS2_NAND
1611 int read_jffs2_nand(size_t start, size_t len,
1612 size_t * retlen, u_char * buf, int nanddev)
1614 return nand_legacy_rw(nand_dev_desc + nanddev, NANDRW_READ | NANDRW_JFFS2,
1615 start, len, retlen, buf);
1617 #endif /* CONFIG_JFFS2_NAND */