2 * Altera 10/100/1000 triple speed ethernet mac driver
4 * Copyright (C) 2008 Altera Corporation.
5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
14 #include <fdt_support.h>
18 #include <asm/cache.h>
19 #include <asm/dma-mapping.h>
21 #include "altera_tse.h"
23 DECLARE_GLOBAL_DATA_PTR;
25 static inline void alt_sgdma_construct_descriptor(
26 struct alt_sgdma_descriptor *desc,
27 struct alt_sgdma_descriptor *next,
33 int write_fixed_or_sop)
38 * Mark the "next" descriptor as "not" owned by hardware. This prevents
39 * The SGDMA controller from continuing to process the chain.
41 next->descriptor_control = next->descriptor_control &
42 ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
44 memset(desc, 0, sizeof(struct alt_sgdma_descriptor));
45 desc->source = virt_to_phys(read_addr);
46 desc->destination = virt_to_phys(write_addr);
47 desc->next = virt_to_phys(next);
48 desc->bytes_to_transfer = length_or_eop;
51 * Set the descriptor control block as follows:
52 * - Set "owned by hardware" bit
53 * - Optionally set "generate EOP" bit
54 * - Optionally set the "read from fixed address" bit
55 * - Optionally set the "write to fixed address bit (which serves
56 * serves as a "generate SOP" control bit in memory-to-stream mode).
57 * - Set the 4-bit atlantic channel, if specified
59 * Note this step is performed after all other descriptor information
60 * has been filled out so that, if the controller already happens to be
61 * pointing at this descriptor, it will not run (via the "owned by
62 * hardware" bit) until all other descriptor has been set up.
64 val = ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
66 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK;
68 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK;
69 if (write_fixed_or_sop)
70 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK;
71 desc->descriptor_control = val;
74 static int alt_sgdma_wait_transfer(struct alt_sgdma_registers *regs)
79 /* Wait for the descriptor (chain) to complete */
82 status = readl(®s->status);
83 if (!(status & ALT_SGDMA_STATUS_BUSY_MSK))
85 if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) {
87 debug("sgdma timeout\n");
93 writel(0, ®s->control);
95 writel(0xff, ®s->status);
100 static int alt_sgdma_start_transfer(struct alt_sgdma_registers *regs,
101 struct alt_sgdma_descriptor *desc)
105 /* Point the controller at the descriptor */
106 writel(virt_to_phys(desc), ®s->next_descriptor_pointer);
109 * Set up SGDMA controller to:
110 * - Disable interrupt generation
111 * - Run once a valid descriptor is written to controller
112 * - Stop on an error with any particular descriptor
114 val = ALT_SGDMA_CONTROL_RUN_MSK | ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK;
115 writel(val, ®s->control);
120 static void tse_adjust_link(struct altera_tse_priv *priv,
121 struct phy_device *phydev)
123 struct alt_tse_mac *mac_dev = priv->mac_dev;
127 debug("%s: No link.\n", phydev->dev->name);
131 refvar = readl(&mac_dev->command_config);
134 refvar |= ALTERA_TSE_CMD_HD_ENA_MSK;
136 refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK;
138 switch (phydev->speed) {
140 refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK;
141 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
144 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
145 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
148 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
149 refvar |= ALTERA_TSE_CMD_ENA_10_MSK;
152 writel(refvar, &mac_dev->command_config);
155 static int altera_tse_send_sgdma(struct udevice *dev, void *packet, int length)
157 struct altera_tse_priv *priv = dev_get_priv(dev);
158 struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
160 alt_sgdma_construct_descriptor(
163 packet, /* read addr */
164 NULL, /* write addr */
165 length, /* length or EOP ,will change for each tx */
168 1 /* write fixed or sop */
171 /* send the packet */
172 alt_sgdma_start_transfer(priv->sgdma_tx, tx_desc);
173 alt_sgdma_wait_transfer(priv->sgdma_tx);
174 debug("sent %d bytes\n", tx_desc->actual_bytes_transferred);
176 return tx_desc->actual_bytes_transferred;
179 static int altera_tse_recv_sgdma(struct udevice *dev, int flags,
182 struct altera_tse_priv *priv = dev_get_priv(dev);
183 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
186 if (rx_desc->descriptor_status &
187 ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) {
188 alt_sgdma_wait_transfer(priv->sgdma_rx);
189 packet_length = rx_desc->actual_bytes_transferred;
190 debug("recv %d bytes\n", packet_length);
191 *packetp = priv->rx_buf;
193 return packet_length;
199 static int altera_tse_free_pkt_sgdma(struct udevice *dev, uchar *packet,
202 struct altera_tse_priv *priv = dev_get_priv(dev);
203 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
205 alt_sgdma_construct_descriptor(
208 NULL, /* read addr */
209 priv->rx_buf, /* write addr */
210 0, /* length or EOP */
213 0 /* write fixed or sop */
216 /* setup the sgdma */
217 alt_sgdma_start_transfer(priv->sgdma_rx, rx_desc);
218 debug("recv setup\n");
223 static void altera_tse_stop_mac(struct altera_tse_priv *priv)
225 struct alt_tse_mac *mac_dev = priv->mac_dev;
230 writel(ALTERA_TSE_CMD_SW_RESET_MSK, &mac_dev->command_config);
231 ctime = get_timer(0);
233 status = readl(&mac_dev->command_config);
234 if (!(status & ALTERA_TSE_CMD_SW_RESET_MSK))
236 if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
237 debug("Reset mac timeout\n");
243 static void altera_tse_stop_sgdma(struct udevice *dev)
245 struct altera_tse_priv *priv = dev_get_priv(dev);
246 struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx;
247 struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
248 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
251 /* clear rx desc & wait for sgdma to complete */
252 rx_desc->descriptor_control = 0;
253 writel(0, &rx_sgdma->control);
254 ret = alt_sgdma_wait_transfer(rx_sgdma);
255 if (ret == -ETIMEDOUT)
256 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
259 writel(0, &tx_sgdma->control);
260 ret = alt_sgdma_wait_transfer(tx_sgdma);
261 if (ret == -ETIMEDOUT)
262 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
266 static int tse_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
268 struct altera_tse_priv *priv = bus->priv;
269 struct alt_tse_mac *mac_dev = priv->mac_dev;
272 /* set mdio address */
273 writel(addr, &mac_dev->mdio_phy1_addr);
275 value = readl(&mac_dev->mdio_phy1[reg]);
277 return value & 0xffff;
280 static int tse_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
283 struct altera_tse_priv *priv = bus->priv;
284 struct alt_tse_mac *mac_dev = priv->mac_dev;
286 /* set mdio address */
287 writel(addr, &mac_dev->mdio_phy1_addr);
289 writel(val, &mac_dev->mdio_phy1[reg]);
294 static int tse_mdio_init(const char *name, struct altera_tse_priv *priv)
296 struct mii_dev *bus = mdio_alloc();
299 printf("Failed to allocate MDIO bus\n");
303 bus->read = tse_mdio_read;
304 bus->write = tse_mdio_write;
305 snprintf(bus->name, sizeof(bus->name), name);
307 bus->priv = (void *)priv;
309 return mdio_register(bus);
312 static int tse_phy_init(struct altera_tse_priv *priv, void *dev)
314 struct phy_device *phydev;
315 unsigned int mask = 0xffffffff;
318 mask = 1 << priv->phyaddr;
320 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
324 phy_connect_dev(phydev, dev);
326 phydev->supported &= PHY_GBIT_FEATURES;
327 phydev->advertising = phydev->supported;
329 priv->phydev = phydev;
335 static int altera_tse_write_hwaddr(struct udevice *dev)
337 struct altera_tse_priv *priv = dev_get_priv(dev);
338 struct alt_tse_mac *mac_dev = priv->mac_dev;
339 struct eth_pdata *pdata = dev_get_platdata(dev);
340 u8 *hwaddr = pdata->enetaddr;
343 mac_lo = (hwaddr[3] << 24) | (hwaddr[2] << 16) |
344 (hwaddr[1] << 8) | hwaddr[0];
345 mac_hi = (hwaddr[5] << 8) | hwaddr[4];
346 debug("Set MAC address to 0x%04x%08x\n", mac_hi, mac_lo);
348 writel(mac_lo, &mac_dev->mac_addr_0);
349 writel(mac_hi, &mac_dev->mac_addr_1);
350 writel(mac_lo, &mac_dev->supp_mac_addr_0_0);
351 writel(mac_hi, &mac_dev->supp_mac_addr_0_1);
352 writel(mac_lo, &mac_dev->supp_mac_addr_1_0);
353 writel(mac_hi, &mac_dev->supp_mac_addr_1_1);
354 writel(mac_lo, &mac_dev->supp_mac_addr_2_0);
355 writel(mac_hi, &mac_dev->supp_mac_addr_2_1);
356 writel(mac_lo, &mac_dev->supp_mac_addr_3_0);
357 writel(mac_hi, &mac_dev->supp_mac_addr_3_1);
362 static int altera_tse_send(struct udevice *dev, void *packet, int length)
364 struct altera_tse_priv *priv = dev_get_priv(dev);
365 unsigned long tx_buf = (unsigned long)packet;
367 flush_dcache_range(tx_buf, tx_buf + length);
369 return priv->ops->send(dev, packet, length);
372 static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp)
374 struct altera_tse_priv *priv = dev_get_priv(dev);
376 return priv->ops->recv(dev, flags, packetp);
379 static int altera_tse_free_pkt(struct udevice *dev, uchar *packet,
382 struct altera_tse_priv *priv = dev_get_priv(dev);
383 unsigned long rx_buf = (unsigned long)priv->rx_buf;
385 invalidate_dcache_range(rx_buf, rx_buf + PKTSIZE_ALIGN);
387 return priv->ops->free_pkt(dev, packet, length);
390 static void altera_tse_stop(struct udevice *dev)
392 struct altera_tse_priv *priv = dev_get_priv(dev);
394 priv->ops->stop(dev);
395 altera_tse_stop_mac(priv);
398 static int altera_tse_start(struct udevice *dev)
400 struct altera_tse_priv *priv = dev_get_priv(dev);
401 struct alt_tse_mac *mac_dev = priv->mac_dev;
405 /* need to create sgdma */
406 debug("Configuring rx desc\n");
407 altera_tse_free_pkt(dev, priv->rx_buf, PKTSIZE_ALIGN);
409 debug("Configuring TSE Mac\n");
410 /* Initialize MAC registers */
411 writel(PKTSIZE_ALIGN, &mac_dev->max_frame_length);
412 writel(priv->rx_fifo_depth - 16, &mac_dev->rx_sel_empty_threshold);
413 writel(0, &mac_dev->rx_sel_full_threshold);
414 writel(priv->tx_fifo_depth - 16, &mac_dev->tx_sel_empty_threshold);
415 writel(0, &mac_dev->tx_sel_full_threshold);
416 writel(8, &mac_dev->rx_almost_empty_threshold);
417 writel(8, &mac_dev->rx_almost_full_threshold);
418 writel(8, &mac_dev->tx_almost_empty_threshold);
419 writel(3, &mac_dev->tx_almost_full_threshold);
422 writel(0, &mac_dev->rx_cmd_stat);
423 writel(0, &mac_dev->tx_cmd_stat);
426 val = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK;
427 writel(val, &mac_dev->command_config);
429 /* Start up the PHY */
430 ret = phy_startup(priv->phydev);
432 debug("Could not initialize PHY %s\n",
433 priv->phydev->dev->name);
437 tse_adjust_link(priv, priv->phydev);
439 if (!priv->phydev->link)
445 static const struct tse_ops tse_sgdma_ops = {
446 .send = altera_tse_send_sgdma,
447 .recv = altera_tse_recv_sgdma,
448 .free_pkt = altera_tse_free_pkt_sgdma,
449 .stop = altera_tse_stop_sgdma,
452 static int altera_tse_probe(struct udevice *dev)
454 struct eth_pdata *pdata = dev_get_platdata(dev);
455 struct altera_tse_priv *priv = dev_get_priv(dev);
456 void *blob = (void *)gd->fdt_blob;
457 int node = dev->of_offset;
458 const char *list, *end;
460 void *base, *desc_mem = NULL;
461 unsigned long addr, size;
462 int parent, addrc, sizec;
466 priv->dma_type = dev_get_driver_data(dev);
467 if (priv->dma_type == ALT_SGDMA)
468 priv->ops = &tse_sgdma_ops;
470 * decode regs. there are multiple reg tuples, and they need to
471 * match with reg-names.
473 parent = fdt_parent_offset(blob, node);
474 of_bus_default_count_cells(blob, parent, &addrc, &sizec);
475 list = fdt_getprop(blob, node, "reg-names", &len);
479 cell = fdt_getprop(blob, node, "reg", &len);
484 addr = fdt_translate_address((void *)blob,
486 size = fdt_addr_to_cpu(cell[idx + addrc]);
487 base = ioremap(addr, size);
489 if (strcmp(list, "control_port") == 0)
490 priv->mac_dev = base;
491 else if (strcmp(list, "rx_csr") == 0)
492 priv->sgdma_rx = base;
493 else if (strcmp(list, "tx_csr") == 0)
494 priv->sgdma_tx = base;
495 else if (strcmp(list, "s1") == 0)
497 idx += addrc + sizec;
500 /* decode fifo depth */
501 priv->rx_fifo_depth = fdtdec_get_int(blob, node,
503 priv->tx_fifo_depth = fdtdec_get_int(blob, node,
506 addr = fdtdec_get_int(blob, node,
508 addr = fdt_node_offset_by_phandle(blob, addr);
509 priv->phyaddr = fdtdec_get_int(blob, addr,
512 if (priv->dma_type == ALT_SGDMA) {
513 len = sizeof(struct alt_sgdma_descriptor) * 4;
515 desc_mem = dma_alloc_coherent(len, &addr);
519 memset(desc_mem, 0, len);
520 priv->tx_desc = desc_mem;
521 priv->rx_desc = priv->tx_desc +
522 2 * sizeof(struct alt_sgdma_descriptor);
524 /* allocate recv packet buffer */
525 priv->rx_buf = malloc_cache_aligned(PKTSIZE_ALIGN);
529 /* stop controller */
530 debug("Reset TSE & SGDMAs\n");
531 altera_tse_stop(dev);
534 priv->interface = pdata->phy_interface;
535 tse_mdio_init(dev->name, priv);
536 priv->bus = miiphy_get_dev_by_name(dev->name);
538 ret = tse_phy_init(priv, dev);
543 static int altera_tse_ofdata_to_platdata(struct udevice *dev)
545 struct eth_pdata *pdata = dev_get_platdata(dev);
546 const char *phy_mode;
548 pdata->phy_interface = -1;
549 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
551 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
552 if (pdata->phy_interface == -1) {
553 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
560 static const struct eth_ops altera_tse_ops = {
561 .start = altera_tse_start,
562 .send = altera_tse_send,
563 .recv = altera_tse_recv,
564 .free_pkt = altera_tse_free_pkt,
565 .stop = altera_tse_stop,
566 .write_hwaddr = altera_tse_write_hwaddr,
569 static const struct udevice_id altera_tse_ids[] = {
570 { .compatible = "altr,tse-1.0", .data = ALT_SGDMA },
574 U_BOOT_DRIVER(altera_tse) = {
575 .name = "altera_tse",
577 .of_match = altera_tse_ids,
578 .ops = &altera_tse_ops,
579 .ofdata_to_platdata = altera_tse_ofdata_to_platdata,
580 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
581 .priv_auto_alloc_size = sizeof(struct altera_tse_priv),
582 .probe = altera_tse_probe,