2 * Driver for Blackfin On-Chip MAC device
4 * Copyright (c) 2005-2008 Analog Device, Inc.
6 * Licensed under the GPL-2 or later.
16 #include <linux/mii.h>
18 #include <asm/blackfin.h>
19 #include <asm/mach-common/bits/dma.h>
20 #include <asm/mach-common/bits/emac.h>
21 #include <asm/mach-common/bits/pll.h>
25 #ifndef CONFIG_PHY_ADDR
26 # define CONFIG_PHY_ADDR 1
28 #ifndef CONFIG_PHY_CLOCK_FREQ
29 # define CONFIG_PHY_CLOCK_FREQ 2500000
39 #define DEBUGF(fmt, args...) printf(fmt, ##args)
41 #define DEBUGF(fmt, args...)
44 #define RXBUF_BASE_ADDR 0xFF900000
45 #define TXBUF_BASE_ADDR 0xFF800000
48 #define TOUT_LOOP 1000000
50 ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
51 ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
52 static u16 txIdx; /* index of the current RX buffer */
53 static u16 rxIdx; /* index of the current TX buffer */
55 /* DMAx_CONFIG values at DMA Restart */
56 const ADI_DMA_CONFIG_REG rxdmacfg = {
57 .b_DMA_EN = 1, /* enabled */
58 .b_WNR = 1, /* write to memory */
59 .b_WDSIZE = 2, /* wordsize is 32 bits */
63 .b_DI_EN = 0, /* no interrupt */
64 .b_NDSIZE = 5, /* 5 half words is desc size */
65 .b_FLOW = 7 /* large desc flow */
68 const ADI_DMA_CONFIG_REG txdmacfg = {
69 .b_DMA_EN = 1, /* enabled */
70 .b_WNR = 0, /* read from memory */
71 .b_WDSIZE = 2, /* wordsize is 32 bits */
75 .b_DI_EN = 0, /* no interrupt */
76 .b_NDSIZE = 5, /* 5 half words is desc size */
77 .b_FLOW = 7 /* large desc flow */
80 static int bfin_miiphy_wait(void)
82 /* poll the STABUSY bit */
83 while (bfin_read_EMAC_STAADD() & STABUSY)
88 static int bfin_miiphy_read(char *devname, uchar addr, uchar reg, ushort *val)
90 if (bfin_miiphy_wait())
92 bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STABUSY);
93 if (bfin_miiphy_wait())
95 *val = bfin_read_EMAC_STADAT();
99 static int bfin_miiphy_write(char *devname, uchar addr, uchar reg, ushort val)
101 if (bfin_miiphy_wait())
103 bfin_write_EMAC_STADAT(val);
104 bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STAOP | STABUSY);
108 int bfin_EMAC_initialize(bd_t *bis)
110 struct eth_device *dev;
111 dev = malloc(sizeof(*dev));
115 memset(dev, 0, sizeof(*dev));
116 sprintf(dev->name, "Blackfin EMAC");
120 dev->init = bfin_EMAC_init;
121 dev->halt = bfin_EMAC_halt;
122 dev->send = bfin_EMAC_send;
123 dev->recv = bfin_EMAC_recv;
127 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
128 miiphy_register(dev->name, bfin_miiphy_read, bfin_miiphy_write);
134 static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
140 buf = (unsigned int *)packet;
143 printf("Ethernet: bad packet size: %d\n", length);
147 if ((*pDMA2_IRQ_STATUS & DMA_ERR) != 0) {
148 printf("Ethernet: tx DMA error\n");
152 for (i = 0; (*pDMA2_IRQ_STATUS & DMA_RUN) != 0; i++) {
154 puts("Ethernet: tx time out\n");
158 txbuf[txIdx]->FrmData->NoBytes = length;
159 memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
160 txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
161 *pDMA2_NEXT_DESC_PTR = &txbuf[txIdx]->Dma[0];
162 *pDMA2_CONFIG = *(u16 *) (void *)(&txdmacfg);
165 for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
167 puts("Ethernet: tx error\n");
171 result = txbuf[txIdx]->StatusWord;
172 txbuf[txIdx]->StatusWord = 0;
173 if ((txIdx + 1) >= TX_BUF_CNT)
178 DEBUGF("BFIN EMAC send: length = %d\n", length);
182 static int bfin_EMAC_recv(struct eth_device *dev)
187 if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
191 if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
192 printf("Ethernet: rx dma overrun\n");
195 if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
196 printf("Ethernet: rx error\n");
199 length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
201 printf("Ethernet: bad frame\n");
204 NetRxPackets[rxIdx] =
205 (volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest);
206 NetReceive(NetRxPackets[rxIdx], length - 4);
207 *pDMA1_IRQ_STATUS |= DMA_DONE | DMA_ERR;
208 rxbuf[rxIdx]->StatusWord = 0x00000000;
209 if ((rxIdx + 1) >= PKTBUFSRX)
218 /**************************************************************
220 * Ethernet Initialization Routine
222 *************************************************************/
224 /* MDC = SCLK / MDC_freq / 2 - 1 */
225 #define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)
227 static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
232 /* Enable PHY output */
233 *pVR_CTL |= CLKBUFOE;
235 /* Set all the pins to peripheral mode */
236 #ifdef CONFIG_BFIN_MAC_RMII
238 # if defined(__ADSPBF51x__)
239 *pPORTF_MUX = (*pPORTF_MUX & \
240 ~(PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \
241 PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1;
242 *pPORTF_FER |= PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15;
243 *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1;
244 *pPORTG_FER |= PG0 | PG1 | PG2;
245 # elif defined(__ADSPBF52x__)
246 *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2;
247 *pPORTG_FER |= PG14 | PG15;
248 *pPORTH_MUX = (*pPORTH_MUX & ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK)) | \
249 PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2;
250 *pPORTH_FER |= PH0 | PH1 | PH2 | PH3 | PH4 | PH5 | PH6 | PH7 | PH8;
252 *pPORTH_FER |= PH0 | PH1 | PH4 | PH5 | PH6 | PH8 | PH9 | PH14 | PH15;
255 /* grab MII & RMII pins */
256 # if defined(__ADSPBF51x__)
257 *pPORTF_MUX = (*pPORTF_MUX & \
258 ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \
259 PORT_x_MUX_0_FUNC_1 | PORT_x_MUX_1_FUNC_1 | PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1;
260 *pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15;
261 *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1;
262 *pPORTG_FER |= PG0 | PG1 | PG2;
263 # elif defined(__ADSPBF52x__)
264 *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2;
265 *pPORTG_FER |= PG14 | PG15;
266 *pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2 | PORT_x_MUX_2_FUNC_2;
267 *pPORTH_FER = -1; /* all pins */
269 *pPORTH_FER = -1; /* all pins */
273 /* Odd word alignment for Receive Frame DMA word */
274 /* Configure checksum support and rcve frame word alignment */
275 bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ)));
277 /* turn on auto-negotiation and wait for link to come up */
278 bfin_miiphy_write(dev->name, CONFIG_PHY_ADDR, MII_BMCR, BMCR_ANENABLE);
282 if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_BMSR, &phydat))
284 if (phydat & BMSR_LSTATUS)
287 printf("%s: link down, check cable\n", dev->name);
293 /* see what kind of link we have */
294 if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_LPA, &phydat))
296 if (phydat & LPA_DUPLEX)
301 bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
303 /* Initialize the TX DMA channel registers */
309 /* Initialize the RX DMA channel registers */
318 static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd)
323 DEBUGF("Eth_init: ......\n");
328 /* Initialize System Register */
329 if (bfin_miiphy_init(dev, &dat) < 0)
332 /* Initialize EMAC address */
333 bfin_EMAC_setup_addr(bd);
335 /* Initialize TX and RX buffer */
336 for (i = 0; i < PKTBUFSRX; i++) {
337 rxbuf[i] = SetupRxBuffer(i);
339 rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
341 if (i == (PKTBUFSRX - 1))
342 rxbuf[i]->Dma[1].NEXT_DESC_PTR =
346 for (i = 0; i < TX_BUF_CNT; i++) {
347 txbuf[i] = SetupTxBuffer(i);
349 txbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
351 if (i == (TX_BUF_CNT - 1))
352 txbuf[i]->Dma[1].NEXT_DESC_PTR =
358 *pDMA1_NEXT_DESC_PTR = &rxbuf[0]->Dma[0];
359 *pDMA1_CONFIG = *((u16 *) (void *)&rxbuf[0]->Dma[0].CONFIG);
364 /* We enable only RX here */
365 /* ASTP : Enable Automatic Pad Stripping
366 PR : Promiscuous Mode for test
367 PSF : Receive frames with total length less than 64 bytes.
368 FDMODE : Full Duplex Mode
369 LB : Internal Loopback for test
370 RE : Receiver Enable */
372 opmode = ASTP | FDMODE | PSF;
376 #ifdef CONFIG_BFIN_MAC_RMII
379 /* Turn on the EMAC */
380 *pEMAC_OPMODE = opmode;
384 static void bfin_EMAC_halt(struct eth_device *dev)
386 DEBUGF("Eth_halt: ......\n");
387 /* Turn off the EMAC */
388 *pEMAC_OPMODE = 0x00000000;
389 /* Turn off the EMAC RX DMA */
390 *pDMA1_CONFIG = 0x0000;
391 *pDMA2_CONFIG = 0x0000;
395 void bfin_EMAC_setup_addr(bd_t *bd)
399 bd->bi_enetaddr[1] << 8 |
400 bd->bi_enetaddr[2] << 16 |
401 bd->bi_enetaddr[3] << 24;
404 bd->bi_enetaddr[5] << 8;
407 ADI_ETHER_BUFFER *SetupRxBuffer(int no)
409 ADI_ETHER_FRAME_BUFFER *frmbuf;
410 ADI_ETHER_BUFFER *buf;
411 int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
412 int total_size = nobytes_buffer + RECV_BUFSIZE;
414 buf = (ADI_ETHER_BUFFER *) (RXBUF_BASE_ADDR + no * total_size);
416 (ADI_ETHER_FRAME_BUFFER *) (RXBUF_BASE_ADDR + no * total_size +
419 memset(buf, 0x00, nobytes_buffer);
420 buf->FrmData = frmbuf;
421 memset(frmbuf, 0xfe, RECV_BUFSIZE);
423 /* set up first desc to point to receive frame buffer */
424 buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
425 buf->Dma[0].START_ADDR = (u32) buf->FrmData;
426 buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
427 buf->Dma[0].CONFIG.b_WNR = 1; /* Write to memory */
428 buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
429 buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
430 buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
432 /* set up second desc to point to status word */
433 buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
434 buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
435 buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
436 buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
437 buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
438 buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
439 buf->Dma[1].CONFIG.b_NDSIZE = 5; /* must be 0 when FLOW is 0 */
440 buf->Dma[1].CONFIG.b_FLOW = 7; /* stop */
445 ADI_ETHER_BUFFER *SetupTxBuffer(int no)
447 ADI_ETHER_FRAME_BUFFER *frmbuf;
448 ADI_ETHER_BUFFER *buf;
449 int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
450 int total_size = nobytes_buffer + RECV_BUFSIZE;
452 buf = (ADI_ETHER_BUFFER *) (TXBUF_BASE_ADDR + no * total_size);
454 (ADI_ETHER_FRAME_BUFFER *) (TXBUF_BASE_ADDR + no * total_size +
457 memset(buf, 0x00, nobytes_buffer);
458 buf->FrmData = frmbuf;
459 memset(frmbuf, 0x00, RECV_BUFSIZE);
461 /* set up first desc to point to receive frame buffer */
462 buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
463 buf->Dma[0].START_ADDR = (u32) buf->FrmData;
464 buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
465 buf->Dma[0].CONFIG.b_WNR = 0; /* Read to memory */
466 buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
467 buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
468 buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
470 /* set up second desc to point to status word */
471 buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
472 buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
473 buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
474 buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
475 buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
476 buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
477 buf->Dma[1].CONFIG.b_NDSIZE = 0; /* must be 0 when FLOW is 0 */
478 buf->Dma[1].CONFIG.b_FLOW = 0; /* stop */
483 #if defined(CONFIG_POST) && defined(CONFIG_SYS_POST_ETHER)
484 int ether_post_test(int flags)
490 printf("\n--------");
491 bfin_EMAC_init(NULL, NULL);
492 /* construct the package */
493 buf[0] = buf[6] = (unsigned char)(*pEMAC_ADDRLO & 0xFF);
494 buf[1] = buf[7] = (unsigned char)((*pEMAC_ADDRLO & 0xFF00) >> 8);
495 buf[2] = buf[8] = (unsigned char)((*pEMAC_ADDRLO & 0xFF0000) >> 16);
496 buf[3] = buf[9] = (unsigned char)((*pEMAC_ADDRLO & 0xFF000000) >> 24);
497 buf[4] = buf[10] = (unsigned char)(*pEMAC_ADDRHI & 0xFF);
498 buf[5] = buf[11] = (unsigned char)((*pEMAC_ADDRHI & 0xFF00) >> 8);
499 buf[12] = 0x08; /* Type: ARP */
501 buf[14] = 0x00; /* Hardware type: Ethernet */
503 buf[16] = 0x08; /* Protocal type: IP */
505 buf[18] = 0x06; /* Hardware size */
506 buf[19] = 0x04; /* Protocol size */
507 buf[20] = 0x00; /* Opcode: request */
510 for (i = 0; i < 42; i++)
512 printf("--------Send 64 bytes......\n");
513 bfin_EMAC_send(NULL, (volatile void *)buf, 64);
514 for (i = 0; i < 100; i++) {
516 if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
522 printf("--------EMAC can't receive any data\n");
526 length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
527 for (i = 0; i < length; i++) {
528 if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
529 printf("--------EMAC receive error data!\n");
534 printf("--------receive %d bytes, matched\n", length);
535 bfin_EMAC_halt(NULL);