2 dm9000.c: Version 1.2 12/15/2003
4 A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
5 Copyright (C) 1997 Sten Wang
7 This program is free software; you can redistribute it and/or
8 modify it under the terms of the GNU General Public License
9 as published by the Free Software Foundation; either version 2
10 of the License, or (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
19 V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
20 06/22/2001 Support DM9801 progrmming
21 E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
22 E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
23 R17 = (R17 & 0xfff0) | NF + 3
24 E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
25 R17 = (R17 & 0xfff0) | NF
27 v1.00 modify by simon 2001.9.5
28 change for kernel 2.4.x
30 v1.1 11/09/2001 fix force mode bug
32 v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
34 Added tx/rx 32 bit mode.
35 Cleaned up for kernel merge.
37 --------------------------------------
39 12/15/2003 Initial port to u-boot by
40 Sascha Hauer <saschahauer@web.de>
42 06/03/2008 Remy Bohmer <linux@bohmer.net>
43 - Added autodetect of databus width.
44 - Made debug code compile again.
45 - Adapt eth_send such that it matches the DM9000*
46 application notes. Needed to make it work properly
48 These changes are tested with DM9000{A,EP,E} together
49 with a 200MHz Atmel AT91SAM92161 core
51 TODO: Homerun NIC and longrun NIC are not functional, only internal at the
60 #ifdef CONFIG_DRIVER_DM9000
64 /* Board/System/Debug information/definition ---------------- */
66 #define DM9801_NOISE_FLOOR 0x08
67 #define DM9802_NOISE_FLOOR 0x05
69 /* #define CONFIG_DM9000_DEBUG */
71 #ifdef CONFIG_DM9000_DEBUG
72 #define DM9000_DBG(fmt,args...) printf(fmt, ##args)
73 #define DM9000_DMP_PACKET(func,packet,length) \
76 printf(func ": length: %d\n", length); \
77 for (i = 0; i < length; i++) { \
79 printf("\n%s: %02x: ", func, i); \
80 printf("%02x ", ((unsigned char *) packet)[i]); \
84 #define DM9000_DBG(fmt,args...)
85 #define DM9000_DMP_PACKET(func,packet,length)
88 enum DM9000_PHY_mode { DM9000_10MHD = 0, DM9000_100MHD =
89 1, DM9000_10MFD = 4, DM9000_100MFD = 5, DM9000_AUTO =
90 8, DM9000_1M_HPNA = 0x10
92 enum DM9000_NIC_TYPE { FASTETHER_NIC = 0, HOMERUN_NIC = 1, LONGRUN_NIC = 2
95 /* Structure/enum declaration ------------------------------- */
96 typedef struct board_info {
97 u32 runt_length_counter; /* counter: RX length < 64byte */
98 u32 long_length_counter; /* counter: RX length > 1514byte */
99 u32 reset_counter; /* counter: RESET */
100 u32 reset_tx_timeout; /* RESET caused by TX Timeout */
101 u32 reset_rx_status; /* RESET caused by RX Statsus wrong */
103 u16 queue_start_addr;
106 u8 device_wait_reset; /* device state */
107 u8 nic_type; /* NIC type */
108 unsigned char srom[128];
109 void (*outblk)(void *data_ptr, int count);
110 void (*inblk)(void *data_ptr, int count);
111 void (*rx_status)(u16 *RxStatus, u16 *RxLen);
113 static board_info_t dm9000_info;
115 /* For module input parameter */
116 static int media_mode = DM9000_AUTO;
117 static u8 nfloor = 0;
119 /* function declaration ------------------------------------- */
120 int eth_init(bd_t * bd);
121 int eth_send(volatile void *, int);
124 static int dm9000_probe(void);
125 static u16 phy_read(int);
126 static void phy_write(int, u16);
127 u16 read_srom_word(int);
128 static u8 DM9000_ior(int);
129 static void DM9000_iow(int reg, u8 value);
131 /* DM9000 network board routine ---------------------------- */
133 #define DM9000_outb(d,r) ( *(volatile u8 *)r = d )
134 #define DM9000_outw(d,r) ( *(volatile u16 *)r = d )
135 #define DM9000_outl(d,r) ( *(volatile u32 *)r = d )
136 #define DM9000_inb(r) (*(volatile u8 *)r)
137 #define DM9000_inw(r) (*(volatile u16 *)r)
138 #define DM9000_inl(r) (*(volatile u32 *)r)
140 #ifdef CONFIG_DM9000_DEBUG
145 DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0));
146 DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1));
147 DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2));
148 DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3));
149 DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4));
150 DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5));
151 DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6));
152 DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(DM9000_ISR));
157 static void dm9000_outblk_8bit(void *data_ptr, int count)
160 for (i = 0; i < count; i++)
161 DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA);
164 static void dm9000_outblk_16bit(void *data_ptr, int count)
167 u32 tmplen = (count + 1) / 2;
169 for (i = 0; i < tmplen; i++)
170 DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);
172 static void dm9000_outblk_32bit(void *data_ptr, int count)
175 u32 tmplen = (count + 3) / 4;
177 for (i = 0; i < tmplen; i++)
178 DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);
181 static void dm9000_inblk_8bit(void *data_ptr, int count)
184 for (i = 0; i < count; i++)
185 ((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA);
188 static void dm9000_inblk_16bit(void *data_ptr, int count)
191 u32 tmplen = (count + 1) / 2;
193 for (i = 0; i < tmplen; i++)
194 ((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA);
196 static void dm9000_inblk_32bit(void *data_ptr, int count)
199 u32 tmplen = (count + 3) / 4;
201 for (i = 0; i < tmplen; i++)
202 ((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA);
205 static void dm9000_rx_status_32bit(u16 *RxStatus, u16 *RxLen)
207 u32 tmpdata = DM9000_inl(DM9000_DATA);
209 DM9000_outb(DM9000_MRCMD, DM9000_IO);
212 *RxLen = tmpdata >> 16;
215 static void dm9000_rx_status_16bit(u16 *RxStatus, u16 *RxLen)
217 DM9000_outb(DM9000_MRCMD, DM9000_IO);
219 *RxStatus = DM9000_inw(DM9000_DATA);
220 *RxLen = DM9000_inw(DM9000_DATA);
223 static void dm9000_rx_status_8bit(u16 *RxStatus, u16 *RxLen)
225 DM9000_outb(DM9000_MRCMD, DM9000_IO);
227 *RxStatus = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8);
228 *RxLen = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8);
232 Search DM9000 board, allocate space and register it
238 id_val = DM9000_ior(DM9000_VIDL);
239 id_val |= DM9000_ior(DM9000_VIDH) << 8;
240 id_val |= DM9000_ior(DM9000_PIDL) << 16;
241 id_val |= DM9000_ior(DM9000_PIDH) << 24;
242 if (id_val == DM9000_ID) {
243 printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
247 printf("dm9000 not found at 0x%08x id: 0x%08x\n",
248 CONFIG_DM9000_BASE, id_val);
253 /* Set PHY operationg mode
258 u16 phy_reg4 = 0x01e1, phy_reg0 = 0x1000;
259 if (!(media_mode & DM9000_AUTO)) {
260 switch (media_mode) {
278 phy_write(4, phy_reg4); /* Set PHY media mode */
279 phy_write(0, phy_reg0); /* Tmp */
281 DM9000_iow(DM9000_GPCR, 0x01); /* Let GPIO0 output */
282 DM9000_iow(DM9000_GPR, 0x00); /* Enable PHY */
289 program_dm9801(u16 HPNA_rev)
291 __u16 reg16, reg17, reg24, reg25;
293 nfloor = DM9801_NOISE_FLOOR;
294 reg16 = phy_read(16);
295 reg17 = phy_read(17);
296 reg24 = phy_read(24);
297 reg25 = phy_read(25);
299 case 0xb900: /* DM9801 E3 */
301 reg25 = ((reg24 + nfloor) & 0x00ff) | 0xf000;
303 case 0xb901: /* DM9801 E4 */
304 reg25 = ((reg24 + nfloor) & 0x00ff) | 0xc200;
305 reg17 = (reg17 & 0xfff0) + nfloor + 3;
307 case 0xb902: /* DM9801 E5 */
308 case 0xb903: /* DM9801 E6 */
311 reg25 = ((reg24 + nfloor - 3) & 0x00ff) | 0xc200;
312 reg17 = (reg17 & 0xfff0) + nfloor;
314 phy_write(16, reg16);
315 phy_write(17, reg17);
316 phy_write(25, reg25);
327 nfloor = DM9802_NOISE_FLOOR;
328 reg25 = phy_read(25);
329 reg25 = (reg25 & 0xff00) + nfloor;
330 phy_write(25, reg25);
338 struct board_info *db = &dm9000_info;
340 DM9000_iow(DM9000_NCR, NCR_EXT_PHY);
341 phy_reg3 = phy_read(3);
342 switch (phy_reg3 & 0xfff0) {
344 if (phy_read(31) == 0x4404) {
345 db->nic_type = HOMERUN_NIC;
346 program_dm9801(phy_reg3);
347 DM9000_DBG("found homerun NIC\n");
349 db->nic_type = LONGRUN_NIC;
350 DM9000_DBG("found longrun NIC\n");
355 db->nic_type = FASTETHER_NIC;
358 DM9000_iow(DM9000_NCR, 0);
361 /* General Purpose dm9000 reset routine */
365 DM9000_DBG("resetting\n");
366 DM9000_iow(DM9000_NCR, NCR_RST);
367 udelay(1000); /* delay 1ms */
370 /* Initilize dm9000 board
377 struct board_info *db = &dm9000_info;
379 DM9000_DBG("eth_init()\n");
385 /* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */
386 io_mode = DM9000_ior(DM9000_ISR) >> 6;
389 case 0x0: /* 16-bit mode */
390 printf("DM9000: running in 16 bit mode\n");
391 db->outblk = dm9000_outblk_16bit;
392 db->inblk = dm9000_inblk_16bit;
393 db->rx_status = dm9000_rx_status_16bit;
395 case 0x01: /* 32-bit mode */
396 printf("DM9000: running in 32 bit mode\n");
397 db->outblk = dm9000_outblk_32bit;
398 db->inblk = dm9000_inblk_32bit;
399 db->rx_status = dm9000_rx_status_32bit;
401 case 0x02: /* 8 bit mode */
402 printf("DM9000: running in 8 bit mode\n");
403 db->outblk = dm9000_outblk_8bit;
404 db->inblk = dm9000_inblk_8bit;
405 db->rx_status = dm9000_rx_status_8bit;
408 /* Assume 8 bit mode, will probably not work anyway */
409 printf("DM9000: Undefined IO-mode:0x%x\n", io_mode);
410 db->outblk = dm9000_outblk_8bit;
411 db->inblk = dm9000_inblk_8bit;
412 db->rx_status = dm9000_rx_status_8bit;
416 /* NIC Type: FASTETHER, HOMERUN, LONGRUN */
419 /* GPIO0 on pre-activate PHY */
420 DM9000_iow(DM9000_GPR, 0x00); /*REG_1F bit0 activate phyxcer */
425 /* Program operating register */
426 DM9000_iow(DM9000_NCR, 0x0); /* only intern phy supported by now */
427 DM9000_iow(DM9000_TCR, 0); /* TX Polling clear */
428 DM9000_iow(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
429 DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */
430 DM9000_iow(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */
431 DM9000_iow(DM9000_SMCR, 0); /* Special Mode */
432 DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */
433 DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */
435 /* Set Node address */
436 for (i = 0; i < 6; i++)
437 ((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i);
439 if (is_zero_ether_addr(bd->bi_enetaddr) ||
440 is_multicast_ether_addr(bd->bi_enetaddr)) {
441 /* try reading from environment */
444 s = getenv ("ethaddr");
445 for (i = 0; i < 6; ++i) {
446 bd->bi_enetaddr[i] = s ?
447 simple_strtoul (s, &e, 16) : 0;
449 s = (*e) ? e + 1 : e;
453 printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0],
454 bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3],
455 bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
456 for (i = 0, oft = 0x10; i < 6; i++, oft++)
457 DM9000_iow(oft, bd->bi_enetaddr[i]);
458 for (i = 0, oft = 0x16; i < 8; i++, oft++)
459 DM9000_iow(oft, 0xff);
461 /* read back mac, just to be sure */
462 for (i = 0, oft = 0x10; i < 6; i++, oft++)
463 DM9000_DBG("%02x:", DM9000_ior(oft));
466 /* Activate DM9000 */
467 DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */
468 DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */
470 while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */
474 printf("could not establish link\n");
479 /* see what we've got */
480 lnk = phy_read(17) >> 12;
481 printf("operating at ");
484 printf("10M half duplex ");
487 printf("10M full duplex ");
490 printf("100M half duplex ");
493 printf("100M full duplex ");
496 printf("unknown: %d ", lnk);
504 Hardware start transmission.
505 Send a packet to media from the upper layer.
508 eth_send(volatile void *packet, int length)
512 struct board_info *db = &dm9000_info;
514 DM9000_DMP_PACKET("eth_send", packet, length);
516 DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
518 /* Move data to DM9000 TX RAM */
519 data_ptr = (char *) packet;
520 DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */
522 /* push the data to the TX-fifo */
523 (db->outblk)(data_ptr, length);
525 /* Set TX length to DM9000 */
526 DM9000_iow(DM9000_TXPLL, length & 0xff);
527 DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);
529 /* Issue TX polling command */
530 DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
532 /* wait for end of transmission */
533 tmo = get_timer(0) + 5 * CFG_HZ;
534 while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) ||
535 !(DM9000_ior(DM9000_ISR) & IMR_PTM) ) {
536 if (get_timer(0) >= tmo) {
537 printf("transmission timeout\n");
541 DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
543 DM9000_DBG("transmit done\n\n");
549 The interface is stopped when it is brought.
554 DM9000_DBG("eth_halt\n");
557 phy_write(0, 0x8000); /* PHY RESET */
558 DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */
559 DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */
560 DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */
564 Received a packet and pass to upper layer
569 u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0];
570 u16 RxStatus, RxLen = 0;
571 struct board_info *db = &dm9000_info;
573 /* Check packet ready or not */
574 DM9000_ior(DM9000_MRCMDX); /* Dummy read */
575 rxbyte = DM9000_inb(DM9000_DATA); /* Got most updated data */
579 /* Status check: this byte must be 0 or 1 */
581 DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */
582 DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */
583 DM9000_DBG("rx status check: %d\n", rxbyte);
585 DM9000_DBG("receiving packet\n");
587 /* A packet ready now & Get status/length */
588 DM9000_outb(DM9000_MRCMD, DM9000_IO);
590 (db->rx_status)(&RxStatus, &RxLen);
592 DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen);
594 /* Move data from DM9000 */
595 /* Read received packet from RX SRAM */
596 (db->inblk)(rdptr, RxLen);
598 if ((RxStatus & 0xbf00) || (RxLen < 0x40)
599 || (RxLen > DM9000_PKT_MAX)) {
600 if (RxStatus & 0x100) {
601 printf("rx fifo error\n");
603 if (RxStatus & 0x200) {
604 printf("rx crc error\n");
606 if (RxStatus & 0x8000) {
607 printf("rx length error\n");
609 if (RxLen > DM9000_PKT_MAX) {
610 printf("rx length too big\n");
614 DM9000_DMP_PACKET("eth_rx", rdptr, RxLen);
616 /* Pass to upper layer */
617 DM9000_DBG("passing packet to upper layer\n");
618 NetReceive(NetRxPackets[0], RxLen);
625 Read a word data from SROM
628 read_srom_word(int offset)
630 DM9000_iow(DM9000_EPAR, offset);
631 DM9000_iow(DM9000_EPCR, 0x4);
633 DM9000_iow(DM9000_EPCR, 0x0);
634 return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8));
638 write_srom_word(int offset, u16 val)
640 DM9000_iow(DM9000_EPAR, offset);
641 DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
642 DM9000_iow(DM9000_EPDRL, (val & 0xff));
643 DM9000_iow(DM9000_EPCR, 0x12);
645 DM9000_iow(DM9000_EPCR, 0);
650 Read a byte from I/O port
655 DM9000_outb(reg, DM9000_IO);
656 return DM9000_inb(DM9000_DATA);
660 Write a byte to I/O port
663 DM9000_iow(int reg, u8 value)
665 DM9000_outb(reg, DM9000_IO);
666 DM9000_outb(value, DM9000_DATA);
670 Read a word from phyxcer
677 /* Fill the phyxcer register into REG_0C */
678 DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
679 DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
680 udelay(100); /* Wait read complete */
681 DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
682 val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);
684 /* The read data keeps on REG_0D & REG_0E */
685 DM9000_DBG("phy_read(0x%x): 0x%x\n", reg, val);
690 Write a word to phyxcer
693 phy_write(int reg, u16 value)
696 /* Fill the phyxcer register into REG_0C */
697 DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
699 /* Fill the written data into REG_0D & REG_0E */
700 DM9000_iow(DM9000_EPDRL, (value & 0xff));
701 DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
702 DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
703 udelay(500); /* Wait write complete */
704 DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
705 DM9000_DBG("phy_write(reg:0x%x, value:0x%x)\n", reg, value);
707 #endif /* CONFIG_DRIVER_DM9000 */