git.sur5r.net Git - u-boot/blob - drivers/net/e1000.c

   1 /**************************************************************************
   2 Intel Pro 1000 for ppcboot/das-u-boot
   3 Drivers are port from Intel's Linux driver e1000-4.3.15
   4 and from Etherboot pro 1000 driver by mrakes at vivato dot net
   5 tested on both gig copper and gig fiber boards
   6 ***************************************************************************/
   7 /*******************************************************************************
   8
   9
  10   Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
  11
  12  * SPDX-License-Identifier:     GPL-2.0+
  13
  14   Contact Information:
  15   Linux NICS <linux.nics@intel.com>
  16   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  17
  18 *******************************************************************************/
  19 /*
  20  *  Copyright (C) Archway Digital Solutions.
  21  *
  22  *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
  23  *  2/9/2002
  24  *
  25  *  Copyright (C) Linux Networx.
  26  *  Massive upgrade to work with the new intel gigabit NICs.
  27  *  <ebiederman at lnxi dot com>
  28  *
  29  *  Copyright 2011 Freescale Semiconductor, Inc.
  30  */
  31
  32 #include <common.h>
  33 #include "e1000.h"
  34
  35 #define TOUT_LOOP   100000
  36
  37 #define virt_to_bus(devno, v)   pci_virt_to_mem(devno, (void *) (v))
  38 #define bus_to_phys(devno, a)   pci_mem_to_phys(devno, a)
  39
  40 #define E1000_DEFAULT_PCI_PBA   0x00000030
  41 #define E1000_DEFAULT_PCIE_PBA  0x000a0026
  42
  43 /* NIC specific static variables go here */
  44
  45 /* Intel i210 needs the DMA descriptor rings aligned to 128b */
  46 #define E1000_BUFFER_ALIGN      128
  47
  48 DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
  49 DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
  50 DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
  51
  52 static int tx_tail;
  53 static int rx_tail, rx_last;
  54
  55 static struct pci_device_id e1000_supported[] = {
  56         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542},
  57         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER},
  58         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER},
  59         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER},
  60         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER},
  61         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER},
  62         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM},
  63         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM},
  64         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER},
  65         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER},
  66         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
  67         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
  68         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
  69         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER},
  70         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
  71         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
  72         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
  73         /* E1000 PCIe card */
  74         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER},
  75         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER      },
  76         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES     },
  77         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER},
  78         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER},
  79         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER},
  80         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE},
  81         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL},
  82         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD},
  83         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER},
  84         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER},
  85         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES},
  86         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI},
  87         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E},
  88         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT},
  89         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L},
  90         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L},
  91         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3},
  92         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT},
  93         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
  94         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
  95         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
  96         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED},
  97         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED},
  98         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER},
  99         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER},
 100         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS},
 101         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES},
 102         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS},
 103         {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX},
 104
 105         {}
 106 };
 107
 108 /* Function forward declarations */
 109 static int e1000_setup_link(struct eth_device *nic);
 110 static int e1000_setup_fiber_link(struct eth_device *nic);
 111 static int e1000_setup_copper_link(struct eth_device *nic);
 112 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
 113 static void e1000_config_collision_dist(struct e1000_hw *hw);
 114 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
 115 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
 116 static int e1000_check_for_link(struct eth_device *nic);
 117 static int e1000_wait_autoneg(struct e1000_hw *hw);
 118 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
 119                                        uint16_t * duplex);
 120 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 121                               uint16_t * phy_data);
 122 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
 123                                uint16_t phy_data);
 124 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
 125 static int e1000_phy_reset(struct e1000_hw *hw);
 126 static int e1000_detect_gig_phy(struct e1000_hw *hw);
 127 static void e1000_set_media_type(struct e1000_hw *hw);
 128
 129 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
 130 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
 131 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
 132
 133 #ifndef CONFIG_E1000_NO_NVM
 134 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
 135 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 136                 uint16_t words,
 137                 uint16_t *data);
 138 /******************************************************************************
 139  * Raises the EEPROM's clock input.
 140  *
 141  * hw - Struct containing variables accessed by shared code
 142  * eecd - EECD's current value
 143  *****************************************************************************/
 144 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 145 {
 146         /* Raise the clock input to the EEPROM (by setting the SK bit), and then
 147          * wait 50 microseconds.
 148          */
 149         *eecd = *eecd | E1000_EECD_SK;
 150         E1000_WRITE_REG(hw, EECD, *eecd);
 151         E1000_WRITE_FLUSH(hw);
 152         udelay(50);
 153 }
 154
 155 /******************************************************************************
 156  * Lowers the EEPROM's clock input.
 157  *
 158  * hw - Struct containing variables accessed by shared code
 159  * eecd - EECD's current value
 160  *****************************************************************************/
 161 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
 162 {
 163         /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
 164          * wait 50 microseconds.
 165          */
 166         *eecd = *eecd & ~E1000_EECD_SK;
 167         E1000_WRITE_REG(hw, EECD, *eecd);
 168         E1000_WRITE_FLUSH(hw);
 169         udelay(50);
 170 }
 171
 172 /******************************************************************************
 173  * Shift data bits out to the EEPROM.
 174  *
 175  * hw - Struct containing variables accessed by shared code
 176  * data - data to send to the EEPROM
 177  * count - number of bits to shift out
 178  *****************************************************************************/
 179 static void
 180 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
 181 {
 182         uint32_t eecd;
 183         uint32_t mask;
 184
 185         /* We need to shift "count" bits out to the EEPROM. So, value in the
 186          * "data" parameter will be shifted out to the EEPROM one bit at a time.
 187          * In order to do this, "data" must be broken down into bits.
 188          */
 189         mask = 0x01 << (count - 1);
 190         eecd = E1000_READ_REG(hw, EECD);
 191         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 192         do {
 193                 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
 194                  * and then raising and then lowering the clock (the SK bit controls
 195                  * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
 196                  * by setting "DI" to "0" and then raising and then lowering the clock.
 197                  */
 198                 eecd &= ~E1000_EECD_DI;
 199
 200                 if (data & mask)
 201                         eecd |= E1000_EECD_DI;
 202
 203                 E1000_WRITE_REG(hw, EECD, eecd);
 204                 E1000_WRITE_FLUSH(hw);
 205
 206                 udelay(50);
 207
 208                 e1000_raise_ee_clk(hw, &eecd);
 209                 e1000_lower_ee_clk(hw, &eecd);
 210
 211                 mask = mask >> 1;
 212
 213         } while (mask);
 214
 215         /* We leave the "DI" bit set to "0" when we leave this routine. */
 216         eecd &= ~E1000_EECD_DI;
 217         E1000_WRITE_REG(hw, EECD, eecd);
 218 }
 219
 220 /******************************************************************************
 221  * Shift data bits in from the EEPROM
 222  *
 223  * hw - Struct containing variables accessed by shared code
 224  *****************************************************************************/
 225 static uint16_t
 226 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
 227 {
 228         uint32_t eecd;
 229         uint32_t i;
 230         uint16_t data;
 231
 232         /* In order to read a register from the EEPROM, we need to shift 'count'
 233          * bits in from the EEPROM. Bits are "shifted in" by raising the clock
 234          * input to the EEPROM (setting the SK bit), and then reading the
 235          * value of the "DO" bit.  During this "shifting in" process the
 236          * "DI" bit should always be clear.
 237          */
 238
 239         eecd = E1000_READ_REG(hw, EECD);
 240
 241         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
 242         data = 0;
 243
 244         for (i = 0; i < count; i++) {
 245                 data = data << 1;
 246                 e1000_raise_ee_clk(hw, &eecd);
 247
 248                 eecd = E1000_READ_REG(hw, EECD);
 249
 250                 eecd &= ~(E1000_EECD_DI);
 251                 if (eecd & E1000_EECD_DO)
 252                         data |= 1;
 253
 254                 e1000_lower_ee_clk(hw, &eecd);
 255         }
 256
 257         return data;
 258 }
 259
 260 /******************************************************************************
 261  * Returns EEPROM to a "standby" state
 262  *
 263  * hw - Struct containing variables accessed by shared code
 264  *****************************************************************************/
 265 void e1000_standby_eeprom(struct e1000_hw *hw)
 266 {
 267         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 268         uint32_t eecd;
 269
 270         eecd = E1000_READ_REG(hw, EECD);
 271
 272         if (eeprom->type == e1000_eeprom_microwire) {
 273                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 274                 E1000_WRITE_REG(hw, EECD, eecd);
 275                 E1000_WRITE_FLUSH(hw);
 276                 udelay(eeprom->delay_usec);
 277
 278                 /* Clock high */
 279                 eecd |= E1000_EECD_SK;
 280                 E1000_WRITE_REG(hw, EECD, eecd);
 281                 E1000_WRITE_FLUSH(hw);
 282                 udelay(eeprom->delay_usec);
 283
 284                 /* Select EEPROM */
 285                 eecd |= E1000_EECD_CS;
 286                 E1000_WRITE_REG(hw, EECD, eecd);
 287                 E1000_WRITE_FLUSH(hw);
 288                 udelay(eeprom->delay_usec);
 289
 290                 /* Clock low */
 291                 eecd &= ~E1000_EECD_SK;
 292                 E1000_WRITE_REG(hw, EECD, eecd);
 293                 E1000_WRITE_FLUSH(hw);
 294                 udelay(eeprom->delay_usec);
 295         } else if (eeprom->type == e1000_eeprom_spi) {
 296                 /* Toggle CS to flush commands */
 297                 eecd |= E1000_EECD_CS;
 298                 E1000_WRITE_REG(hw, EECD, eecd);
 299                 E1000_WRITE_FLUSH(hw);
 300                 udelay(eeprom->delay_usec);
 301                 eecd &= ~E1000_EECD_CS;
 302                 E1000_WRITE_REG(hw, EECD, eecd);
 303                 E1000_WRITE_FLUSH(hw);
 304                 udelay(eeprom->delay_usec);
 305         }
 306 }
 307
 308 /***************************************************************************
 309 * Description:     Determines if the onboard NVM is FLASH or EEPROM.
 310 *
 311 * hw - Struct containing variables accessed by shared code
 312 ****************************************************************************/
 313 static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
 314 {
 315         uint32_t eecd = 0;
 316
 317         DEBUGFUNC();
 318
 319         if (hw->mac_type == e1000_ich8lan)
 320                 return false;
 321
 322         if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
 323                 eecd = E1000_READ_REG(hw, EECD);
 324
 325                 /* Isolate bits 15 & 16 */
 326                 eecd = ((eecd >> 15) & 0x03);
 327
 328                 /* If both bits are set, device is Flash type */
 329                 if (eecd == 0x03)
 330                         return false;
 331         }
 332         return true;
 333 }
 334
 335 /******************************************************************************
 336  * Prepares EEPROM for access
 337  *
 338  * hw - Struct containing variables accessed by shared code
 339  *
 340  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
 341  * function should be called before issuing a command to the EEPROM.
 342  *****************************************************************************/
 343 int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
 344 {
 345         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 346         uint32_t eecd, i = 0;
 347
 348         DEBUGFUNC();
 349
 350         if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
 351                 return -E1000_ERR_SWFW_SYNC;
 352         eecd = E1000_READ_REG(hw, EECD);
 353
 354         if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
 355                 /* Request EEPROM Access */
 356                 if (hw->mac_type > e1000_82544) {
 357                         eecd |= E1000_EECD_REQ;
 358                         E1000_WRITE_REG(hw, EECD, eecd);
 359                         eecd = E1000_READ_REG(hw, EECD);
 360                         while ((!(eecd & E1000_EECD_GNT)) &&
 361                                 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
 362                                 i++;
 363                                 udelay(5);
 364                                 eecd = E1000_READ_REG(hw, EECD);
 365                         }
 366                         if (!(eecd & E1000_EECD_GNT)) {
 367                                 eecd &= ~E1000_EECD_REQ;
 368                                 E1000_WRITE_REG(hw, EECD, eecd);
 369                                 DEBUGOUT("Could not acquire EEPROM grant\n");
 370                                 return -E1000_ERR_EEPROM;
 371                         }
 372                 }
 373         }
 374
 375         /* Setup EEPROM for Read/Write */
 376
 377         if (eeprom->type == e1000_eeprom_microwire) {
 378                 /* Clear SK and DI */
 379                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
 380                 E1000_WRITE_REG(hw, EECD, eecd);
 381
 382                 /* Set CS */
 383                 eecd |= E1000_EECD_CS;
 384                 E1000_WRITE_REG(hw, EECD, eecd);
 385         } else if (eeprom->type == e1000_eeprom_spi) {
 386                 /* Clear SK and CS */
 387                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 388                 E1000_WRITE_REG(hw, EECD, eecd);
 389                 udelay(1);
 390         }
 391
 392         return E1000_SUCCESS;
 393 }
 394
 395 /******************************************************************************
 396  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
 397  * is configured.  Additionally, if this is ICH8, the flash controller GbE
 398  * registers must be mapped, or this will crash.
 399  *
 400  * hw - Struct containing variables accessed by shared code
 401  *****************************************************************************/
 402 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
 403 {
 404         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 405         uint32_t eecd;
 406         int32_t ret_val = E1000_SUCCESS;
 407         uint16_t eeprom_size;
 408
 409         if (hw->mac_type == e1000_igb)
 410                 eecd = E1000_READ_REG(hw, I210_EECD);
 411         else
 412                 eecd = E1000_READ_REG(hw, EECD);
 413
 414         DEBUGFUNC();
 415
 416         switch (hw->mac_type) {
 417         case e1000_82542_rev2_0:
 418         case e1000_82542_rev2_1:
 419         case e1000_82543:
 420         case e1000_82544:
 421                 eeprom->type = e1000_eeprom_microwire;
 422                 eeprom->word_size = 64;
 423                 eeprom->opcode_bits = 3;
 424                 eeprom->address_bits = 6;
 425                 eeprom->delay_usec = 50;
 426                 eeprom->use_eerd = false;
 427                 eeprom->use_eewr = false;
 428         break;
 429         case e1000_82540:
 430         case e1000_82545:
 431         case e1000_82545_rev_3:
 432         case e1000_82546:
 433         case e1000_82546_rev_3:
 434                 eeprom->type = e1000_eeprom_microwire;
 435                 eeprom->opcode_bits = 3;
 436                 eeprom->delay_usec = 50;
 437                 if (eecd & E1000_EECD_SIZE) {
 438                         eeprom->word_size = 256;
 439                         eeprom->address_bits = 8;
 440                 } else {
 441                         eeprom->word_size = 64;
 442                         eeprom->address_bits = 6;
 443                 }
 444                 eeprom->use_eerd = false;
 445                 eeprom->use_eewr = false;
 446                 break;
 447         case e1000_82541:
 448         case e1000_82541_rev_2:
 449         case e1000_82547:
 450         case e1000_82547_rev_2:
 451                 if (eecd & E1000_EECD_TYPE) {
 452                         eeprom->type = e1000_eeprom_spi;
 453                         eeprom->opcode_bits = 8;
 454                         eeprom->delay_usec = 1;
 455                         if (eecd & E1000_EECD_ADDR_BITS) {
 456                                 eeprom->page_size = 32;
 457                                 eeprom->address_bits = 16;
 458                         } else {
 459                                 eeprom->page_size = 8;
 460                                 eeprom->address_bits = 8;
 461                         }
 462                 } else {
 463                         eeprom->type = e1000_eeprom_microwire;
 464                         eeprom->opcode_bits = 3;
 465                         eeprom->delay_usec = 50;
 466                         if (eecd & E1000_EECD_ADDR_BITS) {
 467                                 eeprom->word_size = 256;
 468                                 eeprom->address_bits = 8;
 469                         } else {
 470                                 eeprom->word_size = 64;
 471                                 eeprom->address_bits = 6;
 472                         }
 473                 }
 474                 eeprom->use_eerd = false;
 475                 eeprom->use_eewr = false;
 476                 break;
 477         case e1000_82571:
 478         case e1000_82572:
 479                 eeprom->type = e1000_eeprom_spi;
 480                 eeprom->opcode_bits = 8;
 481                 eeprom->delay_usec = 1;
 482                 if (eecd & E1000_EECD_ADDR_BITS) {
 483                         eeprom->page_size = 32;
 484                         eeprom->address_bits = 16;
 485                 } else {
 486                         eeprom->page_size = 8;
 487                         eeprom->address_bits = 8;
 488                 }
 489                 eeprom->use_eerd = false;
 490                 eeprom->use_eewr = false;
 491                 break;
 492         case e1000_82573:
 493         case e1000_82574:
 494                 eeprom->type = e1000_eeprom_spi;
 495                 eeprom->opcode_bits = 8;
 496                 eeprom->delay_usec = 1;
 497                 if (eecd & E1000_EECD_ADDR_BITS) {
 498                         eeprom->page_size = 32;
 499                         eeprom->address_bits = 16;
 500                 } else {
 501                         eeprom->page_size = 8;
 502                         eeprom->address_bits = 8;
 503                 }
 504                 if (e1000_is_onboard_nvm_eeprom(hw) == false) {
 505                         eeprom->use_eerd = true;
 506                         eeprom->use_eewr = true;
 507
 508                         eeprom->type = e1000_eeprom_flash;
 509                         eeprom->word_size = 2048;
 510
 511                 /* Ensure that the Autonomous FLASH update bit is cleared due to
 512                  * Flash update issue on parts which use a FLASH for NVM. */
 513                         eecd &= ~E1000_EECD_AUPDEN;
 514                         E1000_WRITE_REG(hw, EECD, eecd);
 515                 }
 516                 break;
 517         case e1000_80003es2lan:
 518                 eeprom->type = e1000_eeprom_spi;
 519                 eeprom->opcode_bits = 8;
 520                 eeprom->delay_usec = 1;
 521                 if (eecd & E1000_EECD_ADDR_BITS) {
 522                         eeprom->page_size = 32;
 523                         eeprom->address_bits = 16;
 524                 } else {
 525                         eeprom->page_size = 8;
 526                         eeprom->address_bits = 8;
 527                 }
 528                 eeprom->use_eerd = true;
 529                 eeprom->use_eewr = false;
 530                 break;
 531         case e1000_igb:
 532                 /* i210 has 4k of iNVM mapped as EEPROM */
 533                 eeprom->type = e1000_eeprom_invm;
 534                 eeprom->opcode_bits = 8;
 535                 eeprom->delay_usec = 1;
 536                 eeprom->page_size = 32;
 537                 eeprom->address_bits = 16;
 538                 eeprom->use_eerd = true;
 539                 eeprom->use_eewr = false;
 540                 break;
 541
 542         /* ich8lan does not support currently. if needed, please
 543          * add corresponding code and functions.
 544          */
 545 #if 0
 546         case e1000_ich8lan:
 547                 {
 548                 int32_t  i = 0;
 549
 550                 eeprom->type = e1000_eeprom_ich8;
 551                 eeprom->use_eerd = false;
 552                 eeprom->use_eewr = false;
 553                 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
 554                 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
 555                                 ICH_FLASH_GFPREG);
 556                 /* Zero the shadow RAM structure. But don't load it from NVM
 557                  * so as to save time for driver init */
 558                 if (hw->eeprom_shadow_ram != NULL) {
 559                         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
 560                                 hw->eeprom_shadow_ram[i].modified = false;
 561                                 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
 562                         }
 563                 }
 564
 565                 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
 566                                 ICH_FLASH_SECTOR_SIZE;
 567
 568                 hw->flash_bank_size = ((flash_size >> 16)
 569                                 & ICH_GFPREG_BASE_MASK) + 1;
 570                 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
 571
 572                 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
 573
 574                 hw->flash_bank_size /= 2 * sizeof(uint16_t);
 575                 break;
 576                 }
 577 #endif
 578         default:
 579                 break;
 580         }
 581
 582         if (eeprom->type == e1000_eeprom_spi ||
 583             eeprom->type == e1000_eeprom_invm) {
 584                 /* eeprom_size will be an enum [0..8] that maps
 585                  * to eeprom sizes 128B to
 586                  * 32KB (incremented by powers of 2).
 587                  */
 588                 if (hw->mac_type <= e1000_82547_rev_2) {
 589                         /* Set to default value for initial eeprom read. */
 590                         eeprom->word_size = 64;
 591                         ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
 592                                         &eeprom_size);
 593                         if (ret_val)
 594                                 return ret_val;
 595                         eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
 596                                 >> EEPROM_SIZE_SHIFT;
 597                         /* 256B eeprom size was not supported in earlier
 598                          * hardware, so we bump eeprom_size up one to
 599                          * ensure that "1" (which maps to 256B) is never
 600                          * the result used in the shifting logic below. */
 601                         if (eeprom_size)
 602                                 eeprom_size++;
 603                 } else {
 604                         eeprom_size = (uint16_t)((eecd &
 605                                 E1000_EECD_SIZE_EX_MASK) >>
 606                                 E1000_EECD_SIZE_EX_SHIFT);
 607                 }
 608
 609                 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
 610         }
 611         return ret_val;
 612 }
 613
 614 /******************************************************************************
 615  * Polls the status bit (bit 1) of the EERD to determine when the read is done.
 616  *
 617  * hw - Struct containing variables accessed by shared code
 618  *****************************************************************************/
 619 static int32_t
 620 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
 621 {
 622         uint32_t attempts = 100000;
 623         uint32_t i, reg = 0;
 624         int32_t done = E1000_ERR_EEPROM;
 625
 626         for (i = 0; i < attempts; i++) {
 627                 if (eerd == E1000_EEPROM_POLL_READ) {
 628                         if (hw->mac_type == e1000_igb)
 629                                 reg = E1000_READ_REG(hw, I210_EERD);
 630                         else
 631                                 reg = E1000_READ_REG(hw, EERD);
 632                 } else {
 633                         if (hw->mac_type == e1000_igb)
 634                                 reg = E1000_READ_REG(hw, I210_EEWR);
 635                         else
 636                                 reg = E1000_READ_REG(hw, EEWR);
 637                 }
 638
 639                 if (reg & E1000_EEPROM_RW_REG_DONE) {
 640                         done = E1000_SUCCESS;
 641                         break;
 642                 }
 643                 udelay(5);
 644         }
 645
 646         return done;
 647 }
 648
 649 /******************************************************************************
 650  * Reads a 16 bit word from the EEPROM using the EERD register.
 651  *
 652  * hw - Struct containing variables accessed by shared code
 653  * offset - offset of  word in the EEPROM to read
 654  * data - word read from the EEPROM
 655  * words - number of words to read
 656  *****************************************************************************/
 657 static int32_t
 658 e1000_read_eeprom_eerd(struct e1000_hw *hw,
 659                         uint16_t offset,
 660                         uint16_t words,
 661                         uint16_t *data)
 662 {
 663         uint32_t i, eerd = 0;
 664         int32_t error = 0;
 665
 666         for (i = 0; i < words; i++) {
 667                 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
 668                         E1000_EEPROM_RW_REG_START;
 669
 670                 if (hw->mac_type == e1000_igb)
 671                         E1000_WRITE_REG(hw, I210_EERD, eerd);
 672                 else
 673                         E1000_WRITE_REG(hw, EERD, eerd);
 674
 675                 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
 676
 677                 if (error)
 678                         break;
 679
 680                 if (hw->mac_type == e1000_igb) {
 681                         data[i] = (E1000_READ_REG(hw, I210_EERD) >>
 682                                 E1000_EEPROM_RW_REG_DATA);
 683                 } else {
 684                         data[i] = (E1000_READ_REG(hw, EERD) >>
 685                                 E1000_EEPROM_RW_REG_DATA);
 686                 }
 687
 688         }
 689
 690         return error;
 691 }
 692
 693 void e1000_release_eeprom(struct e1000_hw *hw)
 694 {
 695         uint32_t eecd;
 696
 697         DEBUGFUNC();
 698
 699         eecd = E1000_READ_REG(hw, EECD);
 700
 701         if (hw->eeprom.type == e1000_eeprom_spi) {
 702                 eecd |= E1000_EECD_CS;  /* Pull CS high */
 703                 eecd &= ~E1000_EECD_SK; /* Lower SCK */
 704
 705                 E1000_WRITE_REG(hw, EECD, eecd);
 706
 707                 udelay(hw->eeprom.delay_usec);
 708         } else if (hw->eeprom.type == e1000_eeprom_microwire) {
 709                 /* cleanup eeprom */
 710
 711                 /* CS on Microwire is active-high */
 712                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 713
 714                 E1000_WRITE_REG(hw, EECD, eecd);
 715
 716                 /* Rising edge of clock */
 717                 eecd |= E1000_EECD_SK;
 718                 E1000_WRITE_REG(hw, EECD, eecd);
 719                 E1000_WRITE_FLUSH(hw);
 720                 udelay(hw->eeprom.delay_usec);
 721
 722                 /* Falling edge of clock */
 723                 eecd &= ~E1000_EECD_SK;
 724                 E1000_WRITE_REG(hw, EECD, eecd);
 725                 E1000_WRITE_FLUSH(hw);
 726                 udelay(hw->eeprom.delay_usec);
 727         }
 728
 729         /* Stop requesting EEPROM access */
 730         if (hw->mac_type > e1000_82544) {
 731                 eecd &= ~E1000_EECD_REQ;
 732                 E1000_WRITE_REG(hw, EECD, eecd);
 733         }
 734
 735         e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
 736 }
 737
 738 /******************************************************************************
 739  * Reads a 16 bit word from the EEPROM.
 740  *
 741  * hw - Struct containing variables accessed by shared code
 742  *****************************************************************************/
 743 static int32_t
 744 e1000_spi_eeprom_ready(struct e1000_hw *hw)
 745 {
 746         uint16_t retry_count = 0;
 747         uint8_t spi_stat_reg;
 748
 749         DEBUGFUNC();
 750
 751         /* Read "Status Register" repeatedly until the LSB is cleared.  The
 752          * EEPROM will signal that the command has been completed by clearing
 753          * bit 0 of the internal status register.  If it's not cleared within
 754          * 5 milliseconds, then error out.
 755          */
 756         retry_count = 0;
 757         do {
 758                 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
 759                         hw->eeprom.opcode_bits);
 760                 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
 761                 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
 762                         break;
 763
 764                 udelay(5);
 765                 retry_count += 5;
 766
 767                 e1000_standby_eeprom(hw);
 768         } while (retry_count < EEPROM_MAX_RETRY_SPI);
 769
 770         /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
 771          * only 0-5mSec on 5V devices)
 772          */
 773         if (retry_count >= EEPROM_MAX_RETRY_SPI) {
 774                 DEBUGOUT("SPI EEPROM Status error\n");
 775                 return -E1000_ERR_EEPROM;
 776         }
 777
 778         return E1000_SUCCESS;
 779 }
 780
 781 /******************************************************************************
 782  * Reads a 16 bit word from the EEPROM.
 783  *
 784  * hw - Struct containing variables accessed by shared code
 785  * offset - offset of  word in the EEPROM to read
 786  * data - word read from the EEPROM
 787  *****************************************************************************/
 788 static int32_t
 789 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
 790                 uint16_t words, uint16_t *data)
 791 {
 792         struct e1000_eeprom_info *eeprom = &hw->eeprom;
 793         uint32_t i = 0;
 794
 795         DEBUGFUNC();
 796
 797         /* If eeprom is not yet detected, do so now */
 798         if (eeprom->word_size == 0)
 799                 e1000_init_eeprom_params(hw);
 800
 801         /* A check for invalid values:  offset too large, too many words,
 802          * and not enough words.
 803          */
 804         if ((offset >= eeprom->word_size) ||
 805                 (words > eeprom->word_size - offset) ||
 806                 (words == 0)) {
 807                 DEBUGOUT("\"words\" parameter out of bounds."
 808                         "Words = %d, size = %d\n", offset, eeprom->word_size);
 809                 return -E1000_ERR_EEPROM;
 810         }
 811
 812         /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
 813          * directly. In this case, we need to acquire the EEPROM so that
 814          * FW or other port software does not interrupt.
 815          */
 816         if (e1000_is_onboard_nvm_eeprom(hw) == true &&
 817                 hw->eeprom.use_eerd == false) {
 818
 819                 /* Prepare the EEPROM for bit-bang reading */
 820                 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
 821                         return -E1000_ERR_EEPROM;
 822         }
 823
 824         /* Eerd register EEPROM access requires no eeprom aquire/release */
 825         if (eeprom->use_eerd == true)
 826                 return e1000_read_eeprom_eerd(hw, offset, words, data);
 827
 828         /* ich8lan does not support currently. if needed, please
 829          * add corresponding code and functions.
 830          */
 831 #if 0
 832         /* ICH EEPROM access is done via the ICH flash controller */
 833         if (eeprom->type == e1000_eeprom_ich8)
 834                 return e1000_read_eeprom_ich8(hw, offset, words, data);
 835 #endif
 836         /* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
 837          * acquired the EEPROM at this point, so any returns should relase it */
 838         if (eeprom->type == e1000_eeprom_spi) {
 839                 uint16_t word_in;
 840                 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
 841
 842                 if (e1000_spi_eeprom_ready(hw)) {
 843                         e1000_release_eeprom(hw);
 844                         return -E1000_ERR_EEPROM;
 845                 }
 846
 847                 e1000_standby_eeprom(hw);
 848
 849                 /* Some SPI eeproms use the 8th address bit embedded in
 850                  * the opcode */
 851                 if ((eeprom->address_bits == 8) && (offset >= 128))
 852                         read_opcode |= EEPROM_A8_OPCODE_SPI;
 853
 854                 /* Send the READ command (opcode + addr)  */
 855                 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
 856                 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
 857                                 eeprom->address_bits);
 858
 859                 /* Read the data.  The address of the eeprom internally
 860                  * increments with each byte (spi) being read, saving on the
 861                  * overhead of eeprom setup and tear-down.  The address
 862                  * counter will roll over if reading beyond the size of
 863                  * the eeprom, thus allowing the entire memory to be read
 864                  * starting from any offset. */
 865                 for (i = 0; i < words; i++) {
 866                         word_in = e1000_shift_in_ee_bits(hw, 16);
 867                         data[i] = (word_in >> 8) | (word_in << 8);
 868                 }
 869         } else if (eeprom->type == e1000_eeprom_microwire) {
 870                 for (i = 0; i < words; i++) {
 871                         /* Send the READ command (opcode + addr)  */
 872                         e1000_shift_out_ee_bits(hw,
 873                                 EEPROM_READ_OPCODE_MICROWIRE,
 874                                 eeprom->opcode_bits);
 875                         e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
 876                                 eeprom->address_bits);
 877
 878                         /* Read the data.  For microwire, each word requires
 879                          * the overhead of eeprom setup and tear-down. */
 880                         data[i] = e1000_shift_in_ee_bits(hw, 16);
 881                         e1000_standby_eeprom(hw);
 882                 }
 883         }
 884
 885         /* End this read operation */
 886         e1000_release_eeprom(hw);
 887
 888         return E1000_SUCCESS;
 889 }
 890
 891 /******************************************************************************
 892  * Verifies that the EEPROM has a valid checksum
 893  *
 894  * hw - Struct containing variables accessed by shared code
 895  *
 896  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
 897  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
 898  * valid.
 899  *****************************************************************************/
 900 static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
 901 {
 902         uint16_t i, checksum, checksum_reg, *buf;
 903
 904         DEBUGFUNC();
 905
 906         /* Allocate a temporary buffer */
 907         buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
 908         if (!buf) {
 909                 E1000_ERR(hw->nic, "Unable to allocate EEPROM buffer!\n");
 910                 return -E1000_ERR_EEPROM;
 911         }
 912
 913         /* Read the EEPROM */
 914         if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
 915                 E1000_ERR(hw->nic, "Unable to read EEPROM!\n");
 916                 return -E1000_ERR_EEPROM;
 917         }
 918
 919         /* Compute the checksum */
 920         checksum = 0;
 921         for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
 922                 checksum += buf[i];
 923         checksum = ((uint16_t)EEPROM_SUM) - checksum;
 924         checksum_reg = buf[i];
 925
 926         /* Verify it! */
 927         if (checksum == checksum_reg)
 928                 return 0;
 929
 930         /* Hrm, verification failed, print an error */
 931         E1000_ERR(hw->nic, "EEPROM checksum is incorrect!\n");
 932         E1000_ERR(hw->nic, "  ...register was 0x%04hx, calculated 0x%04hx\n",
 933                         checksum_reg, checksum);
 934
 935         return -E1000_ERR_EEPROM;
 936 }
 937 #endif /* CONFIG_E1000_NO_NVM */
 938
 939 /*****************************************************************************
 940  * Set PHY to class A mode
 941  * Assumes the following operations will follow to enable the new class mode.
 942  *  1. Do a PHY soft reset
 943  *  2. Restart auto-negotiation or force link.
 944  *
 945  * hw - Struct containing variables accessed by shared code
 946  ****************************************************************************/
 947 static int32_t
 948 e1000_set_phy_mode(struct e1000_hw *hw)
 949 {
 950 #ifndef CONFIG_E1000_NO_NVM
 951         int32_t ret_val;
 952         uint16_t eeprom_data;
 953
 954         DEBUGFUNC();
 955
 956         if ((hw->mac_type == e1000_82545_rev_3) &&
 957                 (hw->media_type == e1000_media_type_copper)) {
 958                 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
 959                                 1, &eeprom_data);
 960                 if (ret_val)
 961                         return ret_val;
 962
 963                 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
 964                         (eeprom_data & EEPROM_PHY_CLASS_A)) {
 965                         ret_val = e1000_write_phy_reg(hw,
 966                                         M88E1000_PHY_PAGE_SELECT, 0x000B);
 967                         if (ret_val)
 968                                 return ret_val;
 969                         ret_val = e1000_write_phy_reg(hw,
 970                                         M88E1000_PHY_GEN_CONTROL, 0x8104);
 971                         if (ret_val)
 972                                 return ret_val;
 973
 974                         hw->phy_reset_disable = false;
 975                 }
 976         }
 977 #endif
 978         return E1000_SUCCESS;
 979 }
 980
 981 #ifndef CONFIG_E1000_NO_NVM
 982 /***************************************************************************
 983  *
 984  * Obtaining software semaphore bit (SMBI) before resetting PHY.
 985  *
 986  * hw: Struct containing variables accessed by shared code
 987  *
 988  * returns: - E1000_ERR_RESET if fail to obtain semaphore.
 989  *            E1000_SUCCESS at any other case.
 990  *
 991  ***************************************************************************/
 992 static int32_t
 993 e1000_get_software_semaphore(struct e1000_hw *hw)
 994 {
 995          int32_t timeout = hw->eeprom.word_size + 1;
 996          uint32_t swsm;
 997
 998         DEBUGFUNC();
 999
1000         if (hw->mac_type != e1000_80003es2lan)
1001                 return E1000_SUCCESS;
1002
1003         while (timeout) {
1004                 swsm = E1000_READ_REG(hw, SWSM);
1005                 /* If SMBI bit cleared, it is now set and we hold
1006                  * the semaphore */
1007                 if (!(swsm & E1000_SWSM_SMBI))
1008                         break;
1009                 mdelay(1);
1010                 timeout--;
1011         }
1012
1013         if (!timeout) {
1014                 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1015                 return -E1000_ERR_RESET;
1016         }
1017
1018         return E1000_SUCCESS;
1019 }
1020 #endif
1021
1022 /***************************************************************************
1023  * This function clears HW semaphore bits.
1024  *
1025  * hw: Struct containing variables accessed by shared code
1026  *
1027  * returns: - None.
1028  *
1029  ***************************************************************************/
1030 static void
1031 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
1032 {
1033 #ifndef CONFIG_E1000_NO_NVM
1034          uint32_t swsm;
1035
1036         DEBUGFUNC();
1037
1038         if (!hw->eeprom_semaphore_present)
1039                 return;
1040
1041         swsm = E1000_READ_REG(hw, SWSM);
1042         if (hw->mac_type == e1000_80003es2lan) {
1043                 /* Release both semaphores. */
1044                 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1045         } else
1046                 swsm &= ~(E1000_SWSM_SWESMBI);
1047         E1000_WRITE_REG(hw, SWSM, swsm);
1048 #endif
1049 }
1050
1051 /***************************************************************************
1052  *
1053  * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1054  * adapter or Eeprom access.
1055  *
1056  * hw: Struct containing variables accessed by shared code
1057  *
1058  * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1059  *            E1000_SUCCESS at any other case.
1060  *
1061  ***************************************************************************/
1062 static int32_t
1063 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1064 {
1065 #ifndef CONFIG_E1000_NO_NVM
1066         int32_t timeout;
1067         uint32_t swsm;
1068
1069         DEBUGFUNC();
1070
1071         if (!hw->eeprom_semaphore_present)
1072                 return E1000_SUCCESS;
1073
1074         if (hw->mac_type == e1000_80003es2lan) {
1075                 /* Get the SW semaphore. */
1076                 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1077                         return -E1000_ERR_EEPROM;
1078         }
1079
1080         /* Get the FW semaphore. */
1081         timeout = hw->eeprom.word_size + 1;
1082         while (timeout) {
1083                 swsm = E1000_READ_REG(hw, SWSM);
1084                 swsm |= E1000_SWSM_SWESMBI;
1085                 E1000_WRITE_REG(hw, SWSM, swsm);
1086                 /* if we managed to set the bit we got the semaphore. */
1087                 swsm = E1000_READ_REG(hw, SWSM);
1088                 if (swsm & E1000_SWSM_SWESMBI)
1089                         break;
1090
1091                 udelay(50);
1092                 timeout--;
1093         }
1094
1095         if (!timeout) {
1096                 /* Release semaphores */
1097                 e1000_put_hw_eeprom_semaphore(hw);
1098                 DEBUGOUT("Driver can't access the Eeprom - "
1099                                 "SWESMBI bit is set.\n");
1100                 return -E1000_ERR_EEPROM;
1101         }
1102 #endif
1103         return E1000_SUCCESS;
1104 }
1105
1106 /* Take ownership of the PHY */
1107 static int32_t
1108 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1109 {
1110         uint32_t swfw_sync = 0;
1111         uint32_t swmask = mask;
1112         uint32_t fwmask = mask << 16;
1113         int32_t timeout = 200;
1114
1115         DEBUGFUNC();
1116         while (timeout) {
1117                 if (e1000_get_hw_eeprom_semaphore(hw))
1118                         return -E1000_ERR_SWFW_SYNC;
1119
1120                 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1121                 if (!(swfw_sync & (fwmask | swmask)))
1122                         break;
1123
1124                 /* firmware currently using resource (fwmask) */
1125                 /* or other software thread currently using resource (swmask) */
1126                 e1000_put_hw_eeprom_semaphore(hw);
1127                 mdelay(5);
1128                 timeout--;
1129         }
1130
1131         if (!timeout) {
1132                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1133                 return -E1000_ERR_SWFW_SYNC;
1134         }
1135
1136         swfw_sync |= swmask;
1137         E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1138
1139         e1000_put_hw_eeprom_semaphore(hw);
1140         return E1000_SUCCESS;
1141 }
1142
1143 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
1144 {
1145         uint32_t swfw_sync = 0;
1146
1147         DEBUGFUNC();
1148         while (e1000_get_hw_eeprom_semaphore(hw))
1149                 ; /* Empty */
1150
1151         swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1152         swfw_sync &= ~mask;
1153         E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1154
1155         e1000_put_hw_eeprom_semaphore(hw);
1156 }
1157
1158 static bool e1000_is_second_port(struct e1000_hw *hw)
1159 {
1160         switch (hw->mac_type) {
1161         case e1000_80003es2lan:
1162         case e1000_82546:
1163         case e1000_82571:
1164                 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1165                         return true;
1166                 /* Fallthrough */
1167         default:
1168                 return false;
1169         }
1170 }
1171
1172 #ifndef CONFIG_E1000_NO_NVM
1173 /******************************************************************************
1174  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1175  * second function of dual function devices
1176  *
1177  * nic - Struct containing variables accessed by shared code
1178  *****************************************************************************/
1179 static int
1180 e1000_read_mac_addr(struct eth_device *nic)
1181 {
1182         struct e1000_hw *hw = nic->priv;
1183         uint16_t offset;
1184         uint16_t eeprom_data;
1185         uint32_t reg_data = 0;
1186         int i;
1187
1188         DEBUGFUNC();
1189
1190         for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1191                 offset = i >> 1;
1192                 if (hw->mac_type == e1000_igb) {
1193                         /* i210 preloads MAC address into RAL/RAH registers */
1194                         if (offset == 0)
1195                                 reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
1196                         else if (offset == 1)
1197                                 reg_data >>= 16;
1198                         else if (offset == 2)
1199                                 reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
1200                         eeprom_data = reg_data & 0xffff;
1201                 } else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1202                         DEBUGOUT("EEPROM Read Error\n");
1203                         return -E1000_ERR_EEPROM;
1204                 }
1205                 nic->enetaddr[i] = eeprom_data & 0xff;
1206                 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1207         }
1208
1209         /* Invert the last bit if this is the second device */
1210         if (e1000_is_second_port(hw))
1211                 nic->enetaddr[5] ^= 1;
1212
1213 #ifdef CONFIG_E1000_FALLBACK_MAC
1214         if (!is_valid_ethaddr(nic->enetaddr)) {
1215                 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC;
1216
1217                 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE);
1218         }
1219 #endif
1220         return 0;
1221 }
1222 #endif
1223
1224 /******************************************************************************
1225  * Initializes receive address filters.
1226  *
1227  * hw - Struct containing variables accessed by shared code
1228  *
1229  * Places the MAC address in receive address register 0 and clears the rest
1230  * of the receive addresss registers. Clears the multicast table. Assumes
1231  * the receiver is in reset when the routine is called.
1232  *****************************************************************************/
1233 static void
1234 e1000_init_rx_addrs(struct eth_device *nic)
1235 {
1236         struct e1000_hw *hw = nic->priv;
1237         uint32_t i;
1238         uint32_t addr_low;
1239         uint32_t addr_high;
1240
1241         DEBUGFUNC();
1242
1243         /* Setup the receive address. */
1244         DEBUGOUT("Programming MAC Address into RAR[0]\n");
1245         addr_low = (nic->enetaddr[0] |
1246                     (nic->enetaddr[1] << 8) |
1247                     (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24));
1248
1249         addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV);
1250
1251         E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1252         E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1253
1254         /* Zero out the other 15 receive addresses. */
1255         DEBUGOUT("Clearing RAR[1-15]\n");
1256         for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1257                 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1258                 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1259         }
1260 }
1261
1262 /******************************************************************************
1263  * Clears the VLAN filer table
1264  *
1265  * hw - Struct containing variables accessed by shared code
1266  *****************************************************************************/
1267 static void
1268 e1000_clear_vfta(struct e1000_hw *hw)
1269 {
1270         uint32_t offset;
1271
1272         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1273                 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1274 }
1275
1276 /******************************************************************************
1277  * Set the mac type member in the hw struct.
1278  *
1279  * hw - Struct containing variables accessed by shared code
1280  *****************************************************************************/
1281 int32_t
1282 e1000_set_mac_type(struct e1000_hw *hw)
1283 {
1284         DEBUGFUNC();
1285
1286         switch (hw->device_id) {
1287         case E1000_DEV_ID_82542:
1288                 switch (hw->revision_id) {
1289                 case E1000_82542_2_0_REV_ID:
1290                         hw->mac_type = e1000_82542_rev2_0;
1291                         break;
1292                 case E1000_82542_2_1_REV_ID:
1293                         hw->mac_type = e1000_82542_rev2_1;
1294                         break;
1295                 default:
1296                         /* Invalid 82542 revision ID */
1297                         return -E1000_ERR_MAC_TYPE;
1298                 }
1299                 break;
1300         case E1000_DEV_ID_82543GC_FIBER:
1301         case E1000_DEV_ID_82543GC_COPPER:
1302                 hw->mac_type = e1000_82543;
1303                 break;
1304         case E1000_DEV_ID_82544EI_COPPER:
1305         case E1000_DEV_ID_82544EI_FIBER:
1306         case E1000_DEV_ID_82544GC_COPPER:
1307         case E1000_DEV_ID_82544GC_LOM:
1308                 hw->mac_type = e1000_82544;
1309                 break;
1310         case E1000_DEV_ID_82540EM:
1311         case E1000_DEV_ID_82540EM_LOM:
1312         case E1000_DEV_ID_82540EP:
1313         case E1000_DEV_ID_82540EP_LOM:
1314         case E1000_DEV_ID_82540EP_LP:
1315                 hw->mac_type = e1000_82540;
1316                 break;
1317         case E1000_DEV_ID_82545EM_COPPER:
1318         case E1000_DEV_ID_82545EM_FIBER:
1319                 hw->mac_type = e1000_82545;
1320                 break;
1321         case E1000_DEV_ID_82545GM_COPPER:
1322         case E1000_DEV_ID_82545GM_FIBER:
1323         case E1000_DEV_ID_82545GM_SERDES:
1324                 hw->mac_type = e1000_82545_rev_3;
1325                 break;
1326         case E1000_DEV_ID_82546EB_COPPER:
1327         case E1000_DEV_ID_82546EB_FIBER:
1328         case E1000_DEV_ID_82546EB_QUAD_COPPER:
1329                 hw->mac_type = e1000_82546;
1330                 break;
1331         case E1000_DEV_ID_82546GB_COPPER:
1332         case E1000_DEV_ID_82546GB_FIBER:
1333         case E1000_DEV_ID_82546GB_SERDES:
1334         case E1000_DEV_ID_82546GB_PCIE:
1335         case E1000_DEV_ID_82546GB_QUAD_COPPER:
1336         case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1337                 hw->mac_type = e1000_82546_rev_3;
1338                 break;
1339         case E1000_DEV_ID_82541EI:
1340         case E1000_DEV_ID_82541EI_MOBILE:
1341         case E1000_DEV_ID_82541ER_LOM:
1342                 hw->mac_type = e1000_82541;
1343                 break;
1344         case E1000_DEV_ID_82541ER:
1345         case E1000_DEV_ID_82541GI:
1346         case E1000_DEV_ID_82541GI_LF:
1347         case E1000_DEV_ID_82541GI_MOBILE:
1348                 hw->mac_type = e1000_82541_rev_2;
1349                 break;
1350         case E1000_DEV_ID_82547EI:
1351         case E1000_DEV_ID_82547EI_MOBILE:
1352                 hw->mac_type = e1000_82547;
1353                 break;
1354         case E1000_DEV_ID_82547GI:
1355                 hw->mac_type = e1000_82547_rev_2;
1356                 break;
1357         case E1000_DEV_ID_82571EB_COPPER:
1358         case E1000_DEV_ID_82571EB_FIBER:
1359         case E1000_DEV_ID_82571EB_SERDES:
1360         case E1000_DEV_ID_82571EB_SERDES_DUAL:
1361         case E1000_DEV_ID_82571EB_SERDES_QUAD:
1362         case E1000_DEV_ID_82571EB_QUAD_COPPER:
1363         case E1000_DEV_ID_82571PT_QUAD_COPPER:
1364         case E1000_DEV_ID_82571EB_QUAD_FIBER:
1365         case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1366                 hw->mac_type = e1000_82571;
1367                 break;
1368         case E1000_DEV_ID_82572EI_COPPER:
1369         case E1000_DEV_ID_82572EI_FIBER:
1370         case E1000_DEV_ID_82572EI_SERDES:
1371         case E1000_DEV_ID_82572EI:
1372                 hw->mac_type = e1000_82572;
1373                 break;
1374         case E1000_DEV_ID_82573E:
1375         case E1000_DEV_ID_82573E_IAMT:
1376         case E1000_DEV_ID_82573L:
1377                 hw->mac_type = e1000_82573;
1378                 break;
1379         case E1000_DEV_ID_82574L:
1380                 hw->mac_type = e1000_82574;
1381                 break;
1382         case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1383         case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1384         case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1385         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1386                 hw->mac_type = e1000_80003es2lan;
1387                 break;
1388         case E1000_DEV_ID_ICH8_IGP_M_AMT:
1389         case E1000_DEV_ID_ICH8_IGP_AMT:
1390         case E1000_DEV_ID_ICH8_IGP_C:
1391         case E1000_DEV_ID_ICH8_IFE:
1392         case E1000_DEV_ID_ICH8_IFE_GT:
1393         case E1000_DEV_ID_ICH8_IFE_G:
1394         case E1000_DEV_ID_ICH8_IGP_M:
1395                 hw->mac_type = e1000_ich8lan;
1396                 break;
1397         case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
1398         case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
1399         case PCI_DEVICE_ID_INTEL_I210_COPPER:
1400         case PCI_DEVICE_ID_INTEL_I211_COPPER:
1401         case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
1402         case PCI_DEVICE_ID_INTEL_I210_SERDES:
1403         case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
1404         case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
1405                 hw->mac_type = e1000_igb;
1406                 break;
1407         default:
1408                 /* Should never have loaded on this device */
1409                 return -E1000_ERR_MAC_TYPE;
1410         }
1411         return E1000_SUCCESS;
1412 }
1413
1414 /******************************************************************************
1415  * Reset the transmit and receive units; mask and clear all interrupts.
1416  *
1417  * hw - Struct containing variables accessed by shared code
1418  *****************************************************************************/
1419 void
1420 e1000_reset_hw(struct e1000_hw *hw)
1421 {
1422         uint32_t ctrl;
1423         uint32_t ctrl_ext;
1424         uint32_t manc;
1425         uint32_t pba = 0;
1426         uint32_t reg;
1427
1428         DEBUGFUNC();
1429
1430         /* get the correct pba value for both PCI and PCIe*/
1431         if (hw->mac_type <  e1000_82571)
1432                 pba = E1000_DEFAULT_PCI_PBA;
1433         else
1434                 pba = E1000_DEFAULT_PCIE_PBA;
1435
1436         /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1437         if (hw->mac_type == e1000_82542_rev2_0) {
1438                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1439                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1440                                 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1441         }
1442
1443         /* Clear interrupt mask to stop board from generating interrupts */
1444         DEBUGOUT("Masking off all interrupts\n");
1445         if (hw->mac_type == e1000_igb)
1446                 E1000_WRITE_REG(hw, I210_IAM, 0);
1447         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1448
1449         /* Disable the Transmit and Receive units.  Then delay to allow
1450          * any pending transactions to complete before we hit the MAC with
1451          * the global reset.
1452          */
1453         E1000_WRITE_REG(hw, RCTL, 0);
1454         E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1455         E1000_WRITE_FLUSH(hw);
1456
1457         /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1458         hw->tbi_compatibility_on = false;
1459
1460         /* Delay to allow any outstanding PCI transactions to complete before
1461          * resetting the device
1462          */
1463         mdelay(10);
1464
1465         /* Issue a global reset to the MAC.  This will reset the chip's
1466          * transmit, receive, DMA, and link units.  It will not effect
1467          * the current PCI configuration.  The global reset bit is self-
1468          * clearing, and should clear within a microsecond.
1469          */
1470         DEBUGOUT("Issuing a global reset to MAC\n");
1471         ctrl = E1000_READ_REG(hw, CTRL);
1472
1473         E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1474
1475         /* Force a reload from the EEPROM if necessary */
1476         if (hw->mac_type == e1000_igb) {
1477                 mdelay(20);
1478                 reg = E1000_READ_REG(hw, STATUS);
1479                 if (reg & E1000_STATUS_PF_RST_DONE)
1480                         DEBUGOUT("PF OK\n");
1481                 reg = E1000_READ_REG(hw, I210_EECD);
1482                 if (reg & E1000_EECD_AUTO_RD)
1483                         DEBUGOUT("EEC OK\n");
1484         } else if (hw->mac_type < e1000_82540) {
1485                 /* Wait for reset to complete */
1486                 udelay(10);
1487                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1488                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1489                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1490                 E1000_WRITE_FLUSH(hw);
1491                 /* Wait for EEPROM reload */
1492                 mdelay(2);
1493         } else {
1494                 /* Wait for EEPROM reload (it happens automatically) */
1495                 mdelay(4);
1496                 /* Dissable HW ARPs on ASF enabled adapters */
1497                 manc = E1000_READ_REG(hw, MANC);
1498                 manc &= ~(E1000_MANC_ARP_EN);
1499                 E1000_WRITE_REG(hw, MANC, manc);
1500         }
1501
1502         /* Clear interrupt mask to stop board from generating interrupts */
1503         DEBUGOUT("Masking off all interrupts\n");
1504         if (hw->mac_type == e1000_igb)
1505                 E1000_WRITE_REG(hw, I210_IAM, 0);
1506         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1507
1508         /* Clear any pending interrupt events. */
1509         E1000_READ_REG(hw, ICR);
1510
1511         /* If MWI was previously enabled, reenable it. */
1512         if (hw->mac_type == e1000_82542_rev2_0) {
1513                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1514         }
1515         if (hw->mac_type != e1000_igb)
1516                 E1000_WRITE_REG(hw, PBA, pba);
1517 }
1518
1519 /******************************************************************************
1520  *
1521  * Initialize a number of hardware-dependent bits
1522  *
1523  * hw: Struct containing variables accessed by shared code
1524  *
1525  * This function contains hardware limitation workarounds for PCI-E adapters
1526  *
1527  *****************************************************************************/
1528 static void
1529 e1000_initialize_hardware_bits(struct e1000_hw *hw)
1530 {
1531         if ((hw->mac_type >= e1000_82571) &&
1532                         (!hw->initialize_hw_bits_disable)) {
1533                 /* Settings common to all PCI-express silicon */
1534                 uint32_t reg_ctrl, reg_ctrl_ext;
1535                 uint32_t reg_tarc0, reg_tarc1;
1536                 uint32_t reg_tctl;
1537                 uint32_t reg_txdctl, reg_txdctl1;
1538
1539                 /* link autonegotiation/sync workarounds */
1540                 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1541                 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1542
1543                 /* Enable not-done TX descriptor counting */
1544                 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1545                 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1546                 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1547
1548                 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1549                 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1550                 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1551
1552         /* IGB is cool */
1553         if (hw->mac_type == e1000_igb)
1554                 return;
1555
1556                 switch (hw->mac_type) {
1557                 case e1000_82571:
1558                 case e1000_82572:
1559                         /* Clear PHY TX compatible mode bits */
1560                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1561                         reg_tarc1 &= ~((1 << 30)|(1 << 29));
1562
1563                         /* link autonegotiation/sync workarounds */
1564                         reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1565
1566                         /* TX ring control fixes */
1567                         reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1568
1569                         /* Multiple read bit is reversed polarity */
1570                         reg_tctl = E1000_READ_REG(hw, TCTL);
1571                         if (reg_tctl & E1000_TCTL_MULR)
1572                                 reg_tarc1 &= ~(1 << 28);
1573                         else
1574                                 reg_tarc1 |= (1 << 28);
1575
1576                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1577                         break;
1578                 case e1000_82573:
1579                 case e1000_82574:
1580                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1581                         reg_ctrl_ext &= ~(1 << 23);
1582                         reg_ctrl_ext |= (1 << 22);
1583
1584                         /* TX byte count fix */
1585                         reg_ctrl = E1000_READ_REG(hw, CTRL);
1586                         reg_ctrl &= ~(1 << 29);
1587
1588                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1589                         E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1590                         break;
1591                 case e1000_80003es2lan:
1592         /* improve small packet performace for fiber/serdes */
1593                         if ((hw->media_type == e1000_media_type_fiber)
1594                         || (hw->media_type ==
1595                                 e1000_media_type_internal_serdes)) {
1596                                 reg_tarc0 &= ~(1 << 20);
1597                         }
1598
1599                 /* Multiple read bit is reversed polarity */
1600                         reg_tctl = E1000_READ_REG(hw, TCTL);
1601                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1602                         if (reg_tctl & E1000_TCTL_MULR)
1603                                 reg_tarc1 &= ~(1 << 28);
1604                         else
1605                                 reg_tarc1 |= (1 << 28);
1606
1607                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1608                         break;
1609                 case e1000_ich8lan:
1610                         /* Reduce concurrent DMA requests to 3 from 4 */
1611                         if ((hw->revision_id < 3) ||
1612                         ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1613                                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1614                                 reg_tarc0 |= ((1 << 29)|(1 << 28));
1615
1616                         reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1617                         reg_ctrl_ext |= (1 << 22);
1618                         E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1619
1620                         /* workaround TX hang with TSO=on */
1621                         reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1622
1623                         /* Multiple read bit is reversed polarity */
1624                         reg_tctl = E1000_READ_REG(hw, TCTL);
1625                         reg_tarc1 = E1000_READ_REG(hw, TARC1);
1626                         if (reg_tctl & E1000_TCTL_MULR)
1627                                 reg_tarc1 &= ~(1 << 28);
1628                         else
1629                                 reg_tarc1 |= (1 << 28);
1630
1631                         /* workaround TX hang with TSO=on */
1632                         reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1633
1634                         E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1635                         break;
1636                 default:
1637                         break;
1638                 }
1639
1640                 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1641         }
1642 }
1643
1644 /******************************************************************************
1645  * Performs basic configuration of the adapter.
1646  *
1647  * hw - Struct containing variables accessed by shared code
1648  *
1649  * Assumes that the controller has previously been reset and is in a
1650  * post-reset uninitialized state. Initializes the receive address registers,
1651  * multicast table, and VLAN filter table. Calls routines to setup link
1652  * configuration and flow control settings. Clears all on-chip counters. Leaves
1653  * the transmit and receive units disabled and uninitialized.
1654  *****************************************************************************/
1655 static int
1656 e1000_init_hw(struct eth_device *nic)
1657 {
1658         struct e1000_hw *hw = nic->priv;
1659         uint32_t ctrl;
1660         uint32_t i;
1661         int32_t ret_val;
1662         uint16_t pcix_cmd_word;
1663         uint16_t pcix_stat_hi_word;
1664         uint16_t cmd_mmrbc;
1665         uint16_t stat_mmrbc;
1666         uint32_t mta_size;
1667         uint32_t reg_data;
1668         uint32_t ctrl_ext;
1669         DEBUGFUNC();
1670         /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1671         if ((hw->mac_type == e1000_ich8lan) &&
1672                 ((hw->revision_id < 3) ||
1673                 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1674                 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1675                         reg_data = E1000_READ_REG(hw, STATUS);
1676                         reg_data &= ~0x80000000;
1677                         E1000_WRITE_REG(hw, STATUS, reg_data);
1678         }
1679         /* Do not need initialize Identification LED */
1680
1681         /* Set the media type and TBI compatibility */
1682         e1000_set_media_type(hw);
1683
1684         /* Must be called after e1000_set_media_type
1685          * because media_type is used */
1686         e1000_initialize_hardware_bits(hw);
1687
1688         /* Disabling VLAN filtering. */
1689         DEBUGOUT("Initializing the IEEE VLAN\n");
1690         /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1691         if (hw->mac_type != e1000_ich8lan) {
1692                 if (hw->mac_type < e1000_82545_rev_3)
1693                         E1000_WRITE_REG(hw, VET, 0);
1694                 e1000_clear_vfta(hw);
1695         }
1696
1697         /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1698         if (hw->mac_type == e1000_82542_rev2_0) {
1699                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1700                 pci_write_config_word(hw->pdev, PCI_COMMAND,
1701                                       hw->
1702                                       pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1703                 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1704                 E1000_WRITE_FLUSH(hw);
1705                 mdelay(5);
1706         }
1707
1708         /* Setup the receive address. This involves initializing all of the Receive
1709          * Address Registers (RARs 0 - 15).
1710          */
1711         e1000_init_rx_addrs(nic);
1712
1713         /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1714         if (hw->mac_type == e1000_82542_rev2_0) {
1715                 E1000_WRITE_REG(hw, RCTL, 0);
1716                 E1000_WRITE_FLUSH(hw);
1717                 mdelay(1);
1718                 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1719         }
1720
1721         /* Zero out the Multicast HASH table */
1722         DEBUGOUT("Zeroing the MTA\n");
1723         mta_size = E1000_MC_TBL_SIZE;
1724         if (hw->mac_type == e1000_ich8lan)
1725                 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1726         for (i = 0; i < mta_size; i++) {
1727                 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1728                 /* use write flush to prevent Memory Write Block (MWB) from
1729                  * occuring when accessing our register space */
1730                 E1000_WRITE_FLUSH(hw);
1731         }
1732 #if 0
1733         /* Set the PCI priority bit correctly in the CTRL register.  This
1734          * determines if the adapter gives priority to receives, or if it
1735          * gives equal priority to transmits and receives.  Valid only on
1736          * 82542 and 82543 silicon.
1737          */
1738         if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
1739                 ctrl = E1000_READ_REG(hw, CTRL);
1740                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1741         }
1742 #endif
1743         switch (hw->mac_type) {
1744         case e1000_82545_rev_3:
1745         case e1000_82546_rev_3:
1746         case e1000_igb:
1747                 break;
1748         default:
1749         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1750         if (hw->bus_type == e1000_bus_type_pcix) {
1751                 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1752                                      &pcix_cmd_word);
1753                 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1754                                      &pcix_stat_hi_word);
1755                 cmd_mmrbc =
1756                     (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1757                     PCIX_COMMAND_MMRBC_SHIFT;
1758                 stat_mmrbc =
1759                     (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1760                     PCIX_STATUS_HI_MMRBC_SHIFT;
1761                 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1762                         stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1763                 if (cmd_mmrbc > stat_mmrbc) {
1764                         pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1765                         pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1766                         pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1767                                               pcix_cmd_word);
1768                 }
1769         }
1770                 break;
1771         }
1772
1773         /* More time needed for PHY to initialize */
1774         if (hw->mac_type == e1000_ich8lan)
1775                 mdelay(15);
1776         if (hw->mac_type == e1000_igb)
1777                 mdelay(15);
1778
1779         /* Call a subroutine to configure the link and setup flow control. */
1780         ret_val = e1000_setup_link(nic);
1781
1782         /* Set the transmit descriptor write-back policy */
1783         if (hw->mac_type > e1000_82544) {
1784                 ctrl = E1000_READ_REG(hw, TXDCTL);
1785                 ctrl =
1786                     (ctrl & ~E1000_TXDCTL_WTHRESH) |
1787                     E1000_TXDCTL_FULL_TX_DESC_WB;
1788                 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1789         }
1790
1791         /* Set the receive descriptor write back policy */
1792         if (hw->mac_type >= e1000_82571) {
1793                 ctrl = E1000_READ_REG(hw, RXDCTL);
1794                 ctrl =
1795                     (ctrl & ~E1000_RXDCTL_WTHRESH) |
1796                     E1000_RXDCTL_FULL_RX_DESC_WB;
1797                 E1000_WRITE_REG(hw, RXDCTL, ctrl);
1798         }
1799
1800         switch (hw->mac_type) {
1801         default:
1802                 break;
1803         case e1000_80003es2lan:
1804                 /* Enable retransmit on late collisions */
1805                 reg_data = E1000_READ_REG(hw, TCTL);
1806                 reg_data |= E1000_TCTL_RTLC;
1807                 E1000_WRITE_REG(hw, TCTL, reg_data);
1808
1809                 /* Configure Gigabit Carry Extend Padding */
1810                 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1811                 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1812                 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1813                 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1814
1815                 /* Configure Transmit Inter-Packet Gap */
1816                 reg_data = E1000_READ_REG(hw, TIPG);
1817                 reg_data &= ~E1000_TIPG_IPGT_MASK;
1818                 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1819                 E1000_WRITE_REG(hw, TIPG, reg_data);
1820
1821                 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1822                 reg_data &= ~0x00100000;
1823                 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1824                 /* Fall through */
1825         case e1000_82571:
1826         case e1000_82572:
1827         case e1000_ich8lan:
1828                 ctrl = E1000_READ_REG(hw, TXDCTL1);
1829                 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
1830                         | E1000_TXDCTL_FULL_TX_DESC_WB;
1831                 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1832                 break;
1833         case e1000_82573:
1834         case e1000_82574:
1835                 reg_data = E1000_READ_REG(hw, GCR);
1836                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1837                 E1000_WRITE_REG(hw, GCR, reg_data);
1838         case e1000_igb:
1839                 break;
1840         }
1841
1842 #if 0
1843         /* Clear all of the statistics registers (clear on read).  It is
1844          * important that we do this after we have tried to establish link
1845          * because the symbol error count will increment wildly if there
1846          * is no link.
1847          */
1848         e1000_clear_hw_cntrs(hw);
1849
1850         /* ICH8 No-snoop bits are opposite polarity.
1851          * Set to snoop by default after reset. */
1852         if (hw->mac_type == e1000_ich8lan)
1853                 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1854 #endif
1855
1856         if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1857                 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1858                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1859                 /* Relaxed ordering must be disabled to avoid a parity
1860                  * error crash in a PCI slot. */
1861                 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1862                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1863         }
1864
1865         return ret_val;
1866 }
1867
1868 /******************************************************************************
1869  * Configures flow control and link settings.
1870  *
1871  * hw - Struct containing variables accessed by shared code
1872  *
1873  * Determines which flow control settings to use. Calls the apropriate media-
1874  * specific link configuration function. Configures the flow control settings.
1875  * Assuming the adapter has a valid link partner, a valid link should be
1876  * established. Assumes the hardware has previously been reset and the
1877  * transmitter and receiver are not enabled.
1878  *****************************************************************************/
1879 static int
1880 e1000_setup_link(struct eth_device *nic)
1881 {
1882         struct e1000_hw *hw = nic->priv;
1883         int32_t ret_val;
1884 #ifndef CONFIG_E1000_NO_NVM
1885         uint32_t ctrl_ext;
1886         uint16_t eeprom_data;
1887 #endif
1888
1889         DEBUGFUNC();
1890
1891         /* In the case of the phy reset being blocked, we already have a link.
1892          * We do not have to set it up again. */
1893         if (e1000_check_phy_reset_block(hw))
1894                 return E1000_SUCCESS;
1895
1896 #ifndef CONFIG_E1000_NO_NVM
1897         /* Read and store word 0x0F of the EEPROM. This word contains bits
1898          * that determine the hardware's default PAUSE (flow control) mode,
1899          * a bit that determines whether the HW defaults to enabling or
1900          * disabling auto-negotiation, and the direction of the
1901          * SW defined pins. If there is no SW over-ride of the flow
1902          * control setting, then the variable hw->fc will
1903          * be initialized based on a value in the EEPROM.
1904          */
1905         if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
1906                                 &eeprom_data) < 0) {
1907                 DEBUGOUT("EEPROM Read Error\n");
1908                 return -E1000_ERR_EEPROM;
1909         }
1910 #endif
1911         if (hw->fc == e1000_fc_default) {
1912                 switch (hw->mac_type) {
1913                 case e1000_ich8lan:
1914                 case e1000_82573:
1915                 case e1000_82574:
1916                 case e1000_igb:
1917                         hw->fc = e1000_fc_full;
1918                         break;
1919                 default:
1920 #ifndef CONFIG_E1000_NO_NVM
1921                         ret_val = e1000_read_eeprom(hw,
1922                                 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1923                         if (ret_val) {
1924                                 DEBUGOUT("EEPROM Read Error\n");
1925                                 return -E1000_ERR_EEPROM;
1926                         }
1927                         if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1928                                 hw->fc = e1000_fc_none;
1929                         else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1930                                     EEPROM_WORD0F_ASM_DIR)
1931                                 hw->fc = e1000_fc_tx_pause;
1932                         else
1933 #endif
1934                                 hw->fc = e1000_fc_full;
1935                         break;
1936                 }
1937         }
1938
1939         /* We want to save off the original Flow Control configuration just
1940          * in case we get disconnected and then reconnected into a different
1941          * hub or switch with different Flow Control capabilities.
1942          */
1943         if (hw->mac_type == e1000_82542_rev2_0)
1944                 hw->fc &= (~e1000_fc_tx_pause);
1945
1946         if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1947                 hw->fc &= (~e1000_fc_rx_pause);
1948
1949         hw->original_fc = hw->fc;
1950
1951         DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
1952
1953 #ifndef CONFIG_E1000_NO_NVM
1954         /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1955          * polarity value for the SW controlled pins, and setup the
1956          * Extended Device Control reg with that info.
1957          * This is needed because one of the SW controlled pins is used for
1958          * signal detection.  So this should be done before e1000_setup_pcs_link()
1959          * or e1000_phy_setup() is called.
1960          */
1961         if (hw->mac_type == e1000_82543) {
1962                 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1963                             SWDPIO__EXT_SHIFT);
1964                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1965         }
1966 #endif
1967
1968         /* Call the necessary subroutine to configure the link. */
1969         ret_val = (hw->media_type == e1000_media_type_fiber) ?
1970             e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic);
1971         if (ret_val < 0) {
1972                 return ret_val;
1973         }
1974
1975         /* Initialize the flow control address, type, and PAUSE timer
1976          * registers to their default values.  This is done even if flow
1977          * control is disabled, because it does not hurt anything to
1978          * initialize these registers.
1979          */
1980         DEBUGOUT("Initializing the Flow Control address, type"
1981                         "and timer regs\n");
1982
1983         /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1984         if (hw->mac_type != e1000_ich8lan) {
1985                 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1986                 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1987                 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1988         }
1989
1990         E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1991
1992         /* Set the flow control receive threshold registers.  Normally,
1993          * these registers will be set to a default threshold that may be
1994          * adjusted later by the driver's runtime code.  However, if the
1995          * ability to transmit pause frames in not enabled, then these
1996          * registers will be set to 0.
1997          */
1998         if (!(hw->fc & e1000_fc_tx_pause)) {
1999                 E1000_WRITE_REG(hw, FCRTL, 0);
2000                 E1000_WRITE_REG(hw, FCRTH, 0);
2001         } else {
2002                 /* We need to set up the Receive Threshold high and low water marks
2003                  * as well as (optionally) enabling the transmission of XON frames.
2004                  */
2005                 if (hw->fc_send_xon) {
2006                         E1000_WRITE_REG(hw, FCRTL,
2007                                         (hw->fc_low_water | E1000_FCRTL_XONE));
2008                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2009                 } else {
2010                         E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
2011                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2012                 }
2013         }
2014         return ret_val;
2015 }
2016
2017 /******************************************************************************
2018  * Sets up link for a fiber based adapter
2019  *
2020  * hw - Struct containing variables accessed by shared code
2021  *
2022  * Manipulates Physical Coding Sublayer functions in order to configure
2023  * link. Assumes the hardware has been previously reset and the transmitter
2024  * and receiver are not enabled.
2025  *****************************************************************************/
2026 static int
2027 e1000_setup_fiber_link(struct eth_device *nic)
2028 {
2029         struct e1000_hw *hw = nic->priv;
2030         uint32_t ctrl;
2031         uint32_t status;
2032         uint32_t txcw = 0;
2033         uint32_t i;
2034         uint32_t signal;
2035         int32_t ret_val;
2036
2037         DEBUGFUNC();
2038         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
2039          * set when the optics detect a signal. On older adapters, it will be
2040          * cleared when there is a signal
2041          */
2042         ctrl = E1000_READ_REG(hw, CTRL);
2043         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
2044                 signal = E1000_CTRL_SWDPIN1;
2045         else
2046                 signal = 0;
2047
2048         printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal,
2049                ctrl);
2050         /* Take the link out of reset */
2051         ctrl &= ~(E1000_CTRL_LRST);
2052
2053         e1000_config_collision_dist(hw);
2054
2055         /* Check for a software override of the flow control settings, and setup
2056          * the device accordingly.  If auto-negotiation is enabled, then software
2057          * will have to set the "PAUSE" bits to the correct value in the Tranmsit
2058          * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
2059          * auto-negotiation is disabled, then software will have to manually
2060          * configure the two flow control enable bits in the CTRL register.
2061          *
2062          * The possible values of the "fc" parameter are:
2063          *      0:  Flow control is completely disabled
2064          *      1:  Rx flow control is enabled (we can receive pause frames, but
2065          *          not send pause frames).
2066          *      2:  Tx flow control is enabled (we can send pause frames but we do
2067          *          not support receiving pause frames).
2068          *      3:  Both Rx and TX flow control (symmetric) are enabled.
2069          */
2070         switch (hw->fc) {
2071         case e1000_fc_none:
2072                 /* Flow control is completely disabled by a software over-ride. */
2073                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
2074                 break;
2075         case e1000_fc_rx_pause:
2076                 /* RX Flow control is enabled and TX Flow control is disabled by a
2077                  * software over-ride. Since there really isn't a way to advertise
2078                  * that we are capable of RX Pause ONLY, we will advertise that we
2079                  * support both symmetric and asymmetric RX PAUSE. Later, we will
2080                  *  disable the adapter's ability to send PAUSE frames.
2081                  */
2082                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2083                 break;
2084         case e1000_fc_tx_pause:
2085                 /* TX Flow control is enabled, and RX Flow control is disabled, by a
2086                  * software over-ride.
2087                  */
2088                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
2089                 break;
2090         case e1000_fc_full:
2091                 /* Flow control (both RX and TX) is enabled by a software over-ride. */
2092                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2093                 break;
2094         default:
2095                 DEBUGOUT("Flow control param set incorrectly\n");
2096                 return -E1000_ERR_CONFIG;
2097                 break;
2098         }
2099
2100         /* Since auto-negotiation is enabled, take the link out of reset (the link
2101          * will be in reset, because we previously reset the chip). This will
2102          * restart auto-negotiation.  If auto-neogtiation is successful then the
2103          * link-up status bit will be set and the flow control enable bits (RFCE
2104          * and TFCE) will be set according to their negotiated value.
2105          */
2106         DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2107
2108         E1000_WRITE_REG(hw, TXCW, txcw);
2109         E1000_WRITE_REG(hw, CTRL, ctrl);
2110         E1000_WRITE_FLUSH(hw);
2111
2112         hw->txcw = txcw;
2113         mdelay(1);
2114
2115         /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
2116          * indication in the Device Status Register.  Time-out if a link isn't
2117          * seen in 500 milliseconds seconds (Auto-negotiation should complete in
2118          * less than 500 milliseconds even if the other end is doing it in SW).
2119          */
2120         if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2121                 DEBUGOUT("Looking for Link\n");
2122                 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2123                         mdelay(10);
2124                         status = E1000_READ_REG(hw, STATUS);
2125                         if (status & E1000_STATUS_LU)
2126                                 break;
2127                 }
2128                 if (i == (LINK_UP_TIMEOUT / 10)) {
2129                         /* AutoNeg failed to achieve a link, so we'll call
2130                          * e1000_check_for_link. This routine will force the link up if we
2131                          * detect a signal. This will allow us to communicate with
2132                          * non-autonegotiating link partners.
2133                          */
2134                         DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2135                         hw->autoneg_failed = 1;
2136                         ret_val = e1000_check_for_link(nic);
2137                         if (ret_val < 0) {
2138                                 DEBUGOUT("Error while checking for link\n");
2139                                 return ret_val;
2140                         }
2141                         hw->autoneg_failed = 0;
2142                 } else {
2143                         hw->autoneg_failed = 0;
2144                         DEBUGOUT("Valid Link Found\n");
2145                 }
2146         } else {
2147                 DEBUGOUT("No Signal Detected\n");
2148                 return -E1000_ERR_NOLINK;
2149         }
2150         return 0;
2151 }
2152
2153 /******************************************************************************
2154 * Make sure we have a valid PHY and change PHY mode before link setup.
2155 *
2156 * hw - Struct containing variables accessed by shared code
2157 ******************************************************************************/
2158 static int32_t
2159 e1000_copper_link_preconfig(struct e1000_hw *hw)
2160 {
2161         uint32_t ctrl;
2162         int32_t ret_val;
2163         uint16_t phy_data;
2164
2165         DEBUGFUNC();
2166
2167         ctrl = E1000_READ_REG(hw, CTRL);
2168         /* With 82543, we need to force speed and duplex on the MAC equal to what
2169          * the PHY speed and duplex configuration is. In addition, we need to
2170          * perform a hardware reset on the PHY to take it out of reset.
2171          */
2172         if (hw->mac_type > e1000_82543) {
2173                 ctrl |= E1000_CTRL_SLU;
2174                 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2175                 E1000_WRITE_REG(hw, CTRL, ctrl);
2176         } else {
2177                 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2178                                 | E1000_CTRL_SLU);
2179                 E1000_WRITE_REG(hw, CTRL, ctrl);
2180                 ret_val = e1000_phy_hw_reset(hw);
2181                 if (ret_val)
2182                         return ret_val;
2183         }
2184
2185         /* Make sure we have a valid PHY */
2186         ret_val = e1000_detect_gig_phy(hw);
2187         if (ret_val) {
2188                 DEBUGOUT("Error, did not detect valid phy.\n");
2189                 return ret_val;
2190         }
2191         DEBUGOUT("Phy ID = %x\n", hw->phy_id);
2192
2193         /* Set PHY to class A mode (if necessary) */
2194         ret_val = e1000_set_phy_mode(hw);
2195         if (ret_val)
2196                 return ret_val;
2197         if ((hw->mac_type == e1000_82545_rev_3) ||
2198                 (hw->mac_type == e1000_82546_rev_3)) {
2199                 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2200                                 &phy_data);
2201                 phy_data |= 0x00000008;
2202                 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2203                                 phy_data);
2204         }
2205
2206         if (hw->mac_type <= e1000_82543 ||
2207                 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2208                 hw->mac_type == e1000_82541_rev_2
2209                 || hw->mac_type == e1000_82547_rev_2)
2210                         hw->phy_reset_disable = false;
2211
2212         return E1000_SUCCESS;
2213 }
2214
2215 /*****************************************************************************
2216  *
2217  * This function sets the lplu state according to the active flag.  When
2218  * activating lplu this function also disables smart speed and vise versa.
2219  * lplu will not be activated unless the device autonegotiation advertisment
2220  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2221  * hw: Struct containing variables accessed by shared code
2222  * active - true to enable lplu false to disable lplu.
2223  *
2224  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2225  *            E1000_SUCCESS at any other case.
2226  *
2227  ****************************************************************************/
2228
2229 static int32_t
2230 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
2231 {
2232         uint32_t phy_ctrl = 0;
2233         int32_t ret_val;
2234         uint16_t phy_data;
2235         DEBUGFUNC();
2236
2237         if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2238             && hw->phy_type != e1000_phy_igp_3)
2239                 return E1000_SUCCESS;
2240
2241         /* During driver activity LPLU should not be used or it will attain link
2242          * from the lowest speeds starting from 10Mbps. The capability is used
2243          * for Dx transitions and states */
2244         if (hw->mac_type == e1000_82541_rev_2
2245                         || hw->mac_type == e1000_82547_rev_2) {
2246                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2247                                 &phy_data);
2248                 if (ret_val)
2249                         return ret_val;
2250         } else if (hw->mac_type == e1000_ich8lan) {
2251                 /* MAC writes into PHY register based on the state transition
2252                  * and start auto-negotiation. SW driver can overwrite the
2253                  * settings in CSR PHY power control E1000_PHY_CTRL register. */
2254                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2255         } else {
2256                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2257                                 &phy_data);
2258                 if (ret_val)
2259                         return ret_val;
2260         }
2261
2262         if (!active) {
2263                 if (hw->mac_type == e1000_82541_rev_2 ||
2264                         hw->mac_type == e1000_82547_rev_2) {
2265                         phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2266                         ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2267                                         phy_data);
2268                         if (ret_val)
2269                                 return ret_val;
2270                 } else {
2271                         if (hw->mac_type == e1000_ich8lan) {
2272                                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2273                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2274                         } else {
2275                                 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2276                                 ret_val = e1000_write_phy_reg(hw,
2277                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2278                                 if (ret_val)
2279                                         return ret_val;
2280                         }
2281                 }
2282
2283         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2284          * Dx states where the power conservation is most important.  During
2285          * driver activity we should enable SmartSpeed, so performance is
2286          * maintained. */
2287                 if (hw->smart_speed == e1000_smart_speed_on) {
2288                         ret_val = e1000_read_phy_reg(hw,
2289                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2290                         if (ret_val)
2291                                 return ret_val;
2292
2293                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2294                         ret_val = e1000_write_phy_reg(hw,
2295                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2296                         if (ret_val)
2297                                 return ret_val;
2298                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2299                         ret_val = e1000_read_phy_reg(hw,
2300                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2301                         if (ret_val)
2302                                 return ret_val;
2303
2304                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2305                         ret_val = e1000_write_phy_reg(hw,
2306                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2307                         if (ret_val)
2308                                 return ret_val;
2309                 }
2310
2311         } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2312                 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2313                 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2314
2315                 if (hw->mac_type == e1000_82541_rev_2 ||
2316                     hw->mac_type == e1000_82547_rev_2) {
2317                         phy_data |= IGP01E1000_GMII_FLEX_SPD;
2318                         ret_val = e1000_write_phy_reg(hw,
2319                                         IGP01E1000_GMII_FIFO, phy_data);
2320                         if (ret_val)
2321                                 return ret_val;
2322                 } else {
2323                         if (hw->mac_type == e1000_ich8lan) {
2324                                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2325                                 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2326                         } else {
2327                                 phy_data |= IGP02E1000_PM_D3_LPLU;
2328                                 ret_val = e1000_write_phy_reg(hw,
2329                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2330                                 if (ret_val)
2331                                         return ret_val;
2332                         }
2333                 }
2334
2335                 /* When LPLU is enabled we should disable SmartSpeed */
2336                 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2337                                 &phy_data);
2338                 if (ret_val)
2339                         return ret_val;
2340
2341                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2342                 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2343                                 phy_data);
2344                 if (ret_val)
2345                         return ret_val;
2346         }
2347         return E1000_SUCCESS;
2348 }
2349
2350 /*****************************************************************************
2351  *
2352  * This function sets the lplu d0 state according to the active flag.  When
2353  * activating lplu this function also disables smart speed and vise versa.
2354  * lplu will not be activated unless the device autonegotiation advertisment
2355  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2356  * hw: Struct containing variables accessed by shared code
2357  * active - true to enable lplu false to disable lplu.
2358  *
2359  * returns: - E1000_ERR_PHY if fail to read/write the PHY
2360  *            E1000_SUCCESS at any other case.
2361  *
2362  ****************************************************************************/
2363
2364 static int32_t
2365 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2366 {
2367         uint32_t phy_ctrl = 0;
2368         int32_t ret_val;
2369         uint16_t phy_data;
2370         DEBUGFUNC();
2371
2372         if (hw->mac_type <= e1000_82547_rev_2)
2373                 return E1000_SUCCESS;
2374
2375         if (hw->mac_type == e1000_ich8lan) {
2376                 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2377         } else if (hw->mac_type == e1000_igb) {
2378                 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL);
2379         } else {
2380                 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2381                                 &phy_data);
2382                 if (ret_val)
2383                         return ret_val;
2384         }
2385
2386         if (!active) {
2387                 if (hw->mac_type == e1000_ich8lan) {
2388                         phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2389                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2390                 } else if (hw->mac_type == e1000_igb) {
2391                         phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2392                         E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2393                 } else {
2394                         phy_data &= ~IGP02E1000_PM_D0_LPLU;
2395                         ret_val = e1000_write_phy_reg(hw,
2396                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2397                         if (ret_val)
2398                                 return ret_val;
2399                 }
2400
2401                 if (hw->mac_type == e1000_igb)
2402                         return E1000_SUCCESS;
2403
2404         /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
2405          * Dx states where the power conservation is most important.  During
2406          * driver activity we should enable SmartSpeed, so performance is
2407          * maintained. */
2408                 if (hw->smart_speed == e1000_smart_speed_on) {
2409                         ret_val = e1000_read_phy_reg(hw,
2410                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2411                         if (ret_val)
2412                                 return ret_val;
2413
2414                         phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2415                         ret_val = e1000_write_phy_reg(hw,
2416                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2417                         if (ret_val)
2418                                 return ret_val;
2419                 } else if (hw->smart_speed == e1000_smart_speed_off) {
2420                         ret_val = e1000_read_phy_reg(hw,
2421                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2422                         if (ret_val)
2423                                 return ret_val;
2424
2425                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2426                         ret_val = e1000_write_phy_reg(hw,
2427                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2428                         if (ret_val)
2429                                 return ret_val;
2430                 }
2431
2432
2433         } else {
2434
2435                 if (hw->mac_type == e1000_ich8lan) {
2436                         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2437                         E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2438                 } else if (hw->mac_type == e1000_igb) {
2439                         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2440                         E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2441                 } else {
2442                         phy_data |= IGP02E1000_PM_D0_LPLU;
2443                         ret_val = e1000_write_phy_reg(hw,
2444                                         IGP02E1000_PHY_POWER_MGMT, phy_data);
2445                         if (ret_val)
2446                                 return ret_val;
2447                 }
2448
2449                 if (hw->mac_type == e1000_igb)
2450                         return E1000_SUCCESS;
2451
2452                 /* When LPLU is enabled we should disable SmartSpeed */
2453                 ret_val = e1000_read_phy_reg(hw,
2454                                 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2455                 if (ret_val)
2456                         return ret_val;
2457
2458                 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2459                 ret_val = e1000_write_phy_reg(hw,
2460                                 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2461                 if (ret_val)
2462                         return ret_val;
2463
2464         }
2465         return E1000_SUCCESS;
2466 }
2467
2468 /********************************************************************
2469 * Copper link setup for e1000_phy_igp series.
2470 *
2471 * hw - Struct containing variables accessed by shared code
2472 *********************************************************************/
2473 static int32_t
2474 e1000_copper_link_igp_setup(struct e1000_hw *hw)
2475 {
2476         uint32_t led_ctrl;
2477         int32_t ret_val;
2478         uint16_t phy_data;
2479
2480         DEBUGFUNC();
2481
2482         if (hw->phy_reset_disable)
2483                 return E1000_SUCCESS;
2484
2485         ret_val = e1000_phy_reset(hw);
2486         if (ret_val) {
2487                 DEBUGOUT("Error Resetting the PHY\n");
2488                 return ret_val;
2489         }
2490
2491         /* Wait 15ms for MAC to configure PHY from eeprom settings */
2492         mdelay(15);
2493         if (hw->mac_type != e1000_ich8lan) {
2494                 /* Configure activity LED after PHY reset */
2495                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2496                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2497                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2498                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2499         }
2500
2501         /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2502         if (hw->phy_type == e1000_phy_igp) {
2503                 /* disable lplu d3 during driver init */
2504                 ret_val = e1000_set_d3_lplu_state(hw, false);
2505                 if (ret_val) {
2506                         DEBUGOUT("Error Disabling LPLU D3\n");
2507                         return ret_val;
2508                 }
2509         }
2510
2511         /* disable lplu d0 during driver init */
2512         ret_val = e1000_set_d0_lplu_state(hw, false);
2513         if (ret_val) {
2514                 DEBUGOUT("Error Disabling LPLU D0\n");
2515                 return ret_val;
2516         }
2517         /* Configure mdi-mdix settings */
2518         ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2519         if (ret_val)
2520                 return ret_val;
2521
2522         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2523                 hw->dsp_config_state = e1000_dsp_config_disabled;
2524                 /* Force MDI for earlier revs of the IGP PHY */
2525                 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2526                                 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2527                 hw->mdix = 1;
2528
2529         } else {
2530                 hw->dsp_config_state = e1000_dsp_config_enabled;
2531                 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2532
2533                 switch (hw->mdix) {
2534                 case 1:
2535                         phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2536                         break;
2537                 case 2:
2538                         phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2539                         break;
2540                 case 0:
2541                 default:
2542                         phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2543                         break;
2544                 }
2545         }
2546         ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2547         if (ret_val)
2548                 return ret_val;
2549
2550         /* set auto-master slave resolution settings */
2551         if (hw->autoneg) {
2552                 e1000_ms_type phy_ms_setting = hw->master_slave;
2553
2554                 if (hw->ffe_config_state == e1000_ffe_config_active)
2555                         hw->ffe_config_state = e1000_ffe_config_enabled;
2556
2557                 if (hw->dsp_config_state == e1000_dsp_config_activated)
2558                         hw->dsp_config_state = e1000_dsp_config_enabled;
2559
2560                 /* when autonegotiation advertisment is only 1000Mbps then we
2561                   * should disable SmartSpeed and enable Auto MasterSlave
2562                   * resolution as hardware default. */
2563                 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2564                         /* Disable SmartSpeed */
2565                         ret_val = e1000_read_phy_reg(hw,
2566                                         IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2567                         if (ret_val)
2568                                 return ret_val;
2569                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2570                         ret_val = e1000_write_phy_reg(hw,
2571                                         IGP01E1000_PHY_PORT_CONFIG, phy_data);
2572                         if (ret_val)
2573                                 return ret_val;
2574                         /* Set auto Master/Slave resolution process */
2575                         ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2576                                         &phy_data);
2577                         if (ret_val)
2578                                 return ret_val;
2579                         phy_data &= ~CR_1000T_MS_ENABLE;
2580                         ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2581                                         phy_data);
2582                         if (ret_val)
2583                                 return ret_val;
2584                 }
2585
2586                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2587                 if (ret_val)
2588                         return ret_val;
2589
2590                 /* load defaults for future use */
2591                 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2592                                 ((phy_data & CR_1000T_MS_VALUE) ?
2593                                 e1000_ms_force_master :
2594                                 e1000_ms_force_slave) :
2595                                 e1000_ms_auto;
2596
2597                 switch (phy_ms_setting) {
2598                 case e1000_ms_force_master:
2599                         phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2600                         break;
2601                 case e1000_ms_force_slave:
2602                         phy_data |= CR_1000T_MS_ENABLE;
2603                         phy_data &= ~(CR_1000T_MS_VALUE);
2604                         break;
2605                 case e1000_ms_auto:
2606                         phy_data &= ~CR_1000T_MS_ENABLE;
2607                 default:
2608                         break;
2609                 }
2610                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2611                 if (ret_val)
2612                         return ret_val;
2613         }
2614
2615         return E1000_SUCCESS;
2616 }
2617
2618 /*****************************************************************************
2619  * This function checks the mode of the firmware.
2620  *
2621  * returns  - true when the mode is IAMT or false.
2622  ****************************************************************************/
2623 bool
2624 e1000_check_mng_mode(struct e1000_hw *hw)
2625 {
2626         uint32_t fwsm;
2627         DEBUGFUNC();
2628
2629         fwsm = E1000_READ_REG(hw, FWSM);
2630
2631         if (hw->mac_type == e1000_ich8lan) {
2632                 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2633                     (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2634                         return true;
2635         } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2636                        (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2637                         return true;
2638
2639         return false;
2640 }
2641
2642 static int32_t
2643 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2644 {
2645         uint16_t swfw = E1000_SWFW_PHY0_SM;
2646         uint32_t reg_val;
2647         DEBUGFUNC();
2648
2649         if (e1000_is_second_port(hw))
2650                 swfw = E1000_SWFW_PHY1_SM;
2651
2652         if (e1000_swfw_sync_acquire(hw, swfw))
2653                 return -E1000_ERR_SWFW_SYNC;
2654
2655         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2656                         & E1000_KUMCTRLSTA_OFFSET) | data;
2657         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2658         udelay(2);
2659
2660         return E1000_SUCCESS;
2661 }
2662
2663 static int32_t
2664 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2665 {
2666         uint16_t swfw = E1000_SWFW_PHY0_SM;
2667         uint32_t reg_val;
2668         DEBUGFUNC();
2669
2670         if (e1000_is_second_port(hw))
2671                 swfw = E1000_SWFW_PHY1_SM;
2672
2673         if (e1000_swfw_sync_acquire(hw, swfw)) {
2674                 debug("%s[%i]\n", __func__, __LINE__);
2675                 return -E1000_ERR_SWFW_SYNC;
2676         }
2677
2678         /* Write register address */
2679         reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2680                         E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2681         E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2682         udelay(2);
2683
2684         /* Read the data returned */
2685         reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2686         *data = (uint16_t)reg_val;
2687
2688         return E1000_SUCCESS;
2689 }
2690
2691 /********************************************************************
2692 * Copper link setup for e1000_phy_gg82563 series.
2693 *
2694 * hw - Struct containing variables accessed by shared code
2695 *********************************************************************/
2696 static int32_t
2697 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2698 {
2699         int32_t ret_val;
2700         uint16_t phy_data;
2701         uint32_t reg_data;
2702
2703         DEBUGFUNC();
2704
2705         if (!hw->phy_reset_disable) {
2706                 /* Enable CRS on TX for half-duplex operation. */
2707                 ret_val = e1000_read_phy_reg(hw,
2708                                 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2709                 if (ret_val)
2710                         return ret_val;
2711
2712                 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2713                 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2714                 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2715
2716                 ret_val = e1000_write_phy_reg(hw,
2717                                 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2718                 if (ret_val)
2719                         return ret_val;
2720
2721                 /* Options:
2722                  *   MDI/MDI-X = 0 (default)
2723                  *   0 - Auto for all speeds
2724                  *   1 - MDI mode
2725                  *   2 - MDI-X mode
2726                  *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2727                  */
2728                 ret_val = e1000_read_phy_reg(hw,
2729                                 GG82563_PHY_SPEC_CTRL, &phy_data);
2730                 if (ret_val)
2731                         return ret_val;
2732
2733                 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2734
2735                 switch (hw->mdix) {
2736                 case 1:
2737                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2738                         break;
2739                 case 2:
2740                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2741                         break;
2742                 case 0:
2743                 default:
2744                         phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2745                         break;
2746                 }
2747
2748                 /* Options:
2749                  *   disable_polarity_correction = 0 (default)
2750                  *       Automatic Correction for Reversed Cable Polarity
2751                  *   0 - Disabled
2752                  *   1 - Enabled
2753                  */
2754                 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2755                 ret_val = e1000_write_phy_reg(hw,
2756                                 GG82563_PHY_SPEC_CTRL, phy_data);
2757
2758                 if (ret_val)
2759                         return ret_val;
2760
2761                 /* SW Reset the PHY so all changes take effect */
2762                 ret_val = e1000_phy_reset(hw);
2763                 if (ret_val) {
2764                         DEBUGOUT("Error Resetting the PHY\n");
2765                         return ret_val;
2766                 }
2767         } /* phy_reset_disable */
2768
2769         if (hw->mac_type == e1000_80003es2lan) {
2770                 /* Bypass RX and TX FIFO's */
2771                 ret_val = e1000_write_kmrn_reg(hw,
2772                                 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2773                                 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2774                                 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2775                 if (ret_val)
2776                         return ret_val;
2777
2778                 ret_val = e1000_read_phy_reg(hw,
2779                                 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2780                 if (ret_val)
2781                         return ret_val;
2782
2783                 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2784                 ret_val = e1000_write_phy_reg(hw,
2785                                 GG82563_PHY_SPEC_CTRL_2, phy_data);
2786
2787                 if (ret_val)
2788                         return ret_val;
2789
2790                 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2791                 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2792                 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2793
2794                 ret_val = e1000_read_phy_reg(hw,
2795                                 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2796                 if (ret_val)
2797                         return ret_val;
2798
2799         /* Do not init these registers when the HW is in IAMT mode, since the
2800          * firmware will have already initialized them.  We only initialize
2801          * them if the HW is not in IAMT mode.
2802          */
2803                 if (e1000_check_mng_mode(hw) == false) {
2804                         /* Enable Electrical Idle on the PHY */
2805                         phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2806                         ret_val = e1000_write_phy_reg(hw,
2807                                         GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2808                         if (ret_val)
2809                                 return ret_val;
2810
2811                         ret_val = e1000_read_phy_reg(hw,
2812                                         GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2813                         if (ret_val)
2814                                 return ret_val;
2815
2816                         phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2817                         ret_val = e1000_write_phy_reg(hw,
2818                                         GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2819
2820                         if (ret_val)
2821                                 return ret_val;
2822                 }
2823
2824                 /* Workaround: Disable padding in Kumeran interface in the MAC
2825                  * and in the PHY to avoid CRC errors.
2826                  */
2827                 ret_val = e1000_read_phy_reg(hw,
2828                                 GG82563_PHY_INBAND_CTRL, &phy_data);
2829                 if (ret_val)
2830                         return ret_val;
2831                 phy_data |= GG82563_ICR_DIS_PADDING;
2832                 ret_val = e1000_write_phy_reg(hw,
2833                                 GG82563_PHY_INBAND_CTRL, phy_data);
2834                 if (ret_val)
2835                         return ret_val;
2836         }
2837         return E1000_SUCCESS;
2838 }
2839
2840 /********************************************************************
2841 * Copper link setup for e1000_phy_m88 series.
2842 *
2843 * hw - Struct containing variables accessed by shared code
2844 *********************************************************************/
2845 static int32_t
2846 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
2847 {
2848         int32_t ret_val;
2849         uint16_t phy_data;
2850
2851         DEBUGFUNC();
2852
2853         if (hw->phy_reset_disable)
2854                 return E1000_SUCCESS;
2855
2856         /* Enable CRS on TX. This must be set for half-duplex operation. */
2857         ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2858         if (ret_val)
2859                 return ret_val;
2860
2861         phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2862
2863         /* Options:
2864          *   MDI/MDI-X = 0 (default)
2865          *   0 - Auto for all speeds
2866          *   1 - MDI mode
2867          *   2 - MDI-X mode
2868          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2869          */
2870         phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2871
2872         switch (hw->mdix) {
2873         case 1:
2874                 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
2875                 break;
2876         case 2:
2877                 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
2878                 break;
2879         case 3:
2880                 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
2881                 break;
2882         case 0:
2883         default:
2884                 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
2885                 break;
2886         }
2887
2888         /* Options:
2889          *   disable_polarity_correction = 0 (default)
2890          *       Automatic Correction for Reversed Cable Polarity
2891          *   0 - Disabled
2892          *   1 - Enabled
2893          */
2894         phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
2895         ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2896         if (ret_val)
2897                 return ret_val;
2898
2899         if (hw->phy_revision < M88E1011_I_REV_4) {
2900                 /* Force TX_CLK in the Extended PHY Specific Control Register
2901                  * to 25MHz clock.
2902                  */
2903                 ret_val = e1000_read_phy_reg(hw,
2904                                 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2905                 if (ret_val)
2906                         return ret_val;
2907
2908                 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2909
2910                 if ((hw->phy_revision == E1000_REVISION_2) &&
2911                         (hw->phy_id == M88E1111_I_PHY_ID)) {
2912                         /* Vidalia Phy, set the downshift counter to 5x */
2913                         phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
2914                         phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
2915                         ret_val = e1000_write_phy_reg(hw,
2916                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2917                         if (ret_val)
2918                                 return ret_val;
2919                 } else {
2920                         /* Configure Master and Slave downshift values */
2921                         phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
2922                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
2923                         phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
2924                                         | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
2925                         ret_val = e1000_write_phy_reg(hw,
2926                                         M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2927                         if (ret_val)
2928                                 return ret_val;
2929                 }
2930         }
2931
2932         /* SW Reset the PHY so all changes take effect */
2933         ret_val = e1000_phy_reset(hw);
2934         if (ret_val) {
2935                 DEBUGOUT("Error Resetting the PHY\n");
2936                 return ret_val;
2937         }
2938
2939         return E1000_SUCCESS;
2940 }
2941
2942 /********************************************************************
2943 * Setup auto-negotiation and flow control advertisements,
2944 * and then perform auto-negotiation.
2945 *
2946 * hw - Struct containing variables accessed by shared code
2947 *********************************************************************/
2948 static int32_t
2949 e1000_copper_link_autoneg(struct e1000_hw *hw)
2950 {
2951         int32_t ret_val;
2952         uint16_t phy_data;
2953
2954         DEBUGFUNC();
2955
2956         /* Perform some bounds checking on the hw->autoneg_advertised
2957          * parameter.  If this variable is zero, then set it to the default.
2958          */
2959         hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
2960
2961         /* If autoneg_advertised is zero, we assume it was not defaulted
2962          * by the calling code so we set to advertise full capability.
2963          */
2964         if (hw->autoneg_advertised == 0)
2965                 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
2966
2967         /* IFE phy only supports 10/100 */
2968         if (hw->phy_type == e1000_phy_ife)
2969                 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
2970
2971         DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
2972         ret_val = e1000_phy_setup_autoneg(hw);
2973         if (ret_val) {
2974                 DEBUGOUT("Error Setting up Auto-Negotiation\n");
2975                 return ret_val;
2976         }
2977         DEBUGOUT("Restarting Auto-Neg\n");
2978
2979         /* Restart auto-negotiation by setting the Auto Neg Enable bit and
2980          * the Auto Neg Restart bit in the PHY control register.
2981          */
2982         ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2983         if (ret_val)
2984                 return ret_val;
2985
2986         phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
2987         ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2988         if (ret_val)
2989                 return ret_val;
2990
2991         /* Does the user want to wait for Auto-Neg to complete here, or
2992          * check at a later time (for example, callback routine).
2993          */
2994         /* If we do not wait for autonegtation to complete I
2995          * do not see a valid link status.
2996          * wait_autoneg_complete = 1 .
2997          */
2998         if (hw->wait_autoneg_complete) {
2999                 ret_val = e1000_wait_autoneg(hw);
3000                 if (ret_val) {
3001                         DEBUGOUT("Error while waiting for autoneg"
3002                                         "to complete\n");
3003                         return ret_val;
3004                 }
3005         }
3006
3007         hw->get_link_status = true;
3008
3009         return E1000_SUCCESS;
3010 }
3011
3012 /******************************************************************************
3013 * Config the MAC and the PHY after link is up.
3014 *   1) Set up the MAC to the current PHY speed/duplex
3015 *      if we are on 82543.  If we
3016 *      are on newer silicon, we only need to configure
3017 *      collision distance in the Transmit Control Register.
3018 *   2) Set up flow control on the MAC to that established with
3019 *      the link partner.
3020 *   3) Config DSP to improve Gigabit link quality for some PHY revisions.
3021 *
3022 * hw - Struct containing variables accessed by shared code
3023 ******************************************************************************/
3024 static int32_t
3025 e1000_copper_link_postconfig(struct e1000_hw *hw)
3026 {
3027         int32_t ret_val;
3028         DEBUGFUNC();
3029
3030         if (hw->mac_type >= e1000_82544) {
3031                 e1000_config_collision_dist(hw);
3032         } else {
3033                 ret_val = e1000_config_mac_to_phy(hw);
3034                 if (ret_val) {
3035                         DEBUGOUT("Error configuring MAC to PHY settings\n");
3036                         return ret_val;
3037                 }
3038         }
3039         ret_val = e1000_config_fc_after_link_up(hw);
3040         if (ret_val) {
3041                 DEBUGOUT("Error Configuring Flow Control\n");
3042                 return ret_val;
3043         }
3044         return E1000_SUCCESS;
3045 }
3046
3047 /******************************************************************************
3048 * Detects which PHY is present and setup the speed and duplex
3049 *
3050 * hw - Struct containing variables accessed by shared code
3051 ******************************************************************************/
3052 static int
3053 e1000_setup_copper_link(struct eth_device *nic)
3054 {
3055         struct e1000_hw *hw = nic->priv;
3056         int32_t ret_val;
3057         uint16_t i;
3058         uint16_t phy_data;
3059         uint16_t reg_data;
3060
3061         DEBUGFUNC();
3062
3063         switch (hw->mac_type) {
3064         case e1000_80003es2lan:
3065         case e1000_ich8lan:
3066                 /* Set the mac to wait the maximum time between each
3067                  * iteration and increase the max iterations when
3068                  * polling the phy; this fixes erroneous timeouts at 10Mbps. */
3069                 ret_val = e1000_write_kmrn_reg(hw,
3070                                 GG82563_REG(0x34, 4), 0xFFFF);
3071                 if (ret_val)
3072                         return ret_val;
3073                 ret_val = e1000_read_kmrn_reg(hw,
3074                                 GG82563_REG(0x34, 9), &reg_data);
3075                 if (ret_val)
3076                         return ret_val;
3077                 reg_data |= 0x3F;
3078                 ret_val = e1000_write_kmrn_reg(hw,
3079                                 GG82563_REG(0x34, 9), reg_data);
3080                 if (ret_val)
3081                         return ret_val;
3082         default:
3083                 break;
3084         }
3085
3086         /* Check if it is a valid PHY and set PHY mode if necessary. */
3087         ret_val = e1000_copper_link_preconfig(hw);
3088         if (ret_val)
3089                 return ret_val;
3090         switch (hw->mac_type) {
3091         case e1000_80003es2lan:
3092                 /* Kumeran registers are written-only */
3093                 reg_data =
3094                 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
3095                 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
3096                 ret_val = e1000_write_kmrn_reg(hw,
3097                                 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3098                 if (ret_val)
3099                         return ret_val;
3100                 break;
3101         default:
3102                 break;
3103         }
3104
3105         if (hw->phy_type == e1000_phy_igp ||
3106                 hw->phy_type == e1000_phy_igp_3 ||
3107                 hw->phy_type == e1000_phy_igp_2) {
3108                 ret_val = e1000_copper_link_igp_setup(hw);
3109                 if (ret_val)
3110                         return ret_val;
3111         } else if (hw->phy_type == e1000_phy_m88 ||
3112                 hw->phy_type == e1000_phy_igb) {
3113                 ret_val = e1000_copper_link_mgp_setup(hw);
3114                 if (ret_val)
3115                         return ret_val;
3116         } else if (hw->phy_type == e1000_phy_gg82563) {
3117                 ret_val = e1000_copper_link_ggp_setup(hw);
3118                 if (ret_val)
3119                         return ret_val;
3120         }
3121
3122         /* always auto */
3123         /* Setup autoneg and flow control advertisement
3124           * and perform autonegotiation */
3125         ret_val = e1000_copper_link_autoneg(hw);
3126         if (ret_val)
3127                 return ret_val;
3128
3129         /* Check link status. Wait up to 100 microseconds for link to become
3130          * valid.
3131          */
3132         for (i = 0; i < 10; i++) {
3133                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3134                 if (ret_val)
3135                         return ret_val;
3136                 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3137                 if (ret_val)
3138                         return ret_val;
3139
3140                 if (phy_data & MII_SR_LINK_STATUS) {
3141                         /* Config the MAC and PHY after link is up */
3142                         ret_val = e1000_copper_link_postconfig(hw);
3143                         if (ret_val)
3144                                 return ret_val;
3145
3146                         DEBUGOUT("Valid link established!!!\n");
3147                         return E1000_SUCCESS;
3148                 }
3149                 udelay(10);
3150         }
3151
3152         DEBUGOUT("Unable to establish link!!!\n");
3153         return E1000_SUCCESS;
3154 }
3155
3156 /******************************************************************************
3157 * Configures PHY autoneg and flow control advertisement settings
3158 *
3159 * hw - Struct containing variables accessed by shared code
3160 ******************************************************************************/
3161 int32_t
3162 e1000_phy_setup_autoneg(struct e1000_hw *hw)
3163 {
3164         int32_t ret_val;
3165         uint16_t mii_autoneg_adv_reg;
3166         uint16_t mii_1000t_ctrl_reg;
3167
3168         DEBUGFUNC();
3169
3170         /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3171         ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3172         if (ret_val)
3173                 return ret_val;
3174
3175         if (hw->phy_type != e1000_phy_ife) {
3176                 /* Read the MII 1000Base-T Control Register (Address 9). */
3177                 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3178                                 &mii_1000t_ctrl_reg);
3179                 if (ret_val)
3180                         return ret_val;
3181         } else
3182                 mii_1000t_ctrl_reg = 0;
3183
3184         /* Need to parse both autoneg_advertised and fc and set up
3185          * the appropriate PHY registers.  First we will parse for
3186          * autoneg_advertised software override.  Since we can advertise
3187          * a plethora of combinations, we need to check each bit
3188          * individually.
3189          */
3190
3191         /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3192          * Advertisement Register (Address 4) and the 1000 mb speed bits in
3193          * the  1000Base-T Control Register (Address 9).
3194          */
3195         mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3196         mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3197
3198         DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3199
3200         /* Do we want to advertise 10 Mb Half Duplex? */
3201         if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3202                 DEBUGOUT("Advertise 10mb Half duplex\n");
3203                 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3204         }
3205
3206         /* Do we want to advertise 10 Mb Full Duplex? */
3207         if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3208                 DEBUGOUT("Advertise 10mb Full duplex\n");
3209                 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3210         }
3211
3212         /* Do we want to advertise 100 Mb Half Duplex? */
3213         if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3214                 DEBUGOUT("Advertise 100mb Half duplex\n");
3215                 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3216         }
3217
3218         /* Do we want to advertise 100 Mb Full Duplex? */
3219         if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3220                 DEBUGOUT("Advertise 100mb Full duplex\n");
3221                 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3222         }
3223
3224         /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3225         if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3226                 DEBUGOUT
3227                     ("Advertise 1000mb Half duplex requested, request denied!\n");
3228         }
3229
3230         /* Do we want to advertise 1000 Mb Full Duplex? */
3231         if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3232                 DEBUGOUT("Advertise 1000mb Full duplex\n");
3233                 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3234         }
3235
3236         /* Check for a software override of the flow control settings, and
3237          * setup the PHY advertisement registers accordingly.  If
3238          * auto-negotiation is enabled, then software will have to set the
3239          * "PAUSE" bits to the correct value in the Auto-Negotiation
3240          * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3241          *
3242          * The possible values of the "fc" parameter are:
3243          *      0:  Flow control is completely disabled
3244          *      1:  Rx flow control is enabled (we can receive pause frames
3245          *          but not send pause frames).
3246          *      2:  Tx flow control is enabled (we can send pause frames
3247          *          but we do not support receiving pause frames).
3248          *      3:  Both Rx and TX flow control (symmetric) are enabled.
3249          *  other:  No software override.  The flow control configuration
3250          *          in the EEPROM is used.
3251          */
3252         switch (hw->fc) {
3253         case e1000_fc_none:     /* 0 */
3254                 /* Flow control (RX & TX) is completely disabled by a
3255                  * software over-ride.
3256                  */
3257                 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3258                 break;
3259         case e1000_fc_rx_pause: /* 1 */
3260                 /* RX Flow control is enabled, and TX Flow control is
3261                  * disabled, by a software over-ride.
3262                  */
3263                 /* Since there really isn't a way to advertise that we are
3264                  * capable of RX Pause ONLY, we will advertise that we
3265                  * support both symmetric and asymmetric RX PAUSE.  Later
3266                  * (in e1000_config_fc_after_link_up) we will disable the
3267                  *hw's ability to send PAUSE frames.
3268                  */
3269                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3270                 break;
3271         case e1000_fc_tx_pause: /* 2 */
3272                 /* TX Flow control is enabled, and RX Flow control is
3273                  * disabled, by a software over-ride.
3274                  */
3275                 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3276                 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3277                 break;
3278         case e1000_fc_full:     /* 3 */
3279                 /* Flow control (both RX and TX) is enabled by a software
3280                  * over-ride.
3281                  */
3282                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3283                 break;
3284         default:
3285                 DEBUGOUT("Flow control param set incorrectly\n");
3286                 return -E1000_ERR_CONFIG;
3287         }
3288
3289         ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3290         if (ret_val)
3291                 return ret_val;
3292
3293         DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3294
3295         if (hw->phy_type != e1000_phy_ife) {
3296                 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3297                                 mii_1000t_ctrl_reg);
3298                 if (ret_val)
3299                         return ret_val;
3300         }
3301
3302         return E1000_SUCCESS;
3303 }
3304
3305 /******************************************************************************
3306 * Sets the collision distance in the Transmit Control register
3307 *
3308 * hw - Struct containing variables accessed by shared code
3309 *
3310 * Link should have been established previously. Reads the speed and duplex
3311 * information from the Device Status register.
3312 ******************************************************************************/
3313 static void
3314 e1000_config_collision_dist(struct e1000_hw *hw)
3315 {
3316         uint32_t tctl, coll_dist;
3317
3318         DEBUGFUNC();
3319
3320         if (hw->mac_type < e1000_82543)
3321                 coll_dist = E1000_COLLISION_DISTANCE_82542;
3322         else
3323                 coll_dist = E1000_COLLISION_DISTANCE;
3324
3325         tctl = E1000_READ_REG(hw, TCTL);
3326
3327         tctl &= ~E1000_TCTL_COLD;
3328         tctl |= coll_dist << E1000_COLD_SHIFT;
3329
3330         E1000_WRITE_REG(hw, TCTL, tctl);
3331         E1000_WRITE_FLUSH(hw);
3332 }
3333
3334 /******************************************************************************
3335 * Sets MAC speed and duplex settings to reflect the those in the PHY
3336 *
3337 * hw - Struct containing variables accessed by shared code
3338 * mii_reg - data to write to the MII control register
3339 *
3340 * The contents of the PHY register containing the needed information need to
3341 * be passed in.
3342 ******************************************************************************/
3343 static int
3344 e1000_config_mac_to_phy(struct e1000_hw *hw)
3345 {
3346         uint32_t ctrl;
3347         uint16_t phy_data;
3348
3349         DEBUGFUNC();
3350
3351         /* Read the Device Control Register and set the bits to Force Speed
3352          * and Duplex.
3353          */
3354         ctrl = E1000_READ_REG(hw, CTRL);
3355         ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3356         ctrl &= ~(E1000_CTRL_ILOS);
3357         ctrl |= (E1000_CTRL_SPD_SEL);
3358
3359         /* Set up duplex in the Device Control and Transmit Control
3360          * registers depending on negotiated values.
3361          */
3362         if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3363                 DEBUGOUT("PHY Read Error\n");
3364                 return -E1000_ERR_PHY;
3365         }
3366         if (phy_data & M88E1000_PSSR_DPLX)
3367                 ctrl |= E1000_CTRL_FD;
3368         else
3369                 ctrl &= ~E1000_CTRL_FD;
3370
3371         e1000_config_collision_dist(hw);
3372
3373         /* Set up speed in the Device Control register depending on
3374          * negotiated values.
3375          */
3376         if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3377                 ctrl |= E1000_CTRL_SPD_1000;
3378         else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3379                 ctrl |= E1000_CTRL_SPD_100;
3380         /* Write the configured values back to the Device Control Reg. */
3381         E1000_WRITE_REG(hw, CTRL, ctrl);
3382         return 0;
3383 }
3384
3385 /******************************************************************************
3386  * Forces the MAC's flow control settings.
3387  *
3388  * hw - Struct containing variables accessed by shared code
3389  *
3390  * Sets the TFCE and RFCE bits in the device control register to reflect
3391  * the adapter settings. TFCE and RFCE need to be explicitly set by
3392  * software when a Copper PHY is used because autonegotiation is managed
3393  * by the PHY rather than the MAC. Software must also configure these
3394  * bits when link is forced on a fiber connection.
3395  *****************************************************************************/
3396 static int
3397 e1000_force_mac_fc(struct e1000_hw *hw)
3398 {
3399         uint32_t ctrl;
3400
3401         DEBUGFUNC();
3402
3403         /* Get the current configuration of the Device Control Register */
3404         ctrl = E1000_READ_REG(hw, CTRL);
3405
3406         /* Because we didn't get link via the internal auto-negotiation
3407          * mechanism (we either forced link or we got link via PHY
3408          * auto-neg), we have to manually enable/disable transmit an
3409          * receive flow control.
3410          *
3411          * The "Case" statement below enables/disable flow control
3412          * according to the "hw->fc" parameter.
3413          *
3414          * The possible values of the "fc" parameter are:
3415          *      0:  Flow control is completely disabled
3416          *      1:  Rx flow control is enabled (we can receive pause
3417          *          frames but not send pause frames).
3418          *      2:  Tx flow control is enabled (we can send pause frames
3419          *          frames but we do not receive pause frames).
3420          *      3:  Both Rx and TX flow control (symmetric) is enabled.
3421          *  other:  No other values should be possible at this point.
3422          */
3423
3424         switch (hw->fc) {
3425         case e1000_fc_none:
3426                 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3427                 break;
3428         case e1000_fc_rx_pause:
3429                 ctrl &= (~E1000_CTRL_TFCE);
3430                 ctrl |= E1000_CTRL_RFCE;
3431                 break;
3432         case e1000_fc_tx_pause:
3433                 ctrl &= (~E1000_CTRL_RFCE);
3434                 ctrl |= E1000_CTRL_TFCE;
3435                 break;
3436         case e1000_fc_full:
3437                 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3438                 break;
3439         default:
3440                 DEBUGOUT("Flow control param set incorrectly\n");
3441                 return -E1000_ERR_CONFIG;
3442         }
3443
3444         /* Disable TX Flow Control for 82542 (rev 2.0) */
3445         if (hw->mac_type == e1000_82542_rev2_0)
3446                 ctrl &= (~E1000_CTRL_TFCE);
3447
3448         E1000_WRITE_REG(hw, CTRL, ctrl);
3449         return 0;
3450 }
3451
3452 /******************************************************************************
3453  * Configures flow control settings after link is established
3454  *
3455  * hw - Struct containing variables accessed by shared code
3456  *
3457  * Should be called immediately after a valid link has been established.
3458  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3459  * and autonegotiation is enabled, the MAC flow control settings will be set
3460  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3461  * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3462  *****************************************************************************/
3463 static int32_t
3464 e1000_config_fc_after_link_up(struct e1000_hw *hw)
3465 {
3466         int32_t ret_val;
3467         uint16_t mii_status_reg;
3468         uint16_t mii_nway_adv_reg;
3469         uint16_t mii_nway_lp_ability_reg;
3470         uint16_t speed;
3471         uint16_t duplex;
3472
3473         DEBUGFUNC();
3474
3475         /* Check for the case where we have fiber media and auto-neg failed
3476          * so we had to force link.  In this case, we need to force the
3477          * configuration of the MAC to match the "fc" parameter.
3478          */
3479         if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3480                 || ((hw->media_type == e1000_media_type_internal_serdes)
3481                 && (hw->autoneg_failed))
3482                 || ((hw->media_type == e1000_media_type_copper)
3483                 && (!hw->autoneg))) {
3484                 ret_val = e1000_force_mac_fc(hw);
3485                 if (ret_val < 0) {
3486                         DEBUGOUT("Error forcing flow control settings\n");
3487                         return ret_val;
3488                 }
3489         }
3490
3491         /* Check for the case where we have copper media and auto-neg is
3492          * enabled.  In this case, we need to check and see if Auto-Neg
3493          * has completed, and if so, how the PHY and link partner has
3494          * flow control configured.
3495          */
3496         if (hw->media_type == e1000_media_type_copper) {
3497                 /* Read the MII Status Register and check to see if AutoNeg
3498                  * has completed.  We read this twice because this reg has
3499                  * some "sticky" (latched) bits.
3500                  */
3501                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3502                         DEBUGOUT("PHY Read Error\n");
3503                         return -E1000_ERR_PHY;
3504                 }
3505                 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3506                         DEBUGOUT("PHY Read Error\n");
3507                         return -E1000_ERR_PHY;
3508                 }
3509
3510                 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3511                         /* The AutoNeg process has completed, so we now need to
3512                          * read both the Auto Negotiation Advertisement Register
3513                          * (Address 4) and the Auto_Negotiation Base Page Ability
3514                          * Register (Address 5) to determine how flow control was
3515                          * negotiated.
3516                          */
3517                         if (e1000_read_phy_reg
3518                             (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3519                                 DEBUGOUT("PHY Read Error\n");
3520                                 return -E1000_ERR_PHY;
3521                         }
3522                         if (e1000_read_phy_reg
3523                             (hw, PHY_LP_ABILITY,
3524                              &mii_nway_lp_ability_reg) < 0) {
3525                                 DEBUGOUT("PHY Read Error\n");
3526                                 return -E1000_ERR_PHY;
3527                         }
3528
3529                         /* Two bits in the Auto Negotiation Advertisement Register
3530                          * (Address 4) and two bits in the Auto Negotiation Base
3531                          * Page Ability Register (Address 5) determine flow control
3532                          * for both the PHY and the link partner.  The following
3533                          * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3534                          * 1999, describes these PAUSE resolution bits and how flow
3535                          * control is determined based upon these settings.
3536                          * NOTE:  DC = Don't Care
3537                          *
3538                          *   LOCAL DEVICE  |   LINK PARTNER
3539                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3540                          *-------|---------|-------|---------|--------------------
3541                          *   0   |    0    |  DC   |   DC    | e1000_fc_none
3542                          *   0   |    1    |   0   |   DC    | e1000_fc_none
3543                          *   0   |    1    |   1   |    0    | e1000_fc_none
3544                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3545                          *   1   |    0    |   0   |   DC    | e1000_fc_none
3546                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3547                          *   1   |    1    |   0   |    0    | e1000_fc_none
3548                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3549                          *
3550                          */
3551                         /* Are both PAUSE bits set to 1?  If so, this implies
3552                          * Symmetric Flow Control is enabled at both ends.  The
3553                          * ASM_DIR bits are irrelevant per the spec.
3554                          *
3555                          * For Symmetric Flow Control:
3556                          *
3557                          *   LOCAL DEVICE  |   LINK PARTNER
3558                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3559                          *-------|---------|-------|---------|--------------------
3560                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
3561                          *
3562                          */
3563                         if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3564                             (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3565                                 /* Now we need to check if the user selected RX ONLY
3566                                  * of pause frames.  In this case, we had to advertise
3567                                  * FULL flow control because we could not advertise RX
3568                                  * ONLY. Hence, we must now check to see if we need to
3569                                  * turn OFF  the TRANSMISSION of PAUSE frames.
3570                                  */
3571                                 if (hw->original_fc == e1000_fc_full) {
3572                                         hw->fc = e1000_fc_full;
3573                                         DEBUGOUT("Flow Control = FULL.\r\n");
3574                                 } else {
3575                                         hw->fc = e1000_fc_rx_pause;
3576                                         DEBUGOUT
3577                                             ("Flow Control = RX PAUSE frames only.\r\n");
3578                                 }
3579                         }
3580                         /* For receiving PAUSE frames ONLY.
3581                          *
3582                          *   LOCAL DEVICE  |   LINK PARTNER
3583                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3584                          *-------|---------|-------|---------|--------------------
3585                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
3586                          *
3587                          */
3588                         else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3589                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3590                                  (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3591                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3592                         {
3593                                 hw->fc = e1000_fc_tx_pause;
3594                                 DEBUGOUT
3595                                     ("Flow Control = TX PAUSE frames only.\r\n");
3596                         }
3597                         /* For transmitting PAUSE frames ONLY.
3598                          *
3599                          *   LOCAL DEVICE  |   LINK PARTNER
3600                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3601                          *-------|---------|-------|---------|--------------------
3602                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
3603                          *
3604                          */
3605                         else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3606                                  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3607                                  !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3608                                  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3609                         {
3610                                 hw->fc = e1000_fc_rx_pause;
3611                                 DEBUGOUT
3612                                     ("Flow Control = RX PAUSE frames only.\r\n");
3613                         }
3614                         /* Per the IEEE spec, at this point flow control should be
3615                          * disabled.  However, we want to consider that we could
3616                          * be connected to a legacy switch that doesn't advertise
3617                          * desired flow control, but can be forced on the link
3618                          * partner.  So if we advertised no flow control, that is
3619                          * what we will resolve to.  If we advertised some kind of
3620                          * receive capability (Rx Pause Only or Full Flow Control)
3621                          * and the link partner advertised none, we will configure
3622                          * ourselves to enable Rx Flow Control only.  We can do
3623                          * this safely for two reasons:  If the link partner really
3624                          * didn't want flow control enabled, and we enable Rx, no
3625                          * harm done since we won't be receiving any PAUSE frames
3626                          * anyway.  If the intent on the link partner was to have
3627                          * flow control enabled, then by us enabling RX only, we
3628                          * can at least receive pause frames and process them.
3629                          * This is a good idea because in most cases, since we are
3630                          * predominantly a server NIC, more times than not we will
3631                          * be asked to delay transmission of packets than asking
3632                          * our link partner to pause transmission of frames.
3633                          */
3634                         else if (hw->original_fc == e1000_fc_none ||
3635                                  hw->original_fc == e1000_fc_tx_pause) {
3636                                 hw->fc = e1000_fc_none;
3637                                 DEBUGOUT("Flow Control = NONE.\r\n");
3638                         } else {
3639                                 hw->fc = e1000_fc_rx_pause;
3640                                 DEBUGOUT
3641                                     ("Flow Control = RX PAUSE frames only.\r\n");
3642                         }
3643
3644                         /* Now we need to do one last check...  If we auto-
3645                          * negotiated to HALF DUPLEX, flow control should not be
3646                          * enabled per IEEE 802.3 spec.
3647                          */
3648                         e1000_get_speed_and_duplex(hw, &speed, &duplex);
3649
3650                         if (duplex == HALF_DUPLEX)
3651                                 hw->fc = e1000_fc_none;
3652
3653                         /* Now we call a subroutine to actually force the MAC
3654                          * controller to use the correct flow control settings.
3655                          */
3656                         ret_val = e1000_force_mac_fc(hw);
3657                         if (ret_val < 0) {
3658                                 DEBUGOUT
3659                                     ("Error forcing flow control settings\n");
3660                                 return ret_val;
3661                         }
3662                 } else {
3663                         DEBUGOUT
3664                             ("Copper PHY and Auto Neg has not completed.\r\n");
3665                 }
3666         }
3667         return E1000_SUCCESS;
3668 }
3669
3670 /******************************************************************************
3671  * Checks to see if the link status of the hardware has changed.
3672  *
3673  * hw - Struct containing variables accessed by shared code
3674  *
3675  * Called by any function that needs to check the link status of the adapter.
3676  *****************************************************************************/
3677 static int
3678 e1000_check_for_link(struct eth_device *nic)
3679 {
3680         struct e1000_hw *hw = nic->priv;
3681         uint32_t rxcw;
3682         uint32_t ctrl;
3683         uint32_t status;
3684         uint32_t rctl;
3685         uint32_t signal;
3686         int32_t ret_val;
3687         uint16_t phy_data;
3688         uint16_t lp_capability;
3689
3690         DEBUGFUNC();
3691
3692         /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3693          * set when the optics detect a signal. On older adapters, it will be
3694          * cleared when there is a signal
3695          */
3696         ctrl = E1000_READ_REG(hw, CTRL);
3697         if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3698                 signal = E1000_CTRL_SWDPIN1;
3699         else
3700                 signal = 0;
3701
3702         status = E1000_READ_REG(hw, STATUS);
3703         rxcw = E1000_READ_REG(hw, RXCW);
3704         DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3705
3706         /* If we have a copper PHY then we only want to go out to the PHY
3707          * registers to see if Auto-Neg has completed and/or if our link
3708          * status has changed.  The get_link_status flag will be set if we
3709          * receive a Link Status Change interrupt or we have Rx Sequence
3710          * Errors.
3711          */
3712         if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3713                 /* First we want to see if the MII Status Register reports
3714                  * link.  If so, then we want to get the current speed/duplex
3715                  * of the PHY.
3716                  * Read the register twice since the link bit is sticky.
3717                  */
3718                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3719                         DEBUGOUT("PHY Read Error\n");
3720                         return -E1000_ERR_PHY;
3721                 }
3722                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3723                         DEBUGOUT("PHY Read Error\n");
3724                         return -E1000_ERR_PHY;
3725                 }
3726
3727                 if (phy_data & MII_SR_LINK_STATUS) {
3728                         hw->get_link_status = false;
3729                 } else {
3730                         /* No link detected */
3731                         return -E1000_ERR_NOLINK;
3732                 }
3733
3734                 /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
3735                  * have Si on board that is 82544 or newer, Auto
3736                  * Speed Detection takes care of MAC speed/duplex
3737                  * configuration.  So we only need to configure Collision
3738                  * Distance in the MAC.  Otherwise, we need to force
3739                  * speed/duplex on the MAC to the current PHY speed/duplex
3740                  * settings.
3741                  */
3742                 if (hw->mac_type >= e1000_82544)
3743                         e1000_config_collision_dist(hw);
3744                 else {
3745                         ret_val = e1000_config_mac_to_phy(hw);
3746                         if (ret_val < 0) {
3747                                 DEBUGOUT
3748                                     ("Error configuring MAC to PHY settings\n");
3749                                 return ret_val;
3750                         }
3751                 }
3752
3753                 /* Configure Flow Control now that Auto-Neg has completed. First, we
3754                  * need to restore the desired flow control settings because we may
3755                  * have had to re-autoneg with a different link partner.
3756                  */
3757                 ret_val = e1000_config_fc_after_link_up(hw);
3758                 if (ret_val < 0) {
3759                         DEBUGOUT("Error configuring flow control\n");
3760                         return ret_val;
3761                 }
3762
3763                 /* At this point we know that we are on copper and we have
3764                  * auto-negotiated link.  These are conditions for checking the link
3765                  * parter capability register.  We use the link partner capability to
3766                  * determine if TBI Compatibility needs to be turned on or off.  If
3767                  * the link partner advertises any speed in addition to Gigabit, then
3768                  * we assume that they are GMII-based, and TBI compatibility is not
3769                  * needed. If no other speeds are advertised, we assume the link
3770                  * partner is TBI-based, and we turn on TBI Compatibility.
3771                  */
3772                 if (hw->tbi_compatibility_en) {
3773                         if (e1000_read_phy_reg
3774                             (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3775                                 DEBUGOUT("PHY Read Error\n");
3776                                 return -E1000_ERR_PHY;
3777                         }
3778                         if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3779                                              NWAY_LPAR_10T_FD_CAPS |
3780                                              NWAY_LPAR_100TX_HD_CAPS |
3781                                              NWAY_LPAR_100TX_FD_CAPS |
3782                                              NWAY_LPAR_100T4_CAPS)) {
3783                                 /* If our link partner advertises anything in addition to
3784                                  * gigabit, we do not need to enable TBI compatibility.
3785                                  */
3786                                 if (hw->tbi_compatibility_on) {
3787                                         /* If we previously were in the mode, turn it off. */
3788                                         rctl = E1000_READ_REG(hw, RCTL);
3789                                         rctl &= ~E1000_RCTL_SBP;
3790                                         E1000_WRITE_REG(hw, RCTL, rctl);
3791                                         hw->tbi_compatibility_on = false;
3792                                 }
3793                         } else {
3794                                 /* If TBI compatibility is was previously off, turn it on. For
3795                                  * compatibility with a TBI link partner, we will store bad
3796                                  * packets. Some frames have an additional byte on the end and
3797                                  * will look like CRC errors to to the hardware.
3798                                  */
3799                                 if (!hw->tbi_compatibility_on) {
3800                                         hw->tbi_compatibility_on = true;
3801                                         rctl = E1000_READ_REG(hw, RCTL);
3802                                         rctl |= E1000_RCTL_SBP;
3803                                         E1000_WRITE_REG(hw, RCTL, rctl);
3804                                 }
3805                         }
3806                 }
3807         }
3808         /* If we don't have link (auto-negotiation failed or link partner cannot
3809          * auto-negotiate), the cable is plugged in (we have signal), and our
3810          * link partner is not trying to auto-negotiate with us (we are receiving
3811          * idles or data), we need to force link up. We also need to give
3812          * auto-negotiation time to complete, in case the cable was just plugged
3813          * in. The autoneg_failed flag does this.
3814          */
3815         else if ((hw->media_type == e1000_media_type_fiber) &&
3816                  (!(status & E1000_STATUS_LU)) &&
3817                  ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3818                  (!(rxcw & E1000_RXCW_C))) {
3819                 if (hw->autoneg_failed == 0) {
3820                         hw->autoneg_failed = 1;
3821                         return 0;
3822                 }
3823                 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3824
3825                 /* Disable auto-negotiation in the TXCW register */
3826                 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3827
3828                 /* Force link-up and also force full-duplex. */
3829                 ctrl = E1000_READ_REG(hw, CTRL);
3830                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3831                 E1000_WRITE_REG(hw, CTRL, ctrl);
3832
3833                 /* Configure Flow Control after forcing link up. */
3834                 ret_val = e1000_config_fc_after_link_up(hw);
3835                 if (ret_val < 0) {
3836                         DEBUGOUT("Error configuring flow control\n");
3837                         return ret_val;
3838                 }
3839         }
3840         /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3841          * auto-negotiation in the TXCW register and disable forced link in the
3842          * Device Control register in an attempt to auto-negotiate with our link
3843          * partner.
3844          */
3845         else if ((hw->media_type == e1000_media_type_fiber) &&
3846                  (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3847                 DEBUGOUT
3848                     ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3849                 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3850                 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3851         }
3852         return 0;
3853 }
3854
3855 /******************************************************************************
3856 * Configure the MAC-to-PHY interface for 10/100Mbps
3857 *
3858 * hw - Struct containing variables accessed by shared code
3859 ******************************************************************************/
3860 static int32_t
3861 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
3862 {
3863         int32_t ret_val = E1000_SUCCESS;
3864         uint32_t tipg;
3865         uint16_t reg_data;
3866
3867         DEBUGFUNC();
3868
3869         reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
3870         ret_val = e1000_write_kmrn_reg(hw,
3871                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3872         if (ret_val)
3873                 return ret_val;
3874
3875         /* Configure Transmit Inter-Packet Gap */
3876         tipg = E1000_READ_REG(hw, TIPG);
3877         tipg &= ~E1000_TIPG_IPGT_MASK;
3878         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
3879         E1000_WRITE_REG(hw, TIPG, tipg);
3880
3881         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3882
3883         if (ret_val)
3884                 return ret_val;
3885
3886         if (duplex == HALF_DUPLEX)
3887                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
3888         else
3889                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3890
3891         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3892
3893         return ret_val;
3894 }
3895
3896 static int32_t
3897 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
3898 {
3899         int32_t ret_val = E1000_SUCCESS;
3900         uint16_t reg_data;
3901         uint32_t tipg;
3902
3903         DEBUGFUNC();
3904
3905         reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
3906         ret_val = e1000_write_kmrn_reg(hw,
3907                         E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3908         if (ret_val)
3909                 return ret_val;
3910
3911         /* Configure Transmit Inter-Packet Gap */
3912         tipg = E1000_READ_REG(hw, TIPG);
3913         tipg &= ~E1000_TIPG_IPGT_MASK;
3914         tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
3915         E1000_WRITE_REG(hw, TIPG, tipg);
3916
3917         ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3918
3919         if (ret_val)
3920                 return ret_val;
3921
3922         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3923         ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3924
3925         return ret_val;
3926 }
3927
3928 /******************************************************************************
3929  * Detects the current speed and duplex settings of the hardware.
3930  *
3931  * hw - Struct containing variables accessed by shared code
3932  * speed - Speed of the connection
3933  * duplex - Duplex setting of the connection
3934  *****************************************************************************/
3935 static int
3936 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
3937                 uint16_t *duplex)
3938 {
3939         uint32_t status;
3940         int32_t ret_val;
3941         uint16_t phy_data;
3942
3943         DEBUGFUNC();
3944
3945         if (hw->mac_type >= e1000_82543) {
3946                 status = E1000_READ_REG(hw, STATUS);
3947                 if (status & E1000_STATUS_SPEED_1000) {
3948                         *speed = SPEED_1000;
3949                         DEBUGOUT("1000 Mbs, ");
3950                 } else if (status & E1000_STATUS_SPEED_100) {
3951                         *speed = SPEED_100;
3952                         DEBUGOUT("100 Mbs, ");
3953                 } else {
3954                         *speed = SPEED_10;
3955                         DEBUGOUT("10 Mbs, ");
3956                 }
3957
3958                 if (status & E1000_STATUS_FD) {
3959                         *duplex = FULL_DUPLEX;
3960                         DEBUGOUT("Full Duplex\r\n");
3961                 } else {
3962                         *duplex = HALF_DUPLEX;
3963                         DEBUGOUT(" Half Duplex\r\n");
3964                 }
3965         } else {
3966                 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
3967                 *speed = SPEED_1000;
3968                 *duplex = FULL_DUPLEX;
3969         }
3970
3971         /* IGP01 PHY may advertise full duplex operation after speed downgrade
3972          * even if it is operating at half duplex.  Here we set the duplex
3973          * settings to match the duplex in the link partner's capabilities.
3974          */
3975         if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3976                 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3977                 if (ret_val)
3978                         return ret_val;
3979
3980                 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3981                         *duplex = HALF_DUPLEX;
3982                 else {
3983                         ret_val = e1000_read_phy_reg(hw,
3984                                         PHY_LP_ABILITY, &phy_data);
3985                         if (ret_val)
3986                                 return ret_val;
3987                         if ((*speed == SPEED_100 &&
3988                                 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
3989                                 || (*speed == SPEED_10
3990                                 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3991                                 *duplex = HALF_DUPLEX;
3992                 }
3993         }
3994
3995         if ((hw->mac_type == e1000_80003es2lan) &&
3996                 (hw->media_type == e1000_media_type_copper)) {
3997                 if (*speed == SPEED_1000)
3998                         ret_val = e1000_configure_kmrn_for_1000(hw);
3999                 else
4000                         ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
4001                 if (ret_val)
4002                         return ret_val;
4003         }
4004         return E1000_SUCCESS;
4005 }
4006
4007 /******************************************************************************
4008 * Blocks until autoneg completes or times out (~4.5 seconds)
4009 *
4010 * hw - Struct containing variables accessed by shared code
4011 ******************************************************************************/
4012 static int
4013 e1000_wait_autoneg(struct e1000_hw *hw)
4014 {
4015         uint16_t i;
4016         uint16_t phy_data;
4017
4018         DEBUGFUNC();
4019         DEBUGOUT("Waiting for Auto-Neg to complete.\n");
4020
4021         /* We will wait for autoneg to complete or timeout to expire. */
4022         for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
4023                 /* Read the MII Status Register and wait for Auto-Neg
4024                  * Complete bit to be set.
4025                  */
4026                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4027                         DEBUGOUT("PHY Read Error\n");
4028                         return -E1000_ERR_PHY;
4029                 }
4030                 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4031                         DEBUGOUT("PHY Read Error\n");
4032                         return -E1000_ERR_PHY;
4033                 }
4034                 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
4035                         DEBUGOUT("Auto-Neg complete.\n");
4036                         return 0;
4037                 }
4038                 mdelay(100);
4039         }
4040         DEBUGOUT("Auto-Neg timedout.\n");
4041         return -E1000_ERR_TIMEOUT;
4042 }
4043
4044 /******************************************************************************
4045 * Raises the Management Data Clock
4046 *
4047 * hw - Struct containing variables accessed by shared code
4048 * ctrl - Device control register's current value
4049 ******************************************************************************/
4050 static void
4051 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4052 {
4053         /* Raise the clock input to the Management Data Clock (by setting the MDC
4054          * bit), and then delay 2 microseconds.
4055          */
4056         E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
4057         E1000_WRITE_FLUSH(hw);
4058         udelay(2);
4059 }
4060
4061 /******************************************************************************
4062 * Lowers the Management Data Clock
4063 *
4064 * hw - Struct containing variables accessed by shared code
4065 * ctrl - Device control register's current value
4066 ******************************************************************************/
4067 static void
4068 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4069 {
4070         /* Lower the clock input to the Management Data Clock (by clearing the MDC
4071          * bit), and then delay 2 microseconds.
4072          */
4073         E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
4074         E1000_WRITE_FLUSH(hw);
4075         udelay(2);
4076 }
4077
4078 /******************************************************************************
4079 * Shifts data bits out to the PHY
4080 *
4081 * hw - Struct containing variables accessed by shared code
4082 * data - Data to send out to the PHY
4083 * count - Number of bits to shift out
4084 *
4085 * Bits are shifted out in MSB to LSB order.
4086 ******************************************************************************/
4087 static void
4088 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
4089 {
4090         uint32_t ctrl;
4091         uint32_t mask;
4092
4093         /* We need to shift "count" number of bits out to the PHY. So, the value
4094          * in the "data" parameter will be shifted out to the PHY one bit at a
4095          * time. In order to do this, "data" must be broken down into bits.
4096          */
4097         mask = 0x01;
4098         mask <<= (count - 1);
4099
4100         ctrl = E1000_READ_REG(hw, CTRL);
4101
4102         /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
4103         ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4104
4105         while (mask) {
4106                 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4107                  * then raising and lowering the Management Data Clock. A "0" is
4108                  * shifted out to the PHY by setting the MDIO bit to "0" and then
4109                  * raising and lowering the clock.
4110                  */
4111                 if (data & mask)
4112                         ctrl |= E1000_CTRL_MDIO;
4113                 else
4114                         ctrl &= ~E1000_CTRL_MDIO;
4115
4116                 E1000_WRITE_REG(hw, CTRL, ctrl);
4117                 E1000_WRITE_FLUSH(hw);
4118
4119                 udelay(2);
4120
4121                 e1000_raise_mdi_clk(hw, &ctrl);
4122                 e1000_lower_mdi_clk(hw, &ctrl);
4123
4124                 mask = mask >> 1;
4125         }
4126 }
4127
4128 /******************************************************************************
4129 * Shifts data bits in from the PHY
4130 *
4131 * hw - Struct containing variables accessed by shared code
4132 *
4133 * Bits are shifted in in MSB to LSB order.
4134 ******************************************************************************/
4135 static uint16_t
4136 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4137 {
4138         uint32_t ctrl;
4139         uint16_t data = 0;
4140         uint8_t i;
4141
4142         /* In order to read a register from the PHY, we need to shift in a total
4143          * of 18 bits from the PHY. The first two bit (turnaround) times are used
4144          * to avoid contention on the MDIO pin when a read operation is performed.
4145          * These two bits are ignored by us and thrown away. Bits are "shifted in"
4146          * by raising the input to the Management Data Clock (setting the MDC bit),
4147          * and then reading the value of the MDIO bit.
4148          */
4149         ctrl = E1000_READ_REG(hw, CTRL);
4150
4151         /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4152         ctrl &= ~E1000_CTRL_MDIO_DIR;
4153         ctrl &= ~E1000_CTRL_MDIO;
4154
4155         E1000_WRITE_REG(hw, CTRL, ctrl);
4156         E1000_WRITE_FLUSH(hw);
4157
4158         /* Raise and Lower the clock before reading in the data. This accounts for
4159          * the turnaround bits. The first clock occurred when we clocked out the
4160          * last bit of the Register Address.
4161          */
4162         e1000_raise_mdi_clk(hw, &ctrl);
4163         e1000_lower_mdi_clk(hw, &ctrl);
4164
4165         for (data = 0, i = 0; i < 16; i++) {
4166                 data = data << 1;
4167                 e1000_raise_mdi_clk(hw, &ctrl);
4168                 ctrl = E1000_READ_REG(hw, CTRL);
4169                 /* Check to see if we shifted in a "1". */
4170                 if (ctrl & E1000_CTRL_MDIO)
4171                         data |= 1;
4172                 e1000_lower_mdi_clk(hw, &ctrl);
4173         }
4174
4175         e1000_raise_mdi_clk(hw, &ctrl);
4176         e1000_lower_mdi_clk(hw, &ctrl);
4177
4178         return data;
4179 }
4180
4181 /*****************************************************************************
4182 * Reads the value from a PHY register
4183 *
4184 * hw - Struct containing variables accessed by shared code
4185 * reg_addr - address of the PHY register to read
4186 ******************************************************************************/
4187 static int
4188 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4189 {
4190         uint32_t i;
4191         uint32_t mdic = 0;
4192         const uint32_t phy_addr = 1;
4193
4194         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4195                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4196                 return -E1000_ERR_PARAM;
4197         }
4198
4199         if (hw->mac_type > e1000_82543) {
4200                 /* Set up Op-code, Phy Address, and register address in the MDI
4201                  * Control register.  The MAC will take care of interfacing with the
4202                  * PHY to retrieve the desired data.
4203                  */
4204                 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4205                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4206                         (E1000_MDIC_OP_READ));
4207
4208                 E1000_WRITE_REG(hw, MDIC, mdic);
4209
4210                 /* Poll the ready bit to see if the MDI read completed */
4211                 for (i = 0; i < 64; i++) {
4212                         udelay(10);
4213                         mdic = E1000_READ_REG(hw, MDIC);
4214                         if (mdic & E1000_MDIC_READY)
4215                                 break;
4216                 }
4217                 if (!(mdic & E1000_MDIC_READY)) {
4218                         DEBUGOUT("MDI Read did not complete\n");
4219                         return -E1000_ERR_PHY;
4220                 }
4221                 if (mdic & E1000_MDIC_ERROR) {
4222                         DEBUGOUT("MDI Error\n");
4223                         return -E1000_ERR_PHY;
4224                 }
4225                 *phy_data = (uint16_t) mdic;
4226         } else {
4227                 /* We must first send a preamble through the MDIO pin to signal the
4228                  * beginning of an MII instruction.  This is done by sending 32
4229                  * consecutive "1" bits.
4230                  */
4231                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4232
4233                 /* Now combine the next few fields that are required for a read
4234                  * operation.  We use this method instead of calling the
4235                  * e1000_shift_out_mdi_bits routine five different times. The format of
4236                  * a MII read instruction consists of a shift out of 14 bits and is
4237                  * defined as follows:
4238                  *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4239                  * followed by a shift in of 18 bits.  This first two bits shifted in
4240                  * are TurnAround bits used to avoid contention on the MDIO pin when a
4241                  * READ operation is performed.  These two bits are thrown away
4242                  * followed by a shift in of 16 bits which contains the desired data.
4243                  */
4244                 mdic = ((reg_addr) | (phy_addr << 5) |
4245                         (PHY_OP_READ << 10) | (PHY_SOF << 12));
4246
4247                 e1000_shift_out_mdi_bits(hw, mdic, 14);
4248
4249                 /* Now that we've shifted out the read command to the MII, we need to
4250                  * "shift in" the 16-bit value (18 total bits) of the requested PHY
4251                  * register address.
4252                  */
4253                 *phy_data = e1000_shift_in_mdi_bits(hw);
4254         }
4255         return 0;
4256 }
4257
4258 /******************************************************************************
4259 * Writes a value to a PHY register
4260 *
4261 * hw - Struct containing variables accessed by shared code
4262 * reg_addr - address of the PHY register to write
4263 * data - data to write to the PHY
4264 ******************************************************************************/
4265 static int
4266 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4267 {
4268         uint32_t i;
4269         uint32_t mdic = 0;
4270         const uint32_t phy_addr = 1;
4271
4272         if (reg_addr > MAX_PHY_REG_ADDRESS) {
4273                 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4274                 return -E1000_ERR_PARAM;
4275         }
4276
4277         if (hw->mac_type > e1000_82543) {
4278                 /* Set up Op-code, Phy Address, register address, and data intended
4279                  * for the PHY register in the MDI Control register.  The MAC will take
4280                  * care of interfacing with the PHY to send the desired data.
4281                  */
4282                 mdic = (((uint32_t) phy_data) |
4283                         (reg_addr << E1000_MDIC_REG_SHIFT) |
4284                         (phy_addr << E1000_MDIC_PHY_SHIFT) |
4285                         (E1000_MDIC_OP_WRITE));
4286
4287                 E1000_WRITE_REG(hw, MDIC, mdic);
4288
4289                 /* Poll the ready bit to see if the MDI read completed */
4290                 for (i = 0; i < 64; i++) {
4291                         udelay(10);
4292                         mdic = E1000_READ_REG(hw, MDIC);
4293                         if (mdic & E1000_MDIC_READY)
4294                                 break;
4295                 }
4296                 if (!(mdic & E1000_MDIC_READY)) {
4297                         DEBUGOUT("MDI Write did not complete\n");
4298                         return -E1000_ERR_PHY;
4299                 }
4300         } else {
4301                 /* We'll need to use the SW defined pins to shift the write command
4302                  * out to the PHY. We first send a preamble to the PHY to signal the
4303                  * beginning of the MII instruction.  This is done by sending 32
4304                  * consecutive "1" bits.
4305                  */
4306                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4307
4308                 /* Now combine the remaining required fields that will indicate a
4309                  * write operation. We use this method instead of calling the
4310                  * e1000_shift_out_mdi_bits routine for each field in the command. The
4311                  * format of a MII write instruction is as follows:
4312                  * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4313                  */
4314                 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4315                         (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4316                 mdic <<= 16;
4317                 mdic |= (uint32_t) phy_data;
4318
4319                 e1000_shift_out_mdi_bits(hw, mdic, 32);
4320         }
4321         return 0;
4322 }
4323
4324 /******************************************************************************
4325  * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4326  * Returning E1000_BLK_PHY_RESET isn't necessarily an error.  But it's up to
4327  * the caller to figure out how to deal with it.
4328  *
4329  * hw - Struct containing variables accessed by shared code
4330  *
4331  * returns: - E1000_BLK_PHY_RESET
4332  *            E1000_SUCCESS
4333  *
4334  *****************************************************************************/
4335 int32_t
4336 e1000_check_phy_reset_block(struct e1000_hw *hw)
4337 {
4338         uint32_t manc = 0;
4339         uint32_t fwsm = 0;
4340
4341         if (hw->mac_type == e1000_ich8lan) {
4342                 fwsm = E1000_READ_REG(hw, FWSM);
4343                 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4344                                                 : E1000_BLK_PHY_RESET;
4345         }
4346
4347         if (hw->mac_type > e1000_82547_rev_2)
4348                 manc = E1000_READ_REG(hw, MANC);
4349         return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4350                 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4351 }
4352
4353 /***************************************************************************
4354  * Checks if the PHY configuration is done
4355  *
4356  * hw: Struct containing variables accessed by shared code
4357  *
4358  * returns: - E1000_ERR_RESET if fail to reset MAC
4359  *            E1000_SUCCESS at any other case.
4360  *
4361  ***************************************************************************/
4362 static int32_t
4363 e1000_get_phy_cfg_done(struct e1000_hw *hw)
4364 {
4365         int32_t timeout = PHY_CFG_TIMEOUT;
4366         uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4367
4368         DEBUGFUNC();
4369
4370         switch (hw->mac_type) {
4371         default:
4372                 mdelay(10);
4373                 break;
4374
4375         case e1000_80003es2lan:
4376                 /* Separate *_CFG_DONE_* bit for each port */
4377                 if (e1000_is_second_port(hw))
4378                         cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
4379                 /* Fall Through */
4380
4381         case e1000_82571:
4382         case e1000_82572:
4383         case e1000_igb:
4384                 while (timeout) {
4385                         if (hw->mac_type == e1000_igb) {
4386                                 if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
4387                                         break;
4388                         } else {
4389                                 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4390                                         break;
4391                         }
4392                         mdelay(1);
4393                         timeout--;
4394                 }
4395                 if (!timeout) {
4396                         DEBUGOUT("MNG configuration cycle has not "
4397                                         "completed.\n");
4398                         return -E1000_ERR_RESET;
4399                 }
4400                 break;
4401         }
4402
4403         return E1000_SUCCESS;
4404 }
4405
4406 /******************************************************************************
4407 * Returns the PHY to the power-on reset state
4408 *
4409 * hw - Struct containing variables accessed by shared code
4410 ******************************************************************************/
4411 int32_t
4412 e1000_phy_hw_reset(struct e1000_hw *hw)
4413 {
4414         uint16_t swfw = E1000_SWFW_PHY0_SM;
4415         uint32_t ctrl, ctrl_ext;
4416         uint32_t led_ctrl;
4417         int32_t ret_val;
4418
4419         DEBUGFUNC();
4420
4421         /* In the case of the phy reset being blocked, it's not an error, we
4422          * simply return success without performing the reset. */
4423         ret_val = e1000_check_phy_reset_block(hw);
4424         if (ret_val)
4425                 return E1000_SUCCESS;
4426
4427         DEBUGOUT("Resetting Phy...\n");
4428
4429         if (hw->mac_type > e1000_82543) {
4430                 if (e1000_is_second_port(hw))
4431                         swfw = E1000_SWFW_PHY1_SM;
4432
4433                 if (e1000_swfw_sync_acquire(hw, swfw)) {
4434                         DEBUGOUT("Unable to acquire swfw sync\n");
4435                         return -E1000_ERR_SWFW_SYNC;
4436                 }
4437
4438                 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4439                  * bit. Then, take it out of reset.
4440                  */
4441                 ctrl = E1000_READ_REG(hw, CTRL);
4442                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4443                 E1000_WRITE_FLUSH(hw);
4444
4445                 if (hw->mac_type < e1000_82571)
4446                         udelay(10);
4447                 else
4448                         udelay(100);
4449
4450                 E1000_WRITE_REG(hw, CTRL, ctrl);
4451                 E1000_WRITE_FLUSH(hw);
4452
4453                 if (hw->mac_type >= e1000_82571)
4454                         mdelay(10);
4455
4456         } else {
4457                 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4458                  * bit to put the PHY into reset. Then, take it out of reset.
4459                  */
4460                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4461                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4462                 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4463                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4464                 E1000_WRITE_FLUSH(hw);
4465                 mdelay(10);
4466                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4467                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4468                 E1000_WRITE_FLUSH(hw);
4469         }
4470         udelay(150);
4471
4472         if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4473                 /* Configure activity LED after PHY reset */
4474                 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4475                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4476                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4477                 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4478         }
4479
4480         e1000_swfw_sync_release(hw, swfw);
4481
4482         /* Wait for FW to finish PHY configuration. */
4483         ret_val = e1000_get_phy_cfg_done(hw);
4484         if (ret_val != E1000_SUCCESS)
4485                 return ret_val;
4486
4487         return ret_val;
4488 }
4489
4490 /******************************************************************************
4491  * IGP phy init script - initializes the GbE PHY
4492  *
4493  * hw - Struct containing variables accessed by shared code
4494  *****************************************************************************/
4495 static void
4496 e1000_phy_init_script(struct e1000_hw *hw)
4497 {
4498         uint32_t ret_val;
4499         uint16_t phy_saved_data;
4500         DEBUGFUNC();
4501
4502         if (hw->phy_init_script) {
4503                 mdelay(20);
4504
4505                 /* Save off the current value of register 0x2F5B to be
4506                  * restored at the end of this routine. */
4507                 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4508
4509                 /* Disabled the PHY transmitter */
4510                 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4511
4512                 mdelay(20);
4513
4514                 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4515
4516                 mdelay(5);
4517
4518                 switch (hw->mac_type) {
4519                 case e1000_82541:
4520                 case e1000_82547:
4521                         e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4522
4523                         e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4524
4525                         e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4526
4527                         e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4528
4529                         e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4530
4531                         e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4532
4533                         e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4534
4535                         e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4536
4537                         e1000_write_phy_reg(hw, 0x2010, 0x0008);
4538                         break;
4539
4540                 case e1000_82541_rev_2:
4541                 case e1000_82547_rev_2:
4542                         e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4543                         break;
4544                 default:
4545                         break;
4546                 }
4547
4548                 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4549
4550                 mdelay(20);
4551
4552                 /* Now enable the transmitter */
4553                 if (!ret_val)
4554                         e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
4555
4556                 if (hw->mac_type == e1000_82547) {
4557                         uint16_t fused, fine, coarse;
4558
4559                         /* Move to analog registers page */
4560                         e1000_read_phy_reg(hw,
4561                                 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4562
4563                         if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4564                                 e1000_read_phy_reg(hw,
4565                                         IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4566
4567                                 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4568                                 coarse = fused
4569                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4570
4571                                 if (coarse >
4572                                         IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4573                                         coarse -=
4574                                         IGP01E1000_ANALOG_FUSE_COARSE_10;
4575                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4576                                 } else if (coarse
4577                                         == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4578                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4579
4580                                 fused = (fused
4581                                         & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4582                                         (fine
4583                                         & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4584                                         (coarse
4585                                         & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4586
4587                                 e1000_write_phy_reg(hw,
4588                                         IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4589                                 e1000_write_phy_reg(hw,
4590                                         IGP01E1000_ANALOG_FUSE_BYPASS,
4591                                 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4592                         }
4593                 }
4594         }
4595 }
4596
4597 /******************************************************************************
4598 * Resets the PHY
4599 *
4600 * hw - Struct containing variables accessed by shared code
4601 *
4602 * Sets bit 15 of the MII Control register
4603 ******************************************************************************/
4604 int32_t
4605 e1000_phy_reset(struct e1000_hw *hw)
4606 {
4607         int32_t ret_val;
4608         uint16_t phy_data;
4609
4610         DEBUGFUNC();
4611
4612         /* In the case of the phy reset being blocked, it's not an error, we
4613          * simply return success without performing the reset. */
4614         ret_val = e1000_check_phy_reset_block(hw);
4615         if (ret_val)
4616                 return E1000_SUCCESS;
4617
4618         switch (hw->phy_type) {
4619         case e1000_phy_igp:
4620         case e1000_phy_igp_2:
4621         case e1000_phy_igp_3:
4622         case e1000_phy_ife:
4623         case e1000_phy_igb:
4624                 ret_val = e1000_phy_hw_reset(hw);
4625                 if (ret_val)
4626                         return ret_val;
4627                 break;
4628         default:
4629                 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4630                 if (ret_val)
4631                         return ret_val;
4632
4633                 phy_data |= MII_CR_RESET;
4634                 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4635                 if (ret_val)
4636                         return ret_val;
4637
4638                 udelay(1);
4639                 break;
4640         }
4641
4642         if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4643                 e1000_phy_init_script(hw);
4644
4645         return E1000_SUCCESS;
4646 }
4647
4648 static int e1000_set_phy_type (struct e1000_hw *hw)
4649 {
4650         DEBUGFUNC ();
4651
4652         if (hw->mac_type == e1000_undefined)
4653                 return -E1000_ERR_PHY_TYPE;
4654
4655         switch (hw->phy_id) {
4656         case M88E1000_E_PHY_ID:
4657         case M88E1000_I_PHY_ID:
4658         case M88E1011_I_PHY_ID:
4659         case M88E1111_I_PHY_ID:
4660                 hw->phy_type = e1000_phy_m88;
4661                 break;
4662         case IGP01E1000_I_PHY_ID:
4663                 if (hw->mac_type == e1000_82541 ||
4664                         hw->mac_type == e1000_82541_rev_2 ||
4665                         hw->mac_type == e1000_82547 ||
4666                         hw->mac_type == e1000_82547_rev_2) {
4667                         hw->phy_type = e1000_phy_igp;
4668                         break;
4669                 }
4670         case IGP03E1000_E_PHY_ID:
4671                 hw->phy_type = e1000_phy_igp_3;
4672                 break;
4673         case IFE_E_PHY_ID:
4674         case IFE_PLUS_E_PHY_ID:
4675         case IFE_C_E_PHY_ID:
4676                 hw->phy_type = e1000_phy_ife;
4677                 break;
4678         case GG82563_E_PHY_ID:
4679                 if (hw->mac_type == e1000_80003es2lan) {
4680                         hw->phy_type = e1000_phy_gg82563;
4681                         break;
4682                 }
4683         case BME1000_E_PHY_ID:
4684                 hw->phy_type = e1000_phy_bm;
4685                 break;
4686         case I210_I_PHY_ID:
4687                 hw->phy_type = e1000_phy_igb;
4688                 break;
4689                 /* Fall Through */
4690         default:
4691                 /* Should never have loaded on this device */
4692                 hw->phy_type = e1000_phy_undefined;
4693                 return -E1000_ERR_PHY_TYPE;
4694         }
4695
4696         return E1000_SUCCESS;
4697 }
4698
4699 /******************************************************************************
4700 * Probes the expected PHY address for known PHY IDs
4701 *
4702 * hw - Struct containing variables accessed by shared code
4703 ******************************************************************************/
4704 static int32_t
4705 e1000_detect_gig_phy(struct e1000_hw *hw)
4706 {
4707         int32_t phy_init_status, ret_val;
4708         uint16_t phy_id_high, phy_id_low;
4709         bool match = false;
4710
4711         DEBUGFUNC();
4712
4713         /* The 82571 firmware may still be configuring the PHY.  In this
4714          * case, we cannot access the PHY until the configuration is done.  So
4715          * we explicitly set the PHY values. */
4716         if (hw->mac_type == e1000_82571 ||
4717                 hw->mac_type == e1000_82572) {
4718                 hw->phy_id = IGP01E1000_I_PHY_ID;
4719                 hw->phy_type = e1000_phy_igp_2;
4720                 return E1000_SUCCESS;
4721         }
4722
4723         /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4724          * work- around that forces PHY page 0 to be set or the reads fail.
4725          * The rest of the code in this routine uses e1000_read_phy_reg to
4726          * read the PHY ID.  So for ESB-2 we need to have this set so our
4727          * reads won't fail.  If the attached PHY is not a e1000_phy_gg82563,
4728          * the routines below will figure this out as well. */
4729         if (hw->mac_type == e1000_80003es2lan)
4730                 hw->phy_type = e1000_phy_gg82563;
4731
4732         /* Read the PHY ID Registers to identify which PHY is onboard. */
4733         ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4734         if (ret_val)
4735                 return ret_val;
4736
4737         hw->phy_id = (uint32_t) (phy_id_high << 16);
4738         udelay(20);
4739         ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4740         if (ret_val)
4741                 return ret_val;
4742
4743         hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4744         hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4745
4746         switch (hw->mac_type) {
4747         case e1000_82543:
4748                 if (hw->phy_id == M88E1000_E_PHY_ID)
4749                         match = true;
4750                 break;
4751         case e1000_82544:
4752                 if (hw->phy_id == M88E1000_I_PHY_ID)
4753                         match = true;
4754                 break;
4755         case e1000_82540:
4756         case e1000_82545:
4757         case e1000_82545_rev_3:
4758         case e1000_82546:
4759         case e1000_82546_rev_3:
4760                 if (hw->phy_id == M88E1011_I_PHY_ID)
4761                         match = true;
4762                 break;
4763         case e1000_82541:
4764         case e1000_82541_rev_2:
4765         case e1000_82547:
4766         case e1000_82547_rev_2:
4767                 if(hw->phy_id == IGP01E1000_I_PHY_ID)
4768                         match = true;
4769
4770                 break;
4771         case e1000_82573:
4772                 if (hw->phy_id == M88E1111_I_PHY_ID)
4773                         match = true;
4774                 break;
4775         case e1000_82574:
4776                 if (hw->phy_id == BME1000_E_PHY_ID)
4777                         match = true;
4778                 break;
4779         case e1000_80003es2lan:
4780                 if (hw->phy_id == GG82563_E_PHY_ID)
4781                         match = true;
4782                 break;
4783         case e1000_ich8lan:
4784                 if (hw->phy_id == IGP03E1000_E_PHY_ID)
4785                         match = true;
4786                 if (hw->phy_id == IFE_E_PHY_ID)
4787                         match = true;
4788                 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4789                         match = true;
4790                 if (hw->phy_id == IFE_C_E_PHY_ID)
4791                         match = true;
4792                 break;
4793         case e1000_igb:
4794                 if (hw->phy_id == I210_I_PHY_ID)
4795                         match = true;
4796                 break;
4797         default:
4798                 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4799                 return -E1000_ERR_CONFIG;
4800         }
4801
4802         phy_init_status = e1000_set_phy_type(hw);
4803
4804         if ((match) && (phy_init_status == E1000_SUCCESS)) {
4805                 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4806                 return 0;
4807         }
4808         DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4809         return -E1000_ERR_PHY;
4810 }
4811
4812 /*****************************************************************************
4813  * Set media type and TBI compatibility.
4814  *
4815  * hw - Struct containing variables accessed by shared code
4816  * **************************************************************************/
4817 void
4818 e1000_set_media_type(struct e1000_hw *hw)
4819 {
4820         uint32_t status;
4821
4822         DEBUGFUNC();
4823
4824         if (hw->mac_type != e1000_82543) {
4825                 /* tbi_compatibility is only valid on 82543 */
4826                 hw->tbi_compatibility_en = false;
4827         }
4828
4829         switch (hw->device_id) {
4830         case E1000_DEV_ID_82545GM_SERDES:
4831         case E1000_DEV_ID_82546GB_SERDES:
4832         case E1000_DEV_ID_82571EB_SERDES:
4833         case E1000_DEV_ID_82571EB_SERDES_DUAL:
4834         case E1000_DEV_ID_82571EB_SERDES_QUAD:
4835         case E1000_DEV_ID_82572EI_SERDES:
4836         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
4837                 hw->media_type = e1000_media_type_internal_serdes;
4838                 break;
4839         default:
4840                 switch (hw->mac_type) {
4841                 case e1000_82542_rev2_0:
4842                 case e1000_82542_rev2_1:
4843                         hw->media_type = e1000_media_type_fiber;
4844                         break;
4845                 case e1000_ich8lan:
4846                 case e1000_82573:
4847                 case e1000_82574:
4848                 case e1000_igb:
4849                         /* The STATUS_TBIMODE bit is reserved or reused
4850                          * for the this device.
4851                          */
4852                         hw->media_type = e1000_media_type_copper;
4853                         break;
4854                 default:
4855                         status = E1000_READ_REG(hw, STATUS);
4856                         if (status & E1000_STATUS_TBIMODE) {
4857                                 hw->media_type = e1000_media_type_fiber;
4858                                 /* tbi_compatibility not valid on fiber */
4859                                 hw->tbi_compatibility_en = false;
4860                         } else {
4861                                 hw->media_type = e1000_media_type_copper;
4862                         }
4863                         break;
4864                 }
4865         }
4866 }
4867
4868 /**
4869  * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4870  *
4871  * e1000_sw_init initializes the Adapter private data structure.
4872  * Fields are initialized based on PCI device information and
4873  * OS network device settings (MTU size).
4874  **/
4875
4876 static int
4877 e1000_sw_init(struct eth_device *nic)
4878 {
4879         struct e1000_hw *hw = (typeof(hw)) nic->priv;
4880         int result;
4881
4882         /* PCI config space info */
4883         pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
4884         pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
4885         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
4886                              &hw->subsystem_vendor_id);
4887         pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
4888
4889         pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
4890         pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
4891
4892         /* identify the MAC */
4893         result = e1000_set_mac_type(hw);
4894         if (result) {
4895                 E1000_ERR(hw->nic, "Unknown MAC Type\n");
4896                 return result;
4897         }
4898
4899         switch (hw->mac_type) {
4900         default:
4901                 break;
4902         case e1000_82541:
4903         case e1000_82547:
4904         case e1000_82541_rev_2:
4905         case e1000_82547_rev_2:
4906                 hw->phy_init_script = 1;
4907                 break;
4908         }
4909
4910         /* flow control settings */
4911         hw->fc_high_water = E1000_FC_HIGH_THRESH;
4912         hw->fc_low_water = E1000_FC_LOW_THRESH;
4913         hw->fc_pause_time = E1000_FC_PAUSE_TIME;
4914         hw->fc_send_xon = 1;
4915
4916         /* Media type - copper or fiber */
4917         hw->tbi_compatibility_en = true;
4918         e1000_set_media_type(hw);
4919
4920         if (hw->mac_type >= e1000_82543) {
4921                 uint32_t status = E1000_READ_REG(hw, STATUS);
4922
4923                 if (status & E1000_STATUS_TBIMODE) {
4924                         DEBUGOUT("fiber interface\n");
4925                         hw->media_type = e1000_media_type_fiber;
4926                 } else {
4927                         DEBUGOUT("copper interface\n");
4928                         hw->media_type = e1000_media_type_copper;
4929                 }
4930         } else {
4931                 hw->media_type = e1000_media_type_fiber;
4932         }
4933
4934         hw->wait_autoneg_complete = true;
4935         if (hw->mac_type < e1000_82543)
4936                 hw->report_tx_early = 0;
4937         else
4938                 hw->report_tx_early = 1;
4939
4940         return E1000_SUCCESS;
4941 }
4942
4943 void
4944 fill_rx(struct e1000_hw *hw)
4945 {
4946         struct e1000_rx_desc *rd;
4947         unsigned long flush_start, flush_end;
4948
4949         rx_last = rx_tail;
4950         rd = rx_base + rx_tail;
4951         rx_tail = (rx_tail + 1) % 8;
4952         memset(rd, 0, 16);
4953         rd->buffer_addr = cpu_to_le64((unsigned long)packet);
4954
4955         /*
4956          * Make sure there are no stale data in WB over this area, which
4957          * might get written into the memory while the e1000 also writes
4958          * into the same memory area.
4959          */
4960         invalidate_dcache_range((unsigned long)packet,
4961                                 (unsigned long)packet + 4096);
4962         /* Dump the DMA descriptor into RAM. */
4963         flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
4964         flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
4965         flush_dcache_range(flush_start, flush_end);
4966
4967         E1000_WRITE_REG(hw, RDT, rx_tail);
4968 }
4969
4970 /**
4971  * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
4972  * @adapter: board private structure
4973  *
4974  * Configure the Tx unit of the MAC after a reset.
4975  **/
4976
4977 static void
4978 e1000_configure_tx(struct e1000_hw *hw)
4979 {
4980         unsigned long tctl;
4981         unsigned long tipg, tarc;
4982         uint32_t ipgr1, ipgr2;
4983
4984         E1000_WRITE_REG(hw, TDBAL, (unsigned long)tx_base & 0xffffffff);
4985         E1000_WRITE_REG(hw, TDBAH, (unsigned long)tx_base >> 32);
4986
4987         E1000_WRITE_REG(hw, TDLEN, 128);
4988
4989         /* Setup the HW Tx Head and Tail descriptor pointers */
4990         E1000_WRITE_REG(hw, TDH, 0);
4991         E1000_WRITE_REG(hw, TDT, 0);
4992         tx_tail = 0;
4993
4994         /* Set the default values for the Tx Inter Packet Gap timer */
4995         if (hw->mac_type <= e1000_82547_rev_2 &&
4996             (hw->media_type == e1000_media_type_fiber ||
4997              hw->media_type == e1000_media_type_internal_serdes))
4998                 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
4999         else
5000                 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
5001
5002         /* Set the default values for the Tx Inter Packet Gap timer */
5003         switch (hw->mac_type) {
5004         case e1000_82542_rev2_0:
5005         case e1000_82542_rev2_1:
5006                 tipg = DEFAULT_82542_TIPG_IPGT;
5007                 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
5008                 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
5009                 break;
5010         case e1000_80003es2lan:
5011                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5012                 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
5013                 break;
5014         default:
5015                 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5016                 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
5017                 break;
5018         }
5019         tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
5020         tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
5021         E1000_WRITE_REG(hw, TIPG, tipg);
5022         /* Program the Transmit Control Register */
5023         tctl = E1000_READ_REG(hw, TCTL);
5024         tctl &= ~E1000_TCTL_CT;
5025         tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
5026             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
5027
5028         if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
5029                 tarc = E1000_READ_REG(hw, TARC0);
5030                 /* set the speed mode bit, we'll clear it if we're not at
5031                  * gigabit link later */
5032                 /* git bit can be set to 1*/
5033         } else if (hw->mac_type == e1000_80003es2lan) {
5034                 tarc = E1000_READ_REG(hw, TARC0);
5035                 tarc |= 1;
5036                 E1000_WRITE_REG(hw, TARC0, tarc);
5037                 tarc = E1000_READ_REG(hw, TARC1);
5038                 tarc |= 1;
5039                 E1000_WRITE_REG(hw, TARC1, tarc);
5040         }
5041
5042
5043         e1000_config_collision_dist(hw);
5044         /* Setup Transmit Descriptor Settings for eop descriptor */
5045         hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
5046
5047         /* Need to set up RS bit */
5048         if (hw->mac_type < e1000_82543)
5049                 hw->txd_cmd |= E1000_TXD_CMD_RPS;
5050         else
5051                 hw->txd_cmd |= E1000_TXD_CMD_RS;
5052
5053
5054         if (hw->mac_type == e1000_igb) {
5055                 E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
5056
5057                 uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL);
5058                 reg_txdctl |= 1 << 25;
5059                 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
5060                 mdelay(20);
5061         }
5062
5063
5064
5065         E1000_WRITE_REG(hw, TCTL, tctl);
5066
5067
5068 }
5069
5070 /**
5071  * e1000_setup_rctl - configure the receive control register
5072  * @adapter: Board private structure
5073  **/
5074 static void
5075 e1000_setup_rctl(struct e1000_hw *hw)
5076 {
5077         uint32_t rctl;
5078
5079         rctl = E1000_READ_REG(hw, RCTL);
5080
5081         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
5082
5083         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
5084                 | E1000_RCTL_RDMTS_HALF;        /* |
5085                         (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
5086
5087         if (hw->tbi_compatibility_on == 1)
5088                 rctl |= E1000_RCTL_SBP;
5089         else
5090                 rctl &= ~E1000_RCTL_SBP;
5091
5092         rctl &= ~(E1000_RCTL_SZ_4096);
5093                 rctl |= E1000_RCTL_SZ_2048;
5094                 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
5095         E1000_WRITE_REG(hw, RCTL, rctl);
5096 }
5097
5098 /**
5099  * e1000_configure_rx - Configure 8254x Receive Unit after Reset
5100  * @adapter: board private structure
5101  *
5102  * Configure the Rx unit of the MAC after a reset.
5103  **/
5104 static void
5105 e1000_configure_rx(struct e1000_hw *hw)
5106 {
5107         unsigned long rctl, ctrl_ext;
5108         rx_tail = 0;
5109         /* make sure receives are disabled while setting up the descriptors */
5110         rctl = E1000_READ_REG(hw, RCTL);
5111         E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
5112         if (hw->mac_type >= e1000_82540) {
5113                 /* Set the interrupt throttling rate.  Value is calculated
5114                  * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
5115 #define MAX_INTS_PER_SEC        8000
5116 #define DEFAULT_ITR             1000000000/(MAX_INTS_PER_SEC * 256)
5117                 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
5118         }
5119
5120         if (hw->mac_type >= e1000_82571) {
5121                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5122                 /* Reset delay timers after every interrupt */
5123                 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
5124                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5125                 E1000_WRITE_FLUSH(hw);
5126         }
5127         /* Setup the Base and Length of the Rx Descriptor Ring */
5128         E1000_WRITE_REG(hw, RDBAL, (unsigned long)rx_base & 0xffffffff);
5129         E1000_WRITE_REG(hw, RDBAH, (unsigned long)rx_base >> 32);
5130
5131         E1000_WRITE_REG(hw, RDLEN, 128);
5132
5133         /* Setup the HW Rx Head and Tail Descriptor Pointers */
5134         E1000_WRITE_REG(hw, RDH, 0);
5135         E1000_WRITE_REG(hw, RDT, 0);
5136         /* Enable Receives */
5137
5138         if (hw->mac_type == e1000_igb) {
5139
5140                 uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL);
5141                 reg_rxdctl |= 1 << 25;
5142                 E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl);
5143                 mdelay(20);
5144         }
5145
5146         E1000_WRITE_REG(hw, RCTL, rctl);
5147
5148         fill_rx(hw);
5149 }
5150
5151 /**************************************************************************
5152 POLL - Wait for a frame
5153 ***************************************************************************/
5154 static int
5155 e1000_poll(struct eth_device *nic)
5156 {
5157         struct e1000_hw *hw = nic->priv;
5158         struct e1000_rx_desc *rd;
5159         unsigned long inval_start, inval_end;
5160         uint32_t len;
5161
5162         /* return true if there's an ethernet packet ready to read */
5163         rd = rx_base + rx_last;
5164
5165         /* Re-load the descriptor from RAM. */
5166         inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
5167         inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5168         invalidate_dcache_range(inval_start, inval_end);
5169
5170         if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
5171                 return 0;
5172         /* DEBUGOUT("recv: packet len=%d\n", rd->length); */
5173         /* Packet received, make sure the data are re-loaded from RAM. */
5174         len = le32_to_cpu(rd->length);
5175         invalidate_dcache_range((unsigned long)packet,
5176                                 (unsigned long)packet +
5177                                 roundup(len, ARCH_DMA_MINALIGN));
5178         net_process_received_packet((uchar *)packet, len);
5179         fill_rx(hw);
5180         return 1;
5181 }
5182
5183 /**************************************************************************
5184 TRANSMIT - Transmit a frame
5185 ***************************************************************************/
5186 static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
5187 {
5188         void *nv_packet = (void *)txpacket;
5189         struct e1000_hw *hw = nic->priv;
5190         struct e1000_tx_desc *txp;
5191         int i = 0;
5192         unsigned long flush_start, flush_end;
5193
5194         txp = tx_base + tx_tail;
5195         tx_tail = (tx_tail + 1) % 8;
5196
5197         txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
5198         txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
5199         txp->upper.data = 0;
5200
5201         /* Dump the packet into RAM so e1000 can pick them. */
5202         flush_dcache_range((unsigned long)nv_packet,
5203                            (unsigned long)nv_packet +
5204                            roundup(length, ARCH_DMA_MINALIGN));
5205         /* Dump the descriptor into RAM as well. */
5206         flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
5207         flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
5208         flush_dcache_range(flush_start, flush_end);
5209
5210         E1000_WRITE_REG(hw, TDT, tx_tail);
5211
5212         E1000_WRITE_FLUSH(hw);
5213         while (1) {
5214                 invalidate_dcache_range(flush_start, flush_end);
5215                 if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)
5216                         break;
5217                 if (i++ > TOUT_LOOP) {
5218                         DEBUGOUT("e1000: tx timeout\n");
5219                         return 0;
5220                 }
5221                 udelay(10);     /* give the nic a chance to write to the register */
5222         }
5223         return 1;
5224 }
5225
5226 /*reset function*/
5227 static inline int
5228 e1000_reset(struct eth_device *nic)
5229 {
5230         struct e1000_hw *hw = nic->priv;
5231
5232         e1000_reset_hw(hw);
5233         if (hw->mac_type >= e1000_82544) {
5234                 E1000_WRITE_REG(hw, WUC, 0);
5235         }
5236         return e1000_init_hw(nic);
5237 }
5238
5239 /**************************************************************************
5240 DISABLE - Turn off ethernet interface
5241 ***************************************************************************/
5242 static void
5243 e1000_disable(struct eth_device *nic)
5244 {
5245         struct e1000_hw *hw = nic->priv;
5246
5247         /* Turn off the ethernet interface */
5248         E1000_WRITE_REG(hw, RCTL, 0);
5249         E1000_WRITE_REG(hw, TCTL, 0);
5250
5251         /* Clear the transmit ring */
5252         E1000_WRITE_REG(hw, TDH, 0);
5253         E1000_WRITE_REG(hw, TDT, 0);
5254
5255         /* Clear the receive ring */
5256         E1000_WRITE_REG(hw, RDH, 0);
5257         E1000_WRITE_REG(hw, RDT, 0);
5258
5259         /* put the card in its initial state */
5260 #if 0
5261         E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
5262 #endif
5263         mdelay(10);
5264
5265 }
5266
5267 /**************************************************************************
5268 INIT - set up ethernet interface(s)
5269 ***************************************************************************/
5270 static int
5271 e1000_init(struct eth_device *nic, bd_t * bis)
5272 {
5273         struct e1000_hw *hw = nic->priv;
5274         int ret_val = 0;
5275
5276         ret_val = e1000_reset(nic);
5277         if (ret_val < 0) {
5278                 if ((ret_val == -E1000_ERR_NOLINK) ||
5279                     (ret_val == -E1000_ERR_TIMEOUT)) {
5280                         E1000_ERR(hw->nic, "Valid Link not detected\n");
5281                 } else {
5282                         E1000_ERR(hw->nic, "Hardware Initialization Failed\n");
5283                 }
5284                 return 0;
5285         }
5286         e1000_configure_tx(hw);
5287         e1000_setup_rctl(hw);
5288         e1000_configure_rx(hw);
5289         return 1;
5290 }
5291
5292 /******************************************************************************
5293  * Gets the current PCI bus type of hardware
5294  *
5295  * hw - Struct containing variables accessed by shared code
5296  *****************************************************************************/
5297 void e1000_get_bus_type(struct e1000_hw *hw)
5298 {
5299         uint32_t status;
5300
5301         switch (hw->mac_type) {
5302         case e1000_82542_rev2_0:
5303         case e1000_82542_rev2_1:
5304                 hw->bus_type = e1000_bus_type_pci;
5305                 break;
5306         case e1000_82571:
5307         case e1000_82572:
5308         case e1000_82573:
5309         case e1000_82574:
5310         case e1000_80003es2lan:
5311         case e1000_ich8lan:
5312         case e1000_igb:
5313                 hw->bus_type = e1000_bus_type_pci_express;
5314                 break;
5315         default:
5316                 status = E1000_READ_REG(hw, STATUS);
5317                 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5318                                 e1000_bus_type_pcix : e1000_bus_type_pci;
5319                 break;
5320         }
5321 }
5322
5323 /* A list of all registered e1000 devices */
5324 static LIST_HEAD(e1000_hw_list);
5325
5326 /**************************************************************************
5327 PROBE - Look for an adapter, this routine's visible to the outside
5328 You should omit the last argument struct pci_device * for a non-PCI NIC
5329 ***************************************************************************/
5330 int
5331 e1000_initialize(bd_t * bis)
5332 {
5333         unsigned int i;
5334         pci_dev_t devno;
5335
5336         DEBUGFUNC();
5337
5338         /* Find and probe all the matching PCI devices */
5339         for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
5340                 u32 val;
5341
5342                 /*
5343                  * These will never get freed due to errors, this allows us to
5344                  * perform SPI EEPROM programming from U-boot, for example.
5345                  */
5346                 struct eth_device *nic = malloc(sizeof(*nic));
5347                 struct e1000_hw *hw = malloc(sizeof(*hw));
5348                 if (!nic || !hw) {
5349                         printf("e1000#%u: Out of Memory!\n", i);
5350                         free(nic);
5351                         free(hw);
5352                         continue;
5353                 }
5354
5355                 /* Make sure all of the fields are initially zeroed */
5356                 memset(nic, 0, sizeof(*nic));
5357                 memset(hw, 0, sizeof(*hw));
5358
5359                 /* Assign the passed-in values */
5360                 hw->cardnum = i;
5361                 hw->pdev = devno;
5362                 hw->nic = nic;
5363                 nic->priv = hw;
5364
5365                 /* Generate a card name */
5366                 sprintf(nic->name, "e1000#%u", hw->cardnum);
5367
5368                 /* Print a debug message with the IO base address */
5369                 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
5370                 E1000_DBG(nic, "iobase 0x%08x\n", val & 0xfffffff0);
5371
5372                 /* Try to enable I/O accesses and bus-mastering */
5373                 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
5374                 pci_write_config_dword(devno, PCI_COMMAND, val);
5375
5376                 /* Make sure it worked */
5377                 pci_read_config_dword(devno, PCI_COMMAND, &val);
5378                 if (!(val & PCI_COMMAND_MEMORY)) {
5379                         E1000_ERR(nic, "Can't enable I/O memory\n");
5380                         continue;
5381                 }
5382                 if (!(val & PCI_COMMAND_MASTER)) {
5383                         E1000_ERR(nic, "Can't enable bus-mastering\n");
5384                         continue;
5385                 }
5386
5387                 /* Are these variables needed? */
5388                 hw->fc = e1000_fc_default;
5389                 hw->original_fc = e1000_fc_default;
5390                 hw->autoneg_failed = 0;
5391                 hw->autoneg = 1;
5392                 hw->get_link_status = true;
5393 #ifndef CONFIG_E1000_NO_NVM
5394                 hw->eeprom_semaphore_present = true;
5395 #endif
5396                 hw->hw_addr = pci_map_bar(devno,        PCI_BASE_ADDRESS_0,
5397                                                         PCI_REGION_MEM);
5398                 hw->mac_type = e1000_undefined;
5399
5400                 /* MAC and Phy settings */
5401                 if (e1000_sw_init(nic) < 0) {
5402                         E1000_ERR(nic, "Software init failed\n");
5403                         continue;
5404                 }
5405                 if (e1000_check_phy_reset_block(hw))
5406                         E1000_ERR(nic, "PHY Reset is blocked!\n");
5407
5408                 /* Basic init was OK, reset the hardware and allow SPI access */
5409                 e1000_reset_hw(hw);
5410                 list_add_tail(&hw->list_node, &e1000_hw_list);
5411
5412 #ifndef CONFIG_E1000_NO_NVM
5413                 /* Validate the EEPROM and get chipset information */
5414 #if !defined(CONFIG_MVBC_1G)
5415                 if (e1000_init_eeprom_params(hw)) {
5416                         E1000_ERR(nic, "EEPROM is invalid!\n");
5417                         continue;
5418                 }
5419                 if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
5420                     e1000_validate_eeprom_checksum(hw))
5421                         continue;
5422 #endif
5423                 e1000_read_mac_addr(nic);
5424 #endif
5425                 e1000_get_bus_type(hw);
5426
5427 #ifndef CONFIG_E1000_NO_NVM
5428                 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n       ",
5429                        nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
5430                        nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
5431 #else
5432                 memset(nic->enetaddr, 0, 6);
5433                 printf("e1000: no NVM\n");
5434 #endif
5435
5436                 /* Set up the function pointers and register the device */
5437                 nic->init = e1000_init;
5438                 nic->recv = e1000_poll;
5439                 nic->send = e1000_transmit;
5440                 nic->halt = e1000_disable;
5441                 eth_register(nic);
5442         }
5443
5444         return i;
5445 }
5446
5447 struct e1000_hw *e1000_find_card(unsigned int cardnum)
5448 {
5449         struct e1000_hw *hw;
5450
5451         list_for_each_entry(hw, &e1000_hw_list, list_node)
5452                 if (hw->cardnum == cardnum)
5453                         return hw;
5454
5455         return NULL;
5456 }
5457
5458 #ifdef CONFIG_CMD_E1000
5459 static int do_e1000(cmd_tbl_t *cmdtp, int flag,
5460                 int argc, char * const argv[])
5461 {
5462         struct e1000_hw *hw;
5463
5464         if (argc < 3) {
5465                 cmd_usage(cmdtp);
5466                 return 1;
5467         }
5468
5469         /* Make sure we can find the requested e1000 card */
5470         hw = e1000_find_card(simple_strtoul(argv[1], NULL, 10));
5471         if (!hw) {
5472                 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
5473                 return 1;
5474         }
5475
5476         if (!strcmp(argv[2], "print-mac-address")) {
5477                 unsigned char *mac = hw->nic->enetaddr;
5478                 printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
5479                         mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
5480                 return 0;
5481         }
5482
5483 #ifdef CONFIG_E1000_SPI
5484         /* Handle the "SPI" subcommand */
5485         if (!strcmp(argv[2], "spi"))
5486                 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
5487 #endif
5488
5489         cmd_usage(cmdtp);
5490         return 1;
5491 }
5492
5493 U_BOOT_CMD(
5494         e1000, 7, 0, do_e1000,
5495         "Intel e1000 controller management",
5496         /*  */"<card#> print-mac-address\n"
5497 #ifdef CONFIG_E1000_SPI
5498         "e1000 <card#> spi show [<offset> [<length>]]\n"
5499         "e1000 <card#> spi dump <addr> <offset> <length>\n"
5500         "e1000 <card#> spi program <addr> <offset> <length>\n"
5501         "e1000 <card#> spi checksum [update]\n"
5502 #endif
5503         "       - Manage the Intel E1000 PCI device"
5504 );
5505 #endif /* not CONFIG_CMD_E1000 */