1 /**************************************************************************
2 Intel Pro 1000 for ppcboot/das-u-boot
3 Drivers are port from Intel's Linux driver e1000-4.3.15
4 and from Etherboot pro 1000 driver by mrakes at vivato dot net
5 tested on both gig copper and gig fiber boards
6 ***************************************************************************/
7 /*******************************************************************************
10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
12 * SPDX-License-Identifier: GPL-2.0+
15 Linux NICS <linux.nics@intel.com>
16 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
18 *******************************************************************************/
20 * Copyright (C) Archway Digital Solutions.
22 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
25 * Copyright (C) Linux Networx.
26 * Massive upgrade to work with the new intel gigabit NICs.
27 * <ebiederman at lnxi dot com>
29 * Copyright 2011 Freescale Semiconductor, Inc.
34 #define TOUT_LOOP 100000
36 #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
37 #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
39 #define E1000_DEFAULT_PCI_PBA 0x00000030
40 #define E1000_DEFAULT_PCIE_PBA 0x000a0026
42 /* NIC specific static variables go here */
44 /* Intel i210 needs the DMA descriptor rings aligned to 128b */
45 #define E1000_BUFFER_ALIGN 128
47 DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
48 DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
49 DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
52 static int rx_tail, rx_last;
54 static struct pci_device_id e1000_supported[] = {
55 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542},
56 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER},
57 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER},
58 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER},
59 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER},
60 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER},
61 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM},
62 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM},
63 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER},
64 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER},
65 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
66 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
67 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
68 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER},
69 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
70 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
71 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
73 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER},
74 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER },
75 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES },
76 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER},
77 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER},
78 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER},
79 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE},
80 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL},
81 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD},
82 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER},
83 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER},
84 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES},
85 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI},
86 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E},
87 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT},
88 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L},
89 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L},
90 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3},
91 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT},
92 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
93 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
94 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
95 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER},
96 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS},
97 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES},
98 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS},
99 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX},
104 /* Function forward declarations */
105 static int e1000_setup_link(struct eth_device *nic);
106 static int e1000_setup_fiber_link(struct eth_device *nic);
107 static int e1000_setup_copper_link(struct eth_device *nic);
108 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
109 static void e1000_config_collision_dist(struct e1000_hw *hw);
110 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
111 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
112 static int e1000_check_for_link(struct eth_device *nic);
113 static int e1000_wait_autoneg(struct e1000_hw *hw);
114 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
116 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
117 uint16_t * phy_data);
118 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
120 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
121 static int e1000_phy_reset(struct e1000_hw *hw);
122 static int e1000_detect_gig_phy(struct e1000_hw *hw);
123 static void e1000_set_media_type(struct e1000_hw *hw);
125 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
126 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
128 #ifndef CONFIG_E1000_NO_NVM
129 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
130 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
133 /******************************************************************************
134 * Raises the EEPROM's clock input.
136 * hw - Struct containing variables accessed by shared code
137 * eecd - EECD's current value
138 *****************************************************************************/
139 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
141 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
142 * wait 50 microseconds.
144 *eecd = *eecd | E1000_EECD_SK;
145 E1000_WRITE_REG(hw, EECD, *eecd);
146 E1000_WRITE_FLUSH(hw);
150 /******************************************************************************
151 * Lowers the EEPROM's clock input.
153 * hw - Struct containing variables accessed by shared code
154 * eecd - EECD's current value
155 *****************************************************************************/
156 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
158 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
159 * wait 50 microseconds.
161 *eecd = *eecd & ~E1000_EECD_SK;
162 E1000_WRITE_REG(hw, EECD, *eecd);
163 E1000_WRITE_FLUSH(hw);
167 /******************************************************************************
168 * Shift data bits out to the EEPROM.
170 * hw - Struct containing variables accessed by shared code
171 * data - data to send to the EEPROM
172 * count - number of bits to shift out
173 *****************************************************************************/
175 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
180 /* We need to shift "count" bits out to the EEPROM. So, value in the
181 * "data" parameter will be shifted out to the EEPROM one bit at a time.
182 * In order to do this, "data" must be broken down into bits.
184 mask = 0x01 << (count - 1);
185 eecd = E1000_READ_REG(hw, EECD);
186 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
188 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
189 * and then raising and then lowering the clock (the SK bit controls
190 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
191 * by setting "DI" to "0" and then raising and then lowering the clock.
193 eecd &= ~E1000_EECD_DI;
196 eecd |= E1000_EECD_DI;
198 E1000_WRITE_REG(hw, EECD, eecd);
199 E1000_WRITE_FLUSH(hw);
203 e1000_raise_ee_clk(hw, &eecd);
204 e1000_lower_ee_clk(hw, &eecd);
210 /* We leave the "DI" bit set to "0" when we leave this routine. */
211 eecd &= ~E1000_EECD_DI;
212 E1000_WRITE_REG(hw, EECD, eecd);
215 /******************************************************************************
216 * Shift data bits in from the EEPROM
218 * hw - Struct containing variables accessed by shared code
219 *****************************************************************************/
221 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
227 /* In order to read a register from the EEPROM, we need to shift 'count'
228 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
229 * input to the EEPROM (setting the SK bit), and then reading the
230 * value of the "DO" bit. During this "shifting in" process the
231 * "DI" bit should always be clear.
234 eecd = E1000_READ_REG(hw, EECD);
236 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
239 for (i = 0; i < count; i++) {
241 e1000_raise_ee_clk(hw, &eecd);
243 eecd = E1000_READ_REG(hw, EECD);
245 eecd &= ~(E1000_EECD_DI);
246 if (eecd & E1000_EECD_DO)
249 e1000_lower_ee_clk(hw, &eecd);
255 /******************************************************************************
256 * Returns EEPROM to a "standby" state
258 * hw - Struct containing variables accessed by shared code
259 *****************************************************************************/
260 void e1000_standby_eeprom(struct e1000_hw *hw)
262 struct e1000_eeprom_info *eeprom = &hw->eeprom;
265 eecd = E1000_READ_REG(hw, EECD);
267 if (eeprom->type == e1000_eeprom_microwire) {
268 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
269 E1000_WRITE_REG(hw, EECD, eecd);
270 E1000_WRITE_FLUSH(hw);
271 udelay(eeprom->delay_usec);
274 eecd |= E1000_EECD_SK;
275 E1000_WRITE_REG(hw, EECD, eecd);
276 E1000_WRITE_FLUSH(hw);
277 udelay(eeprom->delay_usec);
280 eecd |= E1000_EECD_CS;
281 E1000_WRITE_REG(hw, EECD, eecd);
282 E1000_WRITE_FLUSH(hw);
283 udelay(eeprom->delay_usec);
286 eecd &= ~E1000_EECD_SK;
287 E1000_WRITE_REG(hw, EECD, eecd);
288 E1000_WRITE_FLUSH(hw);
289 udelay(eeprom->delay_usec);
290 } else if (eeprom->type == e1000_eeprom_spi) {
291 /* Toggle CS to flush commands */
292 eecd |= E1000_EECD_CS;
293 E1000_WRITE_REG(hw, EECD, eecd);
294 E1000_WRITE_FLUSH(hw);
295 udelay(eeprom->delay_usec);
296 eecd &= ~E1000_EECD_CS;
297 E1000_WRITE_REG(hw, EECD, eecd);
298 E1000_WRITE_FLUSH(hw);
299 udelay(eeprom->delay_usec);
303 /***************************************************************************
304 * Description: Determines if the onboard NVM is FLASH or EEPROM.
306 * hw - Struct containing variables accessed by shared code
307 ****************************************************************************/
308 static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
314 if (hw->mac_type == e1000_ich8lan)
317 if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
318 eecd = E1000_READ_REG(hw, EECD);
320 /* Isolate bits 15 & 16 */
321 eecd = ((eecd >> 15) & 0x03);
323 /* If both bits are set, device is Flash type */
330 /******************************************************************************
331 * Prepares EEPROM for access
333 * hw - Struct containing variables accessed by shared code
335 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
336 * function should be called before issuing a command to the EEPROM.
337 *****************************************************************************/
338 int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
340 struct e1000_eeprom_info *eeprom = &hw->eeprom;
341 uint32_t eecd, i = 0;
345 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
346 return -E1000_ERR_SWFW_SYNC;
347 eecd = E1000_READ_REG(hw, EECD);
349 if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
350 /* Request EEPROM Access */
351 if (hw->mac_type > e1000_82544) {
352 eecd |= E1000_EECD_REQ;
353 E1000_WRITE_REG(hw, EECD, eecd);
354 eecd = E1000_READ_REG(hw, EECD);
355 while ((!(eecd & E1000_EECD_GNT)) &&
356 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
359 eecd = E1000_READ_REG(hw, EECD);
361 if (!(eecd & E1000_EECD_GNT)) {
362 eecd &= ~E1000_EECD_REQ;
363 E1000_WRITE_REG(hw, EECD, eecd);
364 DEBUGOUT("Could not acquire EEPROM grant\n");
365 return -E1000_ERR_EEPROM;
370 /* Setup EEPROM for Read/Write */
372 if (eeprom->type == e1000_eeprom_microwire) {
373 /* Clear SK and DI */
374 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
375 E1000_WRITE_REG(hw, EECD, eecd);
378 eecd |= E1000_EECD_CS;
379 E1000_WRITE_REG(hw, EECD, eecd);
380 } else if (eeprom->type == e1000_eeprom_spi) {
381 /* Clear SK and CS */
382 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
383 E1000_WRITE_REG(hw, EECD, eecd);
387 return E1000_SUCCESS;
390 /******************************************************************************
391 * Sets up eeprom variables in the hw struct. Must be called after mac_type
392 * is configured. Additionally, if this is ICH8, the flash controller GbE
393 * registers must be mapped, or this will crash.
395 * hw - Struct containing variables accessed by shared code
396 *****************************************************************************/
397 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
399 struct e1000_eeprom_info *eeprom = &hw->eeprom;
401 int32_t ret_val = E1000_SUCCESS;
402 uint16_t eeprom_size;
404 if (hw->mac_type == e1000_igb)
405 eecd = E1000_READ_REG(hw, I210_EECD);
407 eecd = E1000_READ_REG(hw, EECD);
411 switch (hw->mac_type) {
412 case e1000_82542_rev2_0:
413 case e1000_82542_rev2_1:
416 eeprom->type = e1000_eeprom_microwire;
417 eeprom->word_size = 64;
418 eeprom->opcode_bits = 3;
419 eeprom->address_bits = 6;
420 eeprom->delay_usec = 50;
421 eeprom->use_eerd = false;
422 eeprom->use_eewr = false;
426 case e1000_82545_rev_3:
428 case e1000_82546_rev_3:
429 eeprom->type = e1000_eeprom_microwire;
430 eeprom->opcode_bits = 3;
431 eeprom->delay_usec = 50;
432 if (eecd & E1000_EECD_SIZE) {
433 eeprom->word_size = 256;
434 eeprom->address_bits = 8;
436 eeprom->word_size = 64;
437 eeprom->address_bits = 6;
439 eeprom->use_eerd = false;
440 eeprom->use_eewr = false;
443 case e1000_82541_rev_2:
445 case e1000_82547_rev_2:
446 if (eecd & E1000_EECD_TYPE) {
447 eeprom->type = e1000_eeprom_spi;
448 eeprom->opcode_bits = 8;
449 eeprom->delay_usec = 1;
450 if (eecd & E1000_EECD_ADDR_BITS) {
451 eeprom->page_size = 32;
452 eeprom->address_bits = 16;
454 eeprom->page_size = 8;
455 eeprom->address_bits = 8;
458 eeprom->type = e1000_eeprom_microwire;
459 eeprom->opcode_bits = 3;
460 eeprom->delay_usec = 50;
461 if (eecd & E1000_EECD_ADDR_BITS) {
462 eeprom->word_size = 256;
463 eeprom->address_bits = 8;
465 eeprom->word_size = 64;
466 eeprom->address_bits = 6;
469 eeprom->use_eerd = false;
470 eeprom->use_eewr = false;
474 eeprom->type = e1000_eeprom_spi;
475 eeprom->opcode_bits = 8;
476 eeprom->delay_usec = 1;
477 if (eecd & E1000_EECD_ADDR_BITS) {
478 eeprom->page_size = 32;
479 eeprom->address_bits = 16;
481 eeprom->page_size = 8;
482 eeprom->address_bits = 8;
484 eeprom->use_eerd = false;
485 eeprom->use_eewr = false;
489 eeprom->type = e1000_eeprom_spi;
490 eeprom->opcode_bits = 8;
491 eeprom->delay_usec = 1;
492 if (eecd & E1000_EECD_ADDR_BITS) {
493 eeprom->page_size = 32;
494 eeprom->address_bits = 16;
496 eeprom->page_size = 8;
497 eeprom->address_bits = 8;
499 if (e1000_is_onboard_nvm_eeprom(hw) == false) {
500 eeprom->use_eerd = true;
501 eeprom->use_eewr = true;
503 eeprom->type = e1000_eeprom_flash;
504 eeprom->word_size = 2048;
506 /* Ensure that the Autonomous FLASH update bit is cleared due to
507 * Flash update issue on parts which use a FLASH for NVM. */
508 eecd &= ~E1000_EECD_AUPDEN;
509 E1000_WRITE_REG(hw, EECD, eecd);
512 case e1000_80003es2lan:
513 eeprom->type = e1000_eeprom_spi;
514 eeprom->opcode_bits = 8;
515 eeprom->delay_usec = 1;
516 if (eecd & E1000_EECD_ADDR_BITS) {
517 eeprom->page_size = 32;
518 eeprom->address_bits = 16;
520 eeprom->page_size = 8;
521 eeprom->address_bits = 8;
523 eeprom->use_eerd = true;
524 eeprom->use_eewr = false;
527 /* i210 has 4k of iNVM mapped as EEPROM */
528 eeprom->type = e1000_eeprom_invm;
529 eeprom->opcode_bits = 8;
530 eeprom->delay_usec = 1;
531 eeprom->page_size = 32;
532 eeprom->address_bits = 16;
533 eeprom->use_eerd = true;
534 eeprom->use_eewr = false;
537 /* ich8lan does not support currently. if needed, please
538 * add corresponding code and functions.
545 eeprom->type = e1000_eeprom_ich8;
546 eeprom->use_eerd = false;
547 eeprom->use_eewr = false;
548 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
549 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
551 /* Zero the shadow RAM structure. But don't load it from NVM
552 * so as to save time for driver init */
553 if (hw->eeprom_shadow_ram != NULL) {
554 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
555 hw->eeprom_shadow_ram[i].modified = false;
556 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
560 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
561 ICH_FLASH_SECTOR_SIZE;
563 hw->flash_bank_size = ((flash_size >> 16)
564 & ICH_GFPREG_BASE_MASK) + 1;
565 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
567 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
569 hw->flash_bank_size /= 2 * sizeof(uint16_t);
577 if (eeprom->type == e1000_eeprom_spi ||
578 eeprom->type == e1000_eeprom_invm) {
579 /* eeprom_size will be an enum [0..8] that maps
580 * to eeprom sizes 128B to
581 * 32KB (incremented by powers of 2).
583 if (hw->mac_type <= e1000_82547_rev_2) {
584 /* Set to default value for initial eeprom read. */
585 eeprom->word_size = 64;
586 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
590 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
591 >> EEPROM_SIZE_SHIFT;
592 /* 256B eeprom size was not supported in earlier
593 * hardware, so we bump eeprom_size up one to
594 * ensure that "1" (which maps to 256B) is never
595 * the result used in the shifting logic below. */
599 eeprom_size = (uint16_t)((eecd &
600 E1000_EECD_SIZE_EX_MASK) >>
601 E1000_EECD_SIZE_EX_SHIFT);
604 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
609 /******************************************************************************
610 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
612 * hw - Struct containing variables accessed by shared code
613 *****************************************************************************/
615 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
617 uint32_t attempts = 100000;
619 int32_t done = E1000_ERR_EEPROM;
621 for (i = 0; i < attempts; i++) {
622 if (eerd == E1000_EEPROM_POLL_READ) {
623 if (hw->mac_type == e1000_igb)
624 reg = E1000_READ_REG(hw, I210_EERD);
626 reg = E1000_READ_REG(hw, EERD);
628 if (hw->mac_type == e1000_igb)
629 reg = E1000_READ_REG(hw, I210_EEWR);
631 reg = E1000_READ_REG(hw, EEWR);
634 if (reg & E1000_EEPROM_RW_REG_DONE) {
635 done = E1000_SUCCESS;
644 /******************************************************************************
645 * Reads a 16 bit word from the EEPROM using the EERD register.
647 * hw - Struct containing variables accessed by shared code
648 * offset - offset of word in the EEPROM to read
649 * data - word read from the EEPROM
650 * words - number of words to read
651 *****************************************************************************/
653 e1000_read_eeprom_eerd(struct e1000_hw *hw,
658 uint32_t i, eerd = 0;
661 for (i = 0; i < words; i++) {
662 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
663 E1000_EEPROM_RW_REG_START;
665 if (hw->mac_type == e1000_igb)
666 E1000_WRITE_REG(hw, I210_EERD, eerd);
668 E1000_WRITE_REG(hw, EERD, eerd);
670 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
675 if (hw->mac_type == e1000_igb) {
676 data[i] = (E1000_READ_REG(hw, I210_EERD) >>
677 E1000_EEPROM_RW_REG_DATA);
679 data[i] = (E1000_READ_REG(hw, EERD) >>
680 E1000_EEPROM_RW_REG_DATA);
688 void e1000_release_eeprom(struct e1000_hw *hw)
694 eecd = E1000_READ_REG(hw, EECD);
696 if (hw->eeprom.type == e1000_eeprom_spi) {
697 eecd |= E1000_EECD_CS; /* Pull CS high */
698 eecd &= ~E1000_EECD_SK; /* Lower SCK */
700 E1000_WRITE_REG(hw, EECD, eecd);
702 udelay(hw->eeprom.delay_usec);
703 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
706 /* CS on Microwire is active-high */
707 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
709 E1000_WRITE_REG(hw, EECD, eecd);
711 /* Rising edge of clock */
712 eecd |= E1000_EECD_SK;
713 E1000_WRITE_REG(hw, EECD, eecd);
714 E1000_WRITE_FLUSH(hw);
715 udelay(hw->eeprom.delay_usec);
717 /* Falling edge of clock */
718 eecd &= ~E1000_EECD_SK;
719 E1000_WRITE_REG(hw, EECD, eecd);
720 E1000_WRITE_FLUSH(hw);
721 udelay(hw->eeprom.delay_usec);
724 /* Stop requesting EEPROM access */
725 if (hw->mac_type > e1000_82544) {
726 eecd &= ~E1000_EECD_REQ;
727 E1000_WRITE_REG(hw, EECD, eecd);
730 /******************************************************************************
731 * Reads a 16 bit word from the EEPROM.
733 * hw - Struct containing variables accessed by shared code
734 *****************************************************************************/
736 e1000_spi_eeprom_ready(struct e1000_hw *hw)
738 uint16_t retry_count = 0;
739 uint8_t spi_stat_reg;
743 /* Read "Status Register" repeatedly until the LSB is cleared. The
744 * EEPROM will signal that the command has been completed by clearing
745 * bit 0 of the internal status register. If it's not cleared within
746 * 5 milliseconds, then error out.
750 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
751 hw->eeprom.opcode_bits);
752 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
753 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
759 e1000_standby_eeprom(hw);
760 } while (retry_count < EEPROM_MAX_RETRY_SPI);
762 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
763 * only 0-5mSec on 5V devices)
765 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
766 DEBUGOUT("SPI EEPROM Status error\n");
767 return -E1000_ERR_EEPROM;
770 return E1000_SUCCESS;
773 /******************************************************************************
774 * Reads a 16 bit word from the EEPROM.
776 * hw - Struct containing variables accessed by shared code
777 * offset - offset of word in the EEPROM to read
778 * data - word read from the EEPROM
779 *****************************************************************************/
781 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
782 uint16_t words, uint16_t *data)
784 struct e1000_eeprom_info *eeprom = &hw->eeprom;
789 /* If eeprom is not yet detected, do so now */
790 if (eeprom->word_size == 0)
791 e1000_init_eeprom_params(hw);
793 /* A check for invalid values: offset too large, too many words,
794 * and not enough words.
796 if ((offset >= eeprom->word_size) ||
797 (words > eeprom->word_size - offset) ||
799 DEBUGOUT("\"words\" parameter out of bounds."
800 "Words = %d, size = %d\n", offset, eeprom->word_size);
801 return -E1000_ERR_EEPROM;
804 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
805 * directly. In this case, we need to acquire the EEPROM so that
806 * FW or other port software does not interrupt.
808 if (e1000_is_onboard_nvm_eeprom(hw) == true &&
809 hw->eeprom.use_eerd == false) {
811 /* Prepare the EEPROM for bit-bang reading */
812 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
813 return -E1000_ERR_EEPROM;
816 /* Eerd register EEPROM access requires no eeprom aquire/release */
817 if (eeprom->use_eerd == true)
818 return e1000_read_eeprom_eerd(hw, offset, words, data);
820 /* ich8lan does not support currently. if needed, please
821 * add corresponding code and functions.
824 /* ICH EEPROM access is done via the ICH flash controller */
825 if (eeprom->type == e1000_eeprom_ich8)
826 return e1000_read_eeprom_ich8(hw, offset, words, data);
828 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
829 * acquired the EEPROM at this point, so any returns should relase it */
830 if (eeprom->type == e1000_eeprom_spi) {
832 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
834 if (e1000_spi_eeprom_ready(hw)) {
835 e1000_release_eeprom(hw);
836 return -E1000_ERR_EEPROM;
839 e1000_standby_eeprom(hw);
841 /* Some SPI eeproms use the 8th address bit embedded in
843 if ((eeprom->address_bits == 8) && (offset >= 128))
844 read_opcode |= EEPROM_A8_OPCODE_SPI;
846 /* Send the READ command (opcode + addr) */
847 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
848 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
849 eeprom->address_bits);
851 /* Read the data. The address of the eeprom internally
852 * increments with each byte (spi) being read, saving on the
853 * overhead of eeprom setup and tear-down. The address
854 * counter will roll over if reading beyond the size of
855 * the eeprom, thus allowing the entire memory to be read
856 * starting from any offset. */
857 for (i = 0; i < words; i++) {
858 word_in = e1000_shift_in_ee_bits(hw, 16);
859 data[i] = (word_in >> 8) | (word_in << 8);
861 } else if (eeprom->type == e1000_eeprom_microwire) {
862 for (i = 0; i < words; i++) {
863 /* Send the READ command (opcode + addr) */
864 e1000_shift_out_ee_bits(hw,
865 EEPROM_READ_OPCODE_MICROWIRE,
866 eeprom->opcode_bits);
867 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
868 eeprom->address_bits);
870 /* Read the data. For microwire, each word requires
871 * the overhead of eeprom setup and tear-down. */
872 data[i] = e1000_shift_in_ee_bits(hw, 16);
873 e1000_standby_eeprom(hw);
877 /* End this read operation */
878 e1000_release_eeprom(hw);
880 return E1000_SUCCESS;
883 /******************************************************************************
884 * Verifies that the EEPROM has a valid checksum
886 * hw - Struct containing variables accessed by shared code
888 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
889 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
891 *****************************************************************************/
892 static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
894 uint16_t i, checksum, checksum_reg, *buf;
898 /* Allocate a temporary buffer */
899 buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
901 E1000_ERR(hw->nic, "Unable to allocate EEPROM buffer!\n");
902 return -E1000_ERR_EEPROM;
905 /* Read the EEPROM */
906 if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
907 E1000_ERR(hw->nic, "Unable to read EEPROM!\n");
908 return -E1000_ERR_EEPROM;
911 /* Compute the checksum */
913 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
915 checksum = ((uint16_t)EEPROM_SUM) - checksum;
916 checksum_reg = buf[i];
919 if (checksum == checksum_reg)
922 /* Hrm, verification failed, print an error */
923 E1000_ERR(hw->nic, "EEPROM checksum is incorrect!\n");
924 E1000_ERR(hw->nic, " ...register was 0x%04hx, calculated 0x%04hx\n",
925 checksum_reg, checksum);
927 return -E1000_ERR_EEPROM;
929 #endif /* CONFIG_E1000_NO_NVM */
931 /*****************************************************************************
932 * Set PHY to class A mode
933 * Assumes the following operations will follow to enable the new class mode.
934 * 1. Do a PHY soft reset
935 * 2. Restart auto-negotiation or force link.
937 * hw - Struct containing variables accessed by shared code
938 ****************************************************************************/
940 e1000_set_phy_mode(struct e1000_hw *hw)
942 #ifndef CONFIG_E1000_NO_NVM
944 uint16_t eeprom_data;
948 if ((hw->mac_type == e1000_82545_rev_3) &&
949 (hw->media_type == e1000_media_type_copper)) {
950 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
955 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
956 (eeprom_data & EEPROM_PHY_CLASS_A)) {
957 ret_val = e1000_write_phy_reg(hw,
958 M88E1000_PHY_PAGE_SELECT, 0x000B);
961 ret_val = e1000_write_phy_reg(hw,
962 M88E1000_PHY_GEN_CONTROL, 0x8104);
966 hw->phy_reset_disable = false;
970 return E1000_SUCCESS;
973 #ifndef CONFIG_E1000_NO_NVM
974 /***************************************************************************
976 * Obtaining software semaphore bit (SMBI) before resetting PHY.
978 * hw: Struct containing variables accessed by shared code
980 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
981 * E1000_SUCCESS at any other case.
983 ***************************************************************************/
985 e1000_get_software_semaphore(struct e1000_hw *hw)
987 int32_t timeout = hw->eeprom.word_size + 1;
992 swsm = E1000_READ_REG(hw, SWSM);
993 swsm &= ~E1000_SWSM_SMBI;
994 E1000_WRITE_REG(hw, SWSM, swsm);
996 if (hw->mac_type != e1000_80003es2lan)
997 return E1000_SUCCESS;
1000 swsm = E1000_READ_REG(hw, SWSM);
1001 /* If SMBI bit cleared, it is now set and we hold
1003 if (!(swsm & E1000_SWSM_SMBI))
1010 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1011 return -E1000_ERR_RESET;
1014 return E1000_SUCCESS;
1018 /***************************************************************************
1019 * This function clears HW semaphore bits.
1021 * hw: Struct containing variables accessed by shared code
1025 ***************************************************************************/
1027 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
1029 #ifndef CONFIG_E1000_NO_NVM
1034 if (!hw->eeprom_semaphore_present)
1037 swsm = E1000_READ_REG(hw, SWSM);
1038 if (hw->mac_type == e1000_80003es2lan) {
1039 /* Release both semaphores. */
1040 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1042 swsm &= ~(E1000_SWSM_SWESMBI);
1043 E1000_WRITE_REG(hw, SWSM, swsm);
1047 /***************************************************************************
1049 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1050 * adapter or Eeprom access.
1052 * hw: Struct containing variables accessed by shared code
1054 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1055 * E1000_SUCCESS at any other case.
1057 ***************************************************************************/
1059 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1061 #ifndef CONFIG_E1000_NO_NVM
1067 if (!hw->eeprom_semaphore_present)
1068 return E1000_SUCCESS;
1070 if (hw->mac_type == e1000_80003es2lan) {
1071 /* Get the SW semaphore. */
1072 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1073 return -E1000_ERR_EEPROM;
1076 /* Get the FW semaphore. */
1077 timeout = hw->eeprom.word_size + 1;
1079 swsm = E1000_READ_REG(hw, SWSM);
1080 swsm |= E1000_SWSM_SWESMBI;
1081 E1000_WRITE_REG(hw, SWSM, swsm);
1082 /* if we managed to set the bit we got the semaphore. */
1083 swsm = E1000_READ_REG(hw, SWSM);
1084 if (swsm & E1000_SWSM_SWESMBI)
1092 /* Release semaphores */
1093 e1000_put_hw_eeprom_semaphore(hw);
1094 DEBUGOUT("Driver can't access the Eeprom - "
1095 "SWESMBI bit is set.\n");
1096 return -E1000_ERR_EEPROM;
1099 return E1000_SUCCESS;
1103 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1105 uint32_t swfw_sync = 0;
1106 uint32_t swmask = mask;
1107 uint32_t fwmask = mask << 16;
1108 int32_t timeout = 200;
1112 if (e1000_get_hw_eeprom_semaphore(hw))
1113 return -E1000_ERR_SWFW_SYNC;
1115 if (hw->mac_type == e1000_igb)
1116 swfw_sync = E1000_READ_REG(hw, I210_SW_FW_SYNC);
1118 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1119 if (!(swfw_sync & (fwmask | swmask)))
1122 /* firmware currently using resource (fwmask) */
1123 /* or other software thread currently using resource (swmask) */
1124 e1000_put_hw_eeprom_semaphore(hw);
1130 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1131 return -E1000_ERR_SWFW_SYNC;
1134 swfw_sync |= swmask;
1135 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1137 e1000_put_hw_eeprom_semaphore(hw);
1138 return E1000_SUCCESS;
1141 static bool e1000_is_second_port(struct e1000_hw *hw)
1143 switch (hw->mac_type) {
1144 case e1000_80003es2lan:
1147 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1155 #ifndef CONFIG_E1000_NO_NVM
1156 /******************************************************************************
1157 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1158 * second function of dual function devices
1160 * nic - Struct containing variables accessed by shared code
1161 *****************************************************************************/
1163 e1000_read_mac_addr(struct eth_device *nic)
1165 struct e1000_hw *hw = nic->priv;
1167 uint16_t eeprom_data;
1168 uint32_t reg_data = 0;
1173 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1175 if (hw->mac_type == e1000_igb) {
1176 /* i210 preloads MAC address into RAL/RAH registers */
1178 reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
1179 else if (offset == 1)
1181 else if (offset == 2)
1182 reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
1183 eeprom_data = reg_data & 0xffff;
1184 } else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1185 DEBUGOUT("EEPROM Read Error\n");
1186 return -E1000_ERR_EEPROM;
1188 nic->enetaddr[i] = eeprom_data & 0xff;
1189 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1192 /* Invert the last bit if this is the second device */
1193 if (e1000_is_second_port(hw))
1194 nic->enetaddr[5] ^= 1;
1196 #ifdef CONFIG_E1000_FALLBACK_MAC
1197 if (!is_valid_ether_addr(nic->enetaddr)) {
1198 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC;
1200 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE);
1207 /******************************************************************************
1208 * Initializes receive address filters.
1210 * hw - Struct containing variables accessed by shared code
1212 * Places the MAC address in receive address register 0 and clears the rest
1213 * of the receive addresss registers. Clears the multicast table. Assumes
1214 * the receiver is in reset when the routine is called.
1215 *****************************************************************************/
1217 e1000_init_rx_addrs(struct eth_device *nic)
1219 struct e1000_hw *hw = nic->priv;
1226 /* Setup the receive address. */
1227 DEBUGOUT("Programming MAC Address into RAR[0]\n");
1228 addr_low = (nic->enetaddr[0] |
1229 (nic->enetaddr[1] << 8) |
1230 (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24));
1232 addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV);
1234 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1235 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1237 /* Zero out the other 15 receive addresses. */
1238 DEBUGOUT("Clearing RAR[1-15]\n");
1239 for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1240 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1241 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1245 /******************************************************************************
1246 * Clears the VLAN filer table
1248 * hw - Struct containing variables accessed by shared code
1249 *****************************************************************************/
1251 e1000_clear_vfta(struct e1000_hw *hw)
1255 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1256 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1259 /******************************************************************************
1260 * Set the mac type member in the hw struct.
1262 * hw - Struct containing variables accessed by shared code
1263 *****************************************************************************/
1265 e1000_set_mac_type(struct e1000_hw *hw)
1269 switch (hw->device_id) {
1270 case E1000_DEV_ID_82542:
1271 switch (hw->revision_id) {
1272 case E1000_82542_2_0_REV_ID:
1273 hw->mac_type = e1000_82542_rev2_0;
1275 case E1000_82542_2_1_REV_ID:
1276 hw->mac_type = e1000_82542_rev2_1;
1279 /* Invalid 82542 revision ID */
1280 return -E1000_ERR_MAC_TYPE;
1283 case E1000_DEV_ID_82543GC_FIBER:
1284 case E1000_DEV_ID_82543GC_COPPER:
1285 hw->mac_type = e1000_82543;
1287 case E1000_DEV_ID_82544EI_COPPER:
1288 case E1000_DEV_ID_82544EI_FIBER:
1289 case E1000_DEV_ID_82544GC_COPPER:
1290 case E1000_DEV_ID_82544GC_LOM:
1291 hw->mac_type = e1000_82544;
1293 case E1000_DEV_ID_82540EM:
1294 case E1000_DEV_ID_82540EM_LOM:
1295 case E1000_DEV_ID_82540EP:
1296 case E1000_DEV_ID_82540EP_LOM:
1297 case E1000_DEV_ID_82540EP_LP:
1298 hw->mac_type = e1000_82540;
1300 case E1000_DEV_ID_82545EM_COPPER:
1301 case E1000_DEV_ID_82545EM_FIBER:
1302 hw->mac_type = e1000_82545;
1304 case E1000_DEV_ID_82545GM_COPPER:
1305 case E1000_DEV_ID_82545GM_FIBER:
1306 case E1000_DEV_ID_82545GM_SERDES:
1307 hw->mac_type = e1000_82545_rev_3;
1309 case E1000_DEV_ID_82546EB_COPPER:
1310 case E1000_DEV_ID_82546EB_FIBER:
1311 case E1000_DEV_ID_82546EB_QUAD_COPPER:
1312 hw->mac_type = e1000_82546;
1314 case E1000_DEV_ID_82546GB_COPPER:
1315 case E1000_DEV_ID_82546GB_FIBER:
1316 case E1000_DEV_ID_82546GB_SERDES:
1317 case E1000_DEV_ID_82546GB_PCIE:
1318 case E1000_DEV_ID_82546GB_QUAD_COPPER:
1319 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1320 hw->mac_type = e1000_82546_rev_3;
1322 case E1000_DEV_ID_82541EI:
1323 case E1000_DEV_ID_82541EI_MOBILE:
1324 case E1000_DEV_ID_82541ER_LOM:
1325 hw->mac_type = e1000_82541;
1327 case E1000_DEV_ID_82541ER:
1328 case E1000_DEV_ID_82541GI:
1329 case E1000_DEV_ID_82541GI_LF:
1330 case E1000_DEV_ID_82541GI_MOBILE:
1331 hw->mac_type = e1000_82541_rev_2;
1333 case E1000_DEV_ID_82547EI:
1334 case E1000_DEV_ID_82547EI_MOBILE:
1335 hw->mac_type = e1000_82547;
1337 case E1000_DEV_ID_82547GI:
1338 hw->mac_type = e1000_82547_rev_2;
1340 case E1000_DEV_ID_82571EB_COPPER:
1341 case E1000_DEV_ID_82571EB_FIBER:
1342 case E1000_DEV_ID_82571EB_SERDES:
1343 case E1000_DEV_ID_82571EB_SERDES_DUAL:
1344 case E1000_DEV_ID_82571EB_SERDES_QUAD:
1345 case E1000_DEV_ID_82571EB_QUAD_COPPER:
1346 case E1000_DEV_ID_82571PT_QUAD_COPPER:
1347 case E1000_DEV_ID_82571EB_QUAD_FIBER:
1348 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1349 hw->mac_type = e1000_82571;
1351 case E1000_DEV_ID_82572EI_COPPER:
1352 case E1000_DEV_ID_82572EI_FIBER:
1353 case E1000_DEV_ID_82572EI_SERDES:
1354 case E1000_DEV_ID_82572EI:
1355 hw->mac_type = e1000_82572;
1357 case E1000_DEV_ID_82573E:
1358 case E1000_DEV_ID_82573E_IAMT:
1359 case E1000_DEV_ID_82573L:
1360 hw->mac_type = e1000_82573;
1362 case E1000_DEV_ID_82574L:
1363 hw->mac_type = e1000_82574;
1365 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1366 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1367 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1368 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1369 hw->mac_type = e1000_80003es2lan;
1371 case E1000_DEV_ID_ICH8_IGP_M_AMT:
1372 case E1000_DEV_ID_ICH8_IGP_AMT:
1373 case E1000_DEV_ID_ICH8_IGP_C:
1374 case E1000_DEV_ID_ICH8_IFE:
1375 case E1000_DEV_ID_ICH8_IFE_GT:
1376 case E1000_DEV_ID_ICH8_IFE_G:
1377 case E1000_DEV_ID_ICH8_IGP_M:
1378 hw->mac_type = e1000_ich8lan;
1380 case PCI_DEVICE_ID_INTEL_I210_COPPER:
1381 case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
1382 case PCI_DEVICE_ID_INTEL_I210_SERDES:
1383 case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
1384 case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
1385 hw->mac_type = e1000_igb;
1388 /* Should never have loaded on this device */
1389 return -E1000_ERR_MAC_TYPE;
1391 return E1000_SUCCESS;
1394 /******************************************************************************
1395 * Reset the transmit and receive units; mask and clear all interrupts.
1397 * hw - Struct containing variables accessed by shared code
1398 *****************************************************************************/
1400 e1000_reset_hw(struct e1000_hw *hw)
1410 /* get the correct pba value for both PCI and PCIe*/
1411 if (hw->mac_type < e1000_82571)
1412 pba = E1000_DEFAULT_PCI_PBA;
1414 pba = E1000_DEFAULT_PCIE_PBA;
1416 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1417 if (hw->mac_type == e1000_82542_rev2_0) {
1418 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1419 pci_write_config_word(hw->pdev, PCI_COMMAND,
1420 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1423 /* Clear interrupt mask to stop board from generating interrupts */
1424 DEBUGOUT("Masking off all interrupts\n");
1425 if (hw->mac_type == e1000_igb)
1426 E1000_WRITE_REG(hw, I210_IAM, 0);
1427 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1429 /* Disable the Transmit and Receive units. Then delay to allow
1430 * any pending transactions to complete before we hit the MAC with
1433 E1000_WRITE_REG(hw, RCTL, 0);
1434 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1435 E1000_WRITE_FLUSH(hw);
1437 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1438 hw->tbi_compatibility_on = false;
1440 /* Delay to allow any outstanding PCI transactions to complete before
1441 * resetting the device
1445 /* Issue a global reset to the MAC. This will reset the chip's
1446 * transmit, receive, DMA, and link units. It will not effect
1447 * the current PCI configuration. The global reset bit is self-
1448 * clearing, and should clear within a microsecond.
1450 DEBUGOUT("Issuing a global reset to MAC\n");
1451 ctrl = E1000_READ_REG(hw, CTRL);
1453 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1455 /* Force a reload from the EEPROM if necessary */
1456 if (hw->mac_type == e1000_igb) {
1458 reg = E1000_READ_REG(hw, STATUS);
1459 if (reg & E1000_STATUS_PF_RST_DONE)
1460 DEBUGOUT("PF OK\n");
1461 reg = E1000_READ_REG(hw, I210_EECD);
1462 if (reg & E1000_EECD_AUTO_RD)
1463 DEBUGOUT("EEC OK\n");
1464 } else if (hw->mac_type < e1000_82540) {
1465 /* Wait for reset to complete */
1467 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1468 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1469 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1470 E1000_WRITE_FLUSH(hw);
1471 /* Wait for EEPROM reload */
1474 /* Wait for EEPROM reload (it happens automatically) */
1476 /* Dissable HW ARPs on ASF enabled adapters */
1477 manc = E1000_READ_REG(hw, MANC);
1478 manc &= ~(E1000_MANC_ARP_EN);
1479 E1000_WRITE_REG(hw, MANC, manc);
1482 /* Clear interrupt mask to stop board from generating interrupts */
1483 DEBUGOUT("Masking off all interrupts\n");
1484 if (hw->mac_type == e1000_igb)
1485 E1000_WRITE_REG(hw, I210_IAM, 0);
1486 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1488 /* Clear any pending interrupt events. */
1489 E1000_READ_REG(hw, ICR);
1491 /* If MWI was previously enabled, reenable it. */
1492 if (hw->mac_type == e1000_82542_rev2_0) {
1493 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1495 if (hw->mac_type != e1000_igb)
1496 E1000_WRITE_REG(hw, PBA, pba);
1499 /******************************************************************************
1501 * Initialize a number of hardware-dependent bits
1503 * hw: Struct containing variables accessed by shared code
1505 * This function contains hardware limitation workarounds for PCI-E adapters
1507 *****************************************************************************/
1509 e1000_initialize_hardware_bits(struct e1000_hw *hw)
1511 if ((hw->mac_type >= e1000_82571) &&
1512 (!hw->initialize_hw_bits_disable)) {
1513 /* Settings common to all PCI-express silicon */
1514 uint32_t reg_ctrl, reg_ctrl_ext;
1515 uint32_t reg_tarc0, reg_tarc1;
1517 uint32_t reg_txdctl, reg_txdctl1;
1519 /* link autonegotiation/sync workarounds */
1520 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1521 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1523 /* Enable not-done TX descriptor counting */
1524 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1525 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1526 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1528 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1529 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1530 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1533 if (hw->mac_type == e1000_igb)
1536 switch (hw->mac_type) {
1539 /* Clear PHY TX compatible mode bits */
1540 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1541 reg_tarc1 &= ~((1 << 30)|(1 << 29));
1543 /* link autonegotiation/sync workarounds */
1544 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1546 /* TX ring control fixes */
1547 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1549 /* Multiple read bit is reversed polarity */
1550 reg_tctl = E1000_READ_REG(hw, TCTL);
1551 if (reg_tctl & E1000_TCTL_MULR)
1552 reg_tarc1 &= ~(1 << 28);
1554 reg_tarc1 |= (1 << 28);
1556 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1560 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1561 reg_ctrl_ext &= ~(1 << 23);
1562 reg_ctrl_ext |= (1 << 22);
1564 /* TX byte count fix */
1565 reg_ctrl = E1000_READ_REG(hw, CTRL);
1566 reg_ctrl &= ~(1 << 29);
1568 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1569 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1571 case e1000_80003es2lan:
1572 /* improve small packet performace for fiber/serdes */
1573 if ((hw->media_type == e1000_media_type_fiber)
1574 || (hw->media_type ==
1575 e1000_media_type_internal_serdes)) {
1576 reg_tarc0 &= ~(1 << 20);
1579 /* Multiple read bit is reversed polarity */
1580 reg_tctl = E1000_READ_REG(hw, TCTL);
1581 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1582 if (reg_tctl & E1000_TCTL_MULR)
1583 reg_tarc1 &= ~(1 << 28);
1585 reg_tarc1 |= (1 << 28);
1587 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1590 /* Reduce concurrent DMA requests to 3 from 4 */
1591 if ((hw->revision_id < 3) ||
1592 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1593 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1594 reg_tarc0 |= ((1 << 29)|(1 << 28));
1596 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1597 reg_ctrl_ext |= (1 << 22);
1598 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1600 /* workaround TX hang with TSO=on */
1601 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1603 /* Multiple read bit is reversed polarity */
1604 reg_tctl = E1000_READ_REG(hw, TCTL);
1605 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1606 if (reg_tctl & E1000_TCTL_MULR)
1607 reg_tarc1 &= ~(1 << 28);
1609 reg_tarc1 |= (1 << 28);
1611 /* workaround TX hang with TSO=on */
1612 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1614 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1620 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1624 /******************************************************************************
1625 * Performs basic configuration of the adapter.
1627 * hw - Struct containing variables accessed by shared code
1629 * Assumes that the controller has previously been reset and is in a
1630 * post-reset uninitialized state. Initializes the receive address registers,
1631 * multicast table, and VLAN filter table. Calls routines to setup link
1632 * configuration and flow control settings. Clears all on-chip counters. Leaves
1633 * the transmit and receive units disabled and uninitialized.
1634 *****************************************************************************/
1636 e1000_init_hw(struct eth_device *nic)
1638 struct e1000_hw *hw = nic->priv;
1642 uint16_t pcix_cmd_word;
1643 uint16_t pcix_stat_hi_word;
1645 uint16_t stat_mmrbc;
1650 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1651 if ((hw->mac_type == e1000_ich8lan) &&
1652 ((hw->revision_id < 3) ||
1653 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1654 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1655 reg_data = E1000_READ_REG(hw, STATUS);
1656 reg_data &= ~0x80000000;
1657 E1000_WRITE_REG(hw, STATUS, reg_data);
1659 /* Do not need initialize Identification LED */
1661 /* Set the media type and TBI compatibility */
1662 e1000_set_media_type(hw);
1664 /* Must be called after e1000_set_media_type
1665 * because media_type is used */
1666 e1000_initialize_hardware_bits(hw);
1668 /* Disabling VLAN filtering. */
1669 DEBUGOUT("Initializing the IEEE VLAN\n");
1670 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1671 if (hw->mac_type != e1000_ich8lan) {
1672 if (hw->mac_type < e1000_82545_rev_3)
1673 E1000_WRITE_REG(hw, VET, 0);
1674 e1000_clear_vfta(hw);
1677 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1678 if (hw->mac_type == e1000_82542_rev2_0) {
1679 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1680 pci_write_config_word(hw->pdev, PCI_COMMAND,
1682 pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1683 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1684 E1000_WRITE_FLUSH(hw);
1688 /* Setup the receive address. This involves initializing all of the Receive
1689 * Address Registers (RARs 0 - 15).
1691 e1000_init_rx_addrs(nic);
1693 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1694 if (hw->mac_type == e1000_82542_rev2_0) {
1695 E1000_WRITE_REG(hw, RCTL, 0);
1696 E1000_WRITE_FLUSH(hw);
1698 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1701 /* Zero out the Multicast HASH table */
1702 DEBUGOUT("Zeroing the MTA\n");
1703 mta_size = E1000_MC_TBL_SIZE;
1704 if (hw->mac_type == e1000_ich8lan)
1705 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1706 for (i = 0; i < mta_size; i++) {
1707 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1708 /* use write flush to prevent Memory Write Block (MWB) from
1709 * occuring when accessing our register space */
1710 E1000_WRITE_FLUSH(hw);
1713 /* Set the PCI priority bit correctly in the CTRL register. This
1714 * determines if the adapter gives priority to receives, or if it
1715 * gives equal priority to transmits and receives. Valid only on
1716 * 82542 and 82543 silicon.
1718 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
1719 ctrl = E1000_READ_REG(hw, CTRL);
1720 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1723 switch (hw->mac_type) {
1724 case e1000_82545_rev_3:
1725 case e1000_82546_rev_3:
1729 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1730 if (hw->bus_type == e1000_bus_type_pcix) {
1731 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1733 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1734 &pcix_stat_hi_word);
1736 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1737 PCIX_COMMAND_MMRBC_SHIFT;
1739 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1740 PCIX_STATUS_HI_MMRBC_SHIFT;
1741 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1742 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1743 if (cmd_mmrbc > stat_mmrbc) {
1744 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1745 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1746 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1753 /* More time needed for PHY to initialize */
1754 if (hw->mac_type == e1000_ich8lan)
1756 if (hw->mac_type == e1000_igb)
1759 /* Call a subroutine to configure the link and setup flow control. */
1760 ret_val = e1000_setup_link(nic);
1762 /* Set the transmit descriptor write-back policy */
1763 if (hw->mac_type > e1000_82544) {
1764 ctrl = E1000_READ_REG(hw, TXDCTL);
1766 (ctrl & ~E1000_TXDCTL_WTHRESH) |
1767 E1000_TXDCTL_FULL_TX_DESC_WB;
1768 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1771 /* Set the receive descriptor write back policy */
1772 if (hw->mac_type >= e1000_82571) {
1773 ctrl = E1000_READ_REG(hw, RXDCTL);
1775 (ctrl & ~E1000_RXDCTL_WTHRESH) |
1776 E1000_RXDCTL_FULL_RX_DESC_WB;
1777 E1000_WRITE_REG(hw, RXDCTL, ctrl);
1780 switch (hw->mac_type) {
1783 case e1000_80003es2lan:
1784 /* Enable retransmit on late collisions */
1785 reg_data = E1000_READ_REG(hw, TCTL);
1786 reg_data |= E1000_TCTL_RTLC;
1787 E1000_WRITE_REG(hw, TCTL, reg_data);
1789 /* Configure Gigabit Carry Extend Padding */
1790 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1791 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1792 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1793 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1795 /* Configure Transmit Inter-Packet Gap */
1796 reg_data = E1000_READ_REG(hw, TIPG);
1797 reg_data &= ~E1000_TIPG_IPGT_MASK;
1798 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1799 E1000_WRITE_REG(hw, TIPG, reg_data);
1801 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1802 reg_data &= ~0x00100000;
1803 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1808 ctrl = E1000_READ_REG(hw, TXDCTL1);
1809 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
1810 | E1000_TXDCTL_FULL_TX_DESC_WB;
1811 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1815 reg_data = E1000_READ_REG(hw, GCR);
1816 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1817 E1000_WRITE_REG(hw, GCR, reg_data);
1823 /* Clear all of the statistics registers (clear on read). It is
1824 * important that we do this after we have tried to establish link
1825 * because the symbol error count will increment wildly if there
1828 e1000_clear_hw_cntrs(hw);
1830 /* ICH8 No-snoop bits are opposite polarity.
1831 * Set to snoop by default after reset. */
1832 if (hw->mac_type == e1000_ich8lan)
1833 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1836 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1837 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1838 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1839 /* Relaxed ordering must be disabled to avoid a parity
1840 * error crash in a PCI slot. */
1841 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1842 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1848 /******************************************************************************
1849 * Configures flow control and link settings.
1851 * hw - Struct containing variables accessed by shared code
1853 * Determines which flow control settings to use. Calls the apropriate media-
1854 * specific link configuration function. Configures the flow control settings.
1855 * Assuming the adapter has a valid link partner, a valid link should be
1856 * established. Assumes the hardware has previously been reset and the
1857 * transmitter and receiver are not enabled.
1858 *****************************************************************************/
1860 e1000_setup_link(struct eth_device *nic)
1862 struct e1000_hw *hw = nic->priv;
1864 #ifndef CONFIG_E1000_NO_NVM
1866 uint16_t eeprom_data;
1871 /* In the case of the phy reset being blocked, we already have a link.
1872 * We do not have to set it up again. */
1873 if (e1000_check_phy_reset_block(hw))
1874 return E1000_SUCCESS;
1876 #ifndef CONFIG_E1000_NO_NVM
1877 /* Read and store word 0x0F of the EEPROM. This word contains bits
1878 * that determine the hardware's default PAUSE (flow control) mode,
1879 * a bit that determines whether the HW defaults to enabling or
1880 * disabling auto-negotiation, and the direction of the
1881 * SW defined pins. If there is no SW over-ride of the flow
1882 * control setting, then the variable hw->fc will
1883 * be initialized based on a value in the EEPROM.
1885 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
1886 &eeprom_data) < 0) {
1887 DEBUGOUT("EEPROM Read Error\n");
1888 return -E1000_ERR_EEPROM;
1891 if (hw->fc == e1000_fc_default) {
1892 switch (hw->mac_type) {
1897 hw->fc = e1000_fc_full;
1900 #ifndef CONFIG_E1000_NO_NVM
1901 ret_val = e1000_read_eeprom(hw,
1902 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1904 DEBUGOUT("EEPROM Read Error\n");
1905 return -E1000_ERR_EEPROM;
1907 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1908 hw->fc = e1000_fc_none;
1909 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1910 EEPROM_WORD0F_ASM_DIR)
1911 hw->fc = e1000_fc_tx_pause;
1914 hw->fc = e1000_fc_full;
1919 /* We want to save off the original Flow Control configuration just
1920 * in case we get disconnected and then reconnected into a different
1921 * hub or switch with different Flow Control capabilities.
1923 if (hw->mac_type == e1000_82542_rev2_0)
1924 hw->fc &= (~e1000_fc_tx_pause);
1926 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1927 hw->fc &= (~e1000_fc_rx_pause);
1929 hw->original_fc = hw->fc;
1931 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
1933 #ifndef CONFIG_E1000_NO_NVM
1934 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1935 * polarity value for the SW controlled pins, and setup the
1936 * Extended Device Control reg with that info.
1937 * This is needed because one of the SW controlled pins is used for
1938 * signal detection. So this should be done before e1000_setup_pcs_link()
1939 * or e1000_phy_setup() is called.
1941 if (hw->mac_type == e1000_82543) {
1942 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1944 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1948 /* Call the necessary subroutine to configure the link. */
1949 ret_val = (hw->media_type == e1000_media_type_fiber) ?
1950 e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic);
1955 /* Initialize the flow control address, type, and PAUSE timer
1956 * registers to their default values. This is done even if flow
1957 * control is disabled, because it does not hurt anything to
1958 * initialize these registers.
1960 DEBUGOUT("Initializing the Flow Control address, type"
1961 "and timer regs\n");
1963 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1964 if (hw->mac_type != e1000_ich8lan) {
1965 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1966 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1967 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1970 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1972 /* Set the flow control receive threshold registers. Normally,
1973 * these registers will be set to a default threshold that may be
1974 * adjusted later by the driver's runtime code. However, if the
1975 * ability to transmit pause frames in not enabled, then these
1976 * registers will be set to 0.
1978 if (!(hw->fc & e1000_fc_tx_pause)) {
1979 E1000_WRITE_REG(hw, FCRTL, 0);
1980 E1000_WRITE_REG(hw, FCRTH, 0);
1982 /* We need to set up the Receive Threshold high and low water marks
1983 * as well as (optionally) enabling the transmission of XON frames.
1985 if (hw->fc_send_xon) {
1986 E1000_WRITE_REG(hw, FCRTL,
1987 (hw->fc_low_water | E1000_FCRTL_XONE));
1988 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1990 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1991 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1997 /******************************************************************************
1998 * Sets up link for a fiber based adapter
2000 * hw - Struct containing variables accessed by shared code
2002 * Manipulates Physical Coding Sublayer functions in order to configure
2003 * link. Assumes the hardware has been previously reset and the transmitter
2004 * and receiver are not enabled.
2005 *****************************************************************************/
2007 e1000_setup_fiber_link(struct eth_device *nic)
2009 struct e1000_hw *hw = nic->priv;
2018 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
2019 * set when the optics detect a signal. On older adapters, it will be
2020 * cleared when there is a signal
2022 ctrl = E1000_READ_REG(hw, CTRL);
2023 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
2024 signal = E1000_CTRL_SWDPIN1;
2028 printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal,
2030 /* Take the link out of reset */
2031 ctrl &= ~(E1000_CTRL_LRST);
2033 e1000_config_collision_dist(hw);
2035 /* Check for a software override of the flow control settings, and setup
2036 * the device accordingly. If auto-negotiation is enabled, then software
2037 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
2038 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
2039 * auto-negotiation is disabled, then software will have to manually
2040 * configure the two flow control enable bits in the CTRL register.
2042 * The possible values of the "fc" parameter are:
2043 * 0: Flow control is completely disabled
2044 * 1: Rx flow control is enabled (we can receive pause frames, but
2045 * not send pause frames).
2046 * 2: Tx flow control is enabled (we can send pause frames but we do
2047 * not support receiving pause frames).
2048 * 3: Both Rx and TX flow control (symmetric) are enabled.
2052 /* Flow control is completely disabled by a software over-ride. */
2053 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
2055 case e1000_fc_rx_pause:
2056 /* RX Flow control is enabled and TX Flow control is disabled by a
2057 * software over-ride. Since there really isn't a way to advertise
2058 * that we are capable of RX Pause ONLY, we will advertise that we
2059 * support both symmetric and asymmetric RX PAUSE. Later, we will
2060 * disable the adapter's ability to send PAUSE frames.
2062 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2064 case e1000_fc_tx_pause:
2065 /* TX Flow control is enabled, and RX Flow control is disabled, by a
2066 * software over-ride.
2068 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
2071 /* Flow control (both RX and TX) is enabled by a software over-ride. */
2072 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2075 DEBUGOUT("Flow control param set incorrectly\n");
2076 return -E1000_ERR_CONFIG;
2080 /* Since auto-negotiation is enabled, take the link out of reset (the link
2081 * will be in reset, because we previously reset the chip). This will
2082 * restart auto-negotiation. If auto-neogtiation is successful then the
2083 * link-up status bit will be set and the flow control enable bits (RFCE
2084 * and TFCE) will be set according to their negotiated value.
2086 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2088 E1000_WRITE_REG(hw, TXCW, txcw);
2089 E1000_WRITE_REG(hw, CTRL, ctrl);
2090 E1000_WRITE_FLUSH(hw);
2095 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
2096 * indication in the Device Status Register. Time-out if a link isn't
2097 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
2098 * less than 500 milliseconds even if the other end is doing it in SW).
2100 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2101 DEBUGOUT("Looking for Link\n");
2102 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2104 status = E1000_READ_REG(hw, STATUS);
2105 if (status & E1000_STATUS_LU)
2108 if (i == (LINK_UP_TIMEOUT / 10)) {
2109 /* AutoNeg failed to achieve a link, so we'll call
2110 * e1000_check_for_link. This routine will force the link up if we
2111 * detect a signal. This will allow us to communicate with
2112 * non-autonegotiating link partners.
2114 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2115 hw->autoneg_failed = 1;
2116 ret_val = e1000_check_for_link(nic);
2118 DEBUGOUT("Error while checking for link\n");
2121 hw->autoneg_failed = 0;
2123 hw->autoneg_failed = 0;
2124 DEBUGOUT("Valid Link Found\n");
2127 DEBUGOUT("No Signal Detected\n");
2128 return -E1000_ERR_NOLINK;
2133 /******************************************************************************
2134 * Make sure we have a valid PHY and change PHY mode before link setup.
2136 * hw - Struct containing variables accessed by shared code
2137 ******************************************************************************/
2139 e1000_copper_link_preconfig(struct e1000_hw *hw)
2147 ctrl = E1000_READ_REG(hw, CTRL);
2148 /* With 82543, we need to force speed and duplex on the MAC equal to what
2149 * the PHY speed and duplex configuration is. In addition, we need to
2150 * perform a hardware reset on the PHY to take it out of reset.
2152 if (hw->mac_type > e1000_82543) {
2153 ctrl |= E1000_CTRL_SLU;
2154 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2155 E1000_WRITE_REG(hw, CTRL, ctrl);
2157 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2159 E1000_WRITE_REG(hw, CTRL, ctrl);
2160 ret_val = e1000_phy_hw_reset(hw);
2165 /* Make sure we have a valid PHY */
2166 ret_val = e1000_detect_gig_phy(hw);
2168 DEBUGOUT("Error, did not detect valid phy.\n");
2171 DEBUGOUT("Phy ID = %x \n", hw->phy_id);
2173 /* Set PHY to class A mode (if necessary) */
2174 ret_val = e1000_set_phy_mode(hw);
2177 if ((hw->mac_type == e1000_82545_rev_3) ||
2178 (hw->mac_type == e1000_82546_rev_3)) {
2179 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2181 phy_data |= 0x00000008;
2182 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2186 if (hw->mac_type <= e1000_82543 ||
2187 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2188 hw->mac_type == e1000_82541_rev_2
2189 || hw->mac_type == e1000_82547_rev_2)
2190 hw->phy_reset_disable = false;
2192 return E1000_SUCCESS;
2195 /*****************************************************************************
2197 * This function sets the lplu state according to the active flag. When
2198 * activating lplu this function also disables smart speed and vise versa.
2199 * lplu will not be activated unless the device autonegotiation advertisment
2200 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2201 * hw: Struct containing variables accessed by shared code
2202 * active - true to enable lplu false to disable lplu.
2204 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2205 * E1000_SUCCESS at any other case.
2207 ****************************************************************************/
2210 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
2212 uint32_t phy_ctrl = 0;
2217 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2218 && hw->phy_type != e1000_phy_igp_3)
2219 return E1000_SUCCESS;
2221 /* During driver activity LPLU should not be used or it will attain link
2222 * from the lowest speeds starting from 10Mbps. The capability is used
2223 * for Dx transitions and states */
2224 if (hw->mac_type == e1000_82541_rev_2
2225 || hw->mac_type == e1000_82547_rev_2) {
2226 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2230 } else if (hw->mac_type == e1000_ich8lan) {
2231 /* MAC writes into PHY register based on the state transition
2232 * and start auto-negotiation. SW driver can overwrite the
2233 * settings in CSR PHY power control E1000_PHY_CTRL register. */
2234 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2236 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2243 if (hw->mac_type == e1000_82541_rev_2 ||
2244 hw->mac_type == e1000_82547_rev_2) {
2245 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2246 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2251 if (hw->mac_type == e1000_ich8lan) {
2252 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2253 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2255 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2256 ret_val = e1000_write_phy_reg(hw,
2257 IGP02E1000_PHY_POWER_MGMT, phy_data);
2263 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2264 * Dx states where the power conservation is most important. During
2265 * driver activity we should enable SmartSpeed, so performance is
2267 if (hw->smart_speed == e1000_smart_speed_on) {
2268 ret_val = e1000_read_phy_reg(hw,
2269 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2273 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2274 ret_val = e1000_write_phy_reg(hw,
2275 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2278 } else if (hw->smart_speed == e1000_smart_speed_off) {
2279 ret_val = e1000_read_phy_reg(hw,
2280 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2284 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2285 ret_val = e1000_write_phy_reg(hw,
2286 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2291 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2292 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2293 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2295 if (hw->mac_type == e1000_82541_rev_2 ||
2296 hw->mac_type == e1000_82547_rev_2) {
2297 phy_data |= IGP01E1000_GMII_FLEX_SPD;
2298 ret_val = e1000_write_phy_reg(hw,
2299 IGP01E1000_GMII_FIFO, phy_data);
2303 if (hw->mac_type == e1000_ich8lan) {
2304 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2305 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2307 phy_data |= IGP02E1000_PM_D3_LPLU;
2308 ret_val = e1000_write_phy_reg(hw,
2309 IGP02E1000_PHY_POWER_MGMT, phy_data);
2315 /* When LPLU is enabled we should disable SmartSpeed */
2316 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2321 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2322 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2327 return E1000_SUCCESS;
2330 /*****************************************************************************
2332 * This function sets the lplu d0 state according to the active flag. When
2333 * activating lplu this function also disables smart speed and vise versa.
2334 * lplu will not be activated unless the device autonegotiation advertisment
2335 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2336 * hw: Struct containing variables accessed by shared code
2337 * active - true to enable lplu false to disable lplu.
2339 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2340 * E1000_SUCCESS at any other case.
2342 ****************************************************************************/
2345 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2347 uint32_t phy_ctrl = 0;
2352 if (hw->mac_type <= e1000_82547_rev_2)
2353 return E1000_SUCCESS;
2355 if (hw->mac_type == e1000_ich8lan) {
2356 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2357 } else if (hw->mac_type == e1000_igb) {
2358 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL);
2360 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2367 if (hw->mac_type == e1000_ich8lan) {
2368 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2369 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2370 } else if (hw->mac_type == e1000_igb) {
2371 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2372 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2374 phy_data &= ~IGP02E1000_PM_D0_LPLU;
2375 ret_val = e1000_write_phy_reg(hw,
2376 IGP02E1000_PHY_POWER_MGMT, phy_data);
2381 if (hw->mac_type == e1000_igb)
2382 return E1000_SUCCESS;
2384 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2385 * Dx states where the power conservation is most important. During
2386 * driver activity we should enable SmartSpeed, so performance is
2388 if (hw->smart_speed == e1000_smart_speed_on) {
2389 ret_val = e1000_read_phy_reg(hw,
2390 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2394 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2395 ret_val = e1000_write_phy_reg(hw,
2396 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2399 } else if (hw->smart_speed == e1000_smart_speed_off) {
2400 ret_val = e1000_read_phy_reg(hw,
2401 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2405 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2406 ret_val = e1000_write_phy_reg(hw,
2407 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2415 if (hw->mac_type == e1000_ich8lan) {
2416 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2417 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2418 } else if (hw->mac_type == e1000_igb) {
2419 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2420 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2422 phy_data |= IGP02E1000_PM_D0_LPLU;
2423 ret_val = e1000_write_phy_reg(hw,
2424 IGP02E1000_PHY_POWER_MGMT, phy_data);
2429 if (hw->mac_type == e1000_igb)
2430 return E1000_SUCCESS;
2432 /* When LPLU is enabled we should disable SmartSpeed */
2433 ret_val = e1000_read_phy_reg(hw,
2434 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2438 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2439 ret_val = e1000_write_phy_reg(hw,
2440 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2445 return E1000_SUCCESS;
2448 /********************************************************************
2449 * Copper link setup for e1000_phy_igp series.
2451 * hw - Struct containing variables accessed by shared code
2452 *********************************************************************/
2454 e1000_copper_link_igp_setup(struct e1000_hw *hw)
2462 if (hw->phy_reset_disable)
2463 return E1000_SUCCESS;
2465 ret_val = e1000_phy_reset(hw);
2467 DEBUGOUT("Error Resetting the PHY\n");
2471 /* Wait 15ms for MAC to configure PHY from eeprom settings */
2473 if (hw->mac_type != e1000_ich8lan) {
2474 /* Configure activity LED after PHY reset */
2475 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2476 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2477 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2478 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2481 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2482 if (hw->phy_type == e1000_phy_igp) {
2483 /* disable lplu d3 during driver init */
2484 ret_val = e1000_set_d3_lplu_state(hw, false);
2486 DEBUGOUT("Error Disabling LPLU D3\n");
2491 /* disable lplu d0 during driver init */
2492 ret_val = e1000_set_d0_lplu_state(hw, false);
2494 DEBUGOUT("Error Disabling LPLU D0\n");
2497 /* Configure mdi-mdix settings */
2498 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2502 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2503 hw->dsp_config_state = e1000_dsp_config_disabled;
2504 /* Force MDI for earlier revs of the IGP PHY */
2505 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2506 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2510 hw->dsp_config_state = e1000_dsp_config_enabled;
2511 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2515 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2518 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2522 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2526 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2530 /* set auto-master slave resolution settings */
2532 e1000_ms_type phy_ms_setting = hw->master_slave;
2534 if (hw->ffe_config_state == e1000_ffe_config_active)
2535 hw->ffe_config_state = e1000_ffe_config_enabled;
2537 if (hw->dsp_config_state == e1000_dsp_config_activated)
2538 hw->dsp_config_state = e1000_dsp_config_enabled;
2540 /* when autonegotiation advertisment is only 1000Mbps then we
2541 * should disable SmartSpeed and enable Auto MasterSlave
2542 * resolution as hardware default. */
2543 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2544 /* Disable SmartSpeed */
2545 ret_val = e1000_read_phy_reg(hw,
2546 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2549 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2550 ret_val = e1000_write_phy_reg(hw,
2551 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2554 /* Set auto Master/Slave resolution process */
2555 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2559 phy_data &= ~CR_1000T_MS_ENABLE;
2560 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2566 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2570 /* load defaults for future use */
2571 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2572 ((phy_data & CR_1000T_MS_VALUE) ?
2573 e1000_ms_force_master :
2574 e1000_ms_force_slave) :
2577 switch (phy_ms_setting) {
2578 case e1000_ms_force_master:
2579 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2581 case e1000_ms_force_slave:
2582 phy_data |= CR_1000T_MS_ENABLE;
2583 phy_data &= ~(CR_1000T_MS_VALUE);
2586 phy_data &= ~CR_1000T_MS_ENABLE;
2590 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2595 return E1000_SUCCESS;
2598 /*****************************************************************************
2599 * This function checks the mode of the firmware.
2601 * returns - true when the mode is IAMT or false.
2602 ****************************************************************************/
2604 e1000_check_mng_mode(struct e1000_hw *hw)
2609 fwsm = E1000_READ_REG(hw, FWSM);
2611 if (hw->mac_type == e1000_ich8lan) {
2612 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2613 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2615 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2616 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2623 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2625 uint16_t swfw = E1000_SWFW_PHY0_SM;
2629 if (e1000_is_second_port(hw))
2630 swfw = E1000_SWFW_PHY1_SM;
2632 if (e1000_swfw_sync_acquire(hw, swfw))
2633 return -E1000_ERR_SWFW_SYNC;
2635 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2636 & E1000_KUMCTRLSTA_OFFSET) | data;
2637 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2640 return E1000_SUCCESS;
2644 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2646 uint16_t swfw = E1000_SWFW_PHY0_SM;
2650 if (e1000_is_second_port(hw))
2651 swfw = E1000_SWFW_PHY1_SM;
2653 if (e1000_swfw_sync_acquire(hw, swfw)) {
2654 debug("%s[%i]\n", __func__, __LINE__);
2655 return -E1000_ERR_SWFW_SYNC;
2658 /* Write register address */
2659 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2660 E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2661 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2664 /* Read the data returned */
2665 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2666 *data = (uint16_t)reg_val;
2668 return E1000_SUCCESS;
2671 /********************************************************************
2672 * Copper link setup for e1000_phy_gg82563 series.
2674 * hw - Struct containing variables accessed by shared code
2675 *********************************************************************/
2677 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2685 if (!hw->phy_reset_disable) {
2686 /* Enable CRS on TX for half-duplex operation. */
2687 ret_val = e1000_read_phy_reg(hw,
2688 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2692 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2693 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2694 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2696 ret_val = e1000_write_phy_reg(hw,
2697 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2702 * MDI/MDI-X = 0 (default)
2703 * 0 - Auto for all speeds
2706 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2708 ret_val = e1000_read_phy_reg(hw,
2709 GG82563_PHY_SPEC_CTRL, &phy_data);
2713 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2717 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2720 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2724 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2729 * disable_polarity_correction = 0 (default)
2730 * Automatic Correction for Reversed Cable Polarity
2734 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2735 ret_val = e1000_write_phy_reg(hw,
2736 GG82563_PHY_SPEC_CTRL, phy_data);
2741 /* SW Reset the PHY so all changes take effect */
2742 ret_val = e1000_phy_reset(hw);
2744 DEBUGOUT("Error Resetting the PHY\n");
2747 } /* phy_reset_disable */
2749 if (hw->mac_type == e1000_80003es2lan) {
2750 /* Bypass RX and TX FIFO's */
2751 ret_val = e1000_write_kmrn_reg(hw,
2752 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2753 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2754 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2758 ret_val = e1000_read_phy_reg(hw,
2759 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2763 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2764 ret_val = e1000_write_phy_reg(hw,
2765 GG82563_PHY_SPEC_CTRL_2, phy_data);
2770 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2771 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2772 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2774 ret_val = e1000_read_phy_reg(hw,
2775 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2779 /* Do not init these registers when the HW is in IAMT mode, since the
2780 * firmware will have already initialized them. We only initialize
2781 * them if the HW is not in IAMT mode.
2783 if (e1000_check_mng_mode(hw) == false) {
2784 /* Enable Electrical Idle on the PHY */
2785 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2786 ret_val = e1000_write_phy_reg(hw,
2787 GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2791 ret_val = e1000_read_phy_reg(hw,
2792 GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2796 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2797 ret_val = e1000_write_phy_reg(hw,
2798 GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2804 /* Workaround: Disable padding in Kumeran interface in the MAC
2805 * and in the PHY to avoid CRC errors.
2807 ret_val = e1000_read_phy_reg(hw,
2808 GG82563_PHY_INBAND_CTRL, &phy_data);
2811 phy_data |= GG82563_ICR_DIS_PADDING;
2812 ret_val = e1000_write_phy_reg(hw,
2813 GG82563_PHY_INBAND_CTRL, phy_data);
2817 return E1000_SUCCESS;
2820 /********************************************************************
2821 * Copper link setup for e1000_phy_m88 series.
2823 * hw - Struct containing variables accessed by shared code
2824 *********************************************************************/
2826 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
2833 if (hw->phy_reset_disable)
2834 return E1000_SUCCESS;
2836 /* Enable CRS on TX. This must be set for half-duplex operation. */
2837 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2841 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2844 * MDI/MDI-X = 0 (default)
2845 * 0 - Auto for all speeds
2848 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2850 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2854 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
2857 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
2860 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
2864 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
2869 * disable_polarity_correction = 0 (default)
2870 * Automatic Correction for Reversed Cable Polarity
2874 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
2875 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2879 if (hw->phy_revision < M88E1011_I_REV_4) {
2880 /* Force TX_CLK in the Extended PHY Specific Control Register
2883 ret_val = e1000_read_phy_reg(hw,
2884 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2888 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2890 if ((hw->phy_revision == E1000_REVISION_2) &&
2891 (hw->phy_id == M88E1111_I_PHY_ID)) {
2892 /* Vidalia Phy, set the downshift counter to 5x */
2893 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
2894 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
2895 ret_val = e1000_write_phy_reg(hw,
2896 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2900 /* Configure Master and Slave downshift values */
2901 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
2902 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
2903 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
2904 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
2905 ret_val = e1000_write_phy_reg(hw,
2906 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2912 /* SW Reset the PHY so all changes take effect */
2913 ret_val = e1000_phy_reset(hw);
2915 DEBUGOUT("Error Resetting the PHY\n");
2919 return E1000_SUCCESS;
2922 /********************************************************************
2923 * Setup auto-negotiation and flow control advertisements,
2924 * and then perform auto-negotiation.
2926 * hw - Struct containing variables accessed by shared code
2927 *********************************************************************/
2929 e1000_copper_link_autoneg(struct e1000_hw *hw)
2936 /* Perform some bounds checking on the hw->autoneg_advertised
2937 * parameter. If this variable is zero, then set it to the default.
2939 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
2941 /* If autoneg_advertised is zero, we assume it was not defaulted
2942 * by the calling code so we set to advertise full capability.
2944 if (hw->autoneg_advertised == 0)
2945 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
2947 /* IFE phy only supports 10/100 */
2948 if (hw->phy_type == e1000_phy_ife)
2949 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
2951 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
2952 ret_val = e1000_phy_setup_autoneg(hw);
2954 DEBUGOUT("Error Setting up Auto-Negotiation\n");
2957 DEBUGOUT("Restarting Auto-Neg\n");
2959 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
2960 * the Auto Neg Restart bit in the PHY control register.
2962 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2966 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
2967 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2971 /* Does the user want to wait for Auto-Neg to complete here, or
2972 * check at a later time (for example, callback routine).
2974 /* If we do not wait for autonegtation to complete I
2975 * do not see a valid link status.
2976 * wait_autoneg_complete = 1 .
2978 if (hw->wait_autoneg_complete) {
2979 ret_val = e1000_wait_autoneg(hw);
2981 DEBUGOUT("Error while waiting for autoneg"
2987 hw->get_link_status = true;
2989 return E1000_SUCCESS;
2992 /******************************************************************************
2993 * Config the MAC and the PHY after link is up.
2994 * 1) Set up the MAC to the current PHY speed/duplex
2995 * if we are on 82543. If we
2996 * are on newer silicon, we only need to configure
2997 * collision distance in the Transmit Control Register.
2998 * 2) Set up flow control on the MAC to that established with
3000 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
3002 * hw - Struct containing variables accessed by shared code
3003 ******************************************************************************/
3005 e1000_copper_link_postconfig(struct e1000_hw *hw)
3010 if (hw->mac_type >= e1000_82544) {
3011 e1000_config_collision_dist(hw);
3013 ret_val = e1000_config_mac_to_phy(hw);
3015 DEBUGOUT("Error configuring MAC to PHY settings\n");
3019 ret_val = e1000_config_fc_after_link_up(hw);
3021 DEBUGOUT("Error Configuring Flow Control\n");
3024 return E1000_SUCCESS;
3027 /******************************************************************************
3028 * Detects which PHY is present and setup the speed and duplex
3030 * hw - Struct containing variables accessed by shared code
3031 ******************************************************************************/
3033 e1000_setup_copper_link(struct eth_device *nic)
3035 struct e1000_hw *hw = nic->priv;
3043 switch (hw->mac_type) {
3044 case e1000_80003es2lan:
3046 /* Set the mac to wait the maximum time between each
3047 * iteration and increase the max iterations when
3048 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
3049 ret_val = e1000_write_kmrn_reg(hw,
3050 GG82563_REG(0x34, 4), 0xFFFF);
3053 ret_val = e1000_read_kmrn_reg(hw,
3054 GG82563_REG(0x34, 9), ®_data);
3058 ret_val = e1000_write_kmrn_reg(hw,
3059 GG82563_REG(0x34, 9), reg_data);
3066 /* Check if it is a valid PHY and set PHY mode if necessary. */
3067 ret_val = e1000_copper_link_preconfig(hw);
3070 switch (hw->mac_type) {
3071 case e1000_80003es2lan:
3072 /* Kumeran registers are written-only */
3074 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
3075 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
3076 ret_val = e1000_write_kmrn_reg(hw,
3077 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3085 if (hw->phy_type == e1000_phy_igp ||
3086 hw->phy_type == e1000_phy_igp_3 ||
3087 hw->phy_type == e1000_phy_igp_2) {
3088 ret_val = e1000_copper_link_igp_setup(hw);
3091 } else if (hw->phy_type == e1000_phy_m88 ||
3092 hw->phy_type == e1000_phy_igb) {
3093 ret_val = e1000_copper_link_mgp_setup(hw);
3096 } else if (hw->phy_type == e1000_phy_gg82563) {
3097 ret_val = e1000_copper_link_ggp_setup(hw);
3103 /* Setup autoneg and flow control advertisement
3104 * and perform autonegotiation */
3105 ret_val = e1000_copper_link_autoneg(hw);
3109 /* Check link status. Wait up to 100 microseconds for link to become
3112 for (i = 0; i < 10; i++) {
3113 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3116 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3120 if (phy_data & MII_SR_LINK_STATUS) {
3121 /* Config the MAC and PHY after link is up */
3122 ret_val = e1000_copper_link_postconfig(hw);
3126 DEBUGOUT("Valid link established!!!\n");
3127 return E1000_SUCCESS;
3132 DEBUGOUT("Unable to establish link!!!\n");
3133 return E1000_SUCCESS;
3136 /******************************************************************************
3137 * Configures PHY autoneg and flow control advertisement settings
3139 * hw - Struct containing variables accessed by shared code
3140 ******************************************************************************/
3142 e1000_phy_setup_autoneg(struct e1000_hw *hw)
3145 uint16_t mii_autoneg_adv_reg;
3146 uint16_t mii_1000t_ctrl_reg;
3150 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3151 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3155 if (hw->phy_type != e1000_phy_ife) {
3156 /* Read the MII 1000Base-T Control Register (Address 9). */
3157 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3158 &mii_1000t_ctrl_reg);
3162 mii_1000t_ctrl_reg = 0;
3164 /* Need to parse both autoneg_advertised and fc and set up
3165 * the appropriate PHY registers. First we will parse for
3166 * autoneg_advertised software override. Since we can advertise
3167 * a plethora of combinations, we need to check each bit
3171 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3172 * Advertisement Register (Address 4) and the 1000 mb speed bits in
3173 * the 1000Base-T Control Register (Address 9).
3175 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3176 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3178 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3180 /* Do we want to advertise 10 Mb Half Duplex? */
3181 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3182 DEBUGOUT("Advertise 10mb Half duplex\n");
3183 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3186 /* Do we want to advertise 10 Mb Full Duplex? */
3187 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3188 DEBUGOUT("Advertise 10mb Full duplex\n");
3189 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3192 /* Do we want to advertise 100 Mb Half Duplex? */
3193 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3194 DEBUGOUT("Advertise 100mb Half duplex\n");
3195 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3198 /* Do we want to advertise 100 Mb Full Duplex? */
3199 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3200 DEBUGOUT("Advertise 100mb Full duplex\n");
3201 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3204 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3205 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3207 ("Advertise 1000mb Half duplex requested, request denied!\n");
3210 /* Do we want to advertise 1000 Mb Full Duplex? */
3211 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3212 DEBUGOUT("Advertise 1000mb Full duplex\n");
3213 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3216 /* Check for a software override of the flow control settings, and
3217 * setup the PHY advertisement registers accordingly. If
3218 * auto-negotiation is enabled, then software will have to set the
3219 * "PAUSE" bits to the correct value in the Auto-Negotiation
3220 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3222 * The possible values of the "fc" parameter are:
3223 * 0: Flow control is completely disabled
3224 * 1: Rx flow control is enabled (we can receive pause frames
3225 * but not send pause frames).
3226 * 2: Tx flow control is enabled (we can send pause frames
3227 * but we do not support receiving pause frames).
3228 * 3: Both Rx and TX flow control (symmetric) are enabled.
3229 * other: No software override. The flow control configuration
3230 * in the EEPROM is used.
3233 case e1000_fc_none: /* 0 */
3234 /* Flow control (RX & TX) is completely disabled by a
3235 * software over-ride.
3237 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3239 case e1000_fc_rx_pause: /* 1 */
3240 /* RX Flow control is enabled, and TX Flow control is
3241 * disabled, by a software over-ride.
3243 /* Since there really isn't a way to advertise that we are
3244 * capable of RX Pause ONLY, we will advertise that we
3245 * support both symmetric and asymmetric RX PAUSE. Later
3246 * (in e1000_config_fc_after_link_up) we will disable the
3247 *hw's ability to send PAUSE frames.
3249 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3251 case e1000_fc_tx_pause: /* 2 */
3252 /* TX Flow control is enabled, and RX Flow control is
3253 * disabled, by a software over-ride.
3255 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3256 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3258 case e1000_fc_full: /* 3 */
3259 /* Flow control (both RX and TX) is enabled by a software
3262 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3265 DEBUGOUT("Flow control param set incorrectly\n");
3266 return -E1000_ERR_CONFIG;
3269 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3273 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3275 if (hw->phy_type != e1000_phy_ife) {
3276 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3277 mii_1000t_ctrl_reg);
3282 return E1000_SUCCESS;
3285 /******************************************************************************
3286 * Sets the collision distance in the Transmit Control register
3288 * hw - Struct containing variables accessed by shared code
3290 * Link should have been established previously. Reads the speed and duplex
3291 * information from the Device Status register.
3292 ******************************************************************************/
3294 e1000_config_collision_dist(struct e1000_hw *hw)
3296 uint32_t tctl, coll_dist;
3300 if (hw->mac_type < e1000_82543)
3301 coll_dist = E1000_COLLISION_DISTANCE_82542;
3303 coll_dist = E1000_COLLISION_DISTANCE;
3305 tctl = E1000_READ_REG(hw, TCTL);
3307 tctl &= ~E1000_TCTL_COLD;
3308 tctl |= coll_dist << E1000_COLD_SHIFT;
3310 E1000_WRITE_REG(hw, TCTL, tctl);
3311 E1000_WRITE_FLUSH(hw);
3314 /******************************************************************************
3315 * Sets MAC speed and duplex settings to reflect the those in the PHY
3317 * hw - Struct containing variables accessed by shared code
3318 * mii_reg - data to write to the MII control register
3320 * The contents of the PHY register containing the needed information need to
3322 ******************************************************************************/
3324 e1000_config_mac_to_phy(struct e1000_hw *hw)
3331 /* Read the Device Control Register and set the bits to Force Speed
3334 ctrl = E1000_READ_REG(hw, CTRL);
3335 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3336 ctrl &= ~(E1000_CTRL_ILOS);
3337 ctrl |= (E1000_CTRL_SPD_SEL);
3339 /* Set up duplex in the Device Control and Transmit Control
3340 * registers depending on negotiated values.
3342 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3343 DEBUGOUT("PHY Read Error\n");
3344 return -E1000_ERR_PHY;
3346 if (phy_data & M88E1000_PSSR_DPLX)
3347 ctrl |= E1000_CTRL_FD;
3349 ctrl &= ~E1000_CTRL_FD;
3351 e1000_config_collision_dist(hw);
3353 /* Set up speed in the Device Control register depending on
3354 * negotiated values.
3356 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3357 ctrl |= E1000_CTRL_SPD_1000;
3358 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3359 ctrl |= E1000_CTRL_SPD_100;
3360 /* Write the configured values back to the Device Control Reg. */
3361 E1000_WRITE_REG(hw, CTRL, ctrl);
3365 /******************************************************************************
3366 * Forces the MAC's flow control settings.
3368 * hw - Struct containing variables accessed by shared code
3370 * Sets the TFCE and RFCE bits in the device control register to reflect
3371 * the adapter settings. TFCE and RFCE need to be explicitly set by
3372 * software when a Copper PHY is used because autonegotiation is managed
3373 * by the PHY rather than the MAC. Software must also configure these
3374 * bits when link is forced on a fiber connection.
3375 *****************************************************************************/
3377 e1000_force_mac_fc(struct e1000_hw *hw)
3383 /* Get the current configuration of the Device Control Register */
3384 ctrl = E1000_READ_REG(hw, CTRL);
3386 /* Because we didn't get link via the internal auto-negotiation
3387 * mechanism (we either forced link or we got link via PHY
3388 * auto-neg), we have to manually enable/disable transmit an
3389 * receive flow control.
3391 * The "Case" statement below enables/disable flow control
3392 * according to the "hw->fc" parameter.
3394 * The possible values of the "fc" parameter are:
3395 * 0: Flow control is completely disabled
3396 * 1: Rx flow control is enabled (we can receive pause
3397 * frames but not send pause frames).
3398 * 2: Tx flow control is enabled (we can send pause frames
3399 * frames but we do not receive pause frames).
3400 * 3: Both Rx and TX flow control (symmetric) is enabled.
3401 * other: No other values should be possible at this point.
3406 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3408 case e1000_fc_rx_pause:
3409 ctrl &= (~E1000_CTRL_TFCE);
3410 ctrl |= E1000_CTRL_RFCE;
3412 case e1000_fc_tx_pause:
3413 ctrl &= (~E1000_CTRL_RFCE);
3414 ctrl |= E1000_CTRL_TFCE;
3417 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3420 DEBUGOUT("Flow control param set incorrectly\n");
3421 return -E1000_ERR_CONFIG;
3424 /* Disable TX Flow Control for 82542 (rev 2.0) */
3425 if (hw->mac_type == e1000_82542_rev2_0)
3426 ctrl &= (~E1000_CTRL_TFCE);
3428 E1000_WRITE_REG(hw, CTRL, ctrl);
3432 /******************************************************************************
3433 * Configures flow control settings after link is established
3435 * hw - Struct containing variables accessed by shared code
3437 * Should be called immediately after a valid link has been established.
3438 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3439 * and autonegotiation is enabled, the MAC flow control settings will be set
3440 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3441 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3442 *****************************************************************************/
3444 e1000_config_fc_after_link_up(struct e1000_hw *hw)
3447 uint16_t mii_status_reg;
3448 uint16_t mii_nway_adv_reg;
3449 uint16_t mii_nway_lp_ability_reg;
3455 /* Check for the case where we have fiber media and auto-neg failed
3456 * so we had to force link. In this case, we need to force the
3457 * configuration of the MAC to match the "fc" parameter.
3459 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3460 || ((hw->media_type == e1000_media_type_internal_serdes)
3461 && (hw->autoneg_failed))
3462 || ((hw->media_type == e1000_media_type_copper)
3463 && (!hw->autoneg))) {
3464 ret_val = e1000_force_mac_fc(hw);
3466 DEBUGOUT("Error forcing flow control settings\n");
3471 /* Check for the case where we have copper media and auto-neg is
3472 * enabled. In this case, we need to check and see if Auto-Neg
3473 * has completed, and if so, how the PHY and link partner has
3474 * flow control configured.
3476 if (hw->media_type == e1000_media_type_copper) {
3477 /* Read the MII Status Register and check to see if AutoNeg
3478 * has completed. We read this twice because this reg has
3479 * some "sticky" (latched) bits.
3481 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3482 DEBUGOUT("PHY Read Error \n");
3483 return -E1000_ERR_PHY;
3485 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3486 DEBUGOUT("PHY Read Error \n");
3487 return -E1000_ERR_PHY;
3490 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3491 /* The AutoNeg process has completed, so we now need to
3492 * read both the Auto Negotiation Advertisement Register
3493 * (Address 4) and the Auto_Negotiation Base Page Ability
3494 * Register (Address 5) to determine how flow control was
3497 if (e1000_read_phy_reg
3498 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3499 DEBUGOUT("PHY Read Error\n");
3500 return -E1000_ERR_PHY;
3502 if (e1000_read_phy_reg
3503 (hw, PHY_LP_ABILITY,
3504 &mii_nway_lp_ability_reg) < 0) {
3505 DEBUGOUT("PHY Read Error\n");
3506 return -E1000_ERR_PHY;
3509 /* Two bits in the Auto Negotiation Advertisement Register
3510 * (Address 4) and two bits in the Auto Negotiation Base
3511 * Page Ability Register (Address 5) determine flow control
3512 * for both the PHY and the link partner. The following
3513 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3514 * 1999, describes these PAUSE resolution bits and how flow
3515 * control is determined based upon these settings.
3516 * NOTE: DC = Don't Care
3518 * LOCAL DEVICE | LINK PARTNER
3519 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3520 *-------|---------|-------|---------|--------------------
3521 * 0 | 0 | DC | DC | e1000_fc_none
3522 * 0 | 1 | 0 | DC | e1000_fc_none
3523 * 0 | 1 | 1 | 0 | e1000_fc_none
3524 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
3525 * 1 | 0 | 0 | DC | e1000_fc_none
3526 * 1 | DC | 1 | DC | e1000_fc_full
3527 * 1 | 1 | 0 | 0 | e1000_fc_none
3528 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
3531 /* Are both PAUSE bits set to 1? If so, this implies
3532 * Symmetric Flow Control is enabled at both ends. The
3533 * ASM_DIR bits are irrelevant per the spec.
3535 * For Symmetric Flow Control:
3537 * LOCAL DEVICE | LINK PARTNER
3538 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3539 *-------|---------|-------|---------|--------------------
3540 * 1 | DC | 1 | DC | e1000_fc_full
3543 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3544 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3545 /* Now we need to check if the user selected RX ONLY
3546 * of pause frames. In this case, we had to advertise
3547 * FULL flow control because we could not advertise RX
3548 * ONLY. Hence, we must now check to see if we need to
3549 * turn OFF the TRANSMISSION of PAUSE frames.
3551 if (hw->original_fc == e1000_fc_full) {
3552 hw->fc = e1000_fc_full;
3553 DEBUGOUT("Flow Control = FULL.\r\n");
3555 hw->fc = e1000_fc_rx_pause;
3557 ("Flow Control = RX PAUSE frames only.\r\n");
3560 /* For receiving PAUSE frames ONLY.
3562 * LOCAL DEVICE | LINK PARTNER
3563 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3564 *-------|---------|-------|---------|--------------------
3565 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
3568 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3569 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3570 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3571 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3573 hw->fc = e1000_fc_tx_pause;
3575 ("Flow Control = TX PAUSE frames only.\r\n");
3577 /* For transmitting PAUSE frames ONLY.
3579 * LOCAL DEVICE | LINK PARTNER
3580 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3581 *-------|---------|-------|---------|--------------------
3582 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
3585 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3586 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3587 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3588 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3590 hw->fc = e1000_fc_rx_pause;
3592 ("Flow Control = RX PAUSE frames only.\r\n");
3594 /* Per the IEEE spec, at this point flow control should be
3595 * disabled. However, we want to consider that we could
3596 * be connected to a legacy switch that doesn't advertise
3597 * desired flow control, but can be forced on the link
3598 * partner. So if we advertised no flow control, that is
3599 * what we will resolve to. If we advertised some kind of
3600 * receive capability (Rx Pause Only or Full Flow Control)
3601 * and the link partner advertised none, we will configure
3602 * ourselves to enable Rx Flow Control only. We can do
3603 * this safely for two reasons: If the link partner really
3604 * didn't want flow control enabled, and we enable Rx, no
3605 * harm done since we won't be receiving any PAUSE frames
3606 * anyway. If the intent on the link partner was to have
3607 * flow control enabled, then by us enabling RX only, we
3608 * can at least receive pause frames and process them.
3609 * This is a good idea because in most cases, since we are
3610 * predominantly a server NIC, more times than not we will
3611 * be asked to delay transmission of packets than asking
3612 * our link partner to pause transmission of frames.
3614 else if (hw->original_fc == e1000_fc_none ||
3615 hw->original_fc == e1000_fc_tx_pause) {
3616 hw->fc = e1000_fc_none;
3617 DEBUGOUT("Flow Control = NONE.\r\n");
3619 hw->fc = e1000_fc_rx_pause;
3621 ("Flow Control = RX PAUSE frames only.\r\n");
3624 /* Now we need to do one last check... If we auto-
3625 * negotiated to HALF DUPLEX, flow control should not be
3626 * enabled per IEEE 802.3 spec.
3628 e1000_get_speed_and_duplex(hw, &speed, &duplex);
3630 if (duplex == HALF_DUPLEX)
3631 hw->fc = e1000_fc_none;
3633 /* Now we call a subroutine to actually force the MAC
3634 * controller to use the correct flow control settings.
3636 ret_val = e1000_force_mac_fc(hw);
3639 ("Error forcing flow control settings\n");
3644 ("Copper PHY and Auto Neg has not completed.\r\n");
3647 return E1000_SUCCESS;
3650 /******************************************************************************
3651 * Checks to see if the link status of the hardware has changed.
3653 * hw - Struct containing variables accessed by shared code
3655 * Called by any function that needs to check the link status of the adapter.
3656 *****************************************************************************/
3658 e1000_check_for_link(struct eth_device *nic)
3660 struct e1000_hw *hw = nic->priv;
3668 uint16_t lp_capability;
3672 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3673 * set when the optics detect a signal. On older adapters, it will be
3674 * cleared when there is a signal
3676 ctrl = E1000_READ_REG(hw, CTRL);
3677 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3678 signal = E1000_CTRL_SWDPIN1;
3682 status = E1000_READ_REG(hw, STATUS);
3683 rxcw = E1000_READ_REG(hw, RXCW);
3684 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3686 /* If we have a copper PHY then we only want to go out to the PHY
3687 * registers to see if Auto-Neg has completed and/or if our link
3688 * status has changed. The get_link_status flag will be set if we
3689 * receive a Link Status Change interrupt or we have Rx Sequence
3692 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3693 /* First we want to see if the MII Status Register reports
3694 * link. If so, then we want to get the current speed/duplex
3696 * Read the register twice since the link bit is sticky.
3698 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3699 DEBUGOUT("PHY Read Error\n");
3700 return -E1000_ERR_PHY;
3702 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3703 DEBUGOUT("PHY Read Error\n");
3704 return -E1000_ERR_PHY;
3707 if (phy_data & MII_SR_LINK_STATUS) {
3708 hw->get_link_status = false;
3710 /* No link detected */
3711 return -E1000_ERR_NOLINK;
3714 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
3715 * have Si on board that is 82544 or newer, Auto
3716 * Speed Detection takes care of MAC speed/duplex
3717 * configuration. So we only need to configure Collision
3718 * Distance in the MAC. Otherwise, we need to force
3719 * speed/duplex on the MAC to the current PHY speed/duplex
3722 if (hw->mac_type >= e1000_82544)
3723 e1000_config_collision_dist(hw);
3725 ret_val = e1000_config_mac_to_phy(hw);
3728 ("Error configuring MAC to PHY settings\n");
3733 /* Configure Flow Control now that Auto-Neg has completed. First, we
3734 * need to restore the desired flow control settings because we may
3735 * have had to re-autoneg with a different link partner.
3737 ret_val = e1000_config_fc_after_link_up(hw);
3739 DEBUGOUT("Error configuring flow control\n");
3743 /* At this point we know that we are on copper and we have
3744 * auto-negotiated link. These are conditions for checking the link
3745 * parter capability register. We use the link partner capability to
3746 * determine if TBI Compatibility needs to be turned on or off. If
3747 * the link partner advertises any speed in addition to Gigabit, then
3748 * we assume that they are GMII-based, and TBI compatibility is not
3749 * needed. If no other speeds are advertised, we assume the link
3750 * partner is TBI-based, and we turn on TBI Compatibility.
3752 if (hw->tbi_compatibility_en) {
3753 if (e1000_read_phy_reg
3754 (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3755 DEBUGOUT("PHY Read Error\n");
3756 return -E1000_ERR_PHY;
3758 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3759 NWAY_LPAR_10T_FD_CAPS |
3760 NWAY_LPAR_100TX_HD_CAPS |
3761 NWAY_LPAR_100TX_FD_CAPS |
3762 NWAY_LPAR_100T4_CAPS)) {
3763 /* If our link partner advertises anything in addition to
3764 * gigabit, we do not need to enable TBI compatibility.
3766 if (hw->tbi_compatibility_on) {
3767 /* If we previously were in the mode, turn it off. */
3768 rctl = E1000_READ_REG(hw, RCTL);
3769 rctl &= ~E1000_RCTL_SBP;
3770 E1000_WRITE_REG(hw, RCTL, rctl);
3771 hw->tbi_compatibility_on = false;
3774 /* If TBI compatibility is was previously off, turn it on. For
3775 * compatibility with a TBI link partner, we will store bad
3776 * packets. Some frames have an additional byte on the end and
3777 * will look like CRC errors to to the hardware.
3779 if (!hw->tbi_compatibility_on) {
3780 hw->tbi_compatibility_on = true;
3781 rctl = E1000_READ_REG(hw, RCTL);
3782 rctl |= E1000_RCTL_SBP;
3783 E1000_WRITE_REG(hw, RCTL, rctl);
3788 /* If we don't have link (auto-negotiation failed or link partner cannot
3789 * auto-negotiate), the cable is plugged in (we have signal), and our
3790 * link partner is not trying to auto-negotiate with us (we are receiving
3791 * idles or data), we need to force link up. We also need to give
3792 * auto-negotiation time to complete, in case the cable was just plugged
3793 * in. The autoneg_failed flag does this.
3795 else if ((hw->media_type == e1000_media_type_fiber) &&
3796 (!(status & E1000_STATUS_LU)) &&
3797 ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3798 (!(rxcw & E1000_RXCW_C))) {
3799 if (hw->autoneg_failed == 0) {
3800 hw->autoneg_failed = 1;
3803 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3805 /* Disable auto-negotiation in the TXCW register */
3806 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3808 /* Force link-up and also force full-duplex. */
3809 ctrl = E1000_READ_REG(hw, CTRL);
3810 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3811 E1000_WRITE_REG(hw, CTRL, ctrl);
3813 /* Configure Flow Control after forcing link up. */
3814 ret_val = e1000_config_fc_after_link_up(hw);
3816 DEBUGOUT("Error configuring flow control\n");
3820 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3821 * auto-negotiation in the TXCW register and disable forced link in the
3822 * Device Control register in an attempt to auto-negotiate with our link
3825 else if ((hw->media_type == e1000_media_type_fiber) &&
3826 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3828 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3829 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3830 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3835 /******************************************************************************
3836 * Configure the MAC-to-PHY interface for 10/100Mbps
3838 * hw - Struct containing variables accessed by shared code
3839 ******************************************************************************/
3841 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
3843 int32_t ret_val = E1000_SUCCESS;
3849 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
3850 ret_val = e1000_write_kmrn_reg(hw,
3851 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3855 /* Configure Transmit Inter-Packet Gap */
3856 tipg = E1000_READ_REG(hw, TIPG);
3857 tipg &= ~E1000_TIPG_IPGT_MASK;
3858 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
3859 E1000_WRITE_REG(hw, TIPG, tipg);
3861 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
3866 if (duplex == HALF_DUPLEX)
3867 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
3869 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3871 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3877 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
3879 int32_t ret_val = E1000_SUCCESS;
3885 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
3886 ret_val = e1000_write_kmrn_reg(hw,
3887 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3891 /* Configure Transmit Inter-Packet Gap */
3892 tipg = E1000_READ_REG(hw, TIPG);
3893 tipg &= ~E1000_TIPG_IPGT_MASK;
3894 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
3895 E1000_WRITE_REG(hw, TIPG, tipg);
3897 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
3902 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3903 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3908 /******************************************************************************
3909 * Detects the current speed and duplex settings of the hardware.
3911 * hw - Struct containing variables accessed by shared code
3912 * speed - Speed of the connection
3913 * duplex - Duplex setting of the connection
3914 *****************************************************************************/
3916 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
3925 if (hw->mac_type >= e1000_82543) {
3926 status = E1000_READ_REG(hw, STATUS);
3927 if (status & E1000_STATUS_SPEED_1000) {
3928 *speed = SPEED_1000;
3929 DEBUGOUT("1000 Mbs, ");
3930 } else if (status & E1000_STATUS_SPEED_100) {
3932 DEBUGOUT("100 Mbs, ");
3935 DEBUGOUT("10 Mbs, ");
3938 if (status & E1000_STATUS_FD) {
3939 *duplex = FULL_DUPLEX;
3940 DEBUGOUT("Full Duplex\r\n");
3942 *duplex = HALF_DUPLEX;
3943 DEBUGOUT(" Half Duplex\r\n");
3946 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
3947 *speed = SPEED_1000;
3948 *duplex = FULL_DUPLEX;
3951 /* IGP01 PHY may advertise full duplex operation after speed downgrade
3952 * even if it is operating at half duplex. Here we set the duplex
3953 * settings to match the duplex in the link partner's capabilities.
3955 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3956 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3960 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3961 *duplex = HALF_DUPLEX;
3963 ret_val = e1000_read_phy_reg(hw,
3964 PHY_LP_ABILITY, &phy_data);
3967 if ((*speed == SPEED_100 &&
3968 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
3969 || (*speed == SPEED_10
3970 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3971 *duplex = HALF_DUPLEX;
3975 if ((hw->mac_type == e1000_80003es2lan) &&
3976 (hw->media_type == e1000_media_type_copper)) {
3977 if (*speed == SPEED_1000)
3978 ret_val = e1000_configure_kmrn_for_1000(hw);
3980 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3984 return E1000_SUCCESS;
3987 /******************************************************************************
3988 * Blocks until autoneg completes or times out (~4.5 seconds)
3990 * hw - Struct containing variables accessed by shared code
3991 ******************************************************************************/
3993 e1000_wait_autoneg(struct e1000_hw *hw)
3999 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
4001 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
4002 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
4003 /* Read the MII Status Register and wait for Auto-Neg
4004 * Complete bit to be set.
4006 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4007 DEBUGOUT("PHY Read Error\n");
4008 return -E1000_ERR_PHY;
4010 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4011 DEBUGOUT("PHY Read Error\n");
4012 return -E1000_ERR_PHY;
4014 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
4015 DEBUGOUT("Auto-Neg complete.\n");
4020 DEBUGOUT("Auto-Neg timedout.\n");
4021 return -E1000_ERR_TIMEOUT;
4024 /******************************************************************************
4025 * Raises the Management Data Clock
4027 * hw - Struct containing variables accessed by shared code
4028 * ctrl - Device control register's current value
4029 ******************************************************************************/
4031 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4033 /* Raise the clock input to the Management Data Clock (by setting the MDC
4034 * bit), and then delay 2 microseconds.
4036 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
4037 E1000_WRITE_FLUSH(hw);
4041 /******************************************************************************
4042 * Lowers the Management Data Clock
4044 * hw - Struct containing variables accessed by shared code
4045 * ctrl - Device control register's current value
4046 ******************************************************************************/
4048 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4050 /* Lower the clock input to the Management Data Clock (by clearing the MDC
4051 * bit), and then delay 2 microseconds.
4053 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
4054 E1000_WRITE_FLUSH(hw);
4058 /******************************************************************************
4059 * Shifts data bits out to the PHY
4061 * hw - Struct containing variables accessed by shared code
4062 * data - Data to send out to the PHY
4063 * count - Number of bits to shift out
4065 * Bits are shifted out in MSB to LSB order.
4066 ******************************************************************************/
4068 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
4073 /* We need to shift "count" number of bits out to the PHY. So, the value
4074 * in the "data" parameter will be shifted out to the PHY one bit at a
4075 * time. In order to do this, "data" must be broken down into bits.
4078 mask <<= (count - 1);
4080 ctrl = E1000_READ_REG(hw, CTRL);
4082 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
4083 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4086 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4087 * then raising and lowering the Management Data Clock. A "0" is
4088 * shifted out to the PHY by setting the MDIO bit to "0" and then
4089 * raising and lowering the clock.
4092 ctrl |= E1000_CTRL_MDIO;
4094 ctrl &= ~E1000_CTRL_MDIO;
4096 E1000_WRITE_REG(hw, CTRL, ctrl);
4097 E1000_WRITE_FLUSH(hw);
4101 e1000_raise_mdi_clk(hw, &ctrl);
4102 e1000_lower_mdi_clk(hw, &ctrl);
4108 /******************************************************************************
4109 * Shifts data bits in from the PHY
4111 * hw - Struct containing variables accessed by shared code
4113 * Bits are shifted in in MSB to LSB order.
4114 ******************************************************************************/
4116 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4122 /* In order to read a register from the PHY, we need to shift in a total
4123 * of 18 bits from the PHY. The first two bit (turnaround) times are used
4124 * to avoid contention on the MDIO pin when a read operation is performed.
4125 * These two bits are ignored by us and thrown away. Bits are "shifted in"
4126 * by raising the input to the Management Data Clock (setting the MDC bit),
4127 * and then reading the value of the MDIO bit.
4129 ctrl = E1000_READ_REG(hw, CTRL);
4131 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4132 ctrl &= ~E1000_CTRL_MDIO_DIR;
4133 ctrl &= ~E1000_CTRL_MDIO;
4135 E1000_WRITE_REG(hw, CTRL, ctrl);
4136 E1000_WRITE_FLUSH(hw);
4138 /* Raise and Lower the clock before reading in the data. This accounts for
4139 * the turnaround bits. The first clock occurred when we clocked out the
4140 * last bit of the Register Address.
4142 e1000_raise_mdi_clk(hw, &ctrl);
4143 e1000_lower_mdi_clk(hw, &ctrl);
4145 for (data = 0, i = 0; i < 16; i++) {
4147 e1000_raise_mdi_clk(hw, &ctrl);
4148 ctrl = E1000_READ_REG(hw, CTRL);
4149 /* Check to see if we shifted in a "1". */
4150 if (ctrl & E1000_CTRL_MDIO)
4152 e1000_lower_mdi_clk(hw, &ctrl);
4155 e1000_raise_mdi_clk(hw, &ctrl);
4156 e1000_lower_mdi_clk(hw, &ctrl);
4161 /*****************************************************************************
4162 * Reads the value from a PHY register
4164 * hw - Struct containing variables accessed by shared code
4165 * reg_addr - address of the PHY register to read
4166 ******************************************************************************/
4168 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4172 const uint32_t phy_addr = 1;
4174 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4175 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4176 return -E1000_ERR_PARAM;
4179 if (hw->mac_type > e1000_82543) {
4180 /* Set up Op-code, Phy Address, and register address in the MDI
4181 * Control register. The MAC will take care of interfacing with the
4182 * PHY to retrieve the desired data.
4184 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4185 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4186 (E1000_MDIC_OP_READ));
4188 E1000_WRITE_REG(hw, MDIC, mdic);
4190 /* Poll the ready bit to see if the MDI read completed */
4191 for (i = 0; i < 64; i++) {
4193 mdic = E1000_READ_REG(hw, MDIC);
4194 if (mdic & E1000_MDIC_READY)
4197 if (!(mdic & E1000_MDIC_READY)) {
4198 DEBUGOUT("MDI Read did not complete\n");
4199 return -E1000_ERR_PHY;
4201 if (mdic & E1000_MDIC_ERROR) {
4202 DEBUGOUT("MDI Error\n");
4203 return -E1000_ERR_PHY;
4205 *phy_data = (uint16_t) mdic;
4207 /* We must first send a preamble through the MDIO pin to signal the
4208 * beginning of an MII instruction. This is done by sending 32
4209 * consecutive "1" bits.
4211 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4213 /* Now combine the next few fields that are required for a read
4214 * operation. We use this method instead of calling the
4215 * e1000_shift_out_mdi_bits routine five different times. The format of
4216 * a MII read instruction consists of a shift out of 14 bits and is
4217 * defined as follows:
4218 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4219 * followed by a shift in of 18 bits. This first two bits shifted in
4220 * are TurnAround bits used to avoid contention on the MDIO pin when a
4221 * READ operation is performed. These two bits are thrown away
4222 * followed by a shift in of 16 bits which contains the desired data.
4224 mdic = ((reg_addr) | (phy_addr << 5) |
4225 (PHY_OP_READ << 10) | (PHY_SOF << 12));
4227 e1000_shift_out_mdi_bits(hw, mdic, 14);
4229 /* Now that we've shifted out the read command to the MII, we need to
4230 * "shift in" the 16-bit value (18 total bits) of the requested PHY
4233 *phy_data = e1000_shift_in_mdi_bits(hw);
4238 /******************************************************************************
4239 * Writes a value to a PHY register
4241 * hw - Struct containing variables accessed by shared code
4242 * reg_addr - address of the PHY register to write
4243 * data - data to write to the PHY
4244 ******************************************************************************/
4246 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4250 const uint32_t phy_addr = 1;
4252 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4253 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4254 return -E1000_ERR_PARAM;
4257 if (hw->mac_type > e1000_82543) {
4258 /* Set up Op-code, Phy Address, register address, and data intended
4259 * for the PHY register in the MDI Control register. The MAC will take
4260 * care of interfacing with the PHY to send the desired data.
4262 mdic = (((uint32_t) phy_data) |
4263 (reg_addr << E1000_MDIC_REG_SHIFT) |
4264 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4265 (E1000_MDIC_OP_WRITE));
4267 E1000_WRITE_REG(hw, MDIC, mdic);
4269 /* Poll the ready bit to see if the MDI read completed */
4270 for (i = 0; i < 64; i++) {
4272 mdic = E1000_READ_REG(hw, MDIC);
4273 if (mdic & E1000_MDIC_READY)
4276 if (!(mdic & E1000_MDIC_READY)) {
4277 DEBUGOUT("MDI Write did not complete\n");
4278 return -E1000_ERR_PHY;
4281 /* We'll need to use the SW defined pins to shift the write command
4282 * out to the PHY. We first send a preamble to the PHY to signal the
4283 * beginning of the MII instruction. This is done by sending 32
4284 * consecutive "1" bits.
4286 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4288 /* Now combine the remaining required fields that will indicate a
4289 * write operation. We use this method instead of calling the
4290 * e1000_shift_out_mdi_bits routine for each field in the command. The
4291 * format of a MII write instruction is as follows:
4292 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4294 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4295 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4297 mdic |= (uint32_t) phy_data;
4299 e1000_shift_out_mdi_bits(hw, mdic, 32);
4304 /******************************************************************************
4305 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4306 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
4307 * the caller to figure out how to deal with it.
4309 * hw - Struct containing variables accessed by shared code
4311 * returns: - E1000_BLK_PHY_RESET
4314 *****************************************************************************/
4316 e1000_check_phy_reset_block(struct e1000_hw *hw)
4321 if (hw->mac_type == e1000_ich8lan) {
4322 fwsm = E1000_READ_REG(hw, FWSM);
4323 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4324 : E1000_BLK_PHY_RESET;
4327 if (hw->mac_type > e1000_82547_rev_2)
4328 manc = E1000_READ_REG(hw, MANC);
4329 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4330 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4333 /***************************************************************************
4334 * Checks if the PHY configuration is done
4336 * hw: Struct containing variables accessed by shared code
4338 * returns: - E1000_ERR_RESET if fail to reset MAC
4339 * E1000_SUCCESS at any other case.
4341 ***************************************************************************/
4343 e1000_get_phy_cfg_done(struct e1000_hw *hw)
4345 int32_t timeout = PHY_CFG_TIMEOUT;
4346 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4350 switch (hw->mac_type) {
4355 case e1000_80003es2lan:
4356 /* Separate *_CFG_DONE_* bit for each port */
4357 if (e1000_is_second_port(hw))
4358 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
4365 if (hw->mac_type == e1000_igb) {
4366 if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
4369 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4376 DEBUGOUT("MNG configuration cycle has not "
4378 return -E1000_ERR_RESET;
4383 return E1000_SUCCESS;
4386 /******************************************************************************
4387 * Returns the PHY to the power-on reset state
4389 * hw - Struct containing variables accessed by shared code
4390 ******************************************************************************/
4392 e1000_phy_hw_reset(struct e1000_hw *hw)
4394 uint16_t swfw = E1000_SWFW_PHY0_SM;
4395 uint32_t ctrl, ctrl_ext;
4401 /* In the case of the phy reset being blocked, it's not an error, we
4402 * simply return success without performing the reset. */
4403 ret_val = e1000_check_phy_reset_block(hw);
4405 return E1000_SUCCESS;
4407 DEBUGOUT("Resetting Phy...\n");
4409 if (hw->mac_type > e1000_82543) {
4410 if (e1000_is_second_port(hw))
4411 swfw = E1000_SWFW_PHY1_SM;
4413 if (e1000_swfw_sync_acquire(hw, swfw)) {
4414 DEBUGOUT("Unable to acquire swfw sync\n");
4415 return -E1000_ERR_SWFW_SYNC;
4418 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4419 * bit. Then, take it out of reset.
4421 ctrl = E1000_READ_REG(hw, CTRL);
4422 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4423 E1000_WRITE_FLUSH(hw);
4425 if (hw->mac_type < e1000_82571)
4430 E1000_WRITE_REG(hw, CTRL, ctrl);
4431 E1000_WRITE_FLUSH(hw);
4433 if (hw->mac_type >= e1000_82571)
4436 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4437 * bit to put the PHY into reset. Then, take it out of reset.
4439 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4440 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4441 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4442 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4443 E1000_WRITE_FLUSH(hw);
4445 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4446 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4447 E1000_WRITE_FLUSH(hw);
4451 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4452 /* Configure activity LED after PHY reset */
4453 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4454 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4455 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4456 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4459 /* Wait for FW to finish PHY configuration. */
4460 ret_val = e1000_get_phy_cfg_done(hw);
4461 if (ret_val != E1000_SUCCESS)
4467 /******************************************************************************
4468 * IGP phy init script - initializes the GbE PHY
4470 * hw - Struct containing variables accessed by shared code
4471 *****************************************************************************/
4473 e1000_phy_init_script(struct e1000_hw *hw)
4476 uint16_t phy_saved_data;
4479 if (hw->phy_init_script) {
4482 /* Save off the current value of register 0x2F5B to be
4483 * restored at the end of this routine. */
4484 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4486 /* Disabled the PHY transmitter */
4487 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4491 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4495 switch (hw->mac_type) {
4498 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4500 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4502 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4504 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4506 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4508 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4510 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4512 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4514 e1000_write_phy_reg(hw, 0x2010, 0x0008);
4517 case e1000_82541_rev_2:
4518 case e1000_82547_rev_2:
4519 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4525 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4529 /* Now enable the transmitter */
4531 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
4533 if (hw->mac_type == e1000_82547) {
4534 uint16_t fused, fine, coarse;
4536 /* Move to analog registers page */
4537 e1000_read_phy_reg(hw,
4538 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4540 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4541 e1000_read_phy_reg(hw,
4542 IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4544 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4546 & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4549 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4551 IGP01E1000_ANALOG_FUSE_COARSE_10;
4552 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4554 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4555 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4558 & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4560 & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4562 & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4564 e1000_write_phy_reg(hw,
4565 IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4566 e1000_write_phy_reg(hw,
4567 IGP01E1000_ANALOG_FUSE_BYPASS,
4568 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4574 /******************************************************************************
4577 * hw - Struct containing variables accessed by shared code
4579 * Sets bit 15 of the MII Control register
4580 ******************************************************************************/
4582 e1000_phy_reset(struct e1000_hw *hw)
4589 /* In the case of the phy reset being blocked, it's not an error, we
4590 * simply return success without performing the reset. */
4591 ret_val = e1000_check_phy_reset_block(hw);
4593 return E1000_SUCCESS;
4595 switch (hw->phy_type) {
4597 case e1000_phy_igp_2:
4598 case e1000_phy_igp_3:
4601 ret_val = e1000_phy_hw_reset(hw);
4606 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4610 phy_data |= MII_CR_RESET;
4611 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4619 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4620 e1000_phy_init_script(hw);
4622 return E1000_SUCCESS;
4625 static int e1000_set_phy_type (struct e1000_hw *hw)
4629 if (hw->mac_type == e1000_undefined)
4630 return -E1000_ERR_PHY_TYPE;
4632 switch (hw->phy_id) {
4633 case M88E1000_E_PHY_ID:
4634 case M88E1000_I_PHY_ID:
4635 case M88E1011_I_PHY_ID:
4636 case M88E1111_I_PHY_ID:
4637 hw->phy_type = e1000_phy_m88;
4639 case IGP01E1000_I_PHY_ID:
4640 if (hw->mac_type == e1000_82541 ||
4641 hw->mac_type == e1000_82541_rev_2 ||
4642 hw->mac_type == e1000_82547 ||
4643 hw->mac_type == e1000_82547_rev_2) {
4644 hw->phy_type = e1000_phy_igp;
4647 case IGP03E1000_E_PHY_ID:
4648 hw->phy_type = e1000_phy_igp_3;
4651 case IFE_PLUS_E_PHY_ID:
4652 case IFE_C_E_PHY_ID:
4653 hw->phy_type = e1000_phy_ife;
4655 case GG82563_E_PHY_ID:
4656 if (hw->mac_type == e1000_80003es2lan) {
4657 hw->phy_type = e1000_phy_gg82563;
4660 case BME1000_E_PHY_ID:
4661 hw->phy_type = e1000_phy_bm;
4664 hw->phy_type = e1000_phy_igb;
4668 /* Should never have loaded on this device */
4669 hw->phy_type = e1000_phy_undefined;
4670 return -E1000_ERR_PHY_TYPE;
4673 return E1000_SUCCESS;
4676 /******************************************************************************
4677 * Probes the expected PHY address for known PHY IDs
4679 * hw - Struct containing variables accessed by shared code
4680 ******************************************************************************/
4682 e1000_detect_gig_phy(struct e1000_hw *hw)
4684 int32_t phy_init_status, ret_val;
4685 uint16_t phy_id_high, phy_id_low;
4690 /* The 82571 firmware may still be configuring the PHY. In this
4691 * case, we cannot access the PHY until the configuration is done. So
4692 * we explicitly set the PHY values. */
4693 if (hw->mac_type == e1000_82571 ||
4694 hw->mac_type == e1000_82572) {
4695 hw->phy_id = IGP01E1000_I_PHY_ID;
4696 hw->phy_type = e1000_phy_igp_2;
4697 return E1000_SUCCESS;
4700 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4701 * work- around that forces PHY page 0 to be set or the reads fail.
4702 * The rest of the code in this routine uses e1000_read_phy_reg to
4703 * read the PHY ID. So for ESB-2 we need to have this set so our
4704 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
4705 * the routines below will figure this out as well. */
4706 if (hw->mac_type == e1000_80003es2lan)
4707 hw->phy_type = e1000_phy_gg82563;
4709 /* Read the PHY ID Registers to identify which PHY is onboard. */
4710 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4714 hw->phy_id = (uint32_t) (phy_id_high << 16);
4716 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4720 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4721 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4723 switch (hw->mac_type) {
4725 if (hw->phy_id == M88E1000_E_PHY_ID)
4729 if (hw->phy_id == M88E1000_I_PHY_ID)
4734 case e1000_82545_rev_3:
4736 case e1000_82546_rev_3:
4737 if (hw->phy_id == M88E1011_I_PHY_ID)
4741 case e1000_82541_rev_2:
4743 case e1000_82547_rev_2:
4744 if(hw->phy_id == IGP01E1000_I_PHY_ID)
4749 if (hw->phy_id == M88E1111_I_PHY_ID)
4753 if (hw->phy_id == BME1000_E_PHY_ID)
4756 case e1000_80003es2lan:
4757 if (hw->phy_id == GG82563_E_PHY_ID)
4761 if (hw->phy_id == IGP03E1000_E_PHY_ID)
4763 if (hw->phy_id == IFE_E_PHY_ID)
4765 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4767 if (hw->phy_id == IFE_C_E_PHY_ID)
4771 if (hw->phy_id == I210_I_PHY_ID)
4775 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4776 return -E1000_ERR_CONFIG;
4779 phy_init_status = e1000_set_phy_type(hw);
4781 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4782 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4785 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4786 return -E1000_ERR_PHY;
4789 /*****************************************************************************
4790 * Set media type and TBI compatibility.
4792 * hw - Struct containing variables accessed by shared code
4793 * **************************************************************************/
4795 e1000_set_media_type(struct e1000_hw *hw)
4801 if (hw->mac_type != e1000_82543) {
4802 /* tbi_compatibility is only valid on 82543 */
4803 hw->tbi_compatibility_en = false;
4806 switch (hw->device_id) {
4807 case E1000_DEV_ID_82545GM_SERDES:
4808 case E1000_DEV_ID_82546GB_SERDES:
4809 case E1000_DEV_ID_82571EB_SERDES:
4810 case E1000_DEV_ID_82571EB_SERDES_DUAL:
4811 case E1000_DEV_ID_82571EB_SERDES_QUAD:
4812 case E1000_DEV_ID_82572EI_SERDES:
4813 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
4814 hw->media_type = e1000_media_type_internal_serdes;
4817 switch (hw->mac_type) {
4818 case e1000_82542_rev2_0:
4819 case e1000_82542_rev2_1:
4820 hw->media_type = e1000_media_type_fiber;
4826 /* The STATUS_TBIMODE bit is reserved or reused
4827 * for the this device.
4829 hw->media_type = e1000_media_type_copper;
4832 status = E1000_READ_REG(hw, STATUS);
4833 if (status & E1000_STATUS_TBIMODE) {
4834 hw->media_type = e1000_media_type_fiber;
4835 /* tbi_compatibility not valid on fiber */
4836 hw->tbi_compatibility_en = false;
4838 hw->media_type = e1000_media_type_copper;
4846 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4848 * e1000_sw_init initializes the Adapter private data structure.
4849 * Fields are initialized based on PCI device information and
4850 * OS network device settings (MTU size).
4854 e1000_sw_init(struct eth_device *nic)
4856 struct e1000_hw *hw = (typeof(hw)) nic->priv;
4859 /* PCI config space info */
4860 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
4861 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
4862 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
4863 &hw->subsystem_vendor_id);
4864 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
4866 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
4867 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
4869 /* identify the MAC */
4870 result = e1000_set_mac_type(hw);
4872 E1000_ERR(hw->nic, "Unknown MAC Type\n");
4876 switch (hw->mac_type) {
4881 case e1000_82541_rev_2:
4882 case e1000_82547_rev_2:
4883 hw->phy_init_script = 1;
4887 /* flow control settings */
4888 hw->fc_high_water = E1000_FC_HIGH_THRESH;
4889 hw->fc_low_water = E1000_FC_LOW_THRESH;
4890 hw->fc_pause_time = E1000_FC_PAUSE_TIME;
4891 hw->fc_send_xon = 1;
4893 /* Media type - copper or fiber */
4894 hw->tbi_compatibility_en = true;
4895 e1000_set_media_type(hw);
4897 if (hw->mac_type >= e1000_82543) {
4898 uint32_t status = E1000_READ_REG(hw, STATUS);
4900 if (status & E1000_STATUS_TBIMODE) {
4901 DEBUGOUT("fiber interface\n");
4902 hw->media_type = e1000_media_type_fiber;
4904 DEBUGOUT("copper interface\n");
4905 hw->media_type = e1000_media_type_copper;
4908 hw->media_type = e1000_media_type_fiber;
4911 hw->wait_autoneg_complete = true;
4912 if (hw->mac_type < e1000_82543)
4913 hw->report_tx_early = 0;
4915 hw->report_tx_early = 1;
4917 return E1000_SUCCESS;
4921 fill_rx(struct e1000_hw *hw)
4923 struct e1000_rx_desc *rd;
4924 uint32_t flush_start, flush_end;
4927 rd = rx_base + rx_tail;
4928 rx_tail = (rx_tail + 1) % 8;
4930 rd->buffer_addr = cpu_to_le64((u32)packet);
4933 * Make sure there are no stale data in WB over this area, which
4934 * might get written into the memory while the e1000 also writes
4935 * into the same memory area.
4937 invalidate_dcache_range((u32)packet, (u32)packet + 4096);
4938 /* Dump the DMA descriptor into RAM. */
4939 flush_start = ((u32)rd) & ~(ARCH_DMA_MINALIGN - 1);
4940 flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
4941 flush_dcache_range(flush_start, flush_end);
4943 E1000_WRITE_REG(hw, RDT, rx_tail);
4947 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
4948 * @adapter: board private structure
4950 * Configure the Tx unit of the MAC after a reset.
4954 e1000_configure_tx(struct e1000_hw *hw)
4957 unsigned long tipg, tarc;
4958 uint32_t ipgr1, ipgr2;
4960 E1000_WRITE_REG(hw, TDBAL, (u32) tx_base);
4961 E1000_WRITE_REG(hw, TDBAH, 0);
4963 E1000_WRITE_REG(hw, TDLEN, 128);
4965 /* Setup the HW Tx Head and Tail descriptor pointers */
4966 E1000_WRITE_REG(hw, TDH, 0);
4967 E1000_WRITE_REG(hw, TDT, 0);
4970 /* Set the default values for the Tx Inter Packet Gap timer */
4971 if (hw->mac_type <= e1000_82547_rev_2 &&
4972 (hw->media_type == e1000_media_type_fiber ||
4973 hw->media_type == e1000_media_type_internal_serdes))
4974 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
4976 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
4978 /* Set the default values for the Tx Inter Packet Gap timer */
4979 switch (hw->mac_type) {
4980 case e1000_82542_rev2_0:
4981 case e1000_82542_rev2_1:
4982 tipg = DEFAULT_82542_TIPG_IPGT;
4983 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
4984 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
4986 case e1000_80003es2lan:
4987 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4988 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
4991 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4992 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
4995 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
4996 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
4997 E1000_WRITE_REG(hw, TIPG, tipg);
4998 /* Program the Transmit Control Register */
4999 tctl = E1000_READ_REG(hw, TCTL);
5000 tctl &= ~E1000_TCTL_CT;
5001 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
5002 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
5004 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
5005 tarc = E1000_READ_REG(hw, TARC0);
5006 /* set the speed mode bit, we'll clear it if we're not at
5007 * gigabit link later */
5008 /* git bit can be set to 1*/
5009 } else if (hw->mac_type == e1000_80003es2lan) {
5010 tarc = E1000_READ_REG(hw, TARC0);
5012 E1000_WRITE_REG(hw, TARC0, tarc);
5013 tarc = E1000_READ_REG(hw, TARC1);
5015 E1000_WRITE_REG(hw, TARC1, tarc);
5019 e1000_config_collision_dist(hw);
5020 /* Setup Transmit Descriptor Settings for eop descriptor */
5021 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
5023 /* Need to set up RS bit */
5024 if (hw->mac_type < e1000_82543)
5025 hw->txd_cmd |= E1000_TXD_CMD_RPS;
5027 hw->txd_cmd |= E1000_TXD_CMD_RS;
5030 if (hw->mac_type == e1000_igb) {
5031 E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
5033 uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL);
5034 reg_txdctl |= 1 << 25;
5035 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
5041 E1000_WRITE_REG(hw, TCTL, tctl);
5047 * e1000_setup_rctl - configure the receive control register
5048 * @adapter: Board private structure
5051 e1000_setup_rctl(struct e1000_hw *hw)
5055 rctl = E1000_READ_REG(hw, RCTL);
5057 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
5059 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
5060 | E1000_RCTL_RDMTS_HALF; /* |
5061 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
5063 if (hw->tbi_compatibility_on == 1)
5064 rctl |= E1000_RCTL_SBP;
5066 rctl &= ~E1000_RCTL_SBP;
5068 rctl &= ~(E1000_RCTL_SZ_4096);
5069 rctl |= E1000_RCTL_SZ_2048;
5070 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
5071 E1000_WRITE_REG(hw, RCTL, rctl);
5075 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
5076 * @adapter: board private structure
5078 * Configure the Rx unit of the MAC after a reset.
5081 e1000_configure_rx(struct e1000_hw *hw)
5083 unsigned long rctl, ctrl_ext;
5085 /* make sure receives are disabled while setting up the descriptors */
5086 rctl = E1000_READ_REG(hw, RCTL);
5087 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
5088 if (hw->mac_type >= e1000_82540) {
5089 /* Set the interrupt throttling rate. Value is calculated
5090 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
5091 #define MAX_INTS_PER_SEC 8000
5092 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
5093 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
5096 if (hw->mac_type >= e1000_82571) {
5097 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5098 /* Reset delay timers after every interrupt */
5099 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
5100 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5101 E1000_WRITE_FLUSH(hw);
5103 /* Setup the Base and Length of the Rx Descriptor Ring */
5104 E1000_WRITE_REG(hw, RDBAL, (u32) rx_base);
5105 E1000_WRITE_REG(hw, RDBAH, 0);
5107 E1000_WRITE_REG(hw, RDLEN, 128);
5109 /* Setup the HW Rx Head and Tail Descriptor Pointers */
5110 E1000_WRITE_REG(hw, RDH, 0);
5111 E1000_WRITE_REG(hw, RDT, 0);
5112 /* Enable Receives */
5114 if (hw->mac_type == e1000_igb) {
5116 uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL);
5117 reg_rxdctl |= 1 << 25;
5118 E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl);
5122 E1000_WRITE_REG(hw, RCTL, rctl);
5127 /**************************************************************************
5128 POLL - Wait for a frame
5129 ***************************************************************************/
5131 e1000_poll(struct eth_device *nic)
5133 struct e1000_hw *hw = nic->priv;
5134 struct e1000_rx_desc *rd;
5135 uint32_t inval_start, inval_end;
5138 /* return true if there's an ethernet packet ready to read */
5139 rd = rx_base + rx_last;
5141 /* Re-load the descriptor from RAM. */
5142 inval_start = ((u32)rd) & ~(ARCH_DMA_MINALIGN - 1);
5143 inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5144 invalidate_dcache_range(inval_start, inval_end);
5146 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
5148 /*DEBUGOUT("recv: packet len=%d \n", rd->length); */
5149 /* Packet received, make sure the data are re-loaded from RAM. */
5150 len = le32_to_cpu(rd->length);
5151 invalidate_dcache_range((u32)packet,
5152 (u32)packet + roundup(len, ARCH_DMA_MINALIGN));
5153 NetReceive((uchar *)packet, len);
5158 /**************************************************************************
5159 TRANSMIT - Transmit a frame
5160 ***************************************************************************/
5161 static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
5163 void *nv_packet = (void *)txpacket;
5164 struct e1000_hw *hw = nic->priv;
5165 struct e1000_tx_desc *txp;
5167 uint32_t flush_start, flush_end;
5169 txp = tx_base + tx_tail;
5170 tx_tail = (tx_tail + 1) % 8;
5172 txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
5173 txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
5174 txp->upper.data = 0;
5176 /* Dump the packet into RAM so e1000 can pick them. */
5177 flush_dcache_range((u32)nv_packet,
5178 (u32)nv_packet + roundup(length, ARCH_DMA_MINALIGN));
5179 /* Dump the descriptor into RAM as well. */
5180 flush_start = ((u32)txp) & ~(ARCH_DMA_MINALIGN - 1);
5181 flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
5182 flush_dcache_range(flush_start, flush_end);
5184 E1000_WRITE_REG(hw, TDT, tx_tail);
5186 E1000_WRITE_FLUSH(hw);
5188 invalidate_dcache_range(flush_start, flush_end);
5189 if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)
5191 if (i++ > TOUT_LOOP) {
5192 DEBUGOUT("e1000: tx timeout\n");
5195 udelay(10); /* give the nic a chance to write to the register */
5202 e1000_reset(struct eth_device *nic)
5204 struct e1000_hw *hw = nic->priv;
5207 if (hw->mac_type >= e1000_82544) {
5208 E1000_WRITE_REG(hw, WUC, 0);
5210 return e1000_init_hw(nic);
5213 /**************************************************************************
5214 DISABLE - Turn off ethernet interface
5215 ***************************************************************************/
5217 e1000_disable(struct eth_device *nic)
5219 struct e1000_hw *hw = nic->priv;
5221 /* Turn off the ethernet interface */
5222 E1000_WRITE_REG(hw, RCTL, 0);
5223 E1000_WRITE_REG(hw, TCTL, 0);
5225 /* Clear the transmit ring */
5226 E1000_WRITE_REG(hw, TDH, 0);
5227 E1000_WRITE_REG(hw, TDT, 0);
5229 /* Clear the receive ring */
5230 E1000_WRITE_REG(hw, RDH, 0);
5231 E1000_WRITE_REG(hw, RDT, 0);
5233 /* put the card in its initial state */
5235 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
5241 /**************************************************************************
5242 INIT - set up ethernet interface(s)
5243 ***************************************************************************/
5245 e1000_init(struct eth_device *nic, bd_t * bis)
5247 struct e1000_hw *hw = nic->priv;
5250 ret_val = e1000_reset(nic);
5252 if ((ret_val == -E1000_ERR_NOLINK) ||
5253 (ret_val == -E1000_ERR_TIMEOUT)) {
5254 E1000_ERR(hw->nic, "Valid Link not detected\n");
5256 E1000_ERR(hw->nic, "Hardware Initialization Failed\n");
5260 e1000_configure_tx(hw);
5261 e1000_setup_rctl(hw);
5262 e1000_configure_rx(hw);
5266 /******************************************************************************
5267 * Gets the current PCI bus type of hardware
5269 * hw - Struct containing variables accessed by shared code
5270 *****************************************************************************/
5271 void e1000_get_bus_type(struct e1000_hw *hw)
5275 switch (hw->mac_type) {
5276 case e1000_82542_rev2_0:
5277 case e1000_82542_rev2_1:
5278 hw->bus_type = e1000_bus_type_pci;
5284 case e1000_80003es2lan:
5287 hw->bus_type = e1000_bus_type_pci_express;
5290 status = E1000_READ_REG(hw, STATUS);
5291 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5292 e1000_bus_type_pcix : e1000_bus_type_pci;
5297 /* A list of all registered e1000 devices */
5298 static LIST_HEAD(e1000_hw_list);
5300 /**************************************************************************
5301 PROBE - Look for an adapter, this routine's visible to the outside
5302 You should omit the last argument struct pci_device * for a non-PCI NIC
5303 ***************************************************************************/
5305 e1000_initialize(bd_t * bis)
5312 /* Find and probe all the matching PCI devices */
5313 for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
5317 * These will never get freed due to errors, this allows us to
5318 * perform SPI EEPROM programming from U-boot, for example.
5320 struct eth_device *nic = malloc(sizeof(*nic));
5321 struct e1000_hw *hw = malloc(sizeof(*hw));
5323 printf("e1000#%u: Out of Memory!\n", i);
5329 /* Make sure all of the fields are initially zeroed */
5330 memset(nic, 0, sizeof(*nic));
5331 memset(hw, 0, sizeof(*hw));
5333 /* Assign the passed-in values */
5339 /* Generate a card name */
5340 sprintf(nic->name, "e1000#%u", hw->cardnum);
5342 /* Print a debug message with the IO base address */
5343 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
5344 E1000_DBG(nic, "iobase 0x%08x\n", val & 0xfffffff0);
5346 /* Try to enable I/O accesses and bus-mastering */
5347 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
5348 pci_write_config_dword(devno, PCI_COMMAND, val);
5350 /* Make sure it worked */
5351 pci_read_config_dword(devno, PCI_COMMAND, &val);
5352 if (!(val & PCI_COMMAND_MEMORY)) {
5353 E1000_ERR(nic, "Can't enable I/O memory\n");
5356 if (!(val & PCI_COMMAND_MASTER)) {
5357 E1000_ERR(nic, "Can't enable bus-mastering\n");
5361 /* Are these variables needed? */
5362 hw->fc = e1000_fc_default;
5363 hw->original_fc = e1000_fc_default;
5364 hw->autoneg_failed = 0;
5366 hw->get_link_status = true;
5367 #ifndef CONFIG_E1000_NO_NVM
5368 hw->eeprom_semaphore_present = true;
5370 hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
5372 hw->mac_type = e1000_undefined;
5374 /* MAC and Phy settings */
5375 if (e1000_sw_init(nic) < 0) {
5376 E1000_ERR(nic, "Software init failed\n");
5379 if (e1000_check_phy_reset_block(hw))
5380 E1000_ERR(nic, "PHY Reset is blocked!\n");
5382 /* Basic init was OK, reset the hardware and allow SPI access */
5384 list_add_tail(&hw->list_node, &e1000_hw_list);
5386 #ifndef CONFIG_E1000_NO_NVM
5387 /* Validate the EEPROM and get chipset information */
5388 #if !defined(CONFIG_MVBC_1G)
5389 if (e1000_init_eeprom_params(hw)) {
5390 E1000_ERR(nic, "EEPROM is invalid!\n");
5393 if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
5394 e1000_validate_eeprom_checksum(hw))
5397 e1000_read_mac_addr(nic);
5399 e1000_get_bus_type(hw);
5401 #ifndef CONFIG_E1000_NO_NVM
5402 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ",
5403 nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
5404 nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
5406 memset(nic->enetaddr, 0, 6);
5407 printf("e1000: no NVM\n");
5410 /* Set up the function pointers and register the device */
5411 nic->init = e1000_init;
5412 nic->recv = e1000_poll;
5413 nic->send = e1000_transmit;
5414 nic->halt = e1000_disable;
5421 struct e1000_hw *e1000_find_card(unsigned int cardnum)
5423 struct e1000_hw *hw;
5425 list_for_each_entry(hw, &e1000_hw_list, list_node)
5426 if (hw->cardnum == cardnum)
5432 #ifdef CONFIG_CMD_E1000
5433 static int do_e1000(cmd_tbl_t *cmdtp, int flag,
5434 int argc, char * const argv[])
5436 struct e1000_hw *hw;
5443 /* Make sure we can find the requested e1000 card */
5444 hw = e1000_find_card(simple_strtoul(argv[1], NULL, 10));
5446 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
5450 if (!strcmp(argv[2], "print-mac-address")) {
5451 unsigned char *mac = hw->nic->enetaddr;
5452 printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
5453 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
5457 #ifdef CONFIG_E1000_SPI
5458 /* Handle the "SPI" subcommand */
5459 if (!strcmp(argv[2], "spi"))
5460 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
5468 e1000, 7, 0, do_e1000,
5469 "Intel e1000 controller management",
5470 /* */"<card#> print-mac-address\n"
5471 #ifdef CONFIG_E1000_SPI
5472 "e1000 <card#> spi show [<offset> [<length>]]\n"
5473 "e1000 <card#> spi dump <addr> <offset> <length>\n"
5474 "e1000 <card#> spi program <addr> <offset> <length>\n"
5475 "e1000 <card#> spi checksum [update]\n"
5477 " - Manage the Intel E1000 PCI device"
5479 #endif /* not CONFIG_CMD_E1000 */