1 /**************************************************************************
2 Intel Pro 1000 for ppcboot/das-u-boot
3 Drivers are port from Intel's Linux driver e1000-4.3.15
4 and from Etherboot pro 1000 driver by mrakes at vivato dot net
5 tested on both gig copper and gig fiber boards
6 ***************************************************************************/
7 /*******************************************************************************
10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
12 This program is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published by the Free
14 Software Foundation; either version 2 of the License, or (at your option)
17 This program is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 You should have received a copy of the GNU General Public License along with
23 this program; if not, write to the Free Software Foundation, Inc., 59
24 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 The full GNU General Public License is included in this distribution in the
30 Linux NICS <linux.nics@intel.com>
31 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 *******************************************************************************/
35 * Copyright (C) Archway Digital Solutions.
37 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
40 * Copyright (C) Linux Networx.
41 * Massive upgrade to work with the new intel gigabit NICs.
42 * <ebiederman at lnxi dot com>
47 #define TOUT_LOOP 100000
49 #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
50 #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
51 #define mdelay(n) udelay((n)*1000)
53 #define E1000_DEFAULT_PCI_PBA 0x00000030
54 #define E1000_DEFAULT_PCIE_PBA 0x000a0026
56 /* NIC specific static variables go here */
58 static char tx_pool[128 + 16];
59 static char rx_pool[128 + 16];
60 static char packet[2096];
62 static struct e1000_tx_desc *tx_base;
63 static struct e1000_rx_desc *rx_base;
66 static int rx_tail, rx_last;
68 static struct pci_device_id supported[] = {
69 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542},
70 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER},
71 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER},
72 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER},
73 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER},
74 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER},
75 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM},
76 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM},
77 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER},
78 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER},
79 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
80 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
81 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
82 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
83 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
84 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
86 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER},
87 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER },
88 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES },
89 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER},
90 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER},
91 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER},
92 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE},
93 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL},
94 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD},
95 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER},
96 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER},
97 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES},
98 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI},
99 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E},
100 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT},
101 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L},
102 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3},
103 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT},
104 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
105 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
106 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
110 /* Function forward declarations */
111 static int e1000_setup_link(struct eth_device *nic);
112 static int e1000_setup_fiber_link(struct eth_device *nic);
113 static int e1000_setup_copper_link(struct eth_device *nic);
114 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
115 static void e1000_config_collision_dist(struct e1000_hw *hw);
116 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
117 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
118 static int e1000_check_for_link(struct eth_device *nic);
119 static int e1000_wait_autoneg(struct e1000_hw *hw);
120 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
122 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
123 uint16_t * phy_data);
124 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
126 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
127 static int e1000_phy_reset(struct e1000_hw *hw);
128 static int e1000_detect_gig_phy(struct e1000_hw *hw);
129 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
130 static void e1000_set_media_type(struct e1000_hw *hw);
132 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
133 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
134 #define E1000_WRITE_REG(a, reg, value) (writel((value), ((a)->hw_addr + E1000_##reg)))
135 #define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_##reg))
136 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) (\
137 writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))))
138 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
139 readl((a)->hw_addr + E1000_##reg + ((offset) << 2)))
140 #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
142 #ifndef CONFIG_AP1000 /* remove for warnings */
143 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
146 /******************************************************************************
147 * Raises the EEPROM's clock input.
149 * hw - Struct containing variables accessed by shared code
150 * eecd - EECD's current value
151 *****************************************************************************/
153 e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
155 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
156 * wait 50 microseconds.
158 *eecd = *eecd | E1000_EECD_SK;
159 E1000_WRITE_REG(hw, EECD, *eecd);
160 E1000_WRITE_FLUSH(hw);
164 /******************************************************************************
165 * Lowers the EEPROM's clock input.
167 * hw - Struct containing variables accessed by shared code
168 * eecd - EECD's current value
169 *****************************************************************************/
171 e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
173 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
174 * wait 50 microseconds.
176 *eecd = *eecd & ~E1000_EECD_SK;
177 E1000_WRITE_REG(hw, EECD, *eecd);
178 E1000_WRITE_FLUSH(hw);
182 /******************************************************************************
183 * Shift data bits out to the EEPROM.
185 * hw - Struct containing variables accessed by shared code
186 * data - data to send to the EEPROM
187 * count - number of bits to shift out
188 *****************************************************************************/
190 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
195 /* We need to shift "count" bits out to the EEPROM. So, value in the
196 * "data" parameter will be shifted out to the EEPROM one bit at a time.
197 * In order to do this, "data" must be broken down into bits.
199 mask = 0x01 << (count - 1);
200 eecd = E1000_READ_REG(hw, EECD);
201 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
203 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
204 * and then raising and then lowering the clock (the SK bit controls
205 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
206 * by setting "DI" to "0" and then raising and then lowering the clock.
208 eecd &= ~E1000_EECD_DI;
211 eecd |= E1000_EECD_DI;
213 E1000_WRITE_REG(hw, EECD, eecd);
214 E1000_WRITE_FLUSH(hw);
218 e1000_raise_ee_clk(hw, &eecd);
219 e1000_lower_ee_clk(hw, &eecd);
225 /* We leave the "DI" bit set to "0" when we leave this routine. */
226 eecd &= ~E1000_EECD_DI;
227 E1000_WRITE_REG(hw, EECD, eecd);
230 /******************************************************************************
231 * Shift data bits in from the EEPROM
233 * hw - Struct containing variables accessed by shared code
234 *****************************************************************************/
236 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
242 /* In order to read a register from the EEPROM, we need to shift 'count'
243 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
244 * input to the EEPROM (setting the SK bit), and then reading the
245 * value of the "DO" bit. During this "shifting in" process the
246 * "DI" bit should always be clear.
249 eecd = E1000_READ_REG(hw, EECD);
251 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
254 for (i = 0; i < count; i++) {
256 e1000_raise_ee_clk(hw, &eecd);
258 eecd = E1000_READ_REG(hw, EECD);
260 eecd &= ~(E1000_EECD_DI);
261 if (eecd & E1000_EECD_DO)
264 e1000_lower_ee_clk(hw, &eecd);
270 /******************************************************************************
271 * Returns EEPROM to a "standby" state
273 * hw - Struct containing variables accessed by shared code
274 *****************************************************************************/
276 e1000_standby_eeprom(struct e1000_hw *hw)
278 struct e1000_eeprom_info *eeprom = &hw->eeprom;
281 eecd = E1000_READ_REG(hw, EECD);
283 if (eeprom->type == e1000_eeprom_microwire) {
284 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
285 E1000_WRITE_REG(hw, EECD, eecd);
286 E1000_WRITE_FLUSH(hw);
287 udelay(eeprom->delay_usec);
290 eecd |= E1000_EECD_SK;
291 E1000_WRITE_REG(hw, EECD, eecd);
292 E1000_WRITE_FLUSH(hw);
293 udelay(eeprom->delay_usec);
296 eecd |= E1000_EECD_CS;
297 E1000_WRITE_REG(hw, EECD, eecd);
298 E1000_WRITE_FLUSH(hw);
299 udelay(eeprom->delay_usec);
302 eecd &= ~E1000_EECD_SK;
303 E1000_WRITE_REG(hw, EECD, eecd);
304 E1000_WRITE_FLUSH(hw);
305 udelay(eeprom->delay_usec);
306 } else if (eeprom->type == e1000_eeprom_spi) {
307 /* Toggle CS to flush commands */
308 eecd |= E1000_EECD_CS;
309 E1000_WRITE_REG(hw, EECD, eecd);
310 E1000_WRITE_FLUSH(hw);
311 udelay(eeprom->delay_usec);
312 eecd &= ~E1000_EECD_CS;
313 E1000_WRITE_REG(hw, EECD, eecd);
314 E1000_WRITE_FLUSH(hw);
315 udelay(eeprom->delay_usec);
319 /***************************************************************************
320 * Description: Determines if the onboard NVM is FLASH or EEPROM.
322 * hw - Struct containing variables accessed by shared code
323 ****************************************************************************/
324 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
330 if (hw->mac_type == e1000_ich8lan)
333 if (hw->mac_type == e1000_82573) {
334 eecd = E1000_READ_REG(hw, EECD);
336 /* Isolate bits 15 & 16 */
337 eecd = ((eecd >> 15) & 0x03);
339 /* If both bits are set, device is Flash type */
346 /******************************************************************************
347 * Prepares EEPROM for access
349 * hw - Struct containing variables accessed by shared code
351 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
352 * function should be called before issuing a command to the EEPROM.
353 *****************************************************************************/
355 e1000_acquire_eeprom(struct e1000_hw *hw)
357 struct e1000_eeprom_info *eeprom = &hw->eeprom;
358 uint32_t eecd, i = 0;
362 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
363 return -E1000_ERR_SWFW_SYNC;
364 eecd = E1000_READ_REG(hw, EECD);
366 if (hw->mac_type != e1000_82573) {
367 /* Request EEPROM Access */
368 if (hw->mac_type > e1000_82544) {
369 eecd |= E1000_EECD_REQ;
370 E1000_WRITE_REG(hw, EECD, eecd);
371 eecd = E1000_READ_REG(hw, EECD);
372 while ((!(eecd & E1000_EECD_GNT)) &&
373 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
376 eecd = E1000_READ_REG(hw, EECD);
378 if (!(eecd & E1000_EECD_GNT)) {
379 eecd &= ~E1000_EECD_REQ;
380 E1000_WRITE_REG(hw, EECD, eecd);
381 DEBUGOUT("Could not acquire EEPROM grant\n");
382 return -E1000_ERR_EEPROM;
387 /* Setup EEPROM for Read/Write */
389 if (eeprom->type == e1000_eeprom_microwire) {
390 /* Clear SK and DI */
391 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
392 E1000_WRITE_REG(hw, EECD, eecd);
395 eecd |= E1000_EECD_CS;
396 E1000_WRITE_REG(hw, EECD, eecd);
397 } else if (eeprom->type == e1000_eeprom_spi) {
398 /* Clear SK and CS */
399 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
400 E1000_WRITE_REG(hw, EECD, eecd);
404 return E1000_SUCCESS;
407 /******************************************************************************
408 * Sets up eeprom variables in the hw struct. Must be called after mac_type
409 * is configured. Additionally, if this is ICH8, the flash controller GbE
410 * registers must be mapped, or this will crash.
412 * hw - Struct containing variables accessed by shared code
413 *****************************************************************************/
414 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
416 struct e1000_eeprom_info *eeprom = &hw->eeprom;
417 uint32_t eecd = E1000_READ_REG(hw, EECD);
418 int32_t ret_val = E1000_SUCCESS;
419 uint16_t eeprom_size;
423 switch (hw->mac_type) {
424 case e1000_82542_rev2_0:
425 case e1000_82542_rev2_1:
428 eeprom->type = e1000_eeprom_microwire;
429 eeprom->word_size = 64;
430 eeprom->opcode_bits = 3;
431 eeprom->address_bits = 6;
432 eeprom->delay_usec = 50;
433 eeprom->use_eerd = FALSE;
434 eeprom->use_eewr = FALSE;
438 case e1000_82545_rev_3:
440 case e1000_82546_rev_3:
441 eeprom->type = e1000_eeprom_microwire;
442 eeprom->opcode_bits = 3;
443 eeprom->delay_usec = 50;
444 if (eecd & E1000_EECD_SIZE) {
445 eeprom->word_size = 256;
446 eeprom->address_bits = 8;
448 eeprom->word_size = 64;
449 eeprom->address_bits = 6;
451 eeprom->use_eerd = FALSE;
452 eeprom->use_eewr = FALSE;
455 case e1000_82541_rev_2:
457 case e1000_82547_rev_2:
458 if (eecd & E1000_EECD_TYPE) {
459 eeprom->type = e1000_eeprom_spi;
460 eeprom->opcode_bits = 8;
461 eeprom->delay_usec = 1;
462 if (eecd & E1000_EECD_ADDR_BITS) {
463 eeprom->page_size = 32;
464 eeprom->address_bits = 16;
466 eeprom->page_size = 8;
467 eeprom->address_bits = 8;
470 eeprom->type = e1000_eeprom_microwire;
471 eeprom->opcode_bits = 3;
472 eeprom->delay_usec = 50;
473 if (eecd & E1000_EECD_ADDR_BITS) {
474 eeprom->word_size = 256;
475 eeprom->address_bits = 8;
477 eeprom->word_size = 64;
478 eeprom->address_bits = 6;
481 eeprom->use_eerd = FALSE;
482 eeprom->use_eewr = FALSE;
486 eeprom->type = e1000_eeprom_spi;
487 eeprom->opcode_bits = 8;
488 eeprom->delay_usec = 1;
489 if (eecd & E1000_EECD_ADDR_BITS) {
490 eeprom->page_size = 32;
491 eeprom->address_bits = 16;
493 eeprom->page_size = 8;
494 eeprom->address_bits = 8;
496 eeprom->use_eerd = FALSE;
497 eeprom->use_eewr = FALSE;
500 eeprom->type = e1000_eeprom_spi;
501 eeprom->opcode_bits = 8;
502 eeprom->delay_usec = 1;
503 if (eecd & E1000_EECD_ADDR_BITS) {
504 eeprom->page_size = 32;
505 eeprom->address_bits = 16;
507 eeprom->page_size = 8;
508 eeprom->address_bits = 8;
510 eeprom->use_eerd = TRUE;
511 eeprom->use_eewr = TRUE;
512 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
513 eeprom->type = e1000_eeprom_flash;
514 eeprom->word_size = 2048;
516 /* Ensure that the Autonomous FLASH update bit is cleared due to
517 * Flash update issue on parts which use a FLASH for NVM. */
518 eecd &= ~E1000_EECD_AUPDEN;
519 E1000_WRITE_REG(hw, EECD, eecd);
522 case e1000_80003es2lan:
523 eeprom->type = e1000_eeprom_spi;
524 eeprom->opcode_bits = 8;
525 eeprom->delay_usec = 1;
526 if (eecd & E1000_EECD_ADDR_BITS) {
527 eeprom->page_size = 32;
528 eeprom->address_bits = 16;
530 eeprom->page_size = 8;
531 eeprom->address_bits = 8;
533 eeprom->use_eerd = TRUE;
534 eeprom->use_eewr = FALSE;
537 /* ich8lan does not support currently. if needed, please
538 * add corresponding code and functions.
545 eeprom->type = e1000_eeprom_ich8;
546 eeprom->use_eerd = FALSE;
547 eeprom->use_eewr = FALSE;
548 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
549 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
551 /* Zero the shadow RAM structure. But don't load it from NVM
552 * so as to save time for driver init */
553 if (hw->eeprom_shadow_ram != NULL) {
554 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
555 hw->eeprom_shadow_ram[i].modified = FALSE;
556 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
560 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
561 ICH_FLASH_SECTOR_SIZE;
563 hw->flash_bank_size = ((flash_size >> 16)
564 & ICH_GFPREG_BASE_MASK) + 1;
565 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
567 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
569 hw->flash_bank_size /= 2 * sizeof(uint16_t);
577 if (eeprom->type == e1000_eeprom_spi) {
578 /* eeprom_size will be an enum [0..8] that maps
579 * to eeprom sizes 128B to
580 * 32KB (incremented by powers of 2).
582 if (hw->mac_type <= e1000_82547_rev_2) {
583 /* Set to default value for initial eeprom read. */
584 eeprom->word_size = 64;
585 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
589 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
590 >> EEPROM_SIZE_SHIFT;
591 /* 256B eeprom size was not supported in earlier
592 * hardware, so we bump eeprom_size up one to
593 * ensure that "1" (which maps to 256B) is never
594 * the result used in the shifting logic below. */
598 eeprom_size = (uint16_t)((eecd &
599 E1000_EECD_SIZE_EX_MASK) >>
600 E1000_EECD_SIZE_EX_SHIFT);
603 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
608 /******************************************************************************
609 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
611 * hw - Struct containing variables accessed by shared code
612 *****************************************************************************/
614 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
616 uint32_t attempts = 100000;
618 int32_t done = E1000_ERR_EEPROM;
620 for (i = 0; i < attempts; i++) {
621 if (eerd == E1000_EEPROM_POLL_READ)
622 reg = E1000_READ_REG(hw, EERD);
624 reg = E1000_READ_REG(hw, EEWR);
626 if (reg & E1000_EEPROM_RW_REG_DONE) {
627 done = E1000_SUCCESS;
636 /******************************************************************************
637 * Reads a 16 bit word from the EEPROM using the EERD register.
639 * hw - Struct containing variables accessed by shared code
640 * offset - offset of word in the EEPROM to read
641 * data - word read from the EEPROM
642 * words - number of words to read
643 *****************************************************************************/
645 e1000_read_eeprom_eerd(struct e1000_hw *hw,
650 uint32_t i, eerd = 0;
653 for (i = 0; i < words; i++) {
654 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
655 E1000_EEPROM_RW_REG_START;
657 E1000_WRITE_REG(hw, EERD, eerd);
658 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
662 data[i] = (E1000_READ_REG(hw, EERD) >>
663 E1000_EEPROM_RW_REG_DATA);
671 e1000_release_eeprom(struct e1000_hw *hw)
677 eecd = E1000_READ_REG(hw, EECD);
679 if (hw->eeprom.type == e1000_eeprom_spi) {
680 eecd |= E1000_EECD_CS; /* Pull CS high */
681 eecd &= ~E1000_EECD_SK; /* Lower SCK */
683 E1000_WRITE_REG(hw, EECD, eecd);
685 udelay(hw->eeprom.delay_usec);
686 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
689 /* CS on Microwire is active-high */
690 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
692 E1000_WRITE_REG(hw, EECD, eecd);
694 /* Rising edge of clock */
695 eecd |= E1000_EECD_SK;
696 E1000_WRITE_REG(hw, EECD, eecd);
697 E1000_WRITE_FLUSH(hw);
698 udelay(hw->eeprom.delay_usec);
700 /* Falling edge of clock */
701 eecd &= ~E1000_EECD_SK;
702 E1000_WRITE_REG(hw, EECD, eecd);
703 E1000_WRITE_FLUSH(hw);
704 udelay(hw->eeprom.delay_usec);
707 /* Stop requesting EEPROM access */
708 if (hw->mac_type > e1000_82544) {
709 eecd &= ~E1000_EECD_REQ;
710 E1000_WRITE_REG(hw, EECD, eecd);
713 /******************************************************************************
714 * Reads a 16 bit word from the EEPROM.
716 * hw - Struct containing variables accessed by shared code
717 *****************************************************************************/
719 e1000_spi_eeprom_ready(struct e1000_hw *hw)
721 uint16_t retry_count = 0;
722 uint8_t spi_stat_reg;
726 /* Read "Status Register" repeatedly until the LSB is cleared. The
727 * EEPROM will signal that the command has been completed by clearing
728 * bit 0 of the internal status register. If it's not cleared within
729 * 5 milliseconds, then error out.
733 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
734 hw->eeprom.opcode_bits);
735 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
736 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
742 e1000_standby_eeprom(hw);
743 } while (retry_count < EEPROM_MAX_RETRY_SPI);
745 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
746 * only 0-5mSec on 5V devices)
748 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
749 DEBUGOUT("SPI EEPROM Status error\n");
750 return -E1000_ERR_EEPROM;
753 return E1000_SUCCESS;
756 /******************************************************************************
757 * Reads a 16 bit word from the EEPROM.
759 * hw - Struct containing variables accessed by shared code
760 * offset - offset of word in the EEPROM to read
761 * data - word read from the EEPROM
762 *****************************************************************************/
764 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
765 uint16_t words, uint16_t *data)
767 struct e1000_eeprom_info *eeprom = &hw->eeprom;
772 /* If eeprom is not yet detected, do so now */
773 if (eeprom->word_size == 0)
774 e1000_init_eeprom_params(hw);
776 /* A check for invalid values: offset too large, too many words,
777 * and not enough words.
779 if ((offset >= eeprom->word_size) ||
780 (words > eeprom->word_size - offset) ||
782 DEBUGOUT("\"words\" parameter out of bounds."
783 "Words = %d, size = %d\n", offset, eeprom->word_size);
784 return -E1000_ERR_EEPROM;
787 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
788 * directly. In this case, we need to acquire the EEPROM so that
789 * FW or other port software does not interrupt.
791 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
792 hw->eeprom.use_eerd == FALSE) {
794 /* Prepare the EEPROM for bit-bang reading */
795 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
796 return -E1000_ERR_EEPROM;
799 /* Eerd register EEPROM access requires no eeprom aquire/release */
800 if (eeprom->use_eerd == TRUE)
801 return e1000_read_eeprom_eerd(hw, offset, words, data);
803 /* ich8lan does not support currently. if needed, please
804 * add corresponding code and functions.
807 /* ICH EEPROM access is done via the ICH flash controller */
808 if (eeprom->type == e1000_eeprom_ich8)
809 return e1000_read_eeprom_ich8(hw, offset, words, data);
811 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
812 * acquired the EEPROM at this point, so any returns should relase it */
813 if (eeprom->type == e1000_eeprom_spi) {
815 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
817 if (e1000_spi_eeprom_ready(hw)) {
818 e1000_release_eeprom(hw);
819 return -E1000_ERR_EEPROM;
822 e1000_standby_eeprom(hw);
824 /* Some SPI eeproms use the 8th address bit embedded in
826 if ((eeprom->address_bits == 8) && (offset >= 128))
827 read_opcode |= EEPROM_A8_OPCODE_SPI;
829 /* Send the READ command (opcode + addr) */
830 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
831 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
832 eeprom->address_bits);
834 /* Read the data. The address of the eeprom internally
835 * increments with each byte (spi) being read, saving on the
836 * overhead of eeprom setup and tear-down. The address
837 * counter will roll over if reading beyond the size of
838 * the eeprom, thus allowing the entire memory to be read
839 * starting from any offset. */
840 for (i = 0; i < words; i++) {
841 word_in = e1000_shift_in_ee_bits(hw, 16);
842 data[i] = (word_in >> 8) | (word_in << 8);
844 } else if (eeprom->type == e1000_eeprom_microwire) {
845 for (i = 0; i < words; i++) {
846 /* Send the READ command (opcode + addr) */
847 e1000_shift_out_ee_bits(hw,
848 EEPROM_READ_OPCODE_MICROWIRE,
849 eeprom->opcode_bits);
850 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
851 eeprom->address_bits);
853 /* Read the data. For microwire, each word requires
854 * the overhead of eeprom setup and tear-down. */
855 data[i] = e1000_shift_in_ee_bits(hw, 16);
856 e1000_standby_eeprom(hw);
860 /* End this read operation */
861 e1000_release_eeprom(hw);
863 return E1000_SUCCESS;
866 /******************************************************************************
867 * Verifies that the EEPROM has a valid checksum
869 * hw - Struct containing variables accessed by shared code
871 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
872 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
874 *****************************************************************************/
876 e1000_validate_eeprom_checksum(struct eth_device *nic)
878 struct e1000_hw *hw = nic->priv;
879 uint16_t checksum = 0;
880 uint16_t i, eeprom_data;
884 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
885 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
886 DEBUGOUT("EEPROM Read Error\n");
887 return -E1000_ERR_EEPROM;
889 checksum += eeprom_data;
892 if (checksum == (uint16_t) EEPROM_SUM) {
895 DEBUGOUT("EEPROM Checksum Invalid\n");
896 return -E1000_ERR_EEPROM;
900 /*****************************************************************************
901 * Set PHY to class A mode
902 * Assumes the following operations will follow to enable the new class mode.
903 * 1. Do a PHY soft reset
904 * 2. Restart auto-negotiation or force link.
906 * hw - Struct containing variables accessed by shared code
907 ****************************************************************************/
909 e1000_set_phy_mode(struct e1000_hw *hw)
912 uint16_t eeprom_data;
916 if ((hw->mac_type == e1000_82545_rev_3) &&
917 (hw->media_type == e1000_media_type_copper)) {
918 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
923 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
924 (eeprom_data & EEPROM_PHY_CLASS_A)) {
925 ret_val = e1000_write_phy_reg(hw,
926 M88E1000_PHY_PAGE_SELECT, 0x000B);
929 ret_val = e1000_write_phy_reg(hw,
930 M88E1000_PHY_GEN_CONTROL, 0x8104);
934 hw->phy_reset_disable = FALSE;
938 return E1000_SUCCESS;
940 #endif /* #ifndef CONFIG_AP1000 */
942 /***************************************************************************
944 * Obtaining software semaphore bit (SMBI) before resetting PHY.
946 * hw: Struct containing variables accessed by shared code
948 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
949 * E1000_SUCCESS at any other case.
951 ***************************************************************************/
953 e1000_get_software_semaphore(struct e1000_hw *hw)
955 int32_t timeout = hw->eeprom.word_size + 1;
960 if (hw->mac_type != e1000_80003es2lan)
961 return E1000_SUCCESS;
964 swsm = E1000_READ_REG(hw, SWSM);
965 /* If SMBI bit cleared, it is now set and we hold
967 if (!(swsm & E1000_SWSM_SMBI))
974 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
975 return -E1000_ERR_RESET;
978 return E1000_SUCCESS;
981 /***************************************************************************
982 * This function clears HW semaphore bits.
984 * hw: Struct containing variables accessed by shared code
988 ***************************************************************************/
990 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
996 if (!hw->eeprom_semaphore_present)
999 swsm = E1000_READ_REG(hw, SWSM);
1000 if (hw->mac_type == e1000_80003es2lan) {
1001 /* Release both semaphores. */
1002 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1004 swsm &= ~(E1000_SWSM_SWESMBI);
1005 E1000_WRITE_REG(hw, SWSM, swsm);
1008 /***************************************************************************
1010 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1011 * adapter or Eeprom access.
1013 * hw: Struct containing variables accessed by shared code
1015 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1016 * E1000_SUCCESS at any other case.
1018 ***************************************************************************/
1020 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1027 if (!hw->eeprom_semaphore_present)
1028 return E1000_SUCCESS;
1030 if (hw->mac_type == e1000_80003es2lan) {
1031 /* Get the SW semaphore. */
1032 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1033 return -E1000_ERR_EEPROM;
1036 /* Get the FW semaphore. */
1037 timeout = hw->eeprom.word_size + 1;
1039 swsm = E1000_READ_REG(hw, SWSM);
1040 swsm |= E1000_SWSM_SWESMBI;
1041 E1000_WRITE_REG(hw, SWSM, swsm);
1042 /* if we managed to set the bit we got the semaphore. */
1043 swsm = E1000_READ_REG(hw, SWSM);
1044 if (swsm & E1000_SWSM_SWESMBI)
1052 /* Release semaphores */
1053 e1000_put_hw_eeprom_semaphore(hw);
1054 DEBUGOUT("Driver can't access the Eeprom - "
1055 "SWESMBI bit is set.\n");
1056 return -E1000_ERR_EEPROM;
1059 return E1000_SUCCESS;
1063 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1065 uint32_t swfw_sync = 0;
1066 uint32_t swmask = mask;
1067 uint32_t fwmask = mask << 16;
1068 int32_t timeout = 200;
1072 if (e1000_get_hw_eeprom_semaphore(hw))
1073 return -E1000_ERR_SWFW_SYNC;
1075 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1076 if (!(swfw_sync & (fwmask | swmask)))
1079 /* firmware currently using resource (fwmask) */
1080 /* or other software thread currently using resource (swmask) */
1081 e1000_put_hw_eeprom_semaphore(hw);
1087 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1088 return -E1000_ERR_SWFW_SYNC;
1091 swfw_sync |= swmask;
1092 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1094 e1000_put_hw_eeprom_semaphore(hw);
1095 return E1000_SUCCESS;
1098 /******************************************************************************
1099 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1100 * second function of dual function devices
1102 * nic - Struct containing variables accessed by shared code
1103 *****************************************************************************/
1105 e1000_read_mac_addr(struct eth_device *nic)
1107 #ifndef CONFIG_AP1000
1108 struct e1000_hw *hw = nic->priv;
1110 uint16_t eeprom_data;
1115 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1117 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1118 DEBUGOUT("EEPROM Read Error\n");
1119 return -E1000_ERR_EEPROM;
1121 nic->enetaddr[i] = eeprom_data & 0xff;
1122 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1124 if ((hw->mac_type == e1000_82546) &&
1125 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
1126 /* Invert the last bit if this is the second device */
1127 nic->enetaddr[5] += 1;
1129 #ifdef CONFIG_E1000_FALLBACK_MAC
1130 if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 ) {
1131 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC;
1133 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE);
1138 * The AP1000's e1000 has no eeprom; the MAC address is stored in the
1139 * environment variables. Currently this does not support the addition
1140 * of a PMC e1000 card, which is certainly a possibility, so this should
1141 * be updated to properly use the env variable only for the onboard e1000
1149 s = getenv ("ethaddr");
1151 return -E1000_ERR_EEPROM;
1153 for(ii = 0; ii < 6; ii++) {
1154 nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0;
1156 s = (*e) ? e + 1 : e;
1164 /******************************************************************************
1165 * Initializes receive address filters.
1167 * hw - Struct containing variables accessed by shared code
1169 * Places the MAC address in receive address register 0 and clears the rest
1170 * of the receive addresss registers. Clears the multicast table. Assumes
1171 * the receiver is in reset when the routine is called.
1172 *****************************************************************************/
1174 e1000_init_rx_addrs(struct eth_device *nic)
1176 struct e1000_hw *hw = nic->priv;
1183 /* Setup the receive address. */
1184 DEBUGOUT("Programming MAC Address into RAR[0]\n");
1185 addr_low = (nic->enetaddr[0] |
1186 (nic->enetaddr[1] << 8) |
1187 (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24));
1189 addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV);
1191 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1192 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1194 /* Zero out the other 15 receive addresses. */
1195 DEBUGOUT("Clearing RAR[1-15]\n");
1196 for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1197 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1198 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1202 /******************************************************************************
1203 * Clears the VLAN filer table
1205 * hw - Struct containing variables accessed by shared code
1206 *****************************************************************************/
1208 e1000_clear_vfta(struct e1000_hw *hw)
1212 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1213 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1216 /******************************************************************************
1217 * Set the mac type member in the hw struct.
1219 * hw - Struct containing variables accessed by shared code
1220 *****************************************************************************/
1222 e1000_set_mac_type(struct e1000_hw *hw)
1226 switch (hw->device_id) {
1227 case E1000_DEV_ID_82542:
1228 switch (hw->revision_id) {
1229 case E1000_82542_2_0_REV_ID:
1230 hw->mac_type = e1000_82542_rev2_0;
1232 case E1000_82542_2_1_REV_ID:
1233 hw->mac_type = e1000_82542_rev2_1;
1236 /* Invalid 82542 revision ID */
1237 return -E1000_ERR_MAC_TYPE;
1240 case E1000_DEV_ID_82543GC_FIBER:
1241 case E1000_DEV_ID_82543GC_COPPER:
1242 hw->mac_type = e1000_82543;
1244 case E1000_DEV_ID_82544EI_COPPER:
1245 case E1000_DEV_ID_82544EI_FIBER:
1246 case E1000_DEV_ID_82544GC_COPPER:
1247 case E1000_DEV_ID_82544GC_LOM:
1248 hw->mac_type = e1000_82544;
1250 case E1000_DEV_ID_82540EM:
1251 case E1000_DEV_ID_82540EM_LOM:
1252 case E1000_DEV_ID_82540EP:
1253 case E1000_DEV_ID_82540EP_LOM:
1254 case E1000_DEV_ID_82540EP_LP:
1255 hw->mac_type = e1000_82540;
1257 case E1000_DEV_ID_82545EM_COPPER:
1258 case E1000_DEV_ID_82545EM_FIBER:
1259 hw->mac_type = e1000_82545;
1261 case E1000_DEV_ID_82545GM_COPPER:
1262 case E1000_DEV_ID_82545GM_FIBER:
1263 case E1000_DEV_ID_82545GM_SERDES:
1264 hw->mac_type = e1000_82545_rev_3;
1266 case E1000_DEV_ID_82546EB_COPPER:
1267 case E1000_DEV_ID_82546EB_FIBER:
1268 case E1000_DEV_ID_82546EB_QUAD_COPPER:
1269 hw->mac_type = e1000_82546;
1271 case E1000_DEV_ID_82546GB_COPPER:
1272 case E1000_DEV_ID_82546GB_FIBER:
1273 case E1000_DEV_ID_82546GB_SERDES:
1274 case E1000_DEV_ID_82546GB_PCIE:
1275 case E1000_DEV_ID_82546GB_QUAD_COPPER:
1276 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1277 hw->mac_type = e1000_82546_rev_3;
1279 case E1000_DEV_ID_82541EI:
1280 case E1000_DEV_ID_82541EI_MOBILE:
1281 case E1000_DEV_ID_82541ER_LOM:
1282 hw->mac_type = e1000_82541;
1284 case E1000_DEV_ID_82541ER:
1285 case E1000_DEV_ID_82541GI:
1286 case E1000_DEV_ID_82541GI_LF:
1287 case E1000_DEV_ID_82541GI_MOBILE:
1288 hw->mac_type = e1000_82541_rev_2;
1290 case E1000_DEV_ID_82547EI:
1291 case E1000_DEV_ID_82547EI_MOBILE:
1292 hw->mac_type = e1000_82547;
1294 case E1000_DEV_ID_82547GI:
1295 hw->mac_type = e1000_82547_rev_2;
1297 case E1000_DEV_ID_82571EB_COPPER:
1298 case E1000_DEV_ID_82571EB_FIBER:
1299 case E1000_DEV_ID_82571EB_SERDES:
1300 case E1000_DEV_ID_82571EB_SERDES_DUAL:
1301 case E1000_DEV_ID_82571EB_SERDES_QUAD:
1302 case E1000_DEV_ID_82571EB_QUAD_COPPER:
1303 case E1000_DEV_ID_82571PT_QUAD_COPPER:
1304 case E1000_DEV_ID_82571EB_QUAD_FIBER:
1305 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1306 hw->mac_type = e1000_82571;
1308 case E1000_DEV_ID_82572EI_COPPER:
1309 case E1000_DEV_ID_82572EI_FIBER:
1310 case E1000_DEV_ID_82572EI_SERDES:
1311 case E1000_DEV_ID_82572EI:
1312 hw->mac_type = e1000_82572;
1314 case E1000_DEV_ID_82573E:
1315 case E1000_DEV_ID_82573E_IAMT:
1316 case E1000_DEV_ID_82573L:
1317 hw->mac_type = e1000_82573;
1319 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1320 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1321 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1322 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1323 hw->mac_type = e1000_80003es2lan;
1325 case E1000_DEV_ID_ICH8_IGP_M_AMT:
1326 case E1000_DEV_ID_ICH8_IGP_AMT:
1327 case E1000_DEV_ID_ICH8_IGP_C:
1328 case E1000_DEV_ID_ICH8_IFE:
1329 case E1000_DEV_ID_ICH8_IFE_GT:
1330 case E1000_DEV_ID_ICH8_IFE_G:
1331 case E1000_DEV_ID_ICH8_IGP_M:
1332 hw->mac_type = e1000_ich8lan;
1335 /* Should never have loaded on this device */
1336 return -E1000_ERR_MAC_TYPE;
1338 return E1000_SUCCESS;
1341 /******************************************************************************
1342 * Reset the transmit and receive units; mask and clear all interrupts.
1344 * hw - Struct containing variables accessed by shared code
1345 *****************************************************************************/
1347 e1000_reset_hw(struct e1000_hw *hw)
1357 /* get the correct pba value for both PCI and PCIe*/
1358 if (hw->mac_type < e1000_82571)
1359 pba = E1000_DEFAULT_PCI_PBA;
1361 pba = E1000_DEFAULT_PCIE_PBA;
1363 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1364 if (hw->mac_type == e1000_82542_rev2_0) {
1365 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1366 pci_write_config_word(hw->pdev, PCI_COMMAND,
1367 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1370 /* Clear interrupt mask to stop board from generating interrupts */
1371 DEBUGOUT("Masking off all interrupts\n");
1372 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1374 /* Disable the Transmit and Receive units. Then delay to allow
1375 * any pending transactions to complete before we hit the MAC with
1378 E1000_WRITE_REG(hw, RCTL, 0);
1379 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1380 E1000_WRITE_FLUSH(hw);
1382 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1383 hw->tbi_compatibility_on = FALSE;
1385 /* Delay to allow any outstanding PCI transactions to complete before
1386 * resetting the device
1390 /* Issue a global reset to the MAC. This will reset the chip's
1391 * transmit, receive, DMA, and link units. It will not effect
1392 * the current PCI configuration. The global reset bit is self-
1393 * clearing, and should clear within a microsecond.
1395 DEBUGOUT("Issuing a global reset to MAC\n");
1396 ctrl = E1000_READ_REG(hw, CTRL);
1398 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1400 /* Force a reload from the EEPROM if necessary */
1401 if (hw->mac_type < e1000_82540) {
1402 /* Wait for reset to complete */
1404 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1405 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1406 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1407 E1000_WRITE_FLUSH(hw);
1408 /* Wait for EEPROM reload */
1411 /* Wait for EEPROM reload (it happens automatically) */
1413 /* Dissable HW ARPs on ASF enabled adapters */
1414 manc = E1000_READ_REG(hw, MANC);
1415 manc &= ~(E1000_MANC_ARP_EN);
1416 E1000_WRITE_REG(hw, MANC, manc);
1419 /* Clear interrupt mask to stop board from generating interrupts */
1420 DEBUGOUT("Masking off all interrupts\n");
1421 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1423 /* Clear any pending interrupt events. */
1424 icr = E1000_READ_REG(hw, ICR);
1426 /* If MWI was previously enabled, reenable it. */
1427 if (hw->mac_type == e1000_82542_rev2_0) {
1428 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1430 E1000_WRITE_REG(hw, PBA, pba);
1433 /******************************************************************************
1435 * Initialize a number of hardware-dependent bits
1437 * hw: Struct containing variables accessed by shared code
1439 * This function contains hardware limitation workarounds for PCI-E adapters
1441 *****************************************************************************/
1443 e1000_initialize_hardware_bits(struct e1000_hw *hw)
1445 if ((hw->mac_type >= e1000_82571) &&
1446 (!hw->initialize_hw_bits_disable)) {
1447 /* Settings common to all PCI-express silicon */
1448 uint32_t reg_ctrl, reg_ctrl_ext;
1449 uint32_t reg_tarc0, reg_tarc1;
1451 uint32_t reg_txdctl, reg_txdctl1;
1453 /* link autonegotiation/sync workarounds */
1454 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1455 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1457 /* Enable not-done TX descriptor counting */
1458 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1459 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1460 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1462 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1463 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1464 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1466 switch (hw->mac_type) {
1469 /* Clear PHY TX compatible mode bits */
1470 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1471 reg_tarc1 &= ~((1 << 30)|(1 << 29));
1473 /* link autonegotiation/sync workarounds */
1474 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1476 /* TX ring control fixes */
1477 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1479 /* Multiple read bit is reversed polarity */
1480 reg_tctl = E1000_READ_REG(hw, TCTL);
1481 if (reg_tctl & E1000_TCTL_MULR)
1482 reg_tarc1 &= ~(1 << 28);
1484 reg_tarc1 |= (1 << 28);
1486 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1489 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1490 reg_ctrl_ext &= ~(1 << 23);
1491 reg_ctrl_ext |= (1 << 22);
1493 /* TX byte count fix */
1494 reg_ctrl = E1000_READ_REG(hw, CTRL);
1495 reg_ctrl &= ~(1 << 29);
1497 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1498 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1500 case e1000_80003es2lan:
1501 /* improve small packet performace for fiber/serdes */
1502 if ((hw->media_type == e1000_media_type_fiber)
1503 || (hw->media_type ==
1504 e1000_media_type_internal_serdes)) {
1505 reg_tarc0 &= ~(1 << 20);
1508 /* Multiple read bit is reversed polarity */
1509 reg_tctl = E1000_READ_REG(hw, TCTL);
1510 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1511 if (reg_tctl & E1000_TCTL_MULR)
1512 reg_tarc1 &= ~(1 << 28);
1514 reg_tarc1 |= (1 << 28);
1516 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1519 /* Reduce concurrent DMA requests to 3 from 4 */
1520 if ((hw->revision_id < 3) ||
1521 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1522 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1523 reg_tarc0 |= ((1 << 29)|(1 << 28));
1525 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1526 reg_ctrl_ext |= (1 << 22);
1527 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1529 /* workaround TX hang with TSO=on */
1530 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1532 /* Multiple read bit is reversed polarity */
1533 reg_tctl = E1000_READ_REG(hw, TCTL);
1534 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1535 if (reg_tctl & E1000_TCTL_MULR)
1536 reg_tarc1 &= ~(1 << 28);
1538 reg_tarc1 |= (1 << 28);
1540 /* workaround TX hang with TSO=on */
1541 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1543 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1549 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1553 /******************************************************************************
1554 * Performs basic configuration of the adapter.
1556 * hw - Struct containing variables accessed by shared code
1558 * Assumes that the controller has previously been reset and is in a
1559 * post-reset uninitialized state. Initializes the receive address registers,
1560 * multicast table, and VLAN filter table. Calls routines to setup link
1561 * configuration and flow control settings. Clears all on-chip counters. Leaves
1562 * the transmit and receive units disabled and uninitialized.
1563 *****************************************************************************/
1565 e1000_init_hw(struct eth_device *nic)
1567 struct e1000_hw *hw = nic->priv;
1571 uint16_t pcix_cmd_word;
1572 uint16_t pcix_stat_hi_word;
1574 uint16_t stat_mmrbc;
1579 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1580 if ((hw->mac_type == e1000_ich8lan) &&
1581 ((hw->revision_id < 3) ||
1582 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1583 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1584 reg_data = E1000_READ_REG(hw, STATUS);
1585 reg_data &= ~0x80000000;
1586 E1000_WRITE_REG(hw, STATUS, reg_data);
1588 /* Do not need initialize Identification LED */
1590 /* Set the media type and TBI compatibility */
1591 e1000_set_media_type(hw);
1593 /* Must be called after e1000_set_media_type
1594 * because media_type is used */
1595 e1000_initialize_hardware_bits(hw);
1597 /* Disabling VLAN filtering. */
1598 DEBUGOUT("Initializing the IEEE VLAN\n");
1599 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1600 if (hw->mac_type != e1000_ich8lan) {
1601 if (hw->mac_type < e1000_82545_rev_3)
1602 E1000_WRITE_REG(hw, VET, 0);
1603 e1000_clear_vfta(hw);
1606 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1607 if (hw->mac_type == e1000_82542_rev2_0) {
1608 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1609 pci_write_config_word(hw->pdev, PCI_COMMAND,
1611 pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1612 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1613 E1000_WRITE_FLUSH(hw);
1617 /* Setup the receive address. This involves initializing all of the Receive
1618 * Address Registers (RARs 0 - 15).
1620 e1000_init_rx_addrs(nic);
1622 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1623 if (hw->mac_type == e1000_82542_rev2_0) {
1624 E1000_WRITE_REG(hw, RCTL, 0);
1625 E1000_WRITE_FLUSH(hw);
1627 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1630 /* Zero out the Multicast HASH table */
1631 DEBUGOUT("Zeroing the MTA\n");
1632 mta_size = E1000_MC_TBL_SIZE;
1633 if (hw->mac_type == e1000_ich8lan)
1634 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1635 for (i = 0; i < mta_size; i++) {
1636 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1637 /* use write flush to prevent Memory Write Block (MWB) from
1638 * occuring when accessing our register space */
1639 E1000_WRITE_FLUSH(hw);
1642 /* Set the PCI priority bit correctly in the CTRL register. This
1643 * determines if the adapter gives priority to receives, or if it
1644 * gives equal priority to transmits and receives. Valid only on
1645 * 82542 and 82543 silicon.
1647 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
1648 ctrl = E1000_READ_REG(hw, CTRL);
1649 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1652 switch (hw->mac_type) {
1653 case e1000_82545_rev_3:
1654 case e1000_82546_rev_3:
1657 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1658 if (hw->bus_type == e1000_bus_type_pcix) {
1659 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1661 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1662 &pcix_stat_hi_word);
1664 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1665 PCIX_COMMAND_MMRBC_SHIFT;
1667 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1668 PCIX_STATUS_HI_MMRBC_SHIFT;
1669 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1670 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1671 if (cmd_mmrbc > stat_mmrbc) {
1672 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1673 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1674 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1681 /* More time needed for PHY to initialize */
1682 if (hw->mac_type == e1000_ich8lan)
1685 /* Call a subroutine to configure the link and setup flow control. */
1686 ret_val = e1000_setup_link(nic);
1688 /* Set the transmit descriptor write-back policy */
1689 if (hw->mac_type > e1000_82544) {
1690 ctrl = E1000_READ_REG(hw, TXDCTL);
1692 (ctrl & ~E1000_TXDCTL_WTHRESH) |
1693 E1000_TXDCTL_FULL_TX_DESC_WB;
1694 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1697 switch (hw->mac_type) {
1700 case e1000_80003es2lan:
1701 /* Enable retransmit on late collisions */
1702 reg_data = E1000_READ_REG(hw, TCTL);
1703 reg_data |= E1000_TCTL_RTLC;
1704 E1000_WRITE_REG(hw, TCTL, reg_data);
1706 /* Configure Gigabit Carry Extend Padding */
1707 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1708 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1709 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1710 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1712 /* Configure Transmit Inter-Packet Gap */
1713 reg_data = E1000_READ_REG(hw, TIPG);
1714 reg_data &= ~E1000_TIPG_IPGT_MASK;
1715 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1716 E1000_WRITE_REG(hw, TIPG, reg_data);
1718 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1719 reg_data &= ~0x00100000;
1720 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1725 ctrl = E1000_READ_REG(hw, TXDCTL1);
1726 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
1727 | E1000_TXDCTL_FULL_TX_DESC_WB;
1728 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1732 if (hw->mac_type == e1000_82573) {
1733 uint32_t gcr = E1000_READ_REG(hw, GCR);
1734 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1735 E1000_WRITE_REG(hw, GCR, gcr);
1739 /* Clear all of the statistics registers (clear on read). It is
1740 * important that we do this after we have tried to establish link
1741 * because the symbol error count will increment wildly if there
1744 e1000_clear_hw_cntrs(hw);
1746 /* ICH8 No-snoop bits are opposite polarity.
1747 * Set to snoop by default after reset. */
1748 if (hw->mac_type == e1000_ich8lan)
1749 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1752 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1753 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1754 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1755 /* Relaxed ordering must be disabled to avoid a parity
1756 * error crash in a PCI slot. */
1757 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1758 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1764 /******************************************************************************
1765 * Configures flow control and link settings.
1767 * hw - Struct containing variables accessed by shared code
1769 * Determines which flow control settings to use. Calls the apropriate media-
1770 * specific link configuration function. Configures the flow control settings.
1771 * Assuming the adapter has a valid link partner, a valid link should be
1772 * established. Assumes the hardware has previously been reset and the
1773 * transmitter and receiver are not enabled.
1774 *****************************************************************************/
1776 e1000_setup_link(struct eth_device *nic)
1778 struct e1000_hw *hw = nic->priv;
1781 uint16_t eeprom_data;
1785 /* In the case of the phy reset being blocked, we already have a link.
1786 * We do not have to set it up again. */
1787 if (e1000_check_phy_reset_block(hw))
1788 return E1000_SUCCESS;
1790 #ifndef CONFIG_AP1000
1791 /* Read and store word 0x0F of the EEPROM. This word contains bits
1792 * that determine the hardware's default PAUSE (flow control) mode,
1793 * a bit that determines whether the HW defaults to enabling or
1794 * disabling auto-negotiation, and the direction of the
1795 * SW defined pins. If there is no SW over-ride of the flow
1796 * control setting, then the variable hw->fc will
1797 * be initialized based on a value in the EEPROM.
1799 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
1800 &eeprom_data) < 0) {
1801 DEBUGOUT("EEPROM Read Error\n");
1802 return -E1000_ERR_EEPROM;
1805 /* we have to hardcode the proper value for our hardware. */
1806 /* this value is for the 82540EM pci card used for prototyping, and it works. */
1807 eeprom_data = 0xb220;
1810 if (hw->fc == e1000_fc_default) {
1811 switch (hw->mac_type) {
1814 hw->fc = e1000_fc_full;
1817 #ifndef CONFIG_AP1000
1818 ret_val = e1000_read_eeprom(hw,
1819 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1821 DEBUGOUT("EEPROM Read Error\n");
1822 return -E1000_ERR_EEPROM;
1825 eeprom_data = 0xb220;
1827 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1828 hw->fc = e1000_fc_none;
1829 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1830 EEPROM_WORD0F_ASM_DIR)
1831 hw->fc = e1000_fc_tx_pause;
1833 hw->fc = e1000_fc_full;
1838 /* We want to save off the original Flow Control configuration just
1839 * in case we get disconnected and then reconnected into a different
1840 * hub or switch with different Flow Control capabilities.
1842 if (hw->mac_type == e1000_82542_rev2_0)
1843 hw->fc &= (~e1000_fc_tx_pause);
1845 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1846 hw->fc &= (~e1000_fc_rx_pause);
1848 hw->original_fc = hw->fc;
1850 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
1852 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1853 * polarity value for the SW controlled pins, and setup the
1854 * Extended Device Control reg with that info.
1855 * This is needed because one of the SW controlled pins is used for
1856 * signal detection. So this should be done before e1000_setup_pcs_link()
1857 * or e1000_phy_setup() is called.
1859 if (hw->mac_type == e1000_82543) {
1860 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1862 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1865 /* Call the necessary subroutine to configure the link. */
1866 ret_val = (hw->media_type == e1000_media_type_fiber) ?
1867 e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic);
1872 /* Initialize the flow control address, type, and PAUSE timer
1873 * registers to their default values. This is done even if flow
1874 * control is disabled, because it does not hurt anything to
1875 * initialize these registers.
1877 DEBUGOUT("Initializing the Flow Control address, type"
1878 "and timer regs\n");
1880 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1881 if (hw->mac_type != e1000_ich8lan) {
1882 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1883 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1884 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1887 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1889 /* Set the flow control receive threshold registers. Normally,
1890 * these registers will be set to a default threshold that may be
1891 * adjusted later by the driver's runtime code. However, if the
1892 * ability to transmit pause frames in not enabled, then these
1893 * registers will be set to 0.
1895 if (!(hw->fc & e1000_fc_tx_pause)) {
1896 E1000_WRITE_REG(hw, FCRTL, 0);
1897 E1000_WRITE_REG(hw, FCRTH, 0);
1899 /* We need to set up the Receive Threshold high and low water marks
1900 * as well as (optionally) enabling the transmission of XON frames.
1902 if (hw->fc_send_xon) {
1903 E1000_WRITE_REG(hw, FCRTL,
1904 (hw->fc_low_water | E1000_FCRTL_XONE));
1905 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1907 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1908 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1914 /******************************************************************************
1915 * Sets up link for a fiber based adapter
1917 * hw - Struct containing variables accessed by shared code
1919 * Manipulates Physical Coding Sublayer functions in order to configure
1920 * link. Assumes the hardware has been previously reset and the transmitter
1921 * and receiver are not enabled.
1922 *****************************************************************************/
1924 e1000_setup_fiber_link(struct eth_device *nic)
1926 struct e1000_hw *hw = nic->priv;
1935 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
1936 * set when the optics detect a signal. On older adapters, it will be
1937 * cleared when there is a signal
1939 ctrl = E1000_READ_REG(hw, CTRL);
1940 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
1941 signal = E1000_CTRL_SWDPIN1;
1945 printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal,
1947 /* Take the link out of reset */
1948 ctrl &= ~(E1000_CTRL_LRST);
1950 e1000_config_collision_dist(hw);
1952 /* Check for a software override of the flow control settings, and setup
1953 * the device accordingly. If auto-negotiation is enabled, then software
1954 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1955 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1956 * auto-negotiation is disabled, then software will have to manually
1957 * configure the two flow control enable bits in the CTRL register.
1959 * The possible values of the "fc" parameter are:
1960 * 0: Flow control is completely disabled
1961 * 1: Rx flow control is enabled (we can receive pause frames, but
1962 * not send pause frames).
1963 * 2: Tx flow control is enabled (we can send pause frames but we do
1964 * not support receiving pause frames).
1965 * 3: Both Rx and TX flow control (symmetric) are enabled.
1969 /* Flow control is completely disabled by a software over-ride. */
1970 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1972 case e1000_fc_rx_pause:
1973 /* RX Flow control is enabled and TX Flow control is disabled by a
1974 * software over-ride. Since there really isn't a way to advertise
1975 * that we are capable of RX Pause ONLY, we will advertise that we
1976 * support both symmetric and asymmetric RX PAUSE. Later, we will
1977 * disable the adapter's ability to send PAUSE frames.
1979 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1981 case e1000_fc_tx_pause:
1982 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1983 * software over-ride.
1985 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1988 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1989 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1992 DEBUGOUT("Flow control param set incorrectly\n");
1993 return -E1000_ERR_CONFIG;
1997 /* Since auto-negotiation is enabled, take the link out of reset (the link
1998 * will be in reset, because we previously reset the chip). This will
1999 * restart auto-negotiation. If auto-neogtiation is successful then the
2000 * link-up status bit will be set and the flow control enable bits (RFCE
2001 * and TFCE) will be set according to their negotiated value.
2003 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2005 E1000_WRITE_REG(hw, TXCW, txcw);
2006 E1000_WRITE_REG(hw, CTRL, ctrl);
2007 E1000_WRITE_FLUSH(hw);
2012 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
2013 * indication in the Device Status Register. Time-out if a link isn't
2014 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
2015 * less than 500 milliseconds even if the other end is doing it in SW).
2017 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2018 DEBUGOUT("Looking for Link\n");
2019 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2021 status = E1000_READ_REG(hw, STATUS);
2022 if (status & E1000_STATUS_LU)
2025 if (i == (LINK_UP_TIMEOUT / 10)) {
2026 /* AutoNeg failed to achieve a link, so we'll call
2027 * e1000_check_for_link. This routine will force the link up if we
2028 * detect a signal. This will allow us to communicate with
2029 * non-autonegotiating link partners.
2031 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2032 hw->autoneg_failed = 1;
2033 ret_val = e1000_check_for_link(nic);
2035 DEBUGOUT("Error while checking for link\n");
2038 hw->autoneg_failed = 0;
2040 hw->autoneg_failed = 0;
2041 DEBUGOUT("Valid Link Found\n");
2044 DEBUGOUT("No Signal Detected\n");
2045 return -E1000_ERR_NOLINK;
2050 /******************************************************************************
2051 * Make sure we have a valid PHY and change PHY mode before link setup.
2053 * hw - Struct containing variables accessed by shared code
2054 ******************************************************************************/
2056 e1000_copper_link_preconfig(struct e1000_hw *hw)
2064 ctrl = E1000_READ_REG(hw, CTRL);
2065 /* With 82543, we need to force speed and duplex on the MAC equal to what
2066 * the PHY speed and duplex configuration is. In addition, we need to
2067 * perform a hardware reset on the PHY to take it out of reset.
2069 if (hw->mac_type > e1000_82543) {
2070 ctrl |= E1000_CTRL_SLU;
2071 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2072 E1000_WRITE_REG(hw, CTRL, ctrl);
2074 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2076 E1000_WRITE_REG(hw, CTRL, ctrl);
2077 ret_val = e1000_phy_hw_reset(hw);
2082 /* Make sure we have a valid PHY */
2083 ret_val = e1000_detect_gig_phy(hw);
2085 DEBUGOUT("Error, did not detect valid phy.\n");
2088 DEBUGOUT("Phy ID = %x \n", hw->phy_id);
2090 #ifndef CONFIG_AP1000
2091 /* Set PHY to class A mode (if necessary) */
2092 ret_val = e1000_set_phy_mode(hw);
2096 if ((hw->mac_type == e1000_82545_rev_3) ||
2097 (hw->mac_type == e1000_82546_rev_3)) {
2098 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2100 phy_data |= 0x00000008;
2101 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2105 if (hw->mac_type <= e1000_82543 ||
2106 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2107 hw->mac_type == e1000_82541_rev_2
2108 || hw->mac_type == e1000_82547_rev_2)
2109 hw->phy_reset_disable = FALSE;
2111 return E1000_SUCCESS;
2114 /*****************************************************************************
2116 * This function sets the lplu state according to the active flag. When
2117 * activating lplu this function also disables smart speed and vise versa.
2118 * lplu will not be activated unless the device autonegotiation advertisment
2119 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2120 * hw: Struct containing variables accessed by shared code
2121 * active - true to enable lplu false to disable lplu.
2123 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2124 * E1000_SUCCESS at any other case.
2126 ****************************************************************************/
2129 e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active)
2131 uint32_t phy_ctrl = 0;
2136 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2137 && hw->phy_type != e1000_phy_igp_3)
2138 return E1000_SUCCESS;
2140 /* During driver activity LPLU should not be used or it will attain link
2141 * from the lowest speeds starting from 10Mbps. The capability is used
2142 * for Dx transitions and states */
2143 if (hw->mac_type == e1000_82541_rev_2
2144 || hw->mac_type == e1000_82547_rev_2) {
2145 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2149 } else if (hw->mac_type == e1000_ich8lan) {
2150 /* MAC writes into PHY register based on the state transition
2151 * and start auto-negotiation. SW driver can overwrite the
2152 * settings in CSR PHY power control E1000_PHY_CTRL register. */
2153 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2155 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2162 if (hw->mac_type == e1000_82541_rev_2 ||
2163 hw->mac_type == e1000_82547_rev_2) {
2164 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2165 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2170 if (hw->mac_type == e1000_ich8lan) {
2171 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2172 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2174 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2175 ret_val = e1000_write_phy_reg(hw,
2176 IGP02E1000_PHY_POWER_MGMT, phy_data);
2182 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2183 * Dx states where the power conservation is most important. During
2184 * driver activity we should enable SmartSpeed, so performance is
2186 if (hw->smart_speed == e1000_smart_speed_on) {
2187 ret_val = e1000_read_phy_reg(hw,
2188 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2192 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2193 ret_val = e1000_write_phy_reg(hw,
2194 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2197 } else if (hw->smart_speed == e1000_smart_speed_off) {
2198 ret_val = e1000_read_phy_reg(hw,
2199 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2203 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2204 ret_val = e1000_write_phy_reg(hw,
2205 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2210 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2211 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2212 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2214 if (hw->mac_type == e1000_82541_rev_2 ||
2215 hw->mac_type == e1000_82547_rev_2) {
2216 phy_data |= IGP01E1000_GMII_FLEX_SPD;
2217 ret_val = e1000_write_phy_reg(hw,
2218 IGP01E1000_GMII_FIFO, phy_data);
2222 if (hw->mac_type == e1000_ich8lan) {
2223 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2224 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2226 phy_data |= IGP02E1000_PM_D3_LPLU;
2227 ret_val = e1000_write_phy_reg(hw,
2228 IGP02E1000_PHY_POWER_MGMT, phy_data);
2234 /* When LPLU is enabled we should disable SmartSpeed */
2235 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2240 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2241 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2246 return E1000_SUCCESS;
2249 /*****************************************************************************
2251 * This function sets the lplu d0 state according to the active flag. When
2252 * activating lplu this function also disables smart speed and vise versa.
2253 * lplu will not be activated unless the device autonegotiation advertisment
2254 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2255 * hw: Struct containing variables accessed by shared code
2256 * active - true to enable lplu false to disable lplu.
2258 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2259 * E1000_SUCCESS at any other case.
2261 ****************************************************************************/
2264 e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active)
2266 uint32_t phy_ctrl = 0;
2271 if (hw->mac_type <= e1000_82547_rev_2)
2272 return E1000_SUCCESS;
2274 if (hw->mac_type == e1000_ich8lan) {
2275 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2277 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2284 if (hw->mac_type == e1000_ich8lan) {
2285 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2286 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2288 phy_data &= ~IGP02E1000_PM_D0_LPLU;
2289 ret_val = e1000_write_phy_reg(hw,
2290 IGP02E1000_PHY_POWER_MGMT, phy_data);
2295 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2296 * Dx states where the power conservation is most important. During
2297 * driver activity we should enable SmartSpeed, so performance is
2299 if (hw->smart_speed == e1000_smart_speed_on) {
2300 ret_val = e1000_read_phy_reg(hw,
2301 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2305 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2306 ret_val = e1000_write_phy_reg(hw,
2307 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2310 } else if (hw->smart_speed == e1000_smart_speed_off) {
2311 ret_val = e1000_read_phy_reg(hw,
2312 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2316 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2317 ret_val = e1000_write_phy_reg(hw,
2318 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2326 if (hw->mac_type == e1000_ich8lan) {
2327 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2328 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2330 phy_data |= IGP02E1000_PM_D0_LPLU;
2331 ret_val = e1000_write_phy_reg(hw,
2332 IGP02E1000_PHY_POWER_MGMT, phy_data);
2337 /* When LPLU is enabled we should disable SmartSpeed */
2338 ret_val = e1000_read_phy_reg(hw,
2339 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2343 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2344 ret_val = e1000_write_phy_reg(hw,
2345 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2350 return E1000_SUCCESS;
2353 /********************************************************************
2354 * Copper link setup for e1000_phy_igp series.
2356 * hw - Struct containing variables accessed by shared code
2357 *********************************************************************/
2359 e1000_copper_link_igp_setup(struct e1000_hw *hw)
2367 if (hw->phy_reset_disable)
2368 return E1000_SUCCESS;
2370 ret_val = e1000_phy_reset(hw);
2372 DEBUGOUT("Error Resetting the PHY\n");
2376 /* Wait 15ms for MAC to configure PHY from eeprom settings */
2378 if (hw->mac_type != e1000_ich8lan) {
2379 /* Configure activity LED after PHY reset */
2380 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2381 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2382 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2383 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2386 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2387 if (hw->phy_type == e1000_phy_igp) {
2388 /* disable lplu d3 during driver init */
2389 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
2391 DEBUGOUT("Error Disabling LPLU D3\n");
2396 /* disable lplu d0 during driver init */
2397 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
2399 DEBUGOUT("Error Disabling LPLU D0\n");
2402 /* Configure mdi-mdix settings */
2403 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2407 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2408 hw->dsp_config_state = e1000_dsp_config_disabled;
2409 /* Force MDI for earlier revs of the IGP PHY */
2410 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2411 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2415 hw->dsp_config_state = e1000_dsp_config_enabled;
2416 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2420 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2423 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2427 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2431 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2435 /* set auto-master slave resolution settings */
2437 e1000_ms_type phy_ms_setting = hw->master_slave;
2439 if (hw->ffe_config_state == e1000_ffe_config_active)
2440 hw->ffe_config_state = e1000_ffe_config_enabled;
2442 if (hw->dsp_config_state == e1000_dsp_config_activated)
2443 hw->dsp_config_state = e1000_dsp_config_enabled;
2445 /* when autonegotiation advertisment is only 1000Mbps then we
2446 * should disable SmartSpeed and enable Auto MasterSlave
2447 * resolution as hardware default. */
2448 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2449 /* Disable SmartSpeed */
2450 ret_val = e1000_read_phy_reg(hw,
2451 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2454 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2455 ret_val = e1000_write_phy_reg(hw,
2456 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2459 /* Set auto Master/Slave resolution process */
2460 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2464 phy_data &= ~CR_1000T_MS_ENABLE;
2465 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2471 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2475 /* load defaults for future use */
2476 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2477 ((phy_data & CR_1000T_MS_VALUE) ?
2478 e1000_ms_force_master :
2479 e1000_ms_force_slave) :
2482 switch (phy_ms_setting) {
2483 case e1000_ms_force_master:
2484 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2486 case e1000_ms_force_slave:
2487 phy_data |= CR_1000T_MS_ENABLE;
2488 phy_data &= ~(CR_1000T_MS_VALUE);
2491 phy_data &= ~CR_1000T_MS_ENABLE;
2495 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2500 return E1000_SUCCESS;
2503 /*****************************************************************************
2504 * This function checks the mode of the firmware.
2506 * returns - TRUE when the mode is IAMT or FALSE.
2507 ****************************************************************************/
2509 e1000_check_mng_mode(struct e1000_hw *hw)
2514 fwsm = E1000_READ_REG(hw, FWSM);
2516 if (hw->mac_type == e1000_ich8lan) {
2517 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2518 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2520 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2521 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2528 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2534 if ((hw->mac_type == e1000_80003es2lan) &&
2535 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
2536 swfw = E1000_SWFW_PHY1_SM;
2538 swfw = E1000_SWFW_PHY0_SM;
2540 if (e1000_swfw_sync_acquire(hw, swfw))
2541 return -E1000_ERR_SWFW_SYNC;
2543 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2544 & E1000_KUMCTRLSTA_OFFSET) | data;
2545 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2548 return E1000_SUCCESS;
2552 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2558 if ((hw->mac_type == e1000_80003es2lan) &&
2559 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
2560 swfw = E1000_SWFW_PHY1_SM;
2562 swfw = E1000_SWFW_PHY0_SM;
2564 if (e1000_swfw_sync_acquire(hw, swfw))
2565 return -E1000_ERR_SWFW_SYNC;
2567 /* Write register address */
2568 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2569 E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2570 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2573 /* Read the data returned */
2574 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2575 *data = (uint16_t)reg_val;
2577 return E1000_SUCCESS;
2580 /********************************************************************
2581 * Copper link setup for e1000_phy_gg82563 series.
2583 * hw - Struct containing variables accessed by shared code
2584 *********************************************************************/
2586 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2594 if (!hw->phy_reset_disable) {
2595 /* Enable CRS on TX for half-duplex operation. */
2596 ret_val = e1000_read_phy_reg(hw,
2597 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2601 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2602 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2603 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2605 ret_val = e1000_write_phy_reg(hw,
2606 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2611 * MDI/MDI-X = 0 (default)
2612 * 0 - Auto for all speeds
2615 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2617 ret_val = e1000_read_phy_reg(hw,
2618 GG82563_PHY_SPEC_CTRL, &phy_data);
2622 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2626 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2629 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2633 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2638 * disable_polarity_correction = 0 (default)
2639 * Automatic Correction for Reversed Cable Polarity
2643 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2644 ret_val = e1000_write_phy_reg(hw,
2645 GG82563_PHY_SPEC_CTRL, phy_data);
2650 /* SW Reset the PHY so all changes take effect */
2651 ret_val = e1000_phy_reset(hw);
2653 DEBUGOUT("Error Resetting the PHY\n");
2656 } /* phy_reset_disable */
2658 if (hw->mac_type == e1000_80003es2lan) {
2659 /* Bypass RX and TX FIFO's */
2660 ret_val = e1000_write_kmrn_reg(hw,
2661 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2662 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2663 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2667 ret_val = e1000_read_phy_reg(hw,
2668 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2672 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2673 ret_val = e1000_write_phy_reg(hw,
2674 GG82563_PHY_SPEC_CTRL_2, phy_data);
2679 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2680 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2681 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2683 ret_val = e1000_read_phy_reg(hw,
2684 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2688 /* Do not init these registers when the HW is in IAMT mode, since the
2689 * firmware will have already initialized them. We only initialize
2690 * them if the HW is not in IAMT mode.
2692 if (e1000_check_mng_mode(hw) == FALSE) {
2693 /* Enable Electrical Idle on the PHY */
2694 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2695 ret_val = e1000_write_phy_reg(hw,
2696 GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2700 ret_val = e1000_read_phy_reg(hw,
2701 GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2705 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2706 ret_val = e1000_write_phy_reg(hw,
2707 GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2713 /* Workaround: Disable padding in Kumeran interface in the MAC
2714 * and in the PHY to avoid CRC errors.
2716 ret_val = e1000_read_phy_reg(hw,
2717 GG82563_PHY_INBAND_CTRL, &phy_data);
2720 phy_data |= GG82563_ICR_DIS_PADDING;
2721 ret_val = e1000_write_phy_reg(hw,
2722 GG82563_PHY_INBAND_CTRL, phy_data);
2726 return E1000_SUCCESS;
2729 /********************************************************************
2730 * Copper link setup for e1000_phy_m88 series.
2732 * hw - Struct containing variables accessed by shared code
2733 *********************************************************************/
2735 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
2742 if (hw->phy_reset_disable)
2743 return E1000_SUCCESS;
2745 /* Enable CRS on TX. This must be set for half-duplex operation. */
2746 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2750 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2753 * MDI/MDI-X = 0 (default)
2754 * 0 - Auto for all speeds
2757 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2759 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2763 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
2766 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
2769 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
2773 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
2778 * disable_polarity_correction = 0 (default)
2779 * Automatic Correction for Reversed Cable Polarity
2783 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
2784 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2788 if (hw->phy_revision < M88E1011_I_REV_4) {
2789 /* Force TX_CLK in the Extended PHY Specific Control Register
2792 ret_val = e1000_read_phy_reg(hw,
2793 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2797 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2799 if ((hw->phy_revision == E1000_REVISION_2) &&
2800 (hw->phy_id == M88E1111_I_PHY_ID)) {
2801 /* Vidalia Phy, set the downshift counter to 5x */
2802 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
2803 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
2804 ret_val = e1000_write_phy_reg(hw,
2805 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2809 /* Configure Master and Slave downshift values */
2810 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
2811 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
2812 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
2813 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
2814 ret_val = e1000_write_phy_reg(hw,
2815 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2821 /* SW Reset the PHY so all changes take effect */
2822 ret_val = e1000_phy_reset(hw);
2824 DEBUGOUT("Error Resetting the PHY\n");
2828 return E1000_SUCCESS;
2831 /********************************************************************
2832 * Setup auto-negotiation and flow control advertisements,
2833 * and then perform auto-negotiation.
2835 * hw - Struct containing variables accessed by shared code
2836 *********************************************************************/
2838 e1000_copper_link_autoneg(struct e1000_hw *hw)
2845 /* Perform some bounds checking on the hw->autoneg_advertised
2846 * parameter. If this variable is zero, then set it to the default.
2848 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
2850 /* If autoneg_advertised is zero, we assume it was not defaulted
2851 * by the calling code so we set to advertise full capability.
2853 if (hw->autoneg_advertised == 0)
2854 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
2856 /* IFE phy only supports 10/100 */
2857 if (hw->phy_type == e1000_phy_ife)
2858 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
2860 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
2861 ret_val = e1000_phy_setup_autoneg(hw);
2863 DEBUGOUT("Error Setting up Auto-Negotiation\n");
2866 DEBUGOUT("Restarting Auto-Neg\n");
2868 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
2869 * the Auto Neg Restart bit in the PHY control register.
2871 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2875 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
2876 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2880 /* Does the user want to wait for Auto-Neg to complete here, or
2881 * check at a later time (for example, callback routine).
2883 /* If we do not wait for autonegtation to complete I
2884 * do not see a valid link status.
2885 * wait_autoneg_complete = 1 .
2887 if (hw->wait_autoneg_complete) {
2888 ret_val = e1000_wait_autoneg(hw);
2890 DEBUGOUT("Error while waiting for autoneg"
2896 hw->get_link_status = TRUE;
2898 return E1000_SUCCESS;
2901 /******************************************************************************
2902 * Config the MAC and the PHY after link is up.
2903 * 1) Set up the MAC to the current PHY speed/duplex
2904 * if we are on 82543. If we
2905 * are on newer silicon, we only need to configure
2906 * collision distance in the Transmit Control Register.
2907 * 2) Set up flow control on the MAC to that established with
2909 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
2911 * hw - Struct containing variables accessed by shared code
2912 ******************************************************************************/
2914 e1000_copper_link_postconfig(struct e1000_hw *hw)
2919 if (hw->mac_type >= e1000_82544) {
2920 e1000_config_collision_dist(hw);
2922 ret_val = e1000_config_mac_to_phy(hw);
2924 DEBUGOUT("Error configuring MAC to PHY settings\n");
2928 ret_val = e1000_config_fc_after_link_up(hw);
2930 DEBUGOUT("Error Configuring Flow Control\n");
2933 return E1000_SUCCESS;
2936 /******************************************************************************
2937 * Detects which PHY is present and setup the speed and duplex
2939 * hw - Struct containing variables accessed by shared code
2940 ******************************************************************************/
2942 e1000_setup_copper_link(struct eth_device *nic)
2944 struct e1000_hw *hw = nic->priv;
2952 switch (hw->mac_type) {
2953 case e1000_80003es2lan:
2955 /* Set the mac to wait the maximum time between each
2956 * iteration and increase the max iterations when
2957 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
2958 ret_val = e1000_write_kmrn_reg(hw,
2959 GG82563_REG(0x34, 4), 0xFFFF);
2962 ret_val = e1000_read_kmrn_reg(hw,
2963 GG82563_REG(0x34, 9), ®_data);
2967 ret_val = e1000_write_kmrn_reg(hw,
2968 GG82563_REG(0x34, 9), reg_data);
2975 /* Check if it is a valid PHY and set PHY mode if necessary. */
2976 ret_val = e1000_copper_link_preconfig(hw);
2979 switch (hw->mac_type) {
2980 case e1000_80003es2lan:
2981 /* Kumeran registers are written-only */
2983 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
2984 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
2985 ret_val = e1000_write_kmrn_reg(hw,
2986 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
2994 if (hw->phy_type == e1000_phy_igp ||
2995 hw->phy_type == e1000_phy_igp_3 ||
2996 hw->phy_type == e1000_phy_igp_2) {
2997 ret_val = e1000_copper_link_igp_setup(hw);
3000 } else if (hw->phy_type == e1000_phy_m88) {
3001 ret_val = e1000_copper_link_mgp_setup(hw);
3004 } else if (hw->phy_type == e1000_phy_gg82563) {
3005 ret_val = e1000_copper_link_ggp_setup(hw);
3011 /* Setup autoneg and flow control advertisement
3012 * and perform autonegotiation */
3013 ret_val = e1000_copper_link_autoneg(hw);
3017 /* Check link status. Wait up to 100 microseconds for link to become
3020 for (i = 0; i < 10; i++) {
3021 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3024 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3028 if (phy_data & MII_SR_LINK_STATUS) {
3029 /* Config the MAC and PHY after link is up */
3030 ret_val = e1000_copper_link_postconfig(hw);
3034 DEBUGOUT("Valid link established!!!\n");
3035 return E1000_SUCCESS;
3040 DEBUGOUT("Unable to establish link!!!\n");
3041 return E1000_SUCCESS;
3044 /******************************************************************************
3045 * Configures PHY autoneg and flow control advertisement settings
3047 * hw - Struct containing variables accessed by shared code
3048 ******************************************************************************/
3050 e1000_phy_setup_autoneg(struct e1000_hw *hw)
3053 uint16_t mii_autoneg_adv_reg;
3054 uint16_t mii_1000t_ctrl_reg;
3058 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3059 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3063 if (hw->phy_type != e1000_phy_ife) {
3064 /* Read the MII 1000Base-T Control Register (Address 9). */
3065 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3066 &mii_1000t_ctrl_reg);
3070 mii_1000t_ctrl_reg = 0;
3072 /* Need to parse both autoneg_advertised and fc and set up
3073 * the appropriate PHY registers. First we will parse for
3074 * autoneg_advertised software override. Since we can advertise
3075 * a plethora of combinations, we need to check each bit
3079 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3080 * Advertisement Register (Address 4) and the 1000 mb speed bits in
3081 * the 1000Base-T Control Register (Address 9).
3083 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3084 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3086 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3088 /* Do we want to advertise 10 Mb Half Duplex? */
3089 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3090 DEBUGOUT("Advertise 10mb Half duplex\n");
3091 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3094 /* Do we want to advertise 10 Mb Full Duplex? */
3095 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3096 DEBUGOUT("Advertise 10mb Full duplex\n");
3097 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3100 /* Do we want to advertise 100 Mb Half Duplex? */
3101 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3102 DEBUGOUT("Advertise 100mb Half duplex\n");
3103 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3106 /* Do we want to advertise 100 Mb Full Duplex? */
3107 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3108 DEBUGOUT("Advertise 100mb Full duplex\n");
3109 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3112 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3113 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3115 ("Advertise 1000mb Half duplex requested, request denied!\n");
3118 /* Do we want to advertise 1000 Mb Full Duplex? */
3119 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3120 DEBUGOUT("Advertise 1000mb Full duplex\n");
3121 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3124 /* Check for a software override of the flow control settings, and
3125 * setup the PHY advertisement registers accordingly. If
3126 * auto-negotiation is enabled, then software will have to set the
3127 * "PAUSE" bits to the correct value in the Auto-Negotiation
3128 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3130 * The possible values of the "fc" parameter are:
3131 * 0: Flow control is completely disabled
3132 * 1: Rx flow control is enabled (we can receive pause frames
3133 * but not send pause frames).
3134 * 2: Tx flow control is enabled (we can send pause frames
3135 * but we do not support receiving pause frames).
3136 * 3: Both Rx and TX flow control (symmetric) are enabled.
3137 * other: No software override. The flow control configuration
3138 * in the EEPROM is used.
3141 case e1000_fc_none: /* 0 */
3142 /* Flow control (RX & TX) is completely disabled by a
3143 * software over-ride.
3145 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3147 case e1000_fc_rx_pause: /* 1 */
3148 /* RX Flow control is enabled, and TX Flow control is
3149 * disabled, by a software over-ride.
3151 /* Since there really isn't a way to advertise that we are
3152 * capable of RX Pause ONLY, we will advertise that we
3153 * support both symmetric and asymmetric RX PAUSE. Later
3154 * (in e1000_config_fc_after_link_up) we will disable the
3155 *hw's ability to send PAUSE frames.
3157 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3159 case e1000_fc_tx_pause: /* 2 */
3160 /* TX Flow control is enabled, and RX Flow control is
3161 * disabled, by a software over-ride.
3163 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3164 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3166 case e1000_fc_full: /* 3 */
3167 /* Flow control (both RX and TX) is enabled by a software
3170 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3173 DEBUGOUT("Flow control param set incorrectly\n");
3174 return -E1000_ERR_CONFIG;
3177 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3181 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3183 if (hw->phy_type != e1000_phy_ife) {
3184 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3185 mii_1000t_ctrl_reg);
3190 return E1000_SUCCESS;
3193 /******************************************************************************
3194 * Sets the collision distance in the Transmit Control register
3196 * hw - Struct containing variables accessed by shared code
3198 * Link should have been established previously. Reads the speed and duplex
3199 * information from the Device Status register.
3200 ******************************************************************************/
3202 e1000_config_collision_dist(struct e1000_hw *hw)
3204 uint32_t tctl, coll_dist;
3208 if (hw->mac_type < e1000_82543)
3209 coll_dist = E1000_COLLISION_DISTANCE_82542;
3211 coll_dist = E1000_COLLISION_DISTANCE;
3213 tctl = E1000_READ_REG(hw, TCTL);
3215 tctl &= ~E1000_TCTL_COLD;
3216 tctl |= coll_dist << E1000_COLD_SHIFT;
3218 E1000_WRITE_REG(hw, TCTL, tctl);
3219 E1000_WRITE_FLUSH(hw);
3222 /******************************************************************************
3223 * Sets MAC speed and duplex settings to reflect the those in the PHY
3225 * hw - Struct containing variables accessed by shared code
3226 * mii_reg - data to write to the MII control register
3228 * The contents of the PHY register containing the needed information need to
3230 ******************************************************************************/
3232 e1000_config_mac_to_phy(struct e1000_hw *hw)
3239 /* Read the Device Control Register and set the bits to Force Speed
3242 ctrl = E1000_READ_REG(hw, CTRL);
3243 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3244 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
3246 /* Set up duplex in the Device Control and Transmit Control
3247 * registers depending on negotiated values.
3249 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3250 DEBUGOUT("PHY Read Error\n");
3251 return -E1000_ERR_PHY;
3253 if (phy_data & M88E1000_PSSR_DPLX)
3254 ctrl |= E1000_CTRL_FD;
3256 ctrl &= ~E1000_CTRL_FD;
3258 e1000_config_collision_dist(hw);
3260 /* Set up speed in the Device Control register depending on
3261 * negotiated values.
3263 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3264 ctrl |= E1000_CTRL_SPD_1000;
3265 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3266 ctrl |= E1000_CTRL_SPD_100;
3267 /* Write the configured values back to the Device Control Reg. */
3268 E1000_WRITE_REG(hw, CTRL, ctrl);
3272 /******************************************************************************
3273 * Forces the MAC's flow control settings.
3275 * hw - Struct containing variables accessed by shared code
3277 * Sets the TFCE and RFCE bits in the device control register to reflect
3278 * the adapter settings. TFCE and RFCE need to be explicitly set by
3279 * software when a Copper PHY is used because autonegotiation is managed
3280 * by the PHY rather than the MAC. Software must also configure these
3281 * bits when link is forced on a fiber connection.
3282 *****************************************************************************/
3284 e1000_force_mac_fc(struct e1000_hw *hw)
3290 /* Get the current configuration of the Device Control Register */
3291 ctrl = E1000_READ_REG(hw, CTRL);
3293 /* Because we didn't get link via the internal auto-negotiation
3294 * mechanism (we either forced link or we got link via PHY
3295 * auto-neg), we have to manually enable/disable transmit an
3296 * receive flow control.
3298 * The "Case" statement below enables/disable flow control
3299 * according to the "hw->fc" parameter.
3301 * The possible values of the "fc" parameter are:
3302 * 0: Flow control is completely disabled
3303 * 1: Rx flow control is enabled (we can receive pause
3304 * frames but not send pause frames).
3305 * 2: Tx flow control is enabled (we can send pause frames
3306 * frames but we do not receive pause frames).
3307 * 3: Both Rx and TX flow control (symmetric) is enabled.
3308 * other: No other values should be possible at this point.
3313 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3315 case e1000_fc_rx_pause:
3316 ctrl &= (~E1000_CTRL_TFCE);
3317 ctrl |= E1000_CTRL_RFCE;
3319 case e1000_fc_tx_pause:
3320 ctrl &= (~E1000_CTRL_RFCE);
3321 ctrl |= E1000_CTRL_TFCE;
3324 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3327 DEBUGOUT("Flow control param set incorrectly\n");
3328 return -E1000_ERR_CONFIG;
3331 /* Disable TX Flow Control for 82542 (rev 2.0) */
3332 if (hw->mac_type == e1000_82542_rev2_0)
3333 ctrl &= (~E1000_CTRL_TFCE);
3335 E1000_WRITE_REG(hw, CTRL, ctrl);
3339 /******************************************************************************
3340 * Configures flow control settings after link is established
3342 * hw - Struct containing variables accessed by shared code
3344 * Should be called immediately after a valid link has been established.
3345 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3346 * and autonegotiation is enabled, the MAC flow control settings will be set
3347 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3348 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3349 *****************************************************************************/
3351 e1000_config_fc_after_link_up(struct e1000_hw *hw)
3354 uint16_t mii_status_reg;
3355 uint16_t mii_nway_adv_reg;
3356 uint16_t mii_nway_lp_ability_reg;
3362 /* Check for the case where we have fiber media and auto-neg failed
3363 * so we had to force link. In this case, we need to force the
3364 * configuration of the MAC to match the "fc" parameter.
3366 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3367 || ((hw->media_type == e1000_media_type_internal_serdes)
3368 && (hw->autoneg_failed))
3369 || ((hw->media_type == e1000_media_type_copper)
3370 && (!hw->autoneg))) {
3371 ret_val = e1000_force_mac_fc(hw);
3373 DEBUGOUT("Error forcing flow control settings\n");
3378 /* Check for the case where we have copper media and auto-neg is
3379 * enabled. In this case, we need to check and see if Auto-Neg
3380 * has completed, and if so, how the PHY and link partner has
3381 * flow control configured.
3383 if (hw->media_type == e1000_media_type_copper) {
3384 /* Read the MII Status Register and check to see if AutoNeg
3385 * has completed. We read this twice because this reg has
3386 * some "sticky" (latched) bits.
3388 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3389 DEBUGOUT("PHY Read Error \n");
3390 return -E1000_ERR_PHY;
3392 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3393 DEBUGOUT("PHY Read Error \n");
3394 return -E1000_ERR_PHY;
3397 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3398 /* The AutoNeg process has completed, so we now need to
3399 * read both the Auto Negotiation Advertisement Register
3400 * (Address 4) and the Auto_Negotiation Base Page Ability
3401 * Register (Address 5) to determine how flow control was
3404 if (e1000_read_phy_reg
3405 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3406 DEBUGOUT("PHY Read Error\n");
3407 return -E1000_ERR_PHY;
3409 if (e1000_read_phy_reg
3410 (hw, PHY_LP_ABILITY,
3411 &mii_nway_lp_ability_reg) < 0) {
3412 DEBUGOUT("PHY Read Error\n");
3413 return -E1000_ERR_PHY;
3416 /* Two bits in the Auto Negotiation Advertisement Register
3417 * (Address 4) and two bits in the Auto Negotiation Base
3418 * Page Ability Register (Address 5) determine flow control
3419 * for both the PHY and the link partner. The following
3420 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3421 * 1999, describes these PAUSE resolution bits and how flow
3422 * control is determined based upon these settings.
3423 * NOTE: DC = Don't Care
3425 * LOCAL DEVICE | LINK PARTNER
3426 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3427 *-------|---------|-------|---------|--------------------
3428 * 0 | 0 | DC | DC | e1000_fc_none
3429 * 0 | 1 | 0 | DC | e1000_fc_none
3430 * 0 | 1 | 1 | 0 | e1000_fc_none
3431 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
3432 * 1 | 0 | 0 | DC | e1000_fc_none
3433 * 1 | DC | 1 | DC | e1000_fc_full
3434 * 1 | 1 | 0 | 0 | e1000_fc_none
3435 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
3438 /* Are both PAUSE bits set to 1? If so, this implies
3439 * Symmetric Flow Control is enabled at both ends. The
3440 * ASM_DIR bits are irrelevant per the spec.
3442 * For Symmetric Flow Control:
3444 * LOCAL DEVICE | LINK PARTNER
3445 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3446 *-------|---------|-------|---------|--------------------
3447 * 1 | DC | 1 | DC | e1000_fc_full
3450 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3451 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3452 /* Now we need to check if the user selected RX ONLY
3453 * of pause frames. In this case, we had to advertise
3454 * FULL flow control because we could not advertise RX
3455 * ONLY. Hence, we must now check to see if we need to
3456 * turn OFF the TRANSMISSION of PAUSE frames.
3458 if (hw->original_fc == e1000_fc_full) {
3459 hw->fc = e1000_fc_full;
3460 DEBUGOUT("Flow Control = FULL.\r\n");
3462 hw->fc = e1000_fc_rx_pause;
3464 ("Flow Control = RX PAUSE frames only.\r\n");
3467 /* For receiving PAUSE frames ONLY.
3469 * LOCAL DEVICE | LINK PARTNER
3470 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3471 *-------|---------|-------|---------|--------------------
3472 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
3475 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3476 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3477 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3478 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3480 hw->fc = e1000_fc_tx_pause;
3482 ("Flow Control = TX PAUSE frames only.\r\n");
3484 /* For transmitting PAUSE frames ONLY.
3486 * LOCAL DEVICE | LINK PARTNER
3487 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3488 *-------|---------|-------|---------|--------------------
3489 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
3492 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3493 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3494 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3495 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3497 hw->fc = e1000_fc_rx_pause;
3499 ("Flow Control = RX PAUSE frames only.\r\n");
3501 /* Per the IEEE spec, at this point flow control should be
3502 * disabled. However, we want to consider that we could
3503 * be connected to a legacy switch that doesn't advertise
3504 * desired flow control, but can be forced on the link
3505 * partner. So if we advertised no flow control, that is
3506 * what we will resolve to. If we advertised some kind of
3507 * receive capability (Rx Pause Only or Full Flow Control)
3508 * and the link partner advertised none, we will configure
3509 * ourselves to enable Rx Flow Control only. We can do
3510 * this safely for two reasons: If the link partner really
3511 * didn't want flow control enabled, and we enable Rx, no
3512 * harm done since we won't be receiving any PAUSE frames
3513 * anyway. If the intent on the link partner was to have
3514 * flow control enabled, then by us enabling RX only, we
3515 * can at least receive pause frames and process them.
3516 * This is a good idea because in most cases, since we are
3517 * predominantly a server NIC, more times than not we will
3518 * be asked to delay transmission of packets than asking
3519 * our link partner to pause transmission of frames.
3521 else if (hw->original_fc == e1000_fc_none ||
3522 hw->original_fc == e1000_fc_tx_pause) {
3523 hw->fc = e1000_fc_none;
3524 DEBUGOUT("Flow Control = NONE.\r\n");
3526 hw->fc = e1000_fc_rx_pause;
3528 ("Flow Control = RX PAUSE frames only.\r\n");
3531 /* Now we need to do one last check... If we auto-
3532 * negotiated to HALF DUPLEX, flow control should not be
3533 * enabled per IEEE 802.3 spec.
3535 e1000_get_speed_and_duplex(hw, &speed, &duplex);
3537 if (duplex == HALF_DUPLEX)
3538 hw->fc = e1000_fc_none;
3540 /* Now we call a subroutine to actually force the MAC
3541 * controller to use the correct flow control settings.
3543 ret_val = e1000_force_mac_fc(hw);
3546 ("Error forcing flow control settings\n");
3551 ("Copper PHY and Auto Neg has not completed.\r\n");
3554 return E1000_SUCCESS;
3557 /******************************************************************************
3558 * Checks to see if the link status of the hardware has changed.
3560 * hw - Struct containing variables accessed by shared code
3562 * Called by any function that needs to check the link status of the adapter.
3563 *****************************************************************************/
3565 e1000_check_for_link(struct eth_device *nic)
3567 struct e1000_hw *hw = nic->priv;
3575 uint16_t lp_capability;
3579 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3580 * set when the optics detect a signal. On older adapters, it will be
3581 * cleared when there is a signal
3583 ctrl = E1000_READ_REG(hw, CTRL);
3584 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3585 signal = E1000_CTRL_SWDPIN1;
3589 status = E1000_READ_REG(hw, STATUS);
3590 rxcw = E1000_READ_REG(hw, RXCW);
3591 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3593 /* If we have a copper PHY then we only want to go out to the PHY
3594 * registers to see if Auto-Neg has completed and/or if our link
3595 * status has changed. The get_link_status flag will be set if we
3596 * receive a Link Status Change interrupt or we have Rx Sequence
3599 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3600 /* First we want to see if the MII Status Register reports
3601 * link. If so, then we want to get the current speed/duplex
3603 * Read the register twice since the link bit is sticky.
3605 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3606 DEBUGOUT("PHY Read Error\n");
3607 return -E1000_ERR_PHY;
3609 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3610 DEBUGOUT("PHY Read Error\n");
3611 return -E1000_ERR_PHY;
3614 if (phy_data & MII_SR_LINK_STATUS) {
3615 hw->get_link_status = FALSE;
3617 /* No link detected */
3618 return -E1000_ERR_NOLINK;
3621 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
3622 * have Si on board that is 82544 or newer, Auto
3623 * Speed Detection takes care of MAC speed/duplex
3624 * configuration. So we only need to configure Collision
3625 * Distance in the MAC. Otherwise, we need to force
3626 * speed/duplex on the MAC to the current PHY speed/duplex
3629 if (hw->mac_type >= e1000_82544)
3630 e1000_config_collision_dist(hw);
3632 ret_val = e1000_config_mac_to_phy(hw);
3635 ("Error configuring MAC to PHY settings\n");
3640 /* Configure Flow Control now that Auto-Neg has completed. First, we
3641 * need to restore the desired flow control settings because we may
3642 * have had to re-autoneg with a different link partner.
3644 ret_val = e1000_config_fc_after_link_up(hw);
3646 DEBUGOUT("Error configuring flow control\n");
3650 /* At this point we know that we are on copper and we have
3651 * auto-negotiated link. These are conditions for checking the link
3652 * parter capability register. We use the link partner capability to
3653 * determine if TBI Compatibility needs to be turned on or off. If
3654 * the link partner advertises any speed in addition to Gigabit, then
3655 * we assume that they are GMII-based, and TBI compatibility is not
3656 * needed. If no other speeds are advertised, we assume the link
3657 * partner is TBI-based, and we turn on TBI Compatibility.
3659 if (hw->tbi_compatibility_en) {
3660 if (e1000_read_phy_reg
3661 (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3662 DEBUGOUT("PHY Read Error\n");
3663 return -E1000_ERR_PHY;
3665 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3666 NWAY_LPAR_10T_FD_CAPS |
3667 NWAY_LPAR_100TX_HD_CAPS |
3668 NWAY_LPAR_100TX_FD_CAPS |
3669 NWAY_LPAR_100T4_CAPS)) {
3670 /* If our link partner advertises anything in addition to
3671 * gigabit, we do not need to enable TBI compatibility.
3673 if (hw->tbi_compatibility_on) {
3674 /* If we previously were in the mode, turn it off. */
3675 rctl = E1000_READ_REG(hw, RCTL);
3676 rctl &= ~E1000_RCTL_SBP;
3677 E1000_WRITE_REG(hw, RCTL, rctl);
3678 hw->tbi_compatibility_on = FALSE;
3681 /* If TBI compatibility is was previously off, turn it on. For
3682 * compatibility with a TBI link partner, we will store bad
3683 * packets. Some frames have an additional byte on the end and
3684 * will look like CRC errors to to the hardware.
3686 if (!hw->tbi_compatibility_on) {
3687 hw->tbi_compatibility_on = TRUE;
3688 rctl = E1000_READ_REG(hw, RCTL);
3689 rctl |= E1000_RCTL_SBP;
3690 E1000_WRITE_REG(hw, RCTL, rctl);
3695 /* If we don't have link (auto-negotiation failed or link partner cannot
3696 * auto-negotiate), the cable is plugged in (we have signal), and our
3697 * link partner is not trying to auto-negotiate with us (we are receiving
3698 * idles or data), we need to force link up. We also need to give
3699 * auto-negotiation time to complete, in case the cable was just plugged
3700 * in. The autoneg_failed flag does this.
3702 else if ((hw->media_type == e1000_media_type_fiber) &&
3703 (!(status & E1000_STATUS_LU)) &&
3704 ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3705 (!(rxcw & E1000_RXCW_C))) {
3706 if (hw->autoneg_failed == 0) {
3707 hw->autoneg_failed = 1;
3710 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3712 /* Disable auto-negotiation in the TXCW register */
3713 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3715 /* Force link-up and also force full-duplex. */
3716 ctrl = E1000_READ_REG(hw, CTRL);
3717 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3718 E1000_WRITE_REG(hw, CTRL, ctrl);
3720 /* Configure Flow Control after forcing link up. */
3721 ret_val = e1000_config_fc_after_link_up(hw);
3723 DEBUGOUT("Error configuring flow control\n");
3727 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3728 * auto-negotiation in the TXCW register and disable forced link in the
3729 * Device Control register in an attempt to auto-negotiate with our link
3732 else if ((hw->media_type == e1000_media_type_fiber) &&
3733 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3735 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3736 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3737 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3742 /******************************************************************************
3743 * Configure the MAC-to-PHY interface for 10/100Mbps
3745 * hw - Struct containing variables accessed by shared code
3746 ******************************************************************************/
3748 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
3750 int32_t ret_val = E1000_SUCCESS;
3756 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
3757 ret_val = e1000_write_kmrn_reg(hw,
3758 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3762 /* Configure Transmit Inter-Packet Gap */
3763 tipg = E1000_READ_REG(hw, TIPG);
3764 tipg &= ~E1000_TIPG_IPGT_MASK;
3765 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
3766 E1000_WRITE_REG(hw, TIPG, tipg);
3768 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
3773 if (duplex == HALF_DUPLEX)
3774 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
3776 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3778 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3784 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
3786 int32_t ret_val = E1000_SUCCESS;
3792 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
3793 ret_val = e1000_write_kmrn_reg(hw,
3794 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3798 /* Configure Transmit Inter-Packet Gap */
3799 tipg = E1000_READ_REG(hw, TIPG);
3800 tipg &= ~E1000_TIPG_IPGT_MASK;
3801 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
3802 E1000_WRITE_REG(hw, TIPG, tipg);
3804 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
3809 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3810 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3815 /******************************************************************************
3816 * Detects the current speed and duplex settings of the hardware.
3818 * hw - Struct containing variables accessed by shared code
3819 * speed - Speed of the connection
3820 * duplex - Duplex setting of the connection
3821 *****************************************************************************/
3823 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
3832 if (hw->mac_type >= e1000_82543) {
3833 status = E1000_READ_REG(hw, STATUS);
3834 if (status & E1000_STATUS_SPEED_1000) {
3835 *speed = SPEED_1000;
3836 DEBUGOUT("1000 Mbs, ");
3837 } else if (status & E1000_STATUS_SPEED_100) {
3839 DEBUGOUT("100 Mbs, ");
3842 DEBUGOUT("10 Mbs, ");
3845 if (status & E1000_STATUS_FD) {
3846 *duplex = FULL_DUPLEX;
3847 DEBUGOUT("Full Duplex\r\n");
3849 *duplex = HALF_DUPLEX;
3850 DEBUGOUT(" Half Duplex\r\n");
3853 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
3854 *speed = SPEED_1000;
3855 *duplex = FULL_DUPLEX;
3858 /* IGP01 PHY may advertise full duplex operation after speed downgrade
3859 * even if it is operating at half duplex. Here we set the duplex
3860 * settings to match the duplex in the link partner's capabilities.
3862 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3863 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3867 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3868 *duplex = HALF_DUPLEX;
3870 ret_val = e1000_read_phy_reg(hw,
3871 PHY_LP_ABILITY, &phy_data);
3874 if ((*speed == SPEED_100 &&
3875 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
3876 || (*speed == SPEED_10
3877 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3878 *duplex = HALF_DUPLEX;
3882 if ((hw->mac_type == e1000_80003es2lan) &&
3883 (hw->media_type == e1000_media_type_copper)) {
3884 if (*speed == SPEED_1000)
3885 ret_val = e1000_configure_kmrn_for_1000(hw);
3887 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3891 return E1000_SUCCESS;
3894 /******************************************************************************
3895 * Blocks until autoneg completes or times out (~4.5 seconds)
3897 * hw - Struct containing variables accessed by shared code
3898 ******************************************************************************/
3900 e1000_wait_autoneg(struct e1000_hw *hw)
3906 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3908 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3909 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3910 /* Read the MII Status Register and wait for Auto-Neg
3911 * Complete bit to be set.
3913 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3914 DEBUGOUT("PHY Read Error\n");
3915 return -E1000_ERR_PHY;
3917 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3918 DEBUGOUT("PHY Read Error\n");
3919 return -E1000_ERR_PHY;
3921 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3922 DEBUGOUT("Auto-Neg complete.\n");
3927 DEBUGOUT("Auto-Neg timedout.\n");
3928 return -E1000_ERR_TIMEOUT;
3931 /******************************************************************************
3932 * Raises the Management Data Clock
3934 * hw - Struct containing variables accessed by shared code
3935 * ctrl - Device control register's current value
3936 ******************************************************************************/
3938 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
3940 /* Raise the clock input to the Management Data Clock (by setting the MDC
3941 * bit), and then delay 2 microseconds.
3943 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3944 E1000_WRITE_FLUSH(hw);
3948 /******************************************************************************
3949 * Lowers the Management Data Clock
3951 * hw - Struct containing variables accessed by shared code
3952 * ctrl - Device control register's current value
3953 ******************************************************************************/
3955 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
3957 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3958 * bit), and then delay 2 microseconds.
3960 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3961 E1000_WRITE_FLUSH(hw);
3965 /******************************************************************************
3966 * Shifts data bits out to the PHY
3968 * hw - Struct containing variables accessed by shared code
3969 * data - Data to send out to the PHY
3970 * count - Number of bits to shift out
3972 * Bits are shifted out in MSB to LSB order.
3973 ******************************************************************************/
3975 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
3980 /* We need to shift "count" number of bits out to the PHY. So, the value
3981 * in the "data" parameter will be shifted out to the PHY one bit at a
3982 * time. In order to do this, "data" must be broken down into bits.
3985 mask <<= (count - 1);
3987 ctrl = E1000_READ_REG(hw, CTRL);
3989 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3990 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3993 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3994 * then raising and lowering the Management Data Clock. A "0" is
3995 * shifted out to the PHY by setting the MDIO bit to "0" and then
3996 * raising and lowering the clock.
3999 ctrl |= E1000_CTRL_MDIO;
4001 ctrl &= ~E1000_CTRL_MDIO;
4003 E1000_WRITE_REG(hw, CTRL, ctrl);
4004 E1000_WRITE_FLUSH(hw);
4008 e1000_raise_mdi_clk(hw, &ctrl);
4009 e1000_lower_mdi_clk(hw, &ctrl);
4015 /******************************************************************************
4016 * Shifts data bits in from the PHY
4018 * hw - Struct containing variables accessed by shared code
4020 * Bits are shifted in in MSB to LSB order.
4021 ******************************************************************************/
4023 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4029 /* In order to read a register from the PHY, we need to shift in a total
4030 * of 18 bits from the PHY. The first two bit (turnaround) times are used
4031 * to avoid contention on the MDIO pin when a read operation is performed.
4032 * These two bits are ignored by us and thrown away. Bits are "shifted in"
4033 * by raising the input to the Management Data Clock (setting the MDC bit),
4034 * and then reading the value of the MDIO bit.
4036 ctrl = E1000_READ_REG(hw, CTRL);
4038 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4039 ctrl &= ~E1000_CTRL_MDIO_DIR;
4040 ctrl &= ~E1000_CTRL_MDIO;
4042 E1000_WRITE_REG(hw, CTRL, ctrl);
4043 E1000_WRITE_FLUSH(hw);
4045 /* Raise and Lower the clock before reading in the data. This accounts for
4046 * the turnaround bits. The first clock occurred when we clocked out the
4047 * last bit of the Register Address.
4049 e1000_raise_mdi_clk(hw, &ctrl);
4050 e1000_lower_mdi_clk(hw, &ctrl);
4052 for (data = 0, i = 0; i < 16; i++) {
4054 e1000_raise_mdi_clk(hw, &ctrl);
4055 ctrl = E1000_READ_REG(hw, CTRL);
4056 /* Check to see if we shifted in a "1". */
4057 if (ctrl & E1000_CTRL_MDIO)
4059 e1000_lower_mdi_clk(hw, &ctrl);
4062 e1000_raise_mdi_clk(hw, &ctrl);
4063 e1000_lower_mdi_clk(hw, &ctrl);
4068 /*****************************************************************************
4069 * Reads the value from a PHY register
4071 * hw - Struct containing variables accessed by shared code
4072 * reg_addr - address of the PHY register to read
4073 ******************************************************************************/
4075 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4079 const uint32_t phy_addr = 1;
4081 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4082 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4083 return -E1000_ERR_PARAM;
4086 if (hw->mac_type > e1000_82543) {
4087 /* Set up Op-code, Phy Address, and register address in the MDI
4088 * Control register. The MAC will take care of interfacing with the
4089 * PHY to retrieve the desired data.
4091 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4092 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4093 (E1000_MDIC_OP_READ));
4095 E1000_WRITE_REG(hw, MDIC, mdic);
4097 /* Poll the ready bit to see if the MDI read completed */
4098 for (i = 0; i < 64; i++) {
4100 mdic = E1000_READ_REG(hw, MDIC);
4101 if (mdic & E1000_MDIC_READY)
4104 if (!(mdic & E1000_MDIC_READY)) {
4105 DEBUGOUT("MDI Read did not complete\n");
4106 return -E1000_ERR_PHY;
4108 if (mdic & E1000_MDIC_ERROR) {
4109 DEBUGOUT("MDI Error\n");
4110 return -E1000_ERR_PHY;
4112 *phy_data = (uint16_t) mdic;
4114 /* We must first send a preamble through the MDIO pin to signal the
4115 * beginning of an MII instruction. This is done by sending 32
4116 * consecutive "1" bits.
4118 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4120 /* Now combine the next few fields that are required for a read
4121 * operation. We use this method instead of calling the
4122 * e1000_shift_out_mdi_bits routine five different times. The format of
4123 * a MII read instruction consists of a shift out of 14 bits and is
4124 * defined as follows:
4125 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4126 * followed by a shift in of 18 bits. This first two bits shifted in
4127 * are TurnAround bits used to avoid contention on the MDIO pin when a
4128 * READ operation is performed. These two bits are thrown away
4129 * followed by a shift in of 16 bits which contains the desired data.
4131 mdic = ((reg_addr) | (phy_addr << 5) |
4132 (PHY_OP_READ << 10) | (PHY_SOF << 12));
4134 e1000_shift_out_mdi_bits(hw, mdic, 14);
4136 /* Now that we've shifted out the read command to the MII, we need to
4137 * "shift in" the 16-bit value (18 total bits) of the requested PHY
4140 *phy_data = e1000_shift_in_mdi_bits(hw);
4145 /******************************************************************************
4146 * Writes a value to a PHY register
4148 * hw - Struct containing variables accessed by shared code
4149 * reg_addr - address of the PHY register to write
4150 * data - data to write to the PHY
4151 ******************************************************************************/
4153 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4157 const uint32_t phy_addr = 1;
4159 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4160 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4161 return -E1000_ERR_PARAM;
4164 if (hw->mac_type > e1000_82543) {
4165 /* Set up Op-code, Phy Address, register address, and data intended
4166 * for the PHY register in the MDI Control register. The MAC will take
4167 * care of interfacing with the PHY to send the desired data.
4169 mdic = (((uint32_t) phy_data) |
4170 (reg_addr << E1000_MDIC_REG_SHIFT) |
4171 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4172 (E1000_MDIC_OP_WRITE));
4174 E1000_WRITE_REG(hw, MDIC, mdic);
4176 /* Poll the ready bit to see if the MDI read completed */
4177 for (i = 0; i < 64; i++) {
4179 mdic = E1000_READ_REG(hw, MDIC);
4180 if (mdic & E1000_MDIC_READY)
4183 if (!(mdic & E1000_MDIC_READY)) {
4184 DEBUGOUT("MDI Write did not complete\n");
4185 return -E1000_ERR_PHY;
4188 /* We'll need to use the SW defined pins to shift the write command
4189 * out to the PHY. We first send a preamble to the PHY to signal the
4190 * beginning of the MII instruction. This is done by sending 32
4191 * consecutive "1" bits.
4193 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4195 /* Now combine the remaining required fields that will indicate a
4196 * write operation. We use this method instead of calling the
4197 * e1000_shift_out_mdi_bits routine for each field in the command. The
4198 * format of a MII write instruction is as follows:
4199 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4201 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4202 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4204 mdic |= (uint32_t) phy_data;
4206 e1000_shift_out_mdi_bits(hw, mdic, 32);
4211 /******************************************************************************
4212 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4213 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
4214 * the caller to figure out how to deal with it.
4216 * hw - Struct containing variables accessed by shared code
4218 * returns: - E1000_BLK_PHY_RESET
4221 *****************************************************************************/
4223 e1000_check_phy_reset_block(struct e1000_hw *hw)
4228 if (hw->mac_type == e1000_ich8lan) {
4229 fwsm = E1000_READ_REG(hw, FWSM);
4230 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4231 : E1000_BLK_PHY_RESET;
4234 if (hw->mac_type > e1000_82547_rev_2)
4235 manc = E1000_READ_REG(hw, MANC);
4236 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4237 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4240 /***************************************************************************
4241 * Checks if the PHY configuration is done
4243 * hw: Struct containing variables accessed by shared code
4245 * returns: - E1000_ERR_RESET if fail to reset MAC
4246 * E1000_SUCCESS at any other case.
4248 ***************************************************************************/
4250 e1000_get_phy_cfg_done(struct e1000_hw *hw)
4252 int32_t timeout = PHY_CFG_TIMEOUT;
4253 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4257 switch (hw->mac_type) {
4261 case e1000_80003es2lan:
4262 /* Separate *_CFG_DONE_* bit for each port */
4263 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
4264 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
4269 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4276 DEBUGOUT("MNG configuration cycle has not "
4278 return -E1000_ERR_RESET;
4283 return E1000_SUCCESS;
4286 /******************************************************************************
4287 * Returns the PHY to the power-on reset state
4289 * hw - Struct containing variables accessed by shared code
4290 ******************************************************************************/
4292 e1000_phy_hw_reset(struct e1000_hw *hw)
4294 uint32_t ctrl, ctrl_ext;
4301 /* In the case of the phy reset being blocked, it's not an error, we
4302 * simply return success without performing the reset. */
4303 ret_val = e1000_check_phy_reset_block(hw);
4305 return E1000_SUCCESS;
4307 DEBUGOUT("Resetting Phy...\n");
4309 if (hw->mac_type > e1000_82543) {
4310 if ((hw->mac_type == e1000_80003es2lan) &&
4311 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
4312 swfw = E1000_SWFW_PHY1_SM;
4314 swfw = E1000_SWFW_PHY0_SM;
4316 if (e1000_swfw_sync_acquire(hw, swfw)) {
4317 DEBUGOUT("Unable to acquire swfw sync\n");
4318 return -E1000_ERR_SWFW_SYNC;
4320 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4321 * bit. Then, take it out of reset.
4323 ctrl = E1000_READ_REG(hw, CTRL);
4324 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4325 E1000_WRITE_FLUSH(hw);
4327 if (hw->mac_type < e1000_82571)
4332 E1000_WRITE_REG(hw, CTRL, ctrl);
4333 E1000_WRITE_FLUSH(hw);
4335 if (hw->mac_type >= e1000_82571)
4339 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4340 * bit to put the PHY into reset. Then, take it out of reset.
4342 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4343 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4344 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4345 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4346 E1000_WRITE_FLUSH(hw);
4348 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4349 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4350 E1000_WRITE_FLUSH(hw);
4354 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4355 /* Configure activity LED after PHY reset */
4356 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4357 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4358 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4359 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4362 /* Wait for FW to finish PHY configuration. */
4363 ret_val = e1000_get_phy_cfg_done(hw);
4364 if (ret_val != E1000_SUCCESS)
4370 /******************************************************************************
4371 * IGP phy init script - initializes the GbE PHY
4373 * hw - Struct containing variables accessed by shared code
4374 *****************************************************************************/
4376 e1000_phy_init_script(struct e1000_hw *hw)
4379 uint16_t phy_saved_data;
4382 if (hw->phy_init_script) {
4385 /* Save off the current value of register 0x2F5B to be
4386 * restored at the end of this routine. */
4387 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4389 /* Disabled the PHY transmitter */
4390 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4394 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4398 switch (hw->mac_type) {
4401 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4403 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4405 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4407 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4409 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4411 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4413 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4415 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4417 e1000_write_phy_reg(hw, 0x2010, 0x0008);
4420 case e1000_82541_rev_2:
4421 case e1000_82547_rev_2:
4422 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4428 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4432 /* Now enable the transmitter */
4433 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
4435 if (hw->mac_type == e1000_82547) {
4436 uint16_t fused, fine, coarse;
4438 /* Move to analog registers page */
4439 e1000_read_phy_reg(hw,
4440 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4442 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4443 e1000_read_phy_reg(hw,
4444 IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4446 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4448 & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4451 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4453 IGP01E1000_ANALOG_FUSE_COARSE_10;
4454 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4456 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4457 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4460 & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4462 & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4464 & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4466 e1000_write_phy_reg(hw,
4467 IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4468 e1000_write_phy_reg(hw,
4469 IGP01E1000_ANALOG_FUSE_BYPASS,
4470 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4476 /******************************************************************************
4479 * hw - Struct containing variables accessed by shared code
4481 * Sets bit 15 of the MII Control register
4482 ******************************************************************************/
4484 e1000_phy_reset(struct e1000_hw *hw)
4491 /* In the case of the phy reset being blocked, it's not an error, we
4492 * simply return success without performing the reset. */
4493 ret_val = e1000_check_phy_reset_block(hw);
4495 return E1000_SUCCESS;
4497 switch (hw->phy_type) {
4499 case e1000_phy_igp_2:
4500 case e1000_phy_igp_3:
4502 ret_val = e1000_phy_hw_reset(hw);
4507 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4511 phy_data |= MII_CR_RESET;
4512 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4520 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4521 e1000_phy_init_script(hw);
4523 return E1000_SUCCESS;
4526 static int e1000_set_phy_type (struct e1000_hw *hw)
4530 if (hw->mac_type == e1000_undefined)
4531 return -E1000_ERR_PHY_TYPE;
4533 switch (hw->phy_id) {
4534 case M88E1000_E_PHY_ID:
4535 case M88E1000_I_PHY_ID:
4536 case M88E1011_I_PHY_ID:
4537 case M88E1111_I_PHY_ID:
4538 hw->phy_type = e1000_phy_m88;
4540 case IGP01E1000_I_PHY_ID:
4541 if (hw->mac_type == e1000_82541 ||
4542 hw->mac_type == e1000_82541_rev_2 ||
4543 hw->mac_type == e1000_82547 ||
4544 hw->mac_type == e1000_82547_rev_2) {
4545 hw->phy_type = e1000_phy_igp;
4546 hw->phy_type = e1000_phy_igp;
4549 case IGP03E1000_E_PHY_ID:
4550 hw->phy_type = e1000_phy_igp_3;
4553 case IFE_PLUS_E_PHY_ID:
4554 case IFE_C_E_PHY_ID:
4555 hw->phy_type = e1000_phy_ife;
4557 case GG82563_E_PHY_ID:
4558 if (hw->mac_type == e1000_80003es2lan) {
4559 hw->phy_type = e1000_phy_gg82563;
4564 /* Should never have loaded on this device */
4565 hw->phy_type = e1000_phy_undefined;
4566 return -E1000_ERR_PHY_TYPE;
4569 return E1000_SUCCESS;
4572 /******************************************************************************
4573 * Probes the expected PHY address for known PHY IDs
4575 * hw - Struct containing variables accessed by shared code
4576 ******************************************************************************/
4578 e1000_detect_gig_phy(struct e1000_hw *hw)
4580 int32_t phy_init_status, ret_val;
4581 uint16_t phy_id_high, phy_id_low;
4582 boolean_t match = FALSE;
4586 /* The 82571 firmware may still be configuring the PHY. In this
4587 * case, we cannot access the PHY until the configuration is done. So
4588 * we explicitly set the PHY values. */
4589 if (hw->mac_type == e1000_82571 ||
4590 hw->mac_type == e1000_82572) {
4591 hw->phy_id = IGP01E1000_I_PHY_ID;
4592 hw->phy_type = e1000_phy_igp_2;
4593 return E1000_SUCCESS;
4596 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4597 * work- around that forces PHY page 0 to be set or the reads fail.
4598 * The rest of the code in this routine uses e1000_read_phy_reg to
4599 * read the PHY ID. So for ESB-2 we need to have this set so our
4600 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
4601 * the routines below will figure this out as well. */
4602 if (hw->mac_type == e1000_80003es2lan)
4603 hw->phy_type = e1000_phy_gg82563;
4605 /* Read the PHY ID Registers to identify which PHY is onboard. */
4606 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4610 hw->phy_id = (uint32_t) (phy_id_high << 16);
4612 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4616 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4617 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4619 switch (hw->mac_type) {
4621 if (hw->phy_id == M88E1000_E_PHY_ID)
4625 if (hw->phy_id == M88E1000_I_PHY_ID)
4630 case e1000_82545_rev_3:
4632 case e1000_82546_rev_3:
4633 if (hw->phy_id == M88E1011_I_PHY_ID)
4637 case e1000_82541_rev_2:
4639 case e1000_82547_rev_2:
4640 if(hw->phy_id == IGP01E1000_I_PHY_ID)
4645 if (hw->phy_id == M88E1111_I_PHY_ID)
4648 case e1000_80003es2lan:
4649 if (hw->phy_id == GG82563_E_PHY_ID)
4653 if (hw->phy_id == IGP03E1000_E_PHY_ID)
4655 if (hw->phy_id == IFE_E_PHY_ID)
4657 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4659 if (hw->phy_id == IFE_C_E_PHY_ID)
4663 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4664 return -E1000_ERR_CONFIG;
4667 phy_init_status = e1000_set_phy_type(hw);
4669 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4670 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4673 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4674 return -E1000_ERR_PHY;
4677 /*****************************************************************************
4678 * Set media type and TBI compatibility.
4680 * hw - Struct containing variables accessed by shared code
4681 * **************************************************************************/
4683 e1000_set_media_type(struct e1000_hw *hw)
4689 if (hw->mac_type != e1000_82543) {
4690 /* tbi_compatibility is only valid on 82543 */
4691 hw->tbi_compatibility_en = FALSE;
4694 switch (hw->device_id) {
4695 case E1000_DEV_ID_82545GM_SERDES:
4696 case E1000_DEV_ID_82546GB_SERDES:
4697 case E1000_DEV_ID_82571EB_SERDES:
4698 case E1000_DEV_ID_82571EB_SERDES_DUAL:
4699 case E1000_DEV_ID_82571EB_SERDES_QUAD:
4700 case E1000_DEV_ID_82572EI_SERDES:
4701 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
4702 hw->media_type = e1000_media_type_internal_serdes;
4705 switch (hw->mac_type) {
4706 case e1000_82542_rev2_0:
4707 case e1000_82542_rev2_1:
4708 hw->media_type = e1000_media_type_fiber;
4712 /* The STATUS_TBIMODE bit is reserved or reused
4713 * for the this device.
4715 hw->media_type = e1000_media_type_copper;
4718 status = E1000_READ_REG(hw, STATUS);
4719 if (status & E1000_STATUS_TBIMODE) {
4720 hw->media_type = e1000_media_type_fiber;
4721 /* tbi_compatibility not valid on fiber */
4722 hw->tbi_compatibility_en = FALSE;
4724 hw->media_type = e1000_media_type_copper;
4732 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4734 * e1000_sw_init initializes the Adapter private data structure.
4735 * Fields are initialized based on PCI device information and
4736 * OS network device settings (MTU size).
4740 e1000_sw_init(struct eth_device *nic, int cardnum)
4742 struct e1000_hw *hw = (typeof(hw)) nic->priv;
4745 /* PCI config space info */
4746 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
4747 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
4748 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
4749 &hw->subsystem_vendor_id);
4750 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
4752 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
4753 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
4755 /* identify the MAC */
4756 result = e1000_set_mac_type(hw);
4758 E1000_ERR("Unknown MAC Type\n");
4762 switch (hw->mac_type) {
4767 case e1000_82541_rev_2:
4768 case e1000_82547_rev_2:
4769 hw->phy_init_script = 1;
4773 /* lan a vs. lan b settings */
4774 if (hw->mac_type == e1000_82546)
4775 /*this also works w/ multiple 82546 cards */
4776 /*but not if they're intermingled /w other e1000s */
4777 hw->lan_loc = (cardnum % 2) ? e1000_lan_b : e1000_lan_a;
4779 hw->lan_loc = e1000_lan_a;
4781 /* flow control settings */
4782 hw->fc_high_water = E1000_FC_HIGH_THRESH;
4783 hw->fc_low_water = E1000_FC_LOW_THRESH;
4784 hw->fc_pause_time = E1000_FC_PAUSE_TIME;
4785 hw->fc_send_xon = 1;
4787 /* Media type - copper or fiber */
4788 e1000_set_media_type(hw);
4790 if (hw->mac_type >= e1000_82543) {
4791 uint32_t status = E1000_READ_REG(hw, STATUS);
4793 if (status & E1000_STATUS_TBIMODE) {
4794 DEBUGOUT("fiber interface\n");
4795 hw->media_type = e1000_media_type_fiber;
4797 DEBUGOUT("copper interface\n");
4798 hw->media_type = e1000_media_type_copper;
4801 hw->media_type = e1000_media_type_fiber;
4804 hw->tbi_compatibility_en = TRUE;
4805 hw->wait_autoneg_complete = TRUE;
4806 if (hw->mac_type < e1000_82543)
4807 hw->report_tx_early = 0;
4809 hw->report_tx_early = 1;
4811 return E1000_SUCCESS;
4815 fill_rx(struct e1000_hw *hw)
4817 struct e1000_rx_desc *rd;
4820 rd = rx_base + rx_tail;
4821 rx_tail = (rx_tail + 1) % 8;
4823 rd->buffer_addr = cpu_to_le64((u32) & packet);
4824 E1000_WRITE_REG(hw, RDT, rx_tail);
4828 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
4829 * @adapter: board private structure
4831 * Configure the Tx unit of the MAC after a reset.
4835 e1000_configure_tx(struct e1000_hw *hw)
4839 unsigned long tipg, tarc;
4840 uint32_t ipgr1, ipgr2;
4842 ptr = (u32) tx_pool;
4844 ptr = (ptr + 0x10) & (~0xf);
4846 tx_base = (typeof(tx_base)) ptr;
4848 E1000_WRITE_REG(hw, TDBAL, (u32) tx_base);
4849 E1000_WRITE_REG(hw, TDBAH, 0);
4851 E1000_WRITE_REG(hw, TDLEN, 128);
4853 /* Setup the HW Tx Head and Tail descriptor pointers */
4854 E1000_WRITE_REG(hw, TDH, 0);
4855 E1000_WRITE_REG(hw, TDT, 0);
4858 /* Set the default values for the Tx Inter Packet Gap timer */
4859 if (hw->mac_type <= e1000_82547_rev_2 &&
4860 (hw->media_type == e1000_media_type_fiber ||
4861 hw->media_type == e1000_media_type_internal_serdes))
4862 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
4864 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
4866 /* Set the default values for the Tx Inter Packet Gap timer */
4867 switch (hw->mac_type) {
4868 case e1000_82542_rev2_0:
4869 case e1000_82542_rev2_1:
4870 tipg = DEFAULT_82542_TIPG_IPGT;
4871 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
4872 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
4874 case e1000_80003es2lan:
4875 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4876 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
4879 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4880 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
4883 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
4884 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
4885 E1000_WRITE_REG(hw, TIPG, tipg);
4886 /* Program the Transmit Control Register */
4887 tctl = E1000_READ_REG(hw, TCTL);
4888 tctl &= ~E1000_TCTL_CT;
4889 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
4890 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
4892 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
4893 tarc = E1000_READ_REG(hw, TARC0);
4894 /* set the speed mode bit, we'll clear it if we're not at
4895 * gigabit link later */
4896 /* git bit can be set to 1*/
4897 } else if (hw->mac_type == e1000_80003es2lan) {
4898 tarc = E1000_READ_REG(hw, TARC0);
4900 E1000_WRITE_REG(hw, TARC0, tarc);
4901 tarc = E1000_READ_REG(hw, TARC1);
4903 E1000_WRITE_REG(hw, TARC1, tarc);
4907 e1000_config_collision_dist(hw);
4908 /* Setup Transmit Descriptor Settings for eop descriptor */
4909 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
4911 /* Need to set up RS bit */
4912 if (hw->mac_type < e1000_82543)
4913 hw->txd_cmd |= E1000_TXD_CMD_RPS;
4915 hw->txd_cmd |= E1000_TXD_CMD_RS;
4916 E1000_WRITE_REG(hw, TCTL, tctl);
4920 * e1000_setup_rctl - configure the receive control register
4921 * @adapter: Board private structure
4924 e1000_setup_rctl(struct e1000_hw *hw)
4928 rctl = E1000_READ_REG(hw, RCTL);
4930 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
4932 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
4933 | E1000_RCTL_RDMTS_HALF; /* |
4934 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
4936 if (hw->tbi_compatibility_on == 1)
4937 rctl |= E1000_RCTL_SBP;
4939 rctl &= ~E1000_RCTL_SBP;
4941 rctl &= ~(E1000_RCTL_SZ_4096);
4942 rctl |= E1000_RCTL_SZ_2048;
4943 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
4944 E1000_WRITE_REG(hw, RCTL, rctl);
4948 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
4949 * @adapter: board private structure
4951 * Configure the Rx unit of the MAC after a reset.
4954 e1000_configure_rx(struct e1000_hw *hw)
4957 unsigned long rctl, ctrl_ext;
4959 /* make sure receives are disabled while setting up the descriptors */
4960 rctl = E1000_READ_REG(hw, RCTL);
4961 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
4962 if (hw->mac_type >= e1000_82540) {
4963 /* Set the interrupt throttling rate. Value is calculated
4964 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
4965 #define MAX_INTS_PER_SEC 8000
4966 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
4967 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
4970 if (hw->mac_type >= e1000_82571) {
4971 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4972 /* Reset delay timers after every interrupt */
4973 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
4974 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4975 E1000_WRITE_FLUSH(hw);
4977 /* Setup the Base and Length of the Rx Descriptor Ring */
4978 ptr = (u32) rx_pool;
4980 ptr = (ptr + 0x10) & (~0xf);
4981 rx_base = (typeof(rx_base)) ptr;
4982 E1000_WRITE_REG(hw, RDBAL, (u32) rx_base);
4983 E1000_WRITE_REG(hw, RDBAH, 0);
4985 E1000_WRITE_REG(hw, RDLEN, 128);
4987 /* Setup the HW Rx Head and Tail Descriptor Pointers */
4988 E1000_WRITE_REG(hw, RDH, 0);
4989 E1000_WRITE_REG(hw, RDT, 0);
4990 /* Enable Receives */
4992 E1000_WRITE_REG(hw, RCTL, rctl);
4996 /**************************************************************************
4997 POLL - Wait for a frame
4998 ***************************************************************************/
5000 e1000_poll(struct eth_device *nic)
5002 struct e1000_hw *hw = nic->priv;
5003 struct e1000_rx_desc *rd;
5004 /* return true if there's an ethernet packet ready to read */
5005 rd = rx_base + rx_last;
5006 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
5008 /*DEBUGOUT("recv: packet len=%d \n", rd->length); */
5009 NetReceive((uchar *)packet, le32_to_cpu(rd->length));
5014 /**************************************************************************
5015 TRANSMIT - Transmit a frame
5016 ***************************************************************************/
5018 e1000_transmit(struct eth_device *nic, volatile void *packet, int length)
5020 struct e1000_hw *hw = nic->priv;
5021 struct e1000_tx_desc *txp;
5024 txp = tx_base + tx_tail;
5025 tx_tail = (tx_tail + 1) % 8;
5027 txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, packet));
5028 txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
5029 txp->upper.data = 0;
5030 E1000_WRITE_REG(hw, TDT, tx_tail);
5032 E1000_WRITE_FLUSH(hw);
5033 while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) {
5034 if (i++ > TOUT_LOOP) {
5035 DEBUGOUT("e1000: tx timeout\n");
5038 udelay(10); /* give the nic a chance to write to the register */
5045 e1000_reset(struct eth_device *nic)
5047 struct e1000_hw *hw = nic->priv;
5050 if (hw->mac_type >= e1000_82544) {
5051 E1000_WRITE_REG(hw, WUC, 0);
5053 return e1000_init_hw(nic);
5056 /**************************************************************************
5057 DISABLE - Turn off ethernet interface
5058 ***************************************************************************/
5060 e1000_disable(struct eth_device *nic)
5062 struct e1000_hw *hw = nic->priv;
5064 /* Turn off the ethernet interface */
5065 E1000_WRITE_REG(hw, RCTL, 0);
5066 E1000_WRITE_REG(hw, TCTL, 0);
5068 /* Clear the transmit ring */
5069 E1000_WRITE_REG(hw, TDH, 0);
5070 E1000_WRITE_REG(hw, TDT, 0);
5072 /* Clear the receive ring */
5073 E1000_WRITE_REG(hw, RDH, 0);
5074 E1000_WRITE_REG(hw, RDT, 0);
5076 /* put the card in its initial state */
5078 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
5084 /**************************************************************************
5085 INIT - set up ethernet interface(s)
5086 ***************************************************************************/
5088 e1000_init(struct eth_device *nic, bd_t * bis)
5090 struct e1000_hw *hw = nic->priv;
5093 ret_val = e1000_reset(nic);
5095 if ((ret_val == -E1000_ERR_NOLINK) ||
5096 (ret_val == -E1000_ERR_TIMEOUT)) {
5097 E1000_ERR("Valid Link not detected\n");
5099 E1000_ERR("Hardware Initialization Failed\n");
5103 e1000_configure_tx(hw);
5104 e1000_setup_rctl(hw);
5105 e1000_configure_rx(hw);
5109 /******************************************************************************
5110 * Gets the current PCI bus type of hardware
5112 * hw - Struct containing variables accessed by shared code
5113 *****************************************************************************/
5114 void e1000_get_bus_type(struct e1000_hw *hw)
5118 switch (hw->mac_type) {
5119 case e1000_82542_rev2_0:
5120 case e1000_82542_rev2_1:
5121 hw->bus_type = e1000_bus_type_pci;
5126 case e1000_80003es2lan:
5127 hw->bus_type = e1000_bus_type_pci_express;
5130 hw->bus_type = e1000_bus_type_pci_express;
5133 status = E1000_READ_REG(hw, STATUS);
5134 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5135 e1000_bus_type_pcix : e1000_bus_type_pci;
5140 /**************************************************************************
5141 PROBE - Look for an adapter, this routine's visible to the outside
5142 You should omit the last argument struct pci_device * for a non-PCI NIC
5143 ***************************************************************************/
5145 e1000_initialize(bd_t * bis)
5148 int card_number = 0;
5149 struct eth_device *nic = NULL;
5150 struct e1000_hw *hw = NULL;
5157 while (1) { /* Find PCI device(s) */
5158 if ((devno = pci_find_devices(supported, idx++)) < 0) {
5162 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
5163 iobase &= ~0xf; /* Mask the bits that say "this is an io addr" */
5164 DEBUGOUT("e1000#%d: iobase 0x%08x\n", card_number, iobase);
5166 pci_write_config_dword(devno, PCI_COMMAND,
5167 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
5168 /* Check if I/O accesses and Bus Mastering are enabled. */
5169 pci_read_config_dword(devno, PCI_COMMAND, &PciCommandWord);
5170 if (!(PciCommandWord & PCI_COMMAND_MEMORY)) {
5171 printf("Error: Can not enable MEM access.\n");
5173 } else if (!(PciCommandWord & PCI_COMMAND_MASTER)) {
5174 printf("Error: Can not enable Bus Mastering.\n");
5178 nic = (struct eth_device *) malloc(sizeof (*nic));
5179 hw = (struct e1000_hw *) malloc(sizeof (*hw));
5183 sprintf(nic->name, "e1000#%d", card_number);
5185 /* Are these variables needed? */
5186 hw->fc = e1000_fc_default;
5187 hw->original_fc = e1000_fc_default;
5188 hw->autoneg_failed = 0;
5190 hw->get_link_status = TRUE;
5192 pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
5193 hw->mac_type = e1000_undefined;
5195 /* MAC and Phy settings */
5196 if (e1000_sw_init(nic, card_number) < 0) {
5201 if (e1000_check_phy_reset_block(hw))
5202 printf("phy reset block error \n");
5204 #if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G))
5205 if (e1000_init_eeprom_params(hw)) {
5206 printf("The EEPROM Checksum Is Not Valid\n");
5211 if (e1000_validate_eeprom_checksum(nic) < 0) {
5212 printf("The EEPROM Checksum Is Not Valid\n");
5218 e1000_read_mac_addr(nic);
5220 /* get the bus type information */
5221 e1000_get_bus_type(hw);
5223 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n",
5224 nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
5225 nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
5227 nic->init = e1000_init;
5228 nic->recv = e1000_poll;
5229 nic->send = e1000_transmit;
5230 nic->halt = e1000_disable;