1 /**************************************************************************
2 Intel Pro 1000 for ppcboot/das-u-boot
3 Drivers are port from Intel's Linux driver e1000-4.3.15
4 and from Etherboot pro 1000 driver by mrakes at vivato dot net
5 tested on both gig copper and gig fiber boards
6 ***************************************************************************/
7 /*******************************************************************************
10 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
12 * SPDX-License-Identifier: GPL-2.0+
15 Linux NICS <linux.nics@intel.com>
16 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
18 *******************************************************************************/
20 * Copyright (C) Archway Digital Solutions.
22 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
25 * Copyright (C) Linux Networx.
26 * Massive upgrade to work with the new intel gigabit NICs.
27 * <ebiederman at lnxi dot com>
29 * Copyright 2011 Freescale Semiconductor, Inc.
37 #define TOUT_LOOP 100000
39 #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
40 #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
42 #define E1000_DEFAULT_PCI_PBA 0x00000030
43 #define E1000_DEFAULT_PCIE_PBA 0x000a0026
45 /* NIC specific static variables go here */
47 /* Intel i210 needs the DMA descriptor rings aligned to 128b */
48 #define E1000_BUFFER_ALIGN 128
50 DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
51 DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
52 DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
55 static int rx_tail, rx_last;
57 static struct pci_device_id e1000_supported[] = {
58 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) },
59 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) },
60 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) },
61 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) },
62 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) },
63 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) },
64 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) },
65 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) },
66 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) },
67 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) },
68 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) },
69 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) },
70 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) },
71 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) },
72 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) },
73 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) },
74 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) },
76 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) },
77 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) },
78 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) },
79 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) },
80 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) },
81 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) },
82 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) },
83 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) },
84 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) },
85 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) },
86 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) },
87 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) },
88 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) },
89 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) },
90 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) },
91 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) },
92 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) },
93 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) },
94 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) },
95 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) },
96 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) },
97 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) },
98 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) },
99 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) },
100 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) },
101 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) },
102 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) },
103 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) },
104 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) },
105 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) },
110 /* Function forward declarations */
111 static int e1000_setup_link(struct e1000_hw *hw);
112 static int e1000_setup_fiber_link(struct e1000_hw *hw);
113 static int e1000_setup_copper_link(struct e1000_hw *hw);
114 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
115 static void e1000_config_collision_dist(struct e1000_hw *hw);
116 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
117 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
118 static int e1000_check_for_link(struct e1000_hw *hw);
119 static int e1000_wait_autoneg(struct e1000_hw *hw);
120 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
122 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
123 uint16_t * phy_data);
124 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
126 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
127 static int e1000_phy_reset(struct e1000_hw *hw);
128 static int e1000_detect_gig_phy(struct e1000_hw *hw);
129 static void e1000_set_media_type(struct e1000_hw *hw);
131 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
132 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
133 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
135 #ifndef CONFIG_E1000_NO_NVM
136 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
137 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
140 /******************************************************************************
141 * Raises the EEPROM's clock input.
143 * hw - Struct containing variables accessed by shared code
144 * eecd - EECD's current value
145 *****************************************************************************/
146 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
148 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
149 * wait 50 microseconds.
151 *eecd = *eecd | E1000_EECD_SK;
152 E1000_WRITE_REG(hw, EECD, *eecd);
153 E1000_WRITE_FLUSH(hw);
157 /******************************************************************************
158 * Lowers the EEPROM's clock input.
160 * hw - Struct containing variables accessed by shared code
161 * eecd - EECD's current value
162 *****************************************************************************/
163 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
165 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
166 * wait 50 microseconds.
168 *eecd = *eecd & ~E1000_EECD_SK;
169 E1000_WRITE_REG(hw, EECD, *eecd);
170 E1000_WRITE_FLUSH(hw);
174 /******************************************************************************
175 * Shift data bits out to the EEPROM.
177 * hw - Struct containing variables accessed by shared code
178 * data - data to send to the EEPROM
179 * count - number of bits to shift out
180 *****************************************************************************/
182 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
187 /* We need to shift "count" bits out to the EEPROM. So, value in the
188 * "data" parameter will be shifted out to the EEPROM one bit at a time.
189 * In order to do this, "data" must be broken down into bits.
191 mask = 0x01 << (count - 1);
192 eecd = E1000_READ_REG(hw, EECD);
193 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
195 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
196 * and then raising and then lowering the clock (the SK bit controls
197 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
198 * by setting "DI" to "0" and then raising and then lowering the clock.
200 eecd &= ~E1000_EECD_DI;
203 eecd |= E1000_EECD_DI;
205 E1000_WRITE_REG(hw, EECD, eecd);
206 E1000_WRITE_FLUSH(hw);
210 e1000_raise_ee_clk(hw, &eecd);
211 e1000_lower_ee_clk(hw, &eecd);
217 /* We leave the "DI" bit set to "0" when we leave this routine. */
218 eecd &= ~E1000_EECD_DI;
219 E1000_WRITE_REG(hw, EECD, eecd);
222 /******************************************************************************
223 * Shift data bits in from the EEPROM
225 * hw - Struct containing variables accessed by shared code
226 *****************************************************************************/
228 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
234 /* In order to read a register from the EEPROM, we need to shift 'count'
235 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
236 * input to the EEPROM (setting the SK bit), and then reading the
237 * value of the "DO" bit. During this "shifting in" process the
238 * "DI" bit should always be clear.
241 eecd = E1000_READ_REG(hw, EECD);
243 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
246 for (i = 0; i < count; i++) {
248 e1000_raise_ee_clk(hw, &eecd);
250 eecd = E1000_READ_REG(hw, EECD);
252 eecd &= ~(E1000_EECD_DI);
253 if (eecd & E1000_EECD_DO)
256 e1000_lower_ee_clk(hw, &eecd);
262 /******************************************************************************
263 * Returns EEPROM to a "standby" state
265 * hw - Struct containing variables accessed by shared code
266 *****************************************************************************/
267 void e1000_standby_eeprom(struct e1000_hw *hw)
269 struct e1000_eeprom_info *eeprom = &hw->eeprom;
272 eecd = E1000_READ_REG(hw, EECD);
274 if (eeprom->type == e1000_eeprom_microwire) {
275 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
276 E1000_WRITE_REG(hw, EECD, eecd);
277 E1000_WRITE_FLUSH(hw);
278 udelay(eeprom->delay_usec);
281 eecd |= E1000_EECD_SK;
282 E1000_WRITE_REG(hw, EECD, eecd);
283 E1000_WRITE_FLUSH(hw);
284 udelay(eeprom->delay_usec);
287 eecd |= E1000_EECD_CS;
288 E1000_WRITE_REG(hw, EECD, eecd);
289 E1000_WRITE_FLUSH(hw);
290 udelay(eeprom->delay_usec);
293 eecd &= ~E1000_EECD_SK;
294 E1000_WRITE_REG(hw, EECD, eecd);
295 E1000_WRITE_FLUSH(hw);
296 udelay(eeprom->delay_usec);
297 } else if (eeprom->type == e1000_eeprom_spi) {
298 /* Toggle CS to flush commands */
299 eecd |= E1000_EECD_CS;
300 E1000_WRITE_REG(hw, EECD, eecd);
301 E1000_WRITE_FLUSH(hw);
302 udelay(eeprom->delay_usec);
303 eecd &= ~E1000_EECD_CS;
304 E1000_WRITE_REG(hw, EECD, eecd);
305 E1000_WRITE_FLUSH(hw);
306 udelay(eeprom->delay_usec);
310 /***************************************************************************
311 * Description: Determines if the onboard NVM is FLASH or EEPROM.
313 * hw - Struct containing variables accessed by shared code
314 ****************************************************************************/
315 static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
321 if (hw->mac_type == e1000_ich8lan)
324 if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
325 eecd = E1000_READ_REG(hw, EECD);
327 /* Isolate bits 15 & 16 */
328 eecd = ((eecd >> 15) & 0x03);
330 /* If both bits are set, device is Flash type */
337 /******************************************************************************
338 * Prepares EEPROM for access
340 * hw - Struct containing variables accessed by shared code
342 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
343 * function should be called before issuing a command to the EEPROM.
344 *****************************************************************************/
345 int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
347 struct e1000_eeprom_info *eeprom = &hw->eeprom;
348 uint32_t eecd, i = 0;
352 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
353 return -E1000_ERR_SWFW_SYNC;
354 eecd = E1000_READ_REG(hw, EECD);
356 if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
357 /* Request EEPROM Access */
358 if (hw->mac_type > e1000_82544) {
359 eecd |= E1000_EECD_REQ;
360 E1000_WRITE_REG(hw, EECD, eecd);
361 eecd = E1000_READ_REG(hw, EECD);
362 while ((!(eecd & E1000_EECD_GNT)) &&
363 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
366 eecd = E1000_READ_REG(hw, EECD);
368 if (!(eecd & E1000_EECD_GNT)) {
369 eecd &= ~E1000_EECD_REQ;
370 E1000_WRITE_REG(hw, EECD, eecd);
371 DEBUGOUT("Could not acquire EEPROM grant\n");
372 return -E1000_ERR_EEPROM;
377 /* Setup EEPROM for Read/Write */
379 if (eeprom->type == e1000_eeprom_microwire) {
380 /* Clear SK and DI */
381 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
382 E1000_WRITE_REG(hw, EECD, eecd);
385 eecd |= E1000_EECD_CS;
386 E1000_WRITE_REG(hw, EECD, eecd);
387 } else if (eeprom->type == e1000_eeprom_spi) {
388 /* Clear SK and CS */
389 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
390 E1000_WRITE_REG(hw, EECD, eecd);
394 return E1000_SUCCESS;
397 /******************************************************************************
398 * Sets up eeprom variables in the hw struct. Must be called after mac_type
399 * is configured. Additionally, if this is ICH8, the flash controller GbE
400 * registers must be mapped, or this will crash.
402 * hw - Struct containing variables accessed by shared code
403 *****************************************************************************/
404 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
406 struct e1000_eeprom_info *eeprom = &hw->eeprom;
408 int32_t ret_val = E1000_SUCCESS;
409 uint16_t eeprom_size;
411 if (hw->mac_type == e1000_igb)
412 eecd = E1000_READ_REG(hw, I210_EECD);
414 eecd = E1000_READ_REG(hw, EECD);
418 switch (hw->mac_type) {
419 case e1000_82542_rev2_0:
420 case e1000_82542_rev2_1:
423 eeprom->type = e1000_eeprom_microwire;
424 eeprom->word_size = 64;
425 eeprom->opcode_bits = 3;
426 eeprom->address_bits = 6;
427 eeprom->delay_usec = 50;
428 eeprom->use_eerd = false;
429 eeprom->use_eewr = false;
433 case e1000_82545_rev_3:
435 case e1000_82546_rev_3:
436 eeprom->type = e1000_eeprom_microwire;
437 eeprom->opcode_bits = 3;
438 eeprom->delay_usec = 50;
439 if (eecd & E1000_EECD_SIZE) {
440 eeprom->word_size = 256;
441 eeprom->address_bits = 8;
443 eeprom->word_size = 64;
444 eeprom->address_bits = 6;
446 eeprom->use_eerd = false;
447 eeprom->use_eewr = false;
450 case e1000_82541_rev_2:
452 case e1000_82547_rev_2:
453 if (eecd & E1000_EECD_TYPE) {
454 eeprom->type = e1000_eeprom_spi;
455 eeprom->opcode_bits = 8;
456 eeprom->delay_usec = 1;
457 if (eecd & E1000_EECD_ADDR_BITS) {
458 eeprom->page_size = 32;
459 eeprom->address_bits = 16;
461 eeprom->page_size = 8;
462 eeprom->address_bits = 8;
465 eeprom->type = e1000_eeprom_microwire;
466 eeprom->opcode_bits = 3;
467 eeprom->delay_usec = 50;
468 if (eecd & E1000_EECD_ADDR_BITS) {
469 eeprom->word_size = 256;
470 eeprom->address_bits = 8;
472 eeprom->word_size = 64;
473 eeprom->address_bits = 6;
476 eeprom->use_eerd = false;
477 eeprom->use_eewr = false;
481 eeprom->type = e1000_eeprom_spi;
482 eeprom->opcode_bits = 8;
483 eeprom->delay_usec = 1;
484 if (eecd & E1000_EECD_ADDR_BITS) {
485 eeprom->page_size = 32;
486 eeprom->address_bits = 16;
488 eeprom->page_size = 8;
489 eeprom->address_bits = 8;
491 eeprom->use_eerd = false;
492 eeprom->use_eewr = false;
496 eeprom->type = e1000_eeprom_spi;
497 eeprom->opcode_bits = 8;
498 eeprom->delay_usec = 1;
499 if (eecd & E1000_EECD_ADDR_BITS) {
500 eeprom->page_size = 32;
501 eeprom->address_bits = 16;
503 eeprom->page_size = 8;
504 eeprom->address_bits = 8;
506 if (e1000_is_onboard_nvm_eeprom(hw) == false) {
507 eeprom->use_eerd = true;
508 eeprom->use_eewr = true;
510 eeprom->type = e1000_eeprom_flash;
511 eeprom->word_size = 2048;
513 /* Ensure that the Autonomous FLASH update bit is cleared due to
514 * Flash update issue on parts which use a FLASH for NVM. */
515 eecd &= ~E1000_EECD_AUPDEN;
516 E1000_WRITE_REG(hw, EECD, eecd);
519 case e1000_80003es2lan:
520 eeprom->type = e1000_eeprom_spi;
521 eeprom->opcode_bits = 8;
522 eeprom->delay_usec = 1;
523 if (eecd & E1000_EECD_ADDR_BITS) {
524 eeprom->page_size = 32;
525 eeprom->address_bits = 16;
527 eeprom->page_size = 8;
528 eeprom->address_bits = 8;
530 eeprom->use_eerd = true;
531 eeprom->use_eewr = false;
534 /* i210 has 4k of iNVM mapped as EEPROM */
535 eeprom->type = e1000_eeprom_invm;
536 eeprom->opcode_bits = 8;
537 eeprom->delay_usec = 1;
538 eeprom->page_size = 32;
539 eeprom->address_bits = 16;
540 eeprom->use_eerd = true;
541 eeprom->use_eewr = false;
544 /* ich8lan does not support currently. if needed, please
545 * add corresponding code and functions.
552 eeprom->type = e1000_eeprom_ich8;
553 eeprom->use_eerd = false;
554 eeprom->use_eewr = false;
555 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
556 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
558 /* Zero the shadow RAM structure. But don't load it from NVM
559 * so as to save time for driver init */
560 if (hw->eeprom_shadow_ram != NULL) {
561 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
562 hw->eeprom_shadow_ram[i].modified = false;
563 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
567 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
568 ICH_FLASH_SECTOR_SIZE;
570 hw->flash_bank_size = ((flash_size >> 16)
571 & ICH_GFPREG_BASE_MASK) + 1;
572 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
574 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
576 hw->flash_bank_size /= 2 * sizeof(uint16_t);
584 if (eeprom->type == e1000_eeprom_spi ||
585 eeprom->type == e1000_eeprom_invm) {
586 /* eeprom_size will be an enum [0..8] that maps
587 * to eeprom sizes 128B to
588 * 32KB (incremented by powers of 2).
590 if (hw->mac_type <= e1000_82547_rev_2) {
591 /* Set to default value for initial eeprom read. */
592 eeprom->word_size = 64;
593 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
597 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
598 >> EEPROM_SIZE_SHIFT;
599 /* 256B eeprom size was not supported in earlier
600 * hardware, so we bump eeprom_size up one to
601 * ensure that "1" (which maps to 256B) is never
602 * the result used in the shifting logic below. */
606 eeprom_size = (uint16_t)((eecd &
607 E1000_EECD_SIZE_EX_MASK) >>
608 E1000_EECD_SIZE_EX_SHIFT);
611 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
616 /******************************************************************************
617 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
619 * hw - Struct containing variables accessed by shared code
620 *****************************************************************************/
622 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
624 uint32_t attempts = 100000;
626 int32_t done = E1000_ERR_EEPROM;
628 for (i = 0; i < attempts; i++) {
629 if (eerd == E1000_EEPROM_POLL_READ) {
630 if (hw->mac_type == e1000_igb)
631 reg = E1000_READ_REG(hw, I210_EERD);
633 reg = E1000_READ_REG(hw, EERD);
635 if (hw->mac_type == e1000_igb)
636 reg = E1000_READ_REG(hw, I210_EEWR);
638 reg = E1000_READ_REG(hw, EEWR);
641 if (reg & E1000_EEPROM_RW_REG_DONE) {
642 done = E1000_SUCCESS;
651 /******************************************************************************
652 * Reads a 16 bit word from the EEPROM using the EERD register.
654 * hw - Struct containing variables accessed by shared code
655 * offset - offset of word in the EEPROM to read
656 * data - word read from the EEPROM
657 * words - number of words to read
658 *****************************************************************************/
660 e1000_read_eeprom_eerd(struct e1000_hw *hw,
665 uint32_t i, eerd = 0;
668 for (i = 0; i < words; i++) {
669 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
670 E1000_EEPROM_RW_REG_START;
672 if (hw->mac_type == e1000_igb)
673 E1000_WRITE_REG(hw, I210_EERD, eerd);
675 E1000_WRITE_REG(hw, EERD, eerd);
677 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
682 if (hw->mac_type == e1000_igb) {
683 data[i] = (E1000_READ_REG(hw, I210_EERD) >>
684 E1000_EEPROM_RW_REG_DATA);
686 data[i] = (E1000_READ_REG(hw, EERD) >>
687 E1000_EEPROM_RW_REG_DATA);
695 void e1000_release_eeprom(struct e1000_hw *hw)
701 eecd = E1000_READ_REG(hw, EECD);
703 if (hw->eeprom.type == e1000_eeprom_spi) {
704 eecd |= E1000_EECD_CS; /* Pull CS high */
705 eecd &= ~E1000_EECD_SK; /* Lower SCK */
707 E1000_WRITE_REG(hw, EECD, eecd);
709 udelay(hw->eeprom.delay_usec);
710 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
713 /* CS on Microwire is active-high */
714 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
716 E1000_WRITE_REG(hw, EECD, eecd);
718 /* Rising edge of clock */
719 eecd |= E1000_EECD_SK;
720 E1000_WRITE_REG(hw, EECD, eecd);
721 E1000_WRITE_FLUSH(hw);
722 udelay(hw->eeprom.delay_usec);
724 /* Falling edge of clock */
725 eecd &= ~E1000_EECD_SK;
726 E1000_WRITE_REG(hw, EECD, eecd);
727 E1000_WRITE_FLUSH(hw);
728 udelay(hw->eeprom.delay_usec);
731 /* Stop requesting EEPROM access */
732 if (hw->mac_type > e1000_82544) {
733 eecd &= ~E1000_EECD_REQ;
734 E1000_WRITE_REG(hw, EECD, eecd);
737 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
740 /******************************************************************************
741 * Reads a 16 bit word from the EEPROM.
743 * hw - Struct containing variables accessed by shared code
744 *****************************************************************************/
746 e1000_spi_eeprom_ready(struct e1000_hw *hw)
748 uint16_t retry_count = 0;
749 uint8_t spi_stat_reg;
753 /* Read "Status Register" repeatedly until the LSB is cleared. The
754 * EEPROM will signal that the command has been completed by clearing
755 * bit 0 of the internal status register. If it's not cleared within
756 * 5 milliseconds, then error out.
760 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
761 hw->eeprom.opcode_bits);
762 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
763 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
769 e1000_standby_eeprom(hw);
770 } while (retry_count < EEPROM_MAX_RETRY_SPI);
772 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
773 * only 0-5mSec on 5V devices)
775 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
776 DEBUGOUT("SPI EEPROM Status error\n");
777 return -E1000_ERR_EEPROM;
780 return E1000_SUCCESS;
783 /******************************************************************************
784 * Reads a 16 bit word from the EEPROM.
786 * hw - Struct containing variables accessed by shared code
787 * offset - offset of word in the EEPROM to read
788 * data - word read from the EEPROM
789 *****************************************************************************/
791 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
792 uint16_t words, uint16_t *data)
794 struct e1000_eeprom_info *eeprom = &hw->eeprom;
799 /* If eeprom is not yet detected, do so now */
800 if (eeprom->word_size == 0)
801 e1000_init_eeprom_params(hw);
803 /* A check for invalid values: offset too large, too many words,
804 * and not enough words.
806 if ((offset >= eeprom->word_size) ||
807 (words > eeprom->word_size - offset) ||
809 DEBUGOUT("\"words\" parameter out of bounds."
810 "Words = %d, size = %d\n", offset, eeprom->word_size);
811 return -E1000_ERR_EEPROM;
814 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
815 * directly. In this case, we need to acquire the EEPROM so that
816 * FW or other port software does not interrupt.
818 if (e1000_is_onboard_nvm_eeprom(hw) == true &&
819 hw->eeprom.use_eerd == false) {
821 /* Prepare the EEPROM for bit-bang reading */
822 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
823 return -E1000_ERR_EEPROM;
826 /* Eerd register EEPROM access requires no eeprom aquire/release */
827 if (eeprom->use_eerd == true)
828 return e1000_read_eeprom_eerd(hw, offset, words, data);
830 /* ich8lan does not support currently. if needed, please
831 * add corresponding code and functions.
834 /* ICH EEPROM access is done via the ICH flash controller */
835 if (eeprom->type == e1000_eeprom_ich8)
836 return e1000_read_eeprom_ich8(hw, offset, words, data);
838 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
839 * acquired the EEPROM at this point, so any returns should relase it */
840 if (eeprom->type == e1000_eeprom_spi) {
842 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
844 if (e1000_spi_eeprom_ready(hw)) {
845 e1000_release_eeprom(hw);
846 return -E1000_ERR_EEPROM;
849 e1000_standby_eeprom(hw);
851 /* Some SPI eeproms use the 8th address bit embedded in
853 if ((eeprom->address_bits == 8) && (offset >= 128))
854 read_opcode |= EEPROM_A8_OPCODE_SPI;
856 /* Send the READ command (opcode + addr) */
857 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
858 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
859 eeprom->address_bits);
861 /* Read the data. The address of the eeprom internally
862 * increments with each byte (spi) being read, saving on the
863 * overhead of eeprom setup and tear-down. The address
864 * counter will roll over if reading beyond the size of
865 * the eeprom, thus allowing the entire memory to be read
866 * starting from any offset. */
867 for (i = 0; i < words; i++) {
868 word_in = e1000_shift_in_ee_bits(hw, 16);
869 data[i] = (word_in >> 8) | (word_in << 8);
871 } else if (eeprom->type == e1000_eeprom_microwire) {
872 for (i = 0; i < words; i++) {
873 /* Send the READ command (opcode + addr) */
874 e1000_shift_out_ee_bits(hw,
875 EEPROM_READ_OPCODE_MICROWIRE,
876 eeprom->opcode_bits);
877 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
878 eeprom->address_bits);
880 /* Read the data. For microwire, each word requires
881 * the overhead of eeprom setup and tear-down. */
882 data[i] = e1000_shift_in_ee_bits(hw, 16);
883 e1000_standby_eeprom(hw);
887 /* End this read operation */
888 e1000_release_eeprom(hw);
890 return E1000_SUCCESS;
893 /******************************************************************************
894 * Verifies that the EEPROM has a valid checksum
896 * hw - Struct containing variables accessed by shared code
898 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
899 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
901 *****************************************************************************/
902 static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
904 uint16_t i, checksum, checksum_reg, *buf;
908 /* Allocate a temporary buffer */
909 buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
911 E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n");
912 return -E1000_ERR_EEPROM;
915 /* Read the EEPROM */
916 if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
917 E1000_ERR(hw, "Unable to read EEPROM!\n");
918 return -E1000_ERR_EEPROM;
921 /* Compute the checksum */
923 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
925 checksum = ((uint16_t)EEPROM_SUM) - checksum;
926 checksum_reg = buf[i];
929 if (checksum == checksum_reg)
932 /* Hrm, verification failed, print an error */
933 E1000_ERR(hw, "EEPROM checksum is incorrect!\n");
934 E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n",
935 checksum_reg, checksum);
937 return -E1000_ERR_EEPROM;
939 #endif /* CONFIG_E1000_NO_NVM */
941 /*****************************************************************************
942 * Set PHY to class A mode
943 * Assumes the following operations will follow to enable the new class mode.
944 * 1. Do a PHY soft reset
945 * 2. Restart auto-negotiation or force link.
947 * hw - Struct containing variables accessed by shared code
948 ****************************************************************************/
950 e1000_set_phy_mode(struct e1000_hw *hw)
952 #ifndef CONFIG_E1000_NO_NVM
954 uint16_t eeprom_data;
958 if ((hw->mac_type == e1000_82545_rev_3) &&
959 (hw->media_type == e1000_media_type_copper)) {
960 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
965 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
966 (eeprom_data & EEPROM_PHY_CLASS_A)) {
967 ret_val = e1000_write_phy_reg(hw,
968 M88E1000_PHY_PAGE_SELECT, 0x000B);
971 ret_val = e1000_write_phy_reg(hw,
972 M88E1000_PHY_GEN_CONTROL, 0x8104);
976 hw->phy_reset_disable = false;
980 return E1000_SUCCESS;
983 #ifndef CONFIG_E1000_NO_NVM
984 /***************************************************************************
986 * Obtaining software semaphore bit (SMBI) before resetting PHY.
988 * hw: Struct containing variables accessed by shared code
990 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
991 * E1000_SUCCESS at any other case.
993 ***************************************************************************/
995 e1000_get_software_semaphore(struct e1000_hw *hw)
997 int32_t timeout = hw->eeprom.word_size + 1;
1002 if (hw->mac_type != e1000_80003es2lan)
1003 return E1000_SUCCESS;
1006 swsm = E1000_READ_REG(hw, SWSM);
1007 /* If SMBI bit cleared, it is now set and we hold
1009 if (!(swsm & E1000_SWSM_SMBI))
1016 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1017 return -E1000_ERR_RESET;
1020 return E1000_SUCCESS;
1024 /***************************************************************************
1025 * This function clears HW semaphore bits.
1027 * hw: Struct containing variables accessed by shared code
1031 ***************************************************************************/
1033 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
1035 #ifndef CONFIG_E1000_NO_NVM
1040 if (!hw->eeprom_semaphore_present)
1043 swsm = E1000_READ_REG(hw, SWSM);
1044 if (hw->mac_type == e1000_80003es2lan) {
1045 /* Release both semaphores. */
1046 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1048 swsm &= ~(E1000_SWSM_SWESMBI);
1049 E1000_WRITE_REG(hw, SWSM, swsm);
1053 /***************************************************************************
1055 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1056 * adapter or Eeprom access.
1058 * hw: Struct containing variables accessed by shared code
1060 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1061 * E1000_SUCCESS at any other case.
1063 ***************************************************************************/
1065 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1067 #ifndef CONFIG_E1000_NO_NVM
1073 if (!hw->eeprom_semaphore_present)
1074 return E1000_SUCCESS;
1076 if (hw->mac_type == e1000_80003es2lan) {
1077 /* Get the SW semaphore. */
1078 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1079 return -E1000_ERR_EEPROM;
1082 /* Get the FW semaphore. */
1083 timeout = hw->eeprom.word_size + 1;
1085 swsm = E1000_READ_REG(hw, SWSM);
1086 swsm |= E1000_SWSM_SWESMBI;
1087 E1000_WRITE_REG(hw, SWSM, swsm);
1088 /* if we managed to set the bit we got the semaphore. */
1089 swsm = E1000_READ_REG(hw, SWSM);
1090 if (swsm & E1000_SWSM_SWESMBI)
1098 /* Release semaphores */
1099 e1000_put_hw_eeprom_semaphore(hw);
1100 DEBUGOUT("Driver can't access the Eeprom - "
1101 "SWESMBI bit is set.\n");
1102 return -E1000_ERR_EEPROM;
1105 return E1000_SUCCESS;
1108 /* Take ownership of the PHY */
1110 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1112 uint32_t swfw_sync = 0;
1113 uint32_t swmask = mask;
1114 uint32_t fwmask = mask << 16;
1115 int32_t timeout = 200;
1119 if (e1000_get_hw_eeprom_semaphore(hw))
1120 return -E1000_ERR_SWFW_SYNC;
1122 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1123 if (!(swfw_sync & (fwmask | swmask)))
1126 /* firmware currently using resource (fwmask) */
1127 /* or other software thread currently using resource (swmask) */
1128 e1000_put_hw_eeprom_semaphore(hw);
1134 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1135 return -E1000_ERR_SWFW_SYNC;
1138 swfw_sync |= swmask;
1139 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1141 e1000_put_hw_eeprom_semaphore(hw);
1142 return E1000_SUCCESS;
1145 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
1147 uint32_t swfw_sync = 0;
1150 while (e1000_get_hw_eeprom_semaphore(hw))
1153 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1155 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1157 e1000_put_hw_eeprom_semaphore(hw);
1160 static bool e1000_is_second_port(struct e1000_hw *hw)
1162 switch (hw->mac_type) {
1163 case e1000_80003es2lan:
1166 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1174 #ifndef CONFIG_E1000_NO_NVM
1175 /******************************************************************************
1176 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1177 * second function of dual function devices
1179 * nic - Struct containing variables accessed by shared code
1180 *****************************************************************************/
1182 e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6])
1185 uint16_t eeprom_data;
1186 uint32_t reg_data = 0;
1191 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1193 if (hw->mac_type == e1000_igb) {
1194 /* i210 preloads MAC address into RAL/RAH registers */
1196 reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
1197 else if (offset == 1)
1199 else if (offset == 2)
1200 reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
1201 eeprom_data = reg_data & 0xffff;
1202 } else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1203 DEBUGOUT("EEPROM Read Error\n");
1204 return -E1000_ERR_EEPROM;
1206 enetaddr[i] = eeprom_data & 0xff;
1207 enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1210 /* Invert the last bit if this is the second device */
1211 if (e1000_is_second_port(hw))
1214 #ifdef CONFIG_E1000_FALLBACK_MAC
1215 if (!is_valid_ethaddr(nic->enetaddr)) {
1216 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC;
1218 memcpy(enetaddr, fb_mac, NODE_ADDRESS_SIZE);
1225 /******************************************************************************
1226 * Initializes receive address filters.
1228 * hw - Struct containing variables accessed by shared code
1230 * Places the MAC address in receive address register 0 and clears the rest
1231 * of the receive addresss registers. Clears the multicast table. Assumes
1232 * the receiver is in reset when the routine is called.
1233 *****************************************************************************/
1235 e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6])
1243 /* Setup the receive address. */
1244 DEBUGOUT("Programming MAC Address into RAR[0]\n");
1245 addr_low = (enetaddr[0] |
1246 (enetaddr[1] << 8) |
1247 (enetaddr[2] << 16) | (enetaddr[3] << 24));
1249 addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV);
1251 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1252 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1254 /* Zero out the other 15 receive addresses. */
1255 DEBUGOUT("Clearing RAR[1-15]\n");
1256 for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1257 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1258 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1262 /******************************************************************************
1263 * Clears the VLAN filer table
1265 * hw - Struct containing variables accessed by shared code
1266 *****************************************************************************/
1268 e1000_clear_vfta(struct e1000_hw *hw)
1272 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1273 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1276 /******************************************************************************
1277 * Set the mac type member in the hw struct.
1279 * hw - Struct containing variables accessed by shared code
1280 *****************************************************************************/
1282 e1000_set_mac_type(struct e1000_hw *hw)
1286 switch (hw->device_id) {
1287 case E1000_DEV_ID_82542:
1288 switch (hw->revision_id) {
1289 case E1000_82542_2_0_REV_ID:
1290 hw->mac_type = e1000_82542_rev2_0;
1292 case E1000_82542_2_1_REV_ID:
1293 hw->mac_type = e1000_82542_rev2_1;
1296 /* Invalid 82542 revision ID */
1297 return -E1000_ERR_MAC_TYPE;
1300 case E1000_DEV_ID_82543GC_FIBER:
1301 case E1000_DEV_ID_82543GC_COPPER:
1302 hw->mac_type = e1000_82543;
1304 case E1000_DEV_ID_82544EI_COPPER:
1305 case E1000_DEV_ID_82544EI_FIBER:
1306 case E1000_DEV_ID_82544GC_COPPER:
1307 case E1000_DEV_ID_82544GC_LOM:
1308 hw->mac_type = e1000_82544;
1310 case E1000_DEV_ID_82540EM:
1311 case E1000_DEV_ID_82540EM_LOM:
1312 case E1000_DEV_ID_82540EP:
1313 case E1000_DEV_ID_82540EP_LOM:
1314 case E1000_DEV_ID_82540EP_LP:
1315 hw->mac_type = e1000_82540;
1317 case E1000_DEV_ID_82545EM_COPPER:
1318 case E1000_DEV_ID_82545EM_FIBER:
1319 hw->mac_type = e1000_82545;
1321 case E1000_DEV_ID_82545GM_COPPER:
1322 case E1000_DEV_ID_82545GM_FIBER:
1323 case E1000_DEV_ID_82545GM_SERDES:
1324 hw->mac_type = e1000_82545_rev_3;
1326 case E1000_DEV_ID_82546EB_COPPER:
1327 case E1000_DEV_ID_82546EB_FIBER:
1328 case E1000_DEV_ID_82546EB_QUAD_COPPER:
1329 hw->mac_type = e1000_82546;
1331 case E1000_DEV_ID_82546GB_COPPER:
1332 case E1000_DEV_ID_82546GB_FIBER:
1333 case E1000_DEV_ID_82546GB_SERDES:
1334 case E1000_DEV_ID_82546GB_PCIE:
1335 case E1000_DEV_ID_82546GB_QUAD_COPPER:
1336 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1337 hw->mac_type = e1000_82546_rev_3;
1339 case E1000_DEV_ID_82541EI:
1340 case E1000_DEV_ID_82541EI_MOBILE:
1341 case E1000_DEV_ID_82541ER_LOM:
1342 hw->mac_type = e1000_82541;
1344 case E1000_DEV_ID_82541ER:
1345 case E1000_DEV_ID_82541GI:
1346 case E1000_DEV_ID_82541GI_LF:
1347 case E1000_DEV_ID_82541GI_MOBILE:
1348 hw->mac_type = e1000_82541_rev_2;
1350 case E1000_DEV_ID_82547EI:
1351 case E1000_DEV_ID_82547EI_MOBILE:
1352 hw->mac_type = e1000_82547;
1354 case E1000_DEV_ID_82547GI:
1355 hw->mac_type = e1000_82547_rev_2;
1357 case E1000_DEV_ID_82571EB_COPPER:
1358 case E1000_DEV_ID_82571EB_FIBER:
1359 case E1000_DEV_ID_82571EB_SERDES:
1360 case E1000_DEV_ID_82571EB_SERDES_DUAL:
1361 case E1000_DEV_ID_82571EB_SERDES_QUAD:
1362 case E1000_DEV_ID_82571EB_QUAD_COPPER:
1363 case E1000_DEV_ID_82571PT_QUAD_COPPER:
1364 case E1000_DEV_ID_82571EB_QUAD_FIBER:
1365 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1366 hw->mac_type = e1000_82571;
1368 case E1000_DEV_ID_82572EI_COPPER:
1369 case E1000_DEV_ID_82572EI_FIBER:
1370 case E1000_DEV_ID_82572EI_SERDES:
1371 case E1000_DEV_ID_82572EI:
1372 hw->mac_type = e1000_82572;
1374 case E1000_DEV_ID_82573E:
1375 case E1000_DEV_ID_82573E_IAMT:
1376 case E1000_DEV_ID_82573L:
1377 hw->mac_type = e1000_82573;
1379 case E1000_DEV_ID_82574L:
1380 hw->mac_type = e1000_82574;
1382 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1383 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1384 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1385 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1386 hw->mac_type = e1000_80003es2lan;
1388 case E1000_DEV_ID_ICH8_IGP_M_AMT:
1389 case E1000_DEV_ID_ICH8_IGP_AMT:
1390 case E1000_DEV_ID_ICH8_IGP_C:
1391 case E1000_DEV_ID_ICH8_IFE:
1392 case E1000_DEV_ID_ICH8_IFE_GT:
1393 case E1000_DEV_ID_ICH8_IFE_G:
1394 case E1000_DEV_ID_ICH8_IGP_M:
1395 hw->mac_type = e1000_ich8lan;
1397 case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
1398 case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
1399 case PCI_DEVICE_ID_INTEL_I210_COPPER:
1400 case PCI_DEVICE_ID_INTEL_I211_COPPER:
1401 case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
1402 case PCI_DEVICE_ID_INTEL_I210_SERDES:
1403 case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
1404 case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
1405 hw->mac_type = e1000_igb;
1408 /* Should never have loaded on this device */
1409 return -E1000_ERR_MAC_TYPE;
1411 return E1000_SUCCESS;
1414 /******************************************************************************
1415 * Reset the transmit and receive units; mask and clear all interrupts.
1417 * hw - Struct containing variables accessed by shared code
1418 *****************************************************************************/
1420 e1000_reset_hw(struct e1000_hw *hw)
1430 /* get the correct pba value for both PCI and PCIe*/
1431 if (hw->mac_type < e1000_82571)
1432 pba = E1000_DEFAULT_PCI_PBA;
1434 pba = E1000_DEFAULT_PCIE_PBA;
1436 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1437 if (hw->mac_type == e1000_82542_rev2_0) {
1438 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1439 pci_write_config_word(hw->pdev, PCI_COMMAND,
1440 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1443 /* Clear interrupt mask to stop board from generating interrupts */
1444 DEBUGOUT("Masking off all interrupts\n");
1445 if (hw->mac_type == e1000_igb)
1446 E1000_WRITE_REG(hw, I210_IAM, 0);
1447 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1449 /* Disable the Transmit and Receive units. Then delay to allow
1450 * any pending transactions to complete before we hit the MAC with
1453 E1000_WRITE_REG(hw, RCTL, 0);
1454 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1455 E1000_WRITE_FLUSH(hw);
1457 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1458 hw->tbi_compatibility_on = false;
1460 /* Delay to allow any outstanding PCI transactions to complete before
1461 * resetting the device
1465 /* Issue a global reset to the MAC. This will reset the chip's
1466 * transmit, receive, DMA, and link units. It will not effect
1467 * the current PCI configuration. The global reset bit is self-
1468 * clearing, and should clear within a microsecond.
1470 DEBUGOUT("Issuing a global reset to MAC\n");
1471 ctrl = E1000_READ_REG(hw, CTRL);
1473 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1475 /* Force a reload from the EEPROM if necessary */
1476 if (hw->mac_type == e1000_igb) {
1478 reg = E1000_READ_REG(hw, STATUS);
1479 if (reg & E1000_STATUS_PF_RST_DONE)
1480 DEBUGOUT("PF OK\n");
1481 reg = E1000_READ_REG(hw, I210_EECD);
1482 if (reg & E1000_EECD_AUTO_RD)
1483 DEBUGOUT("EEC OK\n");
1484 } else if (hw->mac_type < e1000_82540) {
1485 /* Wait for reset to complete */
1487 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1488 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1489 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1490 E1000_WRITE_FLUSH(hw);
1491 /* Wait for EEPROM reload */
1494 /* Wait for EEPROM reload (it happens automatically) */
1496 /* Dissable HW ARPs on ASF enabled adapters */
1497 manc = E1000_READ_REG(hw, MANC);
1498 manc &= ~(E1000_MANC_ARP_EN);
1499 E1000_WRITE_REG(hw, MANC, manc);
1502 /* Clear interrupt mask to stop board from generating interrupts */
1503 DEBUGOUT("Masking off all interrupts\n");
1504 if (hw->mac_type == e1000_igb)
1505 E1000_WRITE_REG(hw, I210_IAM, 0);
1506 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1508 /* Clear any pending interrupt events. */
1509 E1000_READ_REG(hw, ICR);
1511 /* If MWI was previously enabled, reenable it. */
1512 if (hw->mac_type == e1000_82542_rev2_0) {
1513 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1515 if (hw->mac_type != e1000_igb)
1516 E1000_WRITE_REG(hw, PBA, pba);
1519 /******************************************************************************
1521 * Initialize a number of hardware-dependent bits
1523 * hw: Struct containing variables accessed by shared code
1525 * This function contains hardware limitation workarounds for PCI-E adapters
1527 *****************************************************************************/
1529 e1000_initialize_hardware_bits(struct e1000_hw *hw)
1531 if ((hw->mac_type >= e1000_82571) &&
1532 (!hw->initialize_hw_bits_disable)) {
1533 /* Settings common to all PCI-express silicon */
1534 uint32_t reg_ctrl, reg_ctrl_ext;
1535 uint32_t reg_tarc0, reg_tarc1;
1537 uint32_t reg_txdctl, reg_txdctl1;
1539 /* link autonegotiation/sync workarounds */
1540 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1541 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1543 /* Enable not-done TX descriptor counting */
1544 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1545 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1546 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1548 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1549 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1550 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1553 if (hw->mac_type == e1000_igb)
1556 switch (hw->mac_type) {
1559 /* Clear PHY TX compatible mode bits */
1560 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1561 reg_tarc1 &= ~((1 << 30)|(1 << 29));
1563 /* link autonegotiation/sync workarounds */
1564 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1566 /* TX ring control fixes */
1567 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1569 /* Multiple read bit is reversed polarity */
1570 reg_tctl = E1000_READ_REG(hw, TCTL);
1571 if (reg_tctl & E1000_TCTL_MULR)
1572 reg_tarc1 &= ~(1 << 28);
1574 reg_tarc1 |= (1 << 28);
1576 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1580 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1581 reg_ctrl_ext &= ~(1 << 23);
1582 reg_ctrl_ext |= (1 << 22);
1584 /* TX byte count fix */
1585 reg_ctrl = E1000_READ_REG(hw, CTRL);
1586 reg_ctrl &= ~(1 << 29);
1588 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1589 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1591 case e1000_80003es2lan:
1592 /* improve small packet performace for fiber/serdes */
1593 if ((hw->media_type == e1000_media_type_fiber)
1594 || (hw->media_type ==
1595 e1000_media_type_internal_serdes)) {
1596 reg_tarc0 &= ~(1 << 20);
1599 /* Multiple read bit is reversed polarity */
1600 reg_tctl = E1000_READ_REG(hw, TCTL);
1601 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1602 if (reg_tctl & E1000_TCTL_MULR)
1603 reg_tarc1 &= ~(1 << 28);
1605 reg_tarc1 |= (1 << 28);
1607 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1610 /* Reduce concurrent DMA requests to 3 from 4 */
1611 if ((hw->revision_id < 3) ||
1612 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1613 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1614 reg_tarc0 |= ((1 << 29)|(1 << 28));
1616 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1617 reg_ctrl_ext |= (1 << 22);
1618 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1620 /* workaround TX hang with TSO=on */
1621 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1623 /* Multiple read bit is reversed polarity */
1624 reg_tctl = E1000_READ_REG(hw, TCTL);
1625 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1626 if (reg_tctl & E1000_TCTL_MULR)
1627 reg_tarc1 &= ~(1 << 28);
1629 reg_tarc1 |= (1 << 28);
1631 /* workaround TX hang with TSO=on */
1632 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1634 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1640 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1644 /******************************************************************************
1645 * Performs basic configuration of the adapter.
1647 * hw - Struct containing variables accessed by shared code
1649 * Assumes that the controller has previously been reset and is in a
1650 * post-reset uninitialized state. Initializes the receive address registers,
1651 * multicast table, and VLAN filter table. Calls routines to setup link
1652 * configuration and flow control settings. Clears all on-chip counters. Leaves
1653 * the transmit and receive units disabled and uninitialized.
1654 *****************************************************************************/
1656 e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
1661 uint16_t pcix_cmd_word;
1662 uint16_t pcix_stat_hi_word;
1664 uint16_t stat_mmrbc;
1669 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1670 if ((hw->mac_type == e1000_ich8lan) &&
1671 ((hw->revision_id < 3) ||
1672 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1673 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1674 reg_data = E1000_READ_REG(hw, STATUS);
1675 reg_data &= ~0x80000000;
1676 E1000_WRITE_REG(hw, STATUS, reg_data);
1678 /* Do not need initialize Identification LED */
1680 /* Set the media type and TBI compatibility */
1681 e1000_set_media_type(hw);
1683 /* Must be called after e1000_set_media_type
1684 * because media_type is used */
1685 e1000_initialize_hardware_bits(hw);
1687 /* Disabling VLAN filtering. */
1688 DEBUGOUT("Initializing the IEEE VLAN\n");
1689 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1690 if (hw->mac_type != e1000_ich8lan) {
1691 if (hw->mac_type < e1000_82545_rev_3)
1692 E1000_WRITE_REG(hw, VET, 0);
1693 e1000_clear_vfta(hw);
1696 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1697 if (hw->mac_type == e1000_82542_rev2_0) {
1698 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1699 pci_write_config_word(hw->pdev, PCI_COMMAND,
1701 pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1702 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1703 E1000_WRITE_FLUSH(hw);
1707 /* Setup the receive address. This involves initializing all of the Receive
1708 * Address Registers (RARs 0 - 15).
1710 e1000_init_rx_addrs(hw, enetaddr);
1712 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1713 if (hw->mac_type == e1000_82542_rev2_0) {
1714 E1000_WRITE_REG(hw, RCTL, 0);
1715 E1000_WRITE_FLUSH(hw);
1717 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1720 /* Zero out the Multicast HASH table */
1721 DEBUGOUT("Zeroing the MTA\n");
1722 mta_size = E1000_MC_TBL_SIZE;
1723 if (hw->mac_type == e1000_ich8lan)
1724 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1725 for (i = 0; i < mta_size; i++) {
1726 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1727 /* use write flush to prevent Memory Write Block (MWB) from
1728 * occuring when accessing our register space */
1729 E1000_WRITE_FLUSH(hw);
1732 /* Set the PCI priority bit correctly in the CTRL register. This
1733 * determines if the adapter gives priority to receives, or if it
1734 * gives equal priority to transmits and receives. Valid only on
1735 * 82542 and 82543 silicon.
1737 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
1738 ctrl = E1000_READ_REG(hw, CTRL);
1739 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1742 switch (hw->mac_type) {
1743 case e1000_82545_rev_3:
1744 case e1000_82546_rev_3:
1748 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1749 if (hw->bus_type == e1000_bus_type_pcix) {
1750 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1752 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1753 &pcix_stat_hi_word);
1755 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1756 PCIX_COMMAND_MMRBC_SHIFT;
1758 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1759 PCIX_STATUS_HI_MMRBC_SHIFT;
1760 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1761 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1762 if (cmd_mmrbc > stat_mmrbc) {
1763 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1764 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1765 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1772 /* More time needed for PHY to initialize */
1773 if (hw->mac_type == e1000_ich8lan)
1775 if (hw->mac_type == e1000_igb)
1778 /* Call a subroutine to configure the link and setup flow control. */
1779 ret_val = e1000_setup_link(hw);
1781 /* Set the transmit descriptor write-back policy */
1782 if (hw->mac_type > e1000_82544) {
1783 ctrl = E1000_READ_REG(hw, TXDCTL);
1785 (ctrl & ~E1000_TXDCTL_WTHRESH) |
1786 E1000_TXDCTL_FULL_TX_DESC_WB;
1787 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1790 /* Set the receive descriptor write back policy */
1791 if (hw->mac_type >= e1000_82571) {
1792 ctrl = E1000_READ_REG(hw, RXDCTL);
1794 (ctrl & ~E1000_RXDCTL_WTHRESH) |
1795 E1000_RXDCTL_FULL_RX_DESC_WB;
1796 E1000_WRITE_REG(hw, RXDCTL, ctrl);
1799 switch (hw->mac_type) {
1802 case e1000_80003es2lan:
1803 /* Enable retransmit on late collisions */
1804 reg_data = E1000_READ_REG(hw, TCTL);
1805 reg_data |= E1000_TCTL_RTLC;
1806 E1000_WRITE_REG(hw, TCTL, reg_data);
1808 /* Configure Gigabit Carry Extend Padding */
1809 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1810 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1811 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1812 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1814 /* Configure Transmit Inter-Packet Gap */
1815 reg_data = E1000_READ_REG(hw, TIPG);
1816 reg_data &= ~E1000_TIPG_IPGT_MASK;
1817 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1818 E1000_WRITE_REG(hw, TIPG, reg_data);
1820 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1821 reg_data &= ~0x00100000;
1822 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1827 ctrl = E1000_READ_REG(hw, TXDCTL1);
1828 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
1829 | E1000_TXDCTL_FULL_TX_DESC_WB;
1830 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1834 reg_data = E1000_READ_REG(hw, GCR);
1835 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1836 E1000_WRITE_REG(hw, GCR, reg_data);
1842 /* Clear all of the statistics registers (clear on read). It is
1843 * important that we do this after we have tried to establish link
1844 * because the symbol error count will increment wildly if there
1847 e1000_clear_hw_cntrs(hw);
1849 /* ICH8 No-snoop bits are opposite polarity.
1850 * Set to snoop by default after reset. */
1851 if (hw->mac_type == e1000_ich8lan)
1852 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1855 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1856 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1857 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1858 /* Relaxed ordering must be disabled to avoid a parity
1859 * error crash in a PCI slot. */
1860 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1861 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1867 /******************************************************************************
1868 * Configures flow control and link settings.
1870 * hw - Struct containing variables accessed by shared code
1872 * Determines which flow control settings to use. Calls the apropriate media-
1873 * specific link configuration function. Configures the flow control settings.
1874 * Assuming the adapter has a valid link partner, a valid link should be
1875 * established. Assumes the hardware has previously been reset and the
1876 * transmitter and receiver are not enabled.
1877 *****************************************************************************/
1879 e1000_setup_link(struct e1000_hw *hw)
1882 #ifndef CONFIG_E1000_NO_NVM
1884 uint16_t eeprom_data;
1889 /* In the case of the phy reset being blocked, we already have a link.
1890 * We do not have to set it up again. */
1891 if (e1000_check_phy_reset_block(hw))
1892 return E1000_SUCCESS;
1894 #ifndef CONFIG_E1000_NO_NVM
1895 /* Read and store word 0x0F of the EEPROM. This word contains bits
1896 * that determine the hardware's default PAUSE (flow control) mode,
1897 * a bit that determines whether the HW defaults to enabling or
1898 * disabling auto-negotiation, and the direction of the
1899 * SW defined pins. If there is no SW over-ride of the flow
1900 * control setting, then the variable hw->fc will
1901 * be initialized based on a value in the EEPROM.
1903 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
1904 &eeprom_data) < 0) {
1905 DEBUGOUT("EEPROM Read Error\n");
1906 return -E1000_ERR_EEPROM;
1909 if (hw->fc == e1000_fc_default) {
1910 switch (hw->mac_type) {
1915 hw->fc = e1000_fc_full;
1918 #ifndef CONFIG_E1000_NO_NVM
1919 ret_val = e1000_read_eeprom(hw,
1920 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1922 DEBUGOUT("EEPROM Read Error\n");
1923 return -E1000_ERR_EEPROM;
1925 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1926 hw->fc = e1000_fc_none;
1927 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1928 EEPROM_WORD0F_ASM_DIR)
1929 hw->fc = e1000_fc_tx_pause;
1932 hw->fc = e1000_fc_full;
1937 /* We want to save off the original Flow Control configuration just
1938 * in case we get disconnected and then reconnected into a different
1939 * hub or switch with different Flow Control capabilities.
1941 if (hw->mac_type == e1000_82542_rev2_0)
1942 hw->fc &= (~e1000_fc_tx_pause);
1944 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1945 hw->fc &= (~e1000_fc_rx_pause);
1947 hw->original_fc = hw->fc;
1949 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
1951 #ifndef CONFIG_E1000_NO_NVM
1952 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1953 * polarity value for the SW controlled pins, and setup the
1954 * Extended Device Control reg with that info.
1955 * This is needed because one of the SW controlled pins is used for
1956 * signal detection. So this should be done before e1000_setup_pcs_link()
1957 * or e1000_phy_setup() is called.
1959 if (hw->mac_type == e1000_82543) {
1960 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1962 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1966 /* Call the necessary subroutine to configure the link. */
1967 ret_val = (hw->media_type == e1000_media_type_fiber) ?
1968 e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw);
1973 /* Initialize the flow control address, type, and PAUSE timer
1974 * registers to their default values. This is done even if flow
1975 * control is disabled, because it does not hurt anything to
1976 * initialize these registers.
1978 DEBUGOUT("Initializing the Flow Control address, type"
1979 "and timer regs\n");
1981 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1982 if (hw->mac_type != e1000_ich8lan) {
1983 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1984 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1985 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1988 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1990 /* Set the flow control receive threshold registers. Normally,
1991 * these registers will be set to a default threshold that may be
1992 * adjusted later by the driver's runtime code. However, if the
1993 * ability to transmit pause frames in not enabled, then these
1994 * registers will be set to 0.
1996 if (!(hw->fc & e1000_fc_tx_pause)) {
1997 E1000_WRITE_REG(hw, FCRTL, 0);
1998 E1000_WRITE_REG(hw, FCRTH, 0);
2000 /* We need to set up the Receive Threshold high and low water marks
2001 * as well as (optionally) enabling the transmission of XON frames.
2003 if (hw->fc_send_xon) {
2004 E1000_WRITE_REG(hw, FCRTL,
2005 (hw->fc_low_water | E1000_FCRTL_XONE));
2006 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2008 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
2009 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
2015 /******************************************************************************
2016 * Sets up link for a fiber based adapter
2018 * hw - Struct containing variables accessed by shared code
2020 * Manipulates Physical Coding Sublayer functions in order to configure
2021 * link. Assumes the hardware has been previously reset and the transmitter
2022 * and receiver are not enabled.
2023 *****************************************************************************/
2025 e1000_setup_fiber_link(struct e1000_hw *hw)
2035 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
2036 * set when the optics detect a signal. On older adapters, it will be
2037 * cleared when there is a signal
2039 ctrl = E1000_READ_REG(hw, CTRL);
2040 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
2041 signal = E1000_CTRL_SWDPIN1;
2045 printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal,
2047 /* Take the link out of reset */
2048 ctrl &= ~(E1000_CTRL_LRST);
2050 e1000_config_collision_dist(hw);
2052 /* Check for a software override of the flow control settings, and setup
2053 * the device accordingly. If auto-negotiation is enabled, then software
2054 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
2055 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
2056 * auto-negotiation is disabled, then software will have to manually
2057 * configure the two flow control enable bits in the CTRL register.
2059 * The possible values of the "fc" parameter are:
2060 * 0: Flow control is completely disabled
2061 * 1: Rx flow control is enabled (we can receive pause frames, but
2062 * not send pause frames).
2063 * 2: Tx flow control is enabled (we can send pause frames but we do
2064 * not support receiving pause frames).
2065 * 3: Both Rx and TX flow control (symmetric) are enabled.
2069 /* Flow control is completely disabled by a software over-ride. */
2070 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
2072 case e1000_fc_rx_pause:
2073 /* RX Flow control is enabled and TX Flow control is disabled by a
2074 * software over-ride. Since there really isn't a way to advertise
2075 * that we are capable of RX Pause ONLY, we will advertise that we
2076 * support both symmetric and asymmetric RX PAUSE. Later, we will
2077 * disable the adapter's ability to send PAUSE frames.
2079 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2081 case e1000_fc_tx_pause:
2082 /* TX Flow control is enabled, and RX Flow control is disabled, by a
2083 * software over-ride.
2085 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
2088 /* Flow control (both RX and TX) is enabled by a software over-ride. */
2089 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2092 DEBUGOUT("Flow control param set incorrectly\n");
2093 return -E1000_ERR_CONFIG;
2097 /* Since auto-negotiation is enabled, take the link out of reset (the link
2098 * will be in reset, because we previously reset the chip). This will
2099 * restart auto-negotiation. If auto-neogtiation is successful then the
2100 * link-up status bit will be set and the flow control enable bits (RFCE
2101 * and TFCE) will be set according to their negotiated value.
2103 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2105 E1000_WRITE_REG(hw, TXCW, txcw);
2106 E1000_WRITE_REG(hw, CTRL, ctrl);
2107 E1000_WRITE_FLUSH(hw);
2112 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
2113 * indication in the Device Status Register. Time-out if a link isn't
2114 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
2115 * less than 500 milliseconds even if the other end is doing it in SW).
2117 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2118 DEBUGOUT("Looking for Link\n");
2119 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2121 status = E1000_READ_REG(hw, STATUS);
2122 if (status & E1000_STATUS_LU)
2125 if (i == (LINK_UP_TIMEOUT / 10)) {
2126 /* AutoNeg failed to achieve a link, so we'll call
2127 * e1000_check_for_link. This routine will force the link up if we
2128 * detect a signal. This will allow us to communicate with
2129 * non-autonegotiating link partners.
2131 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2132 hw->autoneg_failed = 1;
2133 ret_val = e1000_check_for_link(hw);
2135 DEBUGOUT("Error while checking for link\n");
2138 hw->autoneg_failed = 0;
2140 hw->autoneg_failed = 0;
2141 DEBUGOUT("Valid Link Found\n");
2144 DEBUGOUT("No Signal Detected\n");
2145 return -E1000_ERR_NOLINK;
2150 /******************************************************************************
2151 * Make sure we have a valid PHY and change PHY mode before link setup.
2153 * hw - Struct containing variables accessed by shared code
2154 ******************************************************************************/
2156 e1000_copper_link_preconfig(struct e1000_hw *hw)
2164 ctrl = E1000_READ_REG(hw, CTRL);
2165 /* With 82543, we need to force speed and duplex on the MAC equal to what
2166 * the PHY speed and duplex configuration is. In addition, we need to
2167 * perform a hardware reset on the PHY to take it out of reset.
2169 if (hw->mac_type > e1000_82543) {
2170 ctrl |= E1000_CTRL_SLU;
2171 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2172 E1000_WRITE_REG(hw, CTRL, ctrl);
2174 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2176 E1000_WRITE_REG(hw, CTRL, ctrl);
2177 ret_val = e1000_phy_hw_reset(hw);
2182 /* Make sure we have a valid PHY */
2183 ret_val = e1000_detect_gig_phy(hw);
2185 DEBUGOUT("Error, did not detect valid phy.\n");
2188 DEBUGOUT("Phy ID = %x\n", hw->phy_id);
2190 /* Set PHY to class A mode (if necessary) */
2191 ret_val = e1000_set_phy_mode(hw);
2194 if ((hw->mac_type == e1000_82545_rev_3) ||
2195 (hw->mac_type == e1000_82546_rev_3)) {
2196 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2198 phy_data |= 0x00000008;
2199 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2203 if (hw->mac_type <= e1000_82543 ||
2204 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2205 hw->mac_type == e1000_82541_rev_2
2206 || hw->mac_type == e1000_82547_rev_2)
2207 hw->phy_reset_disable = false;
2209 return E1000_SUCCESS;
2212 /*****************************************************************************
2214 * This function sets the lplu state according to the active flag. When
2215 * activating lplu this function also disables smart speed and vise versa.
2216 * lplu will not be activated unless the device autonegotiation advertisment
2217 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2218 * hw: Struct containing variables accessed by shared code
2219 * active - true to enable lplu false to disable lplu.
2221 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2222 * E1000_SUCCESS at any other case.
2224 ****************************************************************************/
2227 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
2229 uint32_t phy_ctrl = 0;
2234 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2235 && hw->phy_type != e1000_phy_igp_3)
2236 return E1000_SUCCESS;
2238 /* During driver activity LPLU should not be used or it will attain link
2239 * from the lowest speeds starting from 10Mbps. The capability is used
2240 * for Dx transitions and states */
2241 if (hw->mac_type == e1000_82541_rev_2
2242 || hw->mac_type == e1000_82547_rev_2) {
2243 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2247 } else if (hw->mac_type == e1000_ich8lan) {
2248 /* MAC writes into PHY register based on the state transition
2249 * and start auto-negotiation. SW driver can overwrite the
2250 * settings in CSR PHY power control E1000_PHY_CTRL register. */
2251 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2253 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2260 if (hw->mac_type == e1000_82541_rev_2 ||
2261 hw->mac_type == e1000_82547_rev_2) {
2262 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2263 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2268 if (hw->mac_type == e1000_ich8lan) {
2269 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2270 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2272 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2273 ret_val = e1000_write_phy_reg(hw,
2274 IGP02E1000_PHY_POWER_MGMT, phy_data);
2280 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2281 * Dx states where the power conservation is most important. During
2282 * driver activity we should enable SmartSpeed, so performance is
2284 if (hw->smart_speed == e1000_smart_speed_on) {
2285 ret_val = e1000_read_phy_reg(hw,
2286 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2290 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2291 ret_val = e1000_write_phy_reg(hw,
2292 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2295 } else if (hw->smart_speed == e1000_smart_speed_off) {
2296 ret_val = e1000_read_phy_reg(hw,
2297 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2301 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2302 ret_val = e1000_write_phy_reg(hw,
2303 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2308 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2309 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2310 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2312 if (hw->mac_type == e1000_82541_rev_2 ||
2313 hw->mac_type == e1000_82547_rev_2) {
2314 phy_data |= IGP01E1000_GMII_FLEX_SPD;
2315 ret_val = e1000_write_phy_reg(hw,
2316 IGP01E1000_GMII_FIFO, phy_data);
2320 if (hw->mac_type == e1000_ich8lan) {
2321 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2322 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2324 phy_data |= IGP02E1000_PM_D3_LPLU;
2325 ret_val = e1000_write_phy_reg(hw,
2326 IGP02E1000_PHY_POWER_MGMT, phy_data);
2332 /* When LPLU is enabled we should disable SmartSpeed */
2333 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2338 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2339 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2344 return E1000_SUCCESS;
2347 /*****************************************************************************
2349 * This function sets the lplu d0 state according to the active flag. When
2350 * activating lplu this function also disables smart speed and vise versa.
2351 * lplu will not be activated unless the device autonegotiation advertisment
2352 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2353 * hw: Struct containing variables accessed by shared code
2354 * active - true to enable lplu false to disable lplu.
2356 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2357 * E1000_SUCCESS at any other case.
2359 ****************************************************************************/
2362 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2364 uint32_t phy_ctrl = 0;
2369 if (hw->mac_type <= e1000_82547_rev_2)
2370 return E1000_SUCCESS;
2372 if (hw->mac_type == e1000_ich8lan) {
2373 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2374 } else if (hw->mac_type == e1000_igb) {
2375 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL);
2377 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2384 if (hw->mac_type == e1000_ich8lan) {
2385 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2386 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2387 } else if (hw->mac_type == e1000_igb) {
2388 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2389 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2391 phy_data &= ~IGP02E1000_PM_D0_LPLU;
2392 ret_val = e1000_write_phy_reg(hw,
2393 IGP02E1000_PHY_POWER_MGMT, phy_data);
2398 if (hw->mac_type == e1000_igb)
2399 return E1000_SUCCESS;
2401 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2402 * Dx states where the power conservation is most important. During
2403 * driver activity we should enable SmartSpeed, so performance is
2405 if (hw->smart_speed == e1000_smart_speed_on) {
2406 ret_val = e1000_read_phy_reg(hw,
2407 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2411 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2412 ret_val = e1000_write_phy_reg(hw,
2413 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2416 } else if (hw->smart_speed == e1000_smart_speed_off) {
2417 ret_val = e1000_read_phy_reg(hw,
2418 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2422 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2423 ret_val = e1000_write_phy_reg(hw,
2424 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2432 if (hw->mac_type == e1000_ich8lan) {
2433 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2434 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2435 } else if (hw->mac_type == e1000_igb) {
2436 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2437 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
2439 phy_data |= IGP02E1000_PM_D0_LPLU;
2440 ret_val = e1000_write_phy_reg(hw,
2441 IGP02E1000_PHY_POWER_MGMT, phy_data);
2446 if (hw->mac_type == e1000_igb)
2447 return E1000_SUCCESS;
2449 /* When LPLU is enabled we should disable SmartSpeed */
2450 ret_val = e1000_read_phy_reg(hw,
2451 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2455 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2456 ret_val = e1000_write_phy_reg(hw,
2457 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2462 return E1000_SUCCESS;
2465 /********************************************************************
2466 * Copper link setup for e1000_phy_igp series.
2468 * hw - Struct containing variables accessed by shared code
2469 *********************************************************************/
2471 e1000_copper_link_igp_setup(struct e1000_hw *hw)
2479 if (hw->phy_reset_disable)
2480 return E1000_SUCCESS;
2482 ret_val = e1000_phy_reset(hw);
2484 DEBUGOUT("Error Resetting the PHY\n");
2488 /* Wait 15ms for MAC to configure PHY from eeprom settings */
2490 if (hw->mac_type != e1000_ich8lan) {
2491 /* Configure activity LED after PHY reset */
2492 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2493 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2494 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2495 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2498 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2499 if (hw->phy_type == e1000_phy_igp) {
2500 /* disable lplu d3 during driver init */
2501 ret_val = e1000_set_d3_lplu_state(hw, false);
2503 DEBUGOUT("Error Disabling LPLU D3\n");
2508 /* disable lplu d0 during driver init */
2509 ret_val = e1000_set_d0_lplu_state(hw, false);
2511 DEBUGOUT("Error Disabling LPLU D0\n");
2514 /* Configure mdi-mdix settings */
2515 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2519 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2520 hw->dsp_config_state = e1000_dsp_config_disabled;
2521 /* Force MDI for earlier revs of the IGP PHY */
2522 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2523 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2527 hw->dsp_config_state = e1000_dsp_config_enabled;
2528 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2532 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2535 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2539 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2543 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2547 /* set auto-master slave resolution settings */
2549 e1000_ms_type phy_ms_setting = hw->master_slave;
2551 if (hw->ffe_config_state == e1000_ffe_config_active)
2552 hw->ffe_config_state = e1000_ffe_config_enabled;
2554 if (hw->dsp_config_state == e1000_dsp_config_activated)
2555 hw->dsp_config_state = e1000_dsp_config_enabled;
2557 /* when autonegotiation advertisment is only 1000Mbps then we
2558 * should disable SmartSpeed and enable Auto MasterSlave
2559 * resolution as hardware default. */
2560 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2561 /* Disable SmartSpeed */
2562 ret_val = e1000_read_phy_reg(hw,
2563 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2566 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2567 ret_val = e1000_write_phy_reg(hw,
2568 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2571 /* Set auto Master/Slave resolution process */
2572 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2576 phy_data &= ~CR_1000T_MS_ENABLE;
2577 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2583 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2587 /* load defaults for future use */
2588 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2589 ((phy_data & CR_1000T_MS_VALUE) ?
2590 e1000_ms_force_master :
2591 e1000_ms_force_slave) :
2594 switch (phy_ms_setting) {
2595 case e1000_ms_force_master:
2596 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2598 case e1000_ms_force_slave:
2599 phy_data |= CR_1000T_MS_ENABLE;
2600 phy_data &= ~(CR_1000T_MS_VALUE);
2603 phy_data &= ~CR_1000T_MS_ENABLE;
2607 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2612 return E1000_SUCCESS;
2615 /*****************************************************************************
2616 * This function checks the mode of the firmware.
2618 * returns - true when the mode is IAMT or false.
2619 ****************************************************************************/
2621 e1000_check_mng_mode(struct e1000_hw *hw)
2626 fwsm = E1000_READ_REG(hw, FWSM);
2628 if (hw->mac_type == e1000_ich8lan) {
2629 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2630 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2632 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2633 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2640 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2642 uint16_t swfw = E1000_SWFW_PHY0_SM;
2646 if (e1000_is_second_port(hw))
2647 swfw = E1000_SWFW_PHY1_SM;
2649 if (e1000_swfw_sync_acquire(hw, swfw))
2650 return -E1000_ERR_SWFW_SYNC;
2652 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2653 & E1000_KUMCTRLSTA_OFFSET) | data;
2654 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2657 return E1000_SUCCESS;
2661 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2663 uint16_t swfw = E1000_SWFW_PHY0_SM;
2667 if (e1000_is_second_port(hw))
2668 swfw = E1000_SWFW_PHY1_SM;
2670 if (e1000_swfw_sync_acquire(hw, swfw)) {
2671 debug("%s[%i]\n", __func__, __LINE__);
2672 return -E1000_ERR_SWFW_SYNC;
2675 /* Write register address */
2676 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2677 E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2678 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2681 /* Read the data returned */
2682 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2683 *data = (uint16_t)reg_val;
2685 return E1000_SUCCESS;
2688 /********************************************************************
2689 * Copper link setup for e1000_phy_gg82563 series.
2691 * hw - Struct containing variables accessed by shared code
2692 *********************************************************************/
2694 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2702 if (!hw->phy_reset_disable) {
2703 /* Enable CRS on TX for half-duplex operation. */
2704 ret_val = e1000_read_phy_reg(hw,
2705 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2709 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2710 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2711 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2713 ret_val = e1000_write_phy_reg(hw,
2714 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2719 * MDI/MDI-X = 0 (default)
2720 * 0 - Auto for all speeds
2723 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2725 ret_val = e1000_read_phy_reg(hw,
2726 GG82563_PHY_SPEC_CTRL, &phy_data);
2730 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2734 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2737 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2741 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2746 * disable_polarity_correction = 0 (default)
2747 * Automatic Correction for Reversed Cable Polarity
2751 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2752 ret_val = e1000_write_phy_reg(hw,
2753 GG82563_PHY_SPEC_CTRL, phy_data);
2758 /* SW Reset the PHY so all changes take effect */
2759 ret_val = e1000_phy_reset(hw);
2761 DEBUGOUT("Error Resetting the PHY\n");
2764 } /* phy_reset_disable */
2766 if (hw->mac_type == e1000_80003es2lan) {
2767 /* Bypass RX and TX FIFO's */
2768 ret_val = e1000_write_kmrn_reg(hw,
2769 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2770 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2771 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2775 ret_val = e1000_read_phy_reg(hw,
2776 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2780 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2781 ret_val = e1000_write_phy_reg(hw,
2782 GG82563_PHY_SPEC_CTRL_2, phy_data);
2787 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2788 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2789 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2791 ret_val = e1000_read_phy_reg(hw,
2792 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2796 /* Do not init these registers when the HW is in IAMT mode, since the
2797 * firmware will have already initialized them. We only initialize
2798 * them if the HW is not in IAMT mode.
2800 if (e1000_check_mng_mode(hw) == false) {
2801 /* Enable Electrical Idle on the PHY */
2802 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2803 ret_val = e1000_write_phy_reg(hw,
2804 GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2808 ret_val = e1000_read_phy_reg(hw,
2809 GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2813 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2814 ret_val = e1000_write_phy_reg(hw,
2815 GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2821 /* Workaround: Disable padding in Kumeran interface in the MAC
2822 * and in the PHY to avoid CRC errors.
2824 ret_val = e1000_read_phy_reg(hw,
2825 GG82563_PHY_INBAND_CTRL, &phy_data);
2828 phy_data |= GG82563_ICR_DIS_PADDING;
2829 ret_val = e1000_write_phy_reg(hw,
2830 GG82563_PHY_INBAND_CTRL, phy_data);
2834 return E1000_SUCCESS;
2837 /********************************************************************
2838 * Copper link setup for e1000_phy_m88 series.
2840 * hw - Struct containing variables accessed by shared code
2841 *********************************************************************/
2843 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
2850 if (hw->phy_reset_disable)
2851 return E1000_SUCCESS;
2853 /* Enable CRS on TX. This must be set for half-duplex operation. */
2854 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2858 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2861 * MDI/MDI-X = 0 (default)
2862 * 0 - Auto for all speeds
2865 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2867 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2871 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
2874 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
2877 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
2881 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
2886 * disable_polarity_correction = 0 (default)
2887 * Automatic Correction for Reversed Cable Polarity
2891 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
2892 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2896 if (hw->phy_revision < M88E1011_I_REV_4) {
2897 /* Force TX_CLK in the Extended PHY Specific Control Register
2900 ret_val = e1000_read_phy_reg(hw,
2901 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2905 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2907 if ((hw->phy_revision == E1000_REVISION_2) &&
2908 (hw->phy_id == M88E1111_I_PHY_ID)) {
2909 /* Vidalia Phy, set the downshift counter to 5x */
2910 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
2911 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
2912 ret_val = e1000_write_phy_reg(hw,
2913 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2917 /* Configure Master and Slave downshift values */
2918 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
2919 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
2920 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
2921 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
2922 ret_val = e1000_write_phy_reg(hw,
2923 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2929 /* SW Reset the PHY so all changes take effect */
2930 ret_val = e1000_phy_reset(hw);
2932 DEBUGOUT("Error Resetting the PHY\n");
2936 return E1000_SUCCESS;
2939 /********************************************************************
2940 * Setup auto-negotiation and flow control advertisements,
2941 * and then perform auto-negotiation.
2943 * hw - Struct containing variables accessed by shared code
2944 *********************************************************************/
2946 e1000_copper_link_autoneg(struct e1000_hw *hw)
2953 /* Perform some bounds checking on the hw->autoneg_advertised
2954 * parameter. If this variable is zero, then set it to the default.
2956 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
2958 /* If autoneg_advertised is zero, we assume it was not defaulted
2959 * by the calling code so we set to advertise full capability.
2961 if (hw->autoneg_advertised == 0)
2962 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
2964 /* IFE phy only supports 10/100 */
2965 if (hw->phy_type == e1000_phy_ife)
2966 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
2968 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
2969 ret_val = e1000_phy_setup_autoneg(hw);
2971 DEBUGOUT("Error Setting up Auto-Negotiation\n");
2974 DEBUGOUT("Restarting Auto-Neg\n");
2976 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
2977 * the Auto Neg Restart bit in the PHY control register.
2979 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2983 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
2984 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2988 /* Does the user want to wait for Auto-Neg to complete here, or
2989 * check at a later time (for example, callback routine).
2991 /* If we do not wait for autonegtation to complete I
2992 * do not see a valid link status.
2993 * wait_autoneg_complete = 1 .
2995 if (hw->wait_autoneg_complete) {
2996 ret_val = e1000_wait_autoneg(hw);
2998 DEBUGOUT("Error while waiting for autoneg"
3004 hw->get_link_status = true;
3006 return E1000_SUCCESS;
3009 /******************************************************************************
3010 * Config the MAC and the PHY after link is up.
3011 * 1) Set up the MAC to the current PHY speed/duplex
3012 * if we are on 82543. If we
3013 * are on newer silicon, we only need to configure
3014 * collision distance in the Transmit Control Register.
3015 * 2) Set up flow control on the MAC to that established with
3017 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
3019 * hw - Struct containing variables accessed by shared code
3020 ******************************************************************************/
3022 e1000_copper_link_postconfig(struct e1000_hw *hw)
3027 if (hw->mac_type >= e1000_82544) {
3028 e1000_config_collision_dist(hw);
3030 ret_val = e1000_config_mac_to_phy(hw);
3032 DEBUGOUT("Error configuring MAC to PHY settings\n");
3036 ret_val = e1000_config_fc_after_link_up(hw);
3038 DEBUGOUT("Error Configuring Flow Control\n");
3041 return E1000_SUCCESS;
3044 /******************************************************************************
3045 * Detects which PHY is present and setup the speed and duplex
3047 * hw - Struct containing variables accessed by shared code
3048 ******************************************************************************/
3050 e1000_setup_copper_link(struct e1000_hw *hw)
3059 switch (hw->mac_type) {
3060 case e1000_80003es2lan:
3062 /* Set the mac to wait the maximum time between each
3063 * iteration and increase the max iterations when
3064 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
3065 ret_val = e1000_write_kmrn_reg(hw,
3066 GG82563_REG(0x34, 4), 0xFFFF);
3069 ret_val = e1000_read_kmrn_reg(hw,
3070 GG82563_REG(0x34, 9), ®_data);
3074 ret_val = e1000_write_kmrn_reg(hw,
3075 GG82563_REG(0x34, 9), reg_data);
3082 /* Check if it is a valid PHY and set PHY mode if necessary. */
3083 ret_val = e1000_copper_link_preconfig(hw);
3086 switch (hw->mac_type) {
3087 case e1000_80003es2lan:
3088 /* Kumeran registers are written-only */
3090 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
3091 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
3092 ret_val = e1000_write_kmrn_reg(hw,
3093 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3101 if (hw->phy_type == e1000_phy_igp ||
3102 hw->phy_type == e1000_phy_igp_3 ||
3103 hw->phy_type == e1000_phy_igp_2) {
3104 ret_val = e1000_copper_link_igp_setup(hw);
3107 } else if (hw->phy_type == e1000_phy_m88 ||
3108 hw->phy_type == e1000_phy_igb) {
3109 ret_val = e1000_copper_link_mgp_setup(hw);
3112 } else if (hw->phy_type == e1000_phy_gg82563) {
3113 ret_val = e1000_copper_link_ggp_setup(hw);
3119 /* Setup autoneg and flow control advertisement
3120 * and perform autonegotiation */
3121 ret_val = e1000_copper_link_autoneg(hw);
3125 /* Check link status. Wait up to 100 microseconds for link to become
3128 for (i = 0; i < 10; i++) {
3129 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3132 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3136 if (phy_data & MII_SR_LINK_STATUS) {
3137 /* Config the MAC and PHY after link is up */
3138 ret_val = e1000_copper_link_postconfig(hw);
3142 DEBUGOUT("Valid link established!!!\n");
3143 return E1000_SUCCESS;
3148 DEBUGOUT("Unable to establish link!!!\n");
3149 return E1000_SUCCESS;
3152 /******************************************************************************
3153 * Configures PHY autoneg and flow control advertisement settings
3155 * hw - Struct containing variables accessed by shared code
3156 ******************************************************************************/
3158 e1000_phy_setup_autoneg(struct e1000_hw *hw)
3161 uint16_t mii_autoneg_adv_reg;
3162 uint16_t mii_1000t_ctrl_reg;
3166 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3167 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3171 if (hw->phy_type != e1000_phy_ife) {
3172 /* Read the MII 1000Base-T Control Register (Address 9). */
3173 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3174 &mii_1000t_ctrl_reg);
3178 mii_1000t_ctrl_reg = 0;
3180 /* Need to parse both autoneg_advertised and fc and set up
3181 * the appropriate PHY registers. First we will parse for
3182 * autoneg_advertised software override. Since we can advertise
3183 * a plethora of combinations, we need to check each bit
3187 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3188 * Advertisement Register (Address 4) and the 1000 mb speed bits in
3189 * the 1000Base-T Control Register (Address 9).
3191 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3192 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3194 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3196 /* Do we want to advertise 10 Mb Half Duplex? */
3197 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3198 DEBUGOUT("Advertise 10mb Half duplex\n");
3199 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3202 /* Do we want to advertise 10 Mb Full Duplex? */
3203 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3204 DEBUGOUT("Advertise 10mb Full duplex\n");
3205 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3208 /* Do we want to advertise 100 Mb Half Duplex? */
3209 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3210 DEBUGOUT("Advertise 100mb Half duplex\n");
3211 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3214 /* Do we want to advertise 100 Mb Full Duplex? */
3215 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3216 DEBUGOUT("Advertise 100mb Full duplex\n");
3217 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3220 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3221 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3223 ("Advertise 1000mb Half duplex requested, request denied!\n");
3226 /* Do we want to advertise 1000 Mb Full Duplex? */
3227 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3228 DEBUGOUT("Advertise 1000mb Full duplex\n");
3229 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3232 /* Check for a software override of the flow control settings, and
3233 * setup the PHY advertisement registers accordingly. If
3234 * auto-negotiation is enabled, then software will have to set the
3235 * "PAUSE" bits to the correct value in the Auto-Negotiation
3236 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3238 * The possible values of the "fc" parameter are:
3239 * 0: Flow control is completely disabled
3240 * 1: Rx flow control is enabled (we can receive pause frames
3241 * but not send pause frames).
3242 * 2: Tx flow control is enabled (we can send pause frames
3243 * but we do not support receiving pause frames).
3244 * 3: Both Rx and TX flow control (symmetric) are enabled.
3245 * other: No software override. The flow control configuration
3246 * in the EEPROM is used.
3249 case e1000_fc_none: /* 0 */
3250 /* Flow control (RX & TX) is completely disabled by a
3251 * software over-ride.
3253 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3255 case e1000_fc_rx_pause: /* 1 */
3256 /* RX Flow control is enabled, and TX Flow control is
3257 * disabled, by a software over-ride.
3259 /* Since there really isn't a way to advertise that we are
3260 * capable of RX Pause ONLY, we will advertise that we
3261 * support both symmetric and asymmetric RX PAUSE. Later
3262 * (in e1000_config_fc_after_link_up) we will disable the
3263 *hw's ability to send PAUSE frames.
3265 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3267 case e1000_fc_tx_pause: /* 2 */
3268 /* TX Flow control is enabled, and RX Flow control is
3269 * disabled, by a software over-ride.
3271 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3272 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3274 case e1000_fc_full: /* 3 */
3275 /* Flow control (both RX and TX) is enabled by a software
3278 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3281 DEBUGOUT("Flow control param set incorrectly\n");
3282 return -E1000_ERR_CONFIG;
3285 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3289 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3291 if (hw->phy_type != e1000_phy_ife) {
3292 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3293 mii_1000t_ctrl_reg);
3298 return E1000_SUCCESS;
3301 /******************************************************************************
3302 * Sets the collision distance in the Transmit Control register
3304 * hw - Struct containing variables accessed by shared code
3306 * Link should have been established previously. Reads the speed and duplex
3307 * information from the Device Status register.
3308 ******************************************************************************/
3310 e1000_config_collision_dist(struct e1000_hw *hw)
3312 uint32_t tctl, coll_dist;
3316 if (hw->mac_type < e1000_82543)
3317 coll_dist = E1000_COLLISION_DISTANCE_82542;
3319 coll_dist = E1000_COLLISION_DISTANCE;
3321 tctl = E1000_READ_REG(hw, TCTL);
3323 tctl &= ~E1000_TCTL_COLD;
3324 tctl |= coll_dist << E1000_COLD_SHIFT;
3326 E1000_WRITE_REG(hw, TCTL, tctl);
3327 E1000_WRITE_FLUSH(hw);
3330 /******************************************************************************
3331 * Sets MAC speed and duplex settings to reflect the those in the PHY
3333 * hw - Struct containing variables accessed by shared code
3334 * mii_reg - data to write to the MII control register
3336 * The contents of the PHY register containing the needed information need to
3338 ******************************************************************************/
3340 e1000_config_mac_to_phy(struct e1000_hw *hw)
3347 /* Read the Device Control Register and set the bits to Force Speed
3350 ctrl = E1000_READ_REG(hw, CTRL);
3351 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3352 ctrl &= ~(E1000_CTRL_ILOS);
3353 ctrl |= (E1000_CTRL_SPD_SEL);
3355 /* Set up duplex in the Device Control and Transmit Control
3356 * registers depending on negotiated values.
3358 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3359 DEBUGOUT("PHY Read Error\n");
3360 return -E1000_ERR_PHY;
3362 if (phy_data & M88E1000_PSSR_DPLX)
3363 ctrl |= E1000_CTRL_FD;
3365 ctrl &= ~E1000_CTRL_FD;
3367 e1000_config_collision_dist(hw);
3369 /* Set up speed in the Device Control register depending on
3370 * negotiated values.
3372 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3373 ctrl |= E1000_CTRL_SPD_1000;
3374 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3375 ctrl |= E1000_CTRL_SPD_100;
3376 /* Write the configured values back to the Device Control Reg. */
3377 E1000_WRITE_REG(hw, CTRL, ctrl);
3381 /******************************************************************************
3382 * Forces the MAC's flow control settings.
3384 * hw - Struct containing variables accessed by shared code
3386 * Sets the TFCE and RFCE bits in the device control register to reflect
3387 * the adapter settings. TFCE and RFCE need to be explicitly set by
3388 * software when a Copper PHY is used because autonegotiation is managed
3389 * by the PHY rather than the MAC. Software must also configure these
3390 * bits when link is forced on a fiber connection.
3391 *****************************************************************************/
3393 e1000_force_mac_fc(struct e1000_hw *hw)
3399 /* Get the current configuration of the Device Control Register */
3400 ctrl = E1000_READ_REG(hw, CTRL);
3402 /* Because we didn't get link via the internal auto-negotiation
3403 * mechanism (we either forced link or we got link via PHY
3404 * auto-neg), we have to manually enable/disable transmit an
3405 * receive flow control.
3407 * The "Case" statement below enables/disable flow control
3408 * according to the "hw->fc" parameter.
3410 * The possible values of the "fc" parameter are:
3411 * 0: Flow control is completely disabled
3412 * 1: Rx flow control is enabled (we can receive pause
3413 * frames but not send pause frames).
3414 * 2: Tx flow control is enabled (we can send pause frames
3415 * frames but we do not receive pause frames).
3416 * 3: Both Rx and TX flow control (symmetric) is enabled.
3417 * other: No other values should be possible at this point.
3422 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3424 case e1000_fc_rx_pause:
3425 ctrl &= (~E1000_CTRL_TFCE);
3426 ctrl |= E1000_CTRL_RFCE;
3428 case e1000_fc_tx_pause:
3429 ctrl &= (~E1000_CTRL_RFCE);
3430 ctrl |= E1000_CTRL_TFCE;
3433 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3436 DEBUGOUT("Flow control param set incorrectly\n");
3437 return -E1000_ERR_CONFIG;
3440 /* Disable TX Flow Control for 82542 (rev 2.0) */
3441 if (hw->mac_type == e1000_82542_rev2_0)
3442 ctrl &= (~E1000_CTRL_TFCE);
3444 E1000_WRITE_REG(hw, CTRL, ctrl);
3448 /******************************************************************************
3449 * Configures flow control settings after link is established
3451 * hw - Struct containing variables accessed by shared code
3453 * Should be called immediately after a valid link has been established.
3454 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3455 * and autonegotiation is enabled, the MAC flow control settings will be set
3456 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3457 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3458 *****************************************************************************/
3460 e1000_config_fc_after_link_up(struct e1000_hw *hw)
3463 uint16_t mii_status_reg;
3464 uint16_t mii_nway_adv_reg;
3465 uint16_t mii_nway_lp_ability_reg;
3471 /* Check for the case where we have fiber media and auto-neg failed
3472 * so we had to force link. In this case, we need to force the
3473 * configuration of the MAC to match the "fc" parameter.
3475 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3476 || ((hw->media_type == e1000_media_type_internal_serdes)
3477 && (hw->autoneg_failed))
3478 || ((hw->media_type == e1000_media_type_copper)
3479 && (!hw->autoneg))) {
3480 ret_val = e1000_force_mac_fc(hw);
3482 DEBUGOUT("Error forcing flow control settings\n");
3487 /* Check for the case where we have copper media and auto-neg is
3488 * enabled. In this case, we need to check and see if Auto-Neg
3489 * has completed, and if so, how the PHY and link partner has
3490 * flow control configured.
3492 if (hw->media_type == e1000_media_type_copper) {
3493 /* Read the MII Status Register and check to see if AutoNeg
3494 * has completed. We read this twice because this reg has
3495 * some "sticky" (latched) bits.
3497 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3498 DEBUGOUT("PHY Read Error\n");
3499 return -E1000_ERR_PHY;
3501 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3502 DEBUGOUT("PHY Read Error\n");
3503 return -E1000_ERR_PHY;
3506 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3507 /* The AutoNeg process has completed, so we now need to
3508 * read both the Auto Negotiation Advertisement Register
3509 * (Address 4) and the Auto_Negotiation Base Page Ability
3510 * Register (Address 5) to determine how flow control was
3513 if (e1000_read_phy_reg
3514 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3515 DEBUGOUT("PHY Read Error\n");
3516 return -E1000_ERR_PHY;
3518 if (e1000_read_phy_reg
3519 (hw, PHY_LP_ABILITY,
3520 &mii_nway_lp_ability_reg) < 0) {
3521 DEBUGOUT("PHY Read Error\n");
3522 return -E1000_ERR_PHY;
3525 /* Two bits in the Auto Negotiation Advertisement Register
3526 * (Address 4) and two bits in the Auto Negotiation Base
3527 * Page Ability Register (Address 5) determine flow control
3528 * for both the PHY and the link partner. The following
3529 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3530 * 1999, describes these PAUSE resolution bits and how flow
3531 * control is determined based upon these settings.
3532 * NOTE: DC = Don't Care
3534 * LOCAL DEVICE | LINK PARTNER
3535 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3536 *-------|---------|-------|---------|--------------------
3537 * 0 | 0 | DC | DC | e1000_fc_none
3538 * 0 | 1 | 0 | DC | e1000_fc_none
3539 * 0 | 1 | 1 | 0 | e1000_fc_none
3540 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
3541 * 1 | 0 | 0 | DC | e1000_fc_none
3542 * 1 | DC | 1 | DC | e1000_fc_full
3543 * 1 | 1 | 0 | 0 | e1000_fc_none
3544 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
3547 /* Are both PAUSE bits set to 1? If so, this implies
3548 * Symmetric Flow Control is enabled at both ends. The
3549 * ASM_DIR bits are irrelevant per the spec.
3551 * For Symmetric Flow Control:
3553 * LOCAL DEVICE | LINK PARTNER
3554 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3555 *-------|---------|-------|---------|--------------------
3556 * 1 | DC | 1 | DC | e1000_fc_full
3559 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3560 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3561 /* Now we need to check if the user selected RX ONLY
3562 * of pause frames. In this case, we had to advertise
3563 * FULL flow control because we could not advertise RX
3564 * ONLY. Hence, we must now check to see if we need to
3565 * turn OFF the TRANSMISSION of PAUSE frames.
3567 if (hw->original_fc == e1000_fc_full) {
3568 hw->fc = e1000_fc_full;
3569 DEBUGOUT("Flow Control = FULL.\r\n");
3571 hw->fc = e1000_fc_rx_pause;
3573 ("Flow Control = RX PAUSE frames only.\r\n");
3576 /* For receiving PAUSE frames ONLY.
3578 * LOCAL DEVICE | LINK PARTNER
3579 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3580 *-------|---------|-------|---------|--------------------
3581 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
3584 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3585 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3586 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3587 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3589 hw->fc = e1000_fc_tx_pause;
3591 ("Flow Control = TX PAUSE frames only.\r\n");
3593 /* For transmitting PAUSE frames ONLY.
3595 * LOCAL DEVICE | LINK PARTNER
3596 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3597 *-------|---------|-------|---------|--------------------
3598 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
3601 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3602 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3603 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3604 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3606 hw->fc = e1000_fc_rx_pause;
3608 ("Flow Control = RX PAUSE frames only.\r\n");
3610 /* Per the IEEE spec, at this point flow control should be
3611 * disabled. However, we want to consider that we could
3612 * be connected to a legacy switch that doesn't advertise
3613 * desired flow control, but can be forced on the link
3614 * partner. So if we advertised no flow control, that is
3615 * what we will resolve to. If we advertised some kind of
3616 * receive capability (Rx Pause Only or Full Flow Control)
3617 * and the link partner advertised none, we will configure
3618 * ourselves to enable Rx Flow Control only. We can do
3619 * this safely for two reasons: If the link partner really
3620 * didn't want flow control enabled, and we enable Rx, no
3621 * harm done since we won't be receiving any PAUSE frames
3622 * anyway. If the intent on the link partner was to have
3623 * flow control enabled, then by us enabling RX only, we
3624 * can at least receive pause frames and process them.
3625 * This is a good idea because in most cases, since we are
3626 * predominantly a server NIC, more times than not we will
3627 * be asked to delay transmission of packets than asking
3628 * our link partner to pause transmission of frames.
3630 else if (hw->original_fc == e1000_fc_none ||
3631 hw->original_fc == e1000_fc_tx_pause) {
3632 hw->fc = e1000_fc_none;
3633 DEBUGOUT("Flow Control = NONE.\r\n");
3635 hw->fc = e1000_fc_rx_pause;
3637 ("Flow Control = RX PAUSE frames only.\r\n");
3640 /* Now we need to do one last check... If we auto-
3641 * negotiated to HALF DUPLEX, flow control should not be
3642 * enabled per IEEE 802.3 spec.
3644 e1000_get_speed_and_duplex(hw, &speed, &duplex);
3646 if (duplex == HALF_DUPLEX)
3647 hw->fc = e1000_fc_none;
3649 /* Now we call a subroutine to actually force the MAC
3650 * controller to use the correct flow control settings.
3652 ret_val = e1000_force_mac_fc(hw);
3655 ("Error forcing flow control settings\n");
3660 ("Copper PHY and Auto Neg has not completed.\r\n");
3663 return E1000_SUCCESS;
3666 /******************************************************************************
3667 * Checks to see if the link status of the hardware has changed.
3669 * hw - Struct containing variables accessed by shared code
3671 * Called by any function that needs to check the link status of the adapter.
3672 *****************************************************************************/
3674 e1000_check_for_link(struct e1000_hw *hw)
3683 uint16_t lp_capability;
3687 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3688 * set when the optics detect a signal. On older adapters, it will be
3689 * cleared when there is a signal
3691 ctrl = E1000_READ_REG(hw, CTRL);
3692 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3693 signal = E1000_CTRL_SWDPIN1;
3697 status = E1000_READ_REG(hw, STATUS);
3698 rxcw = E1000_READ_REG(hw, RXCW);
3699 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3701 /* If we have a copper PHY then we only want to go out to the PHY
3702 * registers to see if Auto-Neg has completed and/or if our link
3703 * status has changed. The get_link_status flag will be set if we
3704 * receive a Link Status Change interrupt or we have Rx Sequence
3707 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3708 /* First we want to see if the MII Status Register reports
3709 * link. If so, then we want to get the current speed/duplex
3711 * Read the register twice since the link bit is sticky.
3713 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3714 DEBUGOUT("PHY Read Error\n");
3715 return -E1000_ERR_PHY;
3717 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3718 DEBUGOUT("PHY Read Error\n");
3719 return -E1000_ERR_PHY;
3722 if (phy_data & MII_SR_LINK_STATUS) {
3723 hw->get_link_status = false;
3725 /* No link detected */
3726 return -E1000_ERR_NOLINK;
3729 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
3730 * have Si on board that is 82544 or newer, Auto
3731 * Speed Detection takes care of MAC speed/duplex
3732 * configuration. So we only need to configure Collision
3733 * Distance in the MAC. Otherwise, we need to force
3734 * speed/duplex on the MAC to the current PHY speed/duplex
3737 if (hw->mac_type >= e1000_82544)
3738 e1000_config_collision_dist(hw);
3740 ret_val = e1000_config_mac_to_phy(hw);
3743 ("Error configuring MAC to PHY settings\n");
3748 /* Configure Flow Control now that Auto-Neg has completed. First, we
3749 * need to restore the desired flow control settings because we may
3750 * have had to re-autoneg with a different link partner.
3752 ret_val = e1000_config_fc_after_link_up(hw);
3754 DEBUGOUT("Error configuring flow control\n");
3758 /* At this point we know that we are on copper and we have
3759 * auto-negotiated link. These are conditions for checking the link
3760 * parter capability register. We use the link partner capability to
3761 * determine if TBI Compatibility needs to be turned on or off. If
3762 * the link partner advertises any speed in addition to Gigabit, then
3763 * we assume that they are GMII-based, and TBI compatibility is not
3764 * needed. If no other speeds are advertised, we assume the link
3765 * partner is TBI-based, and we turn on TBI Compatibility.
3767 if (hw->tbi_compatibility_en) {
3768 if (e1000_read_phy_reg
3769 (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3770 DEBUGOUT("PHY Read Error\n");
3771 return -E1000_ERR_PHY;
3773 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3774 NWAY_LPAR_10T_FD_CAPS |
3775 NWAY_LPAR_100TX_HD_CAPS |
3776 NWAY_LPAR_100TX_FD_CAPS |
3777 NWAY_LPAR_100T4_CAPS)) {
3778 /* If our link partner advertises anything in addition to
3779 * gigabit, we do not need to enable TBI compatibility.
3781 if (hw->tbi_compatibility_on) {
3782 /* If we previously were in the mode, turn it off. */
3783 rctl = E1000_READ_REG(hw, RCTL);
3784 rctl &= ~E1000_RCTL_SBP;
3785 E1000_WRITE_REG(hw, RCTL, rctl);
3786 hw->tbi_compatibility_on = false;
3789 /* If TBI compatibility is was previously off, turn it on. For
3790 * compatibility with a TBI link partner, we will store bad
3791 * packets. Some frames have an additional byte on the end and
3792 * will look like CRC errors to to the hardware.
3794 if (!hw->tbi_compatibility_on) {
3795 hw->tbi_compatibility_on = true;
3796 rctl = E1000_READ_REG(hw, RCTL);
3797 rctl |= E1000_RCTL_SBP;
3798 E1000_WRITE_REG(hw, RCTL, rctl);
3803 /* If we don't have link (auto-negotiation failed or link partner cannot
3804 * auto-negotiate), the cable is plugged in (we have signal), and our
3805 * link partner is not trying to auto-negotiate with us (we are receiving
3806 * idles or data), we need to force link up. We also need to give
3807 * auto-negotiation time to complete, in case the cable was just plugged
3808 * in. The autoneg_failed flag does this.
3810 else if ((hw->media_type == e1000_media_type_fiber) &&
3811 (!(status & E1000_STATUS_LU)) &&
3812 ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3813 (!(rxcw & E1000_RXCW_C))) {
3814 if (hw->autoneg_failed == 0) {
3815 hw->autoneg_failed = 1;
3818 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3820 /* Disable auto-negotiation in the TXCW register */
3821 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3823 /* Force link-up and also force full-duplex. */
3824 ctrl = E1000_READ_REG(hw, CTRL);
3825 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3826 E1000_WRITE_REG(hw, CTRL, ctrl);
3828 /* Configure Flow Control after forcing link up. */
3829 ret_val = e1000_config_fc_after_link_up(hw);
3831 DEBUGOUT("Error configuring flow control\n");
3835 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3836 * auto-negotiation in the TXCW register and disable forced link in the
3837 * Device Control register in an attempt to auto-negotiate with our link
3840 else if ((hw->media_type == e1000_media_type_fiber) &&
3841 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3843 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3844 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3845 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3850 /******************************************************************************
3851 * Configure the MAC-to-PHY interface for 10/100Mbps
3853 * hw - Struct containing variables accessed by shared code
3854 ******************************************************************************/
3856 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
3858 int32_t ret_val = E1000_SUCCESS;
3864 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
3865 ret_val = e1000_write_kmrn_reg(hw,
3866 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3870 /* Configure Transmit Inter-Packet Gap */
3871 tipg = E1000_READ_REG(hw, TIPG);
3872 tipg &= ~E1000_TIPG_IPGT_MASK;
3873 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
3874 E1000_WRITE_REG(hw, TIPG, tipg);
3876 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
3881 if (duplex == HALF_DUPLEX)
3882 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
3884 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3886 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3892 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
3894 int32_t ret_val = E1000_SUCCESS;
3900 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
3901 ret_val = e1000_write_kmrn_reg(hw,
3902 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3906 /* Configure Transmit Inter-Packet Gap */
3907 tipg = E1000_READ_REG(hw, TIPG);
3908 tipg &= ~E1000_TIPG_IPGT_MASK;
3909 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
3910 E1000_WRITE_REG(hw, TIPG, tipg);
3912 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
3917 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3918 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3923 /******************************************************************************
3924 * Detects the current speed and duplex settings of the hardware.
3926 * hw - Struct containing variables accessed by shared code
3927 * speed - Speed of the connection
3928 * duplex - Duplex setting of the connection
3929 *****************************************************************************/
3931 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
3940 if (hw->mac_type >= e1000_82543) {
3941 status = E1000_READ_REG(hw, STATUS);
3942 if (status & E1000_STATUS_SPEED_1000) {
3943 *speed = SPEED_1000;
3944 DEBUGOUT("1000 Mbs, ");
3945 } else if (status & E1000_STATUS_SPEED_100) {
3947 DEBUGOUT("100 Mbs, ");
3950 DEBUGOUT("10 Mbs, ");
3953 if (status & E1000_STATUS_FD) {
3954 *duplex = FULL_DUPLEX;
3955 DEBUGOUT("Full Duplex\r\n");
3957 *duplex = HALF_DUPLEX;
3958 DEBUGOUT(" Half Duplex\r\n");
3961 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
3962 *speed = SPEED_1000;
3963 *duplex = FULL_DUPLEX;
3966 /* IGP01 PHY may advertise full duplex operation after speed downgrade
3967 * even if it is operating at half duplex. Here we set the duplex
3968 * settings to match the duplex in the link partner's capabilities.
3970 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3971 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3975 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3976 *duplex = HALF_DUPLEX;
3978 ret_val = e1000_read_phy_reg(hw,
3979 PHY_LP_ABILITY, &phy_data);
3982 if ((*speed == SPEED_100 &&
3983 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
3984 || (*speed == SPEED_10
3985 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3986 *duplex = HALF_DUPLEX;
3990 if ((hw->mac_type == e1000_80003es2lan) &&
3991 (hw->media_type == e1000_media_type_copper)) {
3992 if (*speed == SPEED_1000)
3993 ret_val = e1000_configure_kmrn_for_1000(hw);
3995 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3999 return E1000_SUCCESS;
4002 /******************************************************************************
4003 * Blocks until autoneg completes or times out (~4.5 seconds)
4005 * hw - Struct containing variables accessed by shared code
4006 ******************************************************************************/
4008 e1000_wait_autoneg(struct e1000_hw *hw)
4014 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
4016 /* We will wait for autoneg to complete or timeout to expire. */
4017 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
4018 /* Read the MII Status Register and wait for Auto-Neg
4019 * Complete bit to be set.
4021 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4022 DEBUGOUT("PHY Read Error\n");
4023 return -E1000_ERR_PHY;
4025 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
4026 DEBUGOUT("PHY Read Error\n");
4027 return -E1000_ERR_PHY;
4029 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
4030 DEBUGOUT("Auto-Neg complete.\n");
4035 DEBUGOUT("Auto-Neg timedout.\n");
4036 return -E1000_ERR_TIMEOUT;
4039 /******************************************************************************
4040 * Raises the Management Data Clock
4042 * hw - Struct containing variables accessed by shared code
4043 * ctrl - Device control register's current value
4044 ******************************************************************************/
4046 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4048 /* Raise the clock input to the Management Data Clock (by setting the MDC
4049 * bit), and then delay 2 microseconds.
4051 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
4052 E1000_WRITE_FLUSH(hw);
4056 /******************************************************************************
4057 * Lowers the Management Data Clock
4059 * hw - Struct containing variables accessed by shared code
4060 * ctrl - Device control register's current value
4061 ******************************************************************************/
4063 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
4065 /* Lower the clock input to the Management Data Clock (by clearing the MDC
4066 * bit), and then delay 2 microseconds.
4068 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
4069 E1000_WRITE_FLUSH(hw);
4073 /******************************************************************************
4074 * Shifts data bits out to the PHY
4076 * hw - Struct containing variables accessed by shared code
4077 * data - Data to send out to the PHY
4078 * count - Number of bits to shift out
4080 * Bits are shifted out in MSB to LSB order.
4081 ******************************************************************************/
4083 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
4088 /* We need to shift "count" number of bits out to the PHY. So, the value
4089 * in the "data" parameter will be shifted out to the PHY one bit at a
4090 * time. In order to do this, "data" must be broken down into bits.
4093 mask <<= (count - 1);
4095 ctrl = E1000_READ_REG(hw, CTRL);
4097 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
4098 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4101 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4102 * then raising and lowering the Management Data Clock. A "0" is
4103 * shifted out to the PHY by setting the MDIO bit to "0" and then
4104 * raising and lowering the clock.
4107 ctrl |= E1000_CTRL_MDIO;
4109 ctrl &= ~E1000_CTRL_MDIO;
4111 E1000_WRITE_REG(hw, CTRL, ctrl);
4112 E1000_WRITE_FLUSH(hw);
4116 e1000_raise_mdi_clk(hw, &ctrl);
4117 e1000_lower_mdi_clk(hw, &ctrl);
4123 /******************************************************************************
4124 * Shifts data bits in from the PHY
4126 * hw - Struct containing variables accessed by shared code
4128 * Bits are shifted in in MSB to LSB order.
4129 ******************************************************************************/
4131 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4137 /* In order to read a register from the PHY, we need to shift in a total
4138 * of 18 bits from the PHY. The first two bit (turnaround) times are used
4139 * to avoid contention on the MDIO pin when a read operation is performed.
4140 * These two bits are ignored by us and thrown away. Bits are "shifted in"
4141 * by raising the input to the Management Data Clock (setting the MDC bit),
4142 * and then reading the value of the MDIO bit.
4144 ctrl = E1000_READ_REG(hw, CTRL);
4146 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4147 ctrl &= ~E1000_CTRL_MDIO_DIR;
4148 ctrl &= ~E1000_CTRL_MDIO;
4150 E1000_WRITE_REG(hw, CTRL, ctrl);
4151 E1000_WRITE_FLUSH(hw);
4153 /* Raise and Lower the clock before reading in the data. This accounts for
4154 * the turnaround bits. The first clock occurred when we clocked out the
4155 * last bit of the Register Address.
4157 e1000_raise_mdi_clk(hw, &ctrl);
4158 e1000_lower_mdi_clk(hw, &ctrl);
4160 for (data = 0, i = 0; i < 16; i++) {
4162 e1000_raise_mdi_clk(hw, &ctrl);
4163 ctrl = E1000_READ_REG(hw, CTRL);
4164 /* Check to see if we shifted in a "1". */
4165 if (ctrl & E1000_CTRL_MDIO)
4167 e1000_lower_mdi_clk(hw, &ctrl);
4170 e1000_raise_mdi_clk(hw, &ctrl);
4171 e1000_lower_mdi_clk(hw, &ctrl);
4176 /*****************************************************************************
4177 * Reads the value from a PHY register
4179 * hw - Struct containing variables accessed by shared code
4180 * reg_addr - address of the PHY register to read
4181 ******************************************************************************/
4183 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4187 const uint32_t phy_addr = 1;
4189 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4190 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4191 return -E1000_ERR_PARAM;
4194 if (hw->mac_type > e1000_82543) {
4195 /* Set up Op-code, Phy Address, and register address in the MDI
4196 * Control register. The MAC will take care of interfacing with the
4197 * PHY to retrieve the desired data.
4199 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4200 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4201 (E1000_MDIC_OP_READ));
4203 E1000_WRITE_REG(hw, MDIC, mdic);
4205 /* Poll the ready bit to see if the MDI read completed */
4206 for (i = 0; i < 64; i++) {
4208 mdic = E1000_READ_REG(hw, MDIC);
4209 if (mdic & E1000_MDIC_READY)
4212 if (!(mdic & E1000_MDIC_READY)) {
4213 DEBUGOUT("MDI Read did not complete\n");
4214 return -E1000_ERR_PHY;
4216 if (mdic & E1000_MDIC_ERROR) {
4217 DEBUGOUT("MDI Error\n");
4218 return -E1000_ERR_PHY;
4220 *phy_data = (uint16_t) mdic;
4222 /* We must first send a preamble through the MDIO pin to signal the
4223 * beginning of an MII instruction. This is done by sending 32
4224 * consecutive "1" bits.
4226 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4228 /* Now combine the next few fields that are required for a read
4229 * operation. We use this method instead of calling the
4230 * e1000_shift_out_mdi_bits routine five different times. The format of
4231 * a MII read instruction consists of a shift out of 14 bits and is
4232 * defined as follows:
4233 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4234 * followed by a shift in of 18 bits. This first two bits shifted in
4235 * are TurnAround bits used to avoid contention on the MDIO pin when a
4236 * READ operation is performed. These two bits are thrown away
4237 * followed by a shift in of 16 bits which contains the desired data.
4239 mdic = ((reg_addr) | (phy_addr << 5) |
4240 (PHY_OP_READ << 10) | (PHY_SOF << 12));
4242 e1000_shift_out_mdi_bits(hw, mdic, 14);
4244 /* Now that we've shifted out the read command to the MII, we need to
4245 * "shift in" the 16-bit value (18 total bits) of the requested PHY
4248 *phy_data = e1000_shift_in_mdi_bits(hw);
4253 /******************************************************************************
4254 * Writes a value to a PHY register
4256 * hw - Struct containing variables accessed by shared code
4257 * reg_addr - address of the PHY register to write
4258 * data - data to write to the PHY
4259 ******************************************************************************/
4261 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4265 const uint32_t phy_addr = 1;
4267 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4268 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4269 return -E1000_ERR_PARAM;
4272 if (hw->mac_type > e1000_82543) {
4273 /* Set up Op-code, Phy Address, register address, and data intended
4274 * for the PHY register in the MDI Control register. The MAC will take
4275 * care of interfacing with the PHY to send the desired data.
4277 mdic = (((uint32_t) phy_data) |
4278 (reg_addr << E1000_MDIC_REG_SHIFT) |
4279 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4280 (E1000_MDIC_OP_WRITE));
4282 E1000_WRITE_REG(hw, MDIC, mdic);
4284 /* Poll the ready bit to see if the MDI read completed */
4285 for (i = 0; i < 64; i++) {
4287 mdic = E1000_READ_REG(hw, MDIC);
4288 if (mdic & E1000_MDIC_READY)
4291 if (!(mdic & E1000_MDIC_READY)) {
4292 DEBUGOUT("MDI Write did not complete\n");
4293 return -E1000_ERR_PHY;
4296 /* We'll need to use the SW defined pins to shift the write command
4297 * out to the PHY. We first send a preamble to the PHY to signal the
4298 * beginning of the MII instruction. This is done by sending 32
4299 * consecutive "1" bits.
4301 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4303 /* Now combine the remaining required fields that will indicate a
4304 * write operation. We use this method instead of calling the
4305 * e1000_shift_out_mdi_bits routine for each field in the command. The
4306 * format of a MII write instruction is as follows:
4307 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4309 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4310 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4312 mdic |= (uint32_t) phy_data;
4314 e1000_shift_out_mdi_bits(hw, mdic, 32);
4319 /******************************************************************************
4320 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4321 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
4322 * the caller to figure out how to deal with it.
4324 * hw - Struct containing variables accessed by shared code
4326 * returns: - E1000_BLK_PHY_RESET
4329 *****************************************************************************/
4331 e1000_check_phy_reset_block(struct e1000_hw *hw)
4336 if (hw->mac_type == e1000_ich8lan) {
4337 fwsm = E1000_READ_REG(hw, FWSM);
4338 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4339 : E1000_BLK_PHY_RESET;
4342 if (hw->mac_type > e1000_82547_rev_2)
4343 manc = E1000_READ_REG(hw, MANC);
4344 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4345 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4348 /***************************************************************************
4349 * Checks if the PHY configuration is done
4351 * hw: Struct containing variables accessed by shared code
4353 * returns: - E1000_ERR_RESET if fail to reset MAC
4354 * E1000_SUCCESS at any other case.
4356 ***************************************************************************/
4358 e1000_get_phy_cfg_done(struct e1000_hw *hw)
4360 int32_t timeout = PHY_CFG_TIMEOUT;
4361 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4365 switch (hw->mac_type) {
4370 case e1000_80003es2lan:
4371 /* Separate *_CFG_DONE_* bit for each port */
4372 if (e1000_is_second_port(hw))
4373 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
4380 if (hw->mac_type == e1000_igb) {
4381 if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
4384 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4391 DEBUGOUT("MNG configuration cycle has not "
4393 return -E1000_ERR_RESET;
4398 return E1000_SUCCESS;
4401 /******************************************************************************
4402 * Returns the PHY to the power-on reset state
4404 * hw - Struct containing variables accessed by shared code
4405 ******************************************************************************/
4407 e1000_phy_hw_reset(struct e1000_hw *hw)
4409 uint16_t swfw = E1000_SWFW_PHY0_SM;
4410 uint32_t ctrl, ctrl_ext;
4416 /* In the case of the phy reset being blocked, it's not an error, we
4417 * simply return success without performing the reset. */
4418 ret_val = e1000_check_phy_reset_block(hw);
4420 return E1000_SUCCESS;
4422 DEBUGOUT("Resetting Phy...\n");
4424 if (hw->mac_type > e1000_82543) {
4425 if (e1000_is_second_port(hw))
4426 swfw = E1000_SWFW_PHY1_SM;
4428 if (e1000_swfw_sync_acquire(hw, swfw)) {
4429 DEBUGOUT("Unable to acquire swfw sync\n");
4430 return -E1000_ERR_SWFW_SYNC;
4433 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4434 * bit. Then, take it out of reset.
4436 ctrl = E1000_READ_REG(hw, CTRL);
4437 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4438 E1000_WRITE_FLUSH(hw);
4440 if (hw->mac_type < e1000_82571)
4445 E1000_WRITE_REG(hw, CTRL, ctrl);
4446 E1000_WRITE_FLUSH(hw);
4448 if (hw->mac_type >= e1000_82571)
4452 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4453 * bit to put the PHY into reset. Then, take it out of reset.
4455 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4456 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4457 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4458 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4459 E1000_WRITE_FLUSH(hw);
4461 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4462 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4463 E1000_WRITE_FLUSH(hw);
4467 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4468 /* Configure activity LED after PHY reset */
4469 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4470 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4471 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4472 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4475 e1000_swfw_sync_release(hw, swfw);
4477 /* Wait for FW to finish PHY configuration. */
4478 ret_val = e1000_get_phy_cfg_done(hw);
4479 if (ret_val != E1000_SUCCESS)
4485 /******************************************************************************
4486 * IGP phy init script - initializes the GbE PHY
4488 * hw - Struct containing variables accessed by shared code
4489 *****************************************************************************/
4491 e1000_phy_init_script(struct e1000_hw *hw)
4494 uint16_t phy_saved_data;
4497 if (hw->phy_init_script) {
4500 /* Save off the current value of register 0x2F5B to be
4501 * restored at the end of this routine. */
4502 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4504 /* Disabled the PHY transmitter */
4505 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4509 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4513 switch (hw->mac_type) {
4516 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4518 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4520 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4522 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4524 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4526 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4528 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4530 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4532 e1000_write_phy_reg(hw, 0x2010, 0x0008);
4535 case e1000_82541_rev_2:
4536 case e1000_82547_rev_2:
4537 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4543 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4547 /* Now enable the transmitter */
4549 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
4551 if (hw->mac_type == e1000_82547) {
4552 uint16_t fused, fine, coarse;
4554 /* Move to analog registers page */
4555 e1000_read_phy_reg(hw,
4556 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4558 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4559 e1000_read_phy_reg(hw,
4560 IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4562 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4564 & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4567 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4569 IGP01E1000_ANALOG_FUSE_COARSE_10;
4570 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4572 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4573 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4576 & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4578 & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4580 & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4582 e1000_write_phy_reg(hw,
4583 IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4584 e1000_write_phy_reg(hw,
4585 IGP01E1000_ANALOG_FUSE_BYPASS,
4586 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4592 /******************************************************************************
4595 * hw - Struct containing variables accessed by shared code
4597 * Sets bit 15 of the MII Control register
4598 ******************************************************************************/
4600 e1000_phy_reset(struct e1000_hw *hw)
4607 /* In the case of the phy reset being blocked, it's not an error, we
4608 * simply return success without performing the reset. */
4609 ret_val = e1000_check_phy_reset_block(hw);
4611 return E1000_SUCCESS;
4613 switch (hw->phy_type) {
4615 case e1000_phy_igp_2:
4616 case e1000_phy_igp_3:
4619 ret_val = e1000_phy_hw_reset(hw);
4624 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4628 phy_data |= MII_CR_RESET;
4629 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4637 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4638 e1000_phy_init_script(hw);
4640 return E1000_SUCCESS;
4643 static int e1000_set_phy_type (struct e1000_hw *hw)
4647 if (hw->mac_type == e1000_undefined)
4648 return -E1000_ERR_PHY_TYPE;
4650 switch (hw->phy_id) {
4651 case M88E1000_E_PHY_ID:
4652 case M88E1000_I_PHY_ID:
4653 case M88E1011_I_PHY_ID:
4654 case M88E1111_I_PHY_ID:
4655 hw->phy_type = e1000_phy_m88;
4657 case IGP01E1000_I_PHY_ID:
4658 if (hw->mac_type == e1000_82541 ||
4659 hw->mac_type == e1000_82541_rev_2 ||
4660 hw->mac_type == e1000_82547 ||
4661 hw->mac_type == e1000_82547_rev_2) {
4662 hw->phy_type = e1000_phy_igp;
4665 case IGP03E1000_E_PHY_ID:
4666 hw->phy_type = e1000_phy_igp_3;
4669 case IFE_PLUS_E_PHY_ID:
4670 case IFE_C_E_PHY_ID:
4671 hw->phy_type = e1000_phy_ife;
4673 case GG82563_E_PHY_ID:
4674 if (hw->mac_type == e1000_80003es2lan) {
4675 hw->phy_type = e1000_phy_gg82563;
4678 case BME1000_E_PHY_ID:
4679 hw->phy_type = e1000_phy_bm;
4682 hw->phy_type = e1000_phy_igb;
4686 /* Should never have loaded on this device */
4687 hw->phy_type = e1000_phy_undefined;
4688 return -E1000_ERR_PHY_TYPE;
4691 return E1000_SUCCESS;
4694 /******************************************************************************
4695 * Probes the expected PHY address for known PHY IDs
4697 * hw - Struct containing variables accessed by shared code
4698 ******************************************************************************/
4700 e1000_detect_gig_phy(struct e1000_hw *hw)
4702 int32_t phy_init_status, ret_val;
4703 uint16_t phy_id_high, phy_id_low;
4708 /* The 82571 firmware may still be configuring the PHY. In this
4709 * case, we cannot access the PHY until the configuration is done. So
4710 * we explicitly set the PHY values. */
4711 if (hw->mac_type == e1000_82571 ||
4712 hw->mac_type == e1000_82572) {
4713 hw->phy_id = IGP01E1000_I_PHY_ID;
4714 hw->phy_type = e1000_phy_igp_2;
4715 return E1000_SUCCESS;
4718 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4719 * work- around that forces PHY page 0 to be set or the reads fail.
4720 * The rest of the code in this routine uses e1000_read_phy_reg to
4721 * read the PHY ID. So for ESB-2 we need to have this set so our
4722 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
4723 * the routines below will figure this out as well. */
4724 if (hw->mac_type == e1000_80003es2lan)
4725 hw->phy_type = e1000_phy_gg82563;
4727 /* Read the PHY ID Registers to identify which PHY is onboard. */
4728 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4732 hw->phy_id = (uint32_t) (phy_id_high << 16);
4734 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4738 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4739 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4741 switch (hw->mac_type) {
4743 if (hw->phy_id == M88E1000_E_PHY_ID)
4747 if (hw->phy_id == M88E1000_I_PHY_ID)
4752 case e1000_82545_rev_3:
4754 case e1000_82546_rev_3:
4755 if (hw->phy_id == M88E1011_I_PHY_ID)
4759 case e1000_82541_rev_2:
4761 case e1000_82547_rev_2:
4762 if(hw->phy_id == IGP01E1000_I_PHY_ID)
4767 if (hw->phy_id == M88E1111_I_PHY_ID)
4771 if (hw->phy_id == BME1000_E_PHY_ID)
4774 case e1000_80003es2lan:
4775 if (hw->phy_id == GG82563_E_PHY_ID)
4779 if (hw->phy_id == IGP03E1000_E_PHY_ID)
4781 if (hw->phy_id == IFE_E_PHY_ID)
4783 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4785 if (hw->phy_id == IFE_C_E_PHY_ID)
4789 if (hw->phy_id == I210_I_PHY_ID)
4793 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4794 return -E1000_ERR_CONFIG;
4797 phy_init_status = e1000_set_phy_type(hw);
4799 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4800 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4803 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4804 return -E1000_ERR_PHY;
4807 /*****************************************************************************
4808 * Set media type and TBI compatibility.
4810 * hw - Struct containing variables accessed by shared code
4811 * **************************************************************************/
4813 e1000_set_media_type(struct e1000_hw *hw)
4819 if (hw->mac_type != e1000_82543) {
4820 /* tbi_compatibility is only valid on 82543 */
4821 hw->tbi_compatibility_en = false;
4824 switch (hw->device_id) {
4825 case E1000_DEV_ID_82545GM_SERDES:
4826 case E1000_DEV_ID_82546GB_SERDES:
4827 case E1000_DEV_ID_82571EB_SERDES:
4828 case E1000_DEV_ID_82571EB_SERDES_DUAL:
4829 case E1000_DEV_ID_82571EB_SERDES_QUAD:
4830 case E1000_DEV_ID_82572EI_SERDES:
4831 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
4832 hw->media_type = e1000_media_type_internal_serdes;
4835 switch (hw->mac_type) {
4836 case e1000_82542_rev2_0:
4837 case e1000_82542_rev2_1:
4838 hw->media_type = e1000_media_type_fiber;
4844 /* The STATUS_TBIMODE bit is reserved or reused
4845 * for the this device.
4847 hw->media_type = e1000_media_type_copper;
4850 status = E1000_READ_REG(hw, STATUS);
4851 if (status & E1000_STATUS_TBIMODE) {
4852 hw->media_type = e1000_media_type_fiber;
4853 /* tbi_compatibility not valid on fiber */
4854 hw->tbi_compatibility_en = false;
4856 hw->media_type = e1000_media_type_copper;
4864 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4866 * e1000_sw_init initializes the Adapter private data structure.
4867 * Fields are initialized based on PCI device information and
4868 * OS network device settings (MTU size).
4872 e1000_sw_init(struct e1000_hw *hw)
4876 /* PCI config space info */
4877 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
4878 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
4879 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
4880 &hw->subsystem_vendor_id);
4881 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
4883 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
4884 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
4886 /* identify the MAC */
4887 result = e1000_set_mac_type(hw);
4889 E1000_ERR(hw, "Unknown MAC Type\n");
4893 switch (hw->mac_type) {
4898 case e1000_82541_rev_2:
4899 case e1000_82547_rev_2:
4900 hw->phy_init_script = 1;
4904 /* flow control settings */
4905 hw->fc_high_water = E1000_FC_HIGH_THRESH;
4906 hw->fc_low_water = E1000_FC_LOW_THRESH;
4907 hw->fc_pause_time = E1000_FC_PAUSE_TIME;
4908 hw->fc_send_xon = 1;
4910 /* Media type - copper or fiber */
4911 hw->tbi_compatibility_en = true;
4912 e1000_set_media_type(hw);
4914 if (hw->mac_type >= e1000_82543) {
4915 uint32_t status = E1000_READ_REG(hw, STATUS);
4917 if (status & E1000_STATUS_TBIMODE) {
4918 DEBUGOUT("fiber interface\n");
4919 hw->media_type = e1000_media_type_fiber;
4921 DEBUGOUT("copper interface\n");
4922 hw->media_type = e1000_media_type_copper;
4925 hw->media_type = e1000_media_type_fiber;
4928 hw->wait_autoneg_complete = true;
4929 if (hw->mac_type < e1000_82543)
4930 hw->report_tx_early = 0;
4932 hw->report_tx_early = 1;
4934 return E1000_SUCCESS;
4938 fill_rx(struct e1000_hw *hw)
4940 struct e1000_rx_desc *rd;
4941 unsigned long flush_start, flush_end;
4944 rd = rx_base + rx_tail;
4945 rx_tail = (rx_tail + 1) % 8;
4947 rd->buffer_addr = cpu_to_le64((unsigned long)packet);
4950 * Make sure there are no stale data in WB over this area, which
4951 * might get written into the memory while the e1000 also writes
4952 * into the same memory area.
4954 invalidate_dcache_range((unsigned long)packet,
4955 (unsigned long)packet + 4096);
4956 /* Dump the DMA descriptor into RAM. */
4957 flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
4958 flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
4959 flush_dcache_range(flush_start, flush_end);
4961 E1000_WRITE_REG(hw, RDT, rx_tail);
4965 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
4966 * @adapter: board private structure
4968 * Configure the Tx unit of the MAC after a reset.
4972 e1000_configure_tx(struct e1000_hw *hw)
4975 unsigned long tipg, tarc;
4976 uint32_t ipgr1, ipgr2;
4978 E1000_WRITE_REG(hw, TDBAL, (unsigned long)tx_base & 0xffffffff);
4979 E1000_WRITE_REG(hw, TDBAH, (unsigned long)tx_base >> 32);
4981 E1000_WRITE_REG(hw, TDLEN, 128);
4983 /* Setup the HW Tx Head and Tail descriptor pointers */
4984 E1000_WRITE_REG(hw, TDH, 0);
4985 E1000_WRITE_REG(hw, TDT, 0);
4988 /* Set the default values for the Tx Inter Packet Gap timer */
4989 if (hw->mac_type <= e1000_82547_rev_2 &&
4990 (hw->media_type == e1000_media_type_fiber ||
4991 hw->media_type == e1000_media_type_internal_serdes))
4992 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
4994 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
4996 /* Set the default values for the Tx Inter Packet Gap timer */
4997 switch (hw->mac_type) {
4998 case e1000_82542_rev2_0:
4999 case e1000_82542_rev2_1:
5000 tipg = DEFAULT_82542_TIPG_IPGT;
5001 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
5002 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
5004 case e1000_80003es2lan:
5005 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5006 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
5009 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
5010 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
5013 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
5014 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
5015 E1000_WRITE_REG(hw, TIPG, tipg);
5016 /* Program the Transmit Control Register */
5017 tctl = E1000_READ_REG(hw, TCTL);
5018 tctl &= ~E1000_TCTL_CT;
5019 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
5020 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
5022 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
5023 tarc = E1000_READ_REG(hw, TARC0);
5024 /* set the speed mode bit, we'll clear it if we're not at
5025 * gigabit link later */
5026 /* git bit can be set to 1*/
5027 } else if (hw->mac_type == e1000_80003es2lan) {
5028 tarc = E1000_READ_REG(hw, TARC0);
5030 E1000_WRITE_REG(hw, TARC0, tarc);
5031 tarc = E1000_READ_REG(hw, TARC1);
5033 E1000_WRITE_REG(hw, TARC1, tarc);
5037 e1000_config_collision_dist(hw);
5038 /* Setup Transmit Descriptor Settings for eop descriptor */
5039 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
5041 /* Need to set up RS bit */
5042 if (hw->mac_type < e1000_82543)
5043 hw->txd_cmd |= E1000_TXD_CMD_RPS;
5045 hw->txd_cmd |= E1000_TXD_CMD_RS;
5048 if (hw->mac_type == e1000_igb) {
5049 E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
5051 uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL);
5052 reg_txdctl |= 1 << 25;
5053 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
5059 E1000_WRITE_REG(hw, TCTL, tctl);
5065 * e1000_setup_rctl - configure the receive control register
5066 * @adapter: Board private structure
5069 e1000_setup_rctl(struct e1000_hw *hw)
5073 rctl = E1000_READ_REG(hw, RCTL);
5075 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
5077 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
5078 | E1000_RCTL_RDMTS_HALF; /* |
5079 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
5081 if (hw->tbi_compatibility_on == 1)
5082 rctl |= E1000_RCTL_SBP;
5084 rctl &= ~E1000_RCTL_SBP;
5086 rctl &= ~(E1000_RCTL_SZ_4096);
5087 rctl |= E1000_RCTL_SZ_2048;
5088 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
5089 E1000_WRITE_REG(hw, RCTL, rctl);
5093 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
5094 * @adapter: board private structure
5096 * Configure the Rx unit of the MAC after a reset.
5099 e1000_configure_rx(struct e1000_hw *hw)
5101 unsigned long rctl, ctrl_ext;
5103 /* make sure receives are disabled while setting up the descriptors */
5104 rctl = E1000_READ_REG(hw, RCTL);
5105 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
5106 if (hw->mac_type >= e1000_82540) {
5107 /* Set the interrupt throttling rate. Value is calculated
5108 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
5109 #define MAX_INTS_PER_SEC 8000
5110 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
5111 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
5114 if (hw->mac_type >= e1000_82571) {
5115 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5116 /* Reset delay timers after every interrupt */
5117 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
5118 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5119 E1000_WRITE_FLUSH(hw);
5121 /* Setup the Base and Length of the Rx Descriptor Ring */
5122 E1000_WRITE_REG(hw, RDBAL, (unsigned long)rx_base & 0xffffffff);
5123 E1000_WRITE_REG(hw, RDBAH, (unsigned long)rx_base >> 32);
5125 E1000_WRITE_REG(hw, RDLEN, 128);
5127 /* Setup the HW Rx Head and Tail Descriptor Pointers */
5128 E1000_WRITE_REG(hw, RDH, 0);
5129 E1000_WRITE_REG(hw, RDT, 0);
5130 /* Enable Receives */
5132 if (hw->mac_type == e1000_igb) {
5134 uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL);
5135 reg_rxdctl |= 1 << 25;
5136 E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl);
5140 E1000_WRITE_REG(hw, RCTL, rctl);
5145 /**************************************************************************
5146 POLL - Wait for a frame
5147 ***************************************************************************/
5149 _e1000_poll(struct e1000_hw *hw)
5151 struct e1000_rx_desc *rd;
5152 unsigned long inval_start, inval_end;
5155 /* return true if there's an ethernet packet ready to read */
5156 rd = rx_base + rx_last;
5158 /* Re-load the descriptor from RAM. */
5159 inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
5160 inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5161 invalidate_dcache_range(inval_start, inval_end);
5163 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
5165 /* DEBUGOUT("recv: packet len=%d\n", rd->length); */
5166 /* Packet received, make sure the data are re-loaded from RAM. */
5167 len = le32_to_cpu(rd->length);
5168 invalidate_dcache_range((unsigned long)packet,
5169 (unsigned long)packet +
5170 roundup(len, ARCH_DMA_MINALIGN));
5174 static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length)
5176 void *nv_packet = (void *)txpacket;
5177 struct e1000_tx_desc *txp;
5179 unsigned long flush_start, flush_end;
5181 txp = tx_base + tx_tail;
5182 tx_tail = (tx_tail + 1) % 8;
5184 txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
5185 txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
5186 txp->upper.data = 0;
5188 /* Dump the packet into RAM so e1000 can pick them. */
5189 flush_dcache_range((unsigned long)nv_packet,
5190 (unsigned long)nv_packet +
5191 roundup(length, ARCH_DMA_MINALIGN));
5192 /* Dump the descriptor into RAM as well. */
5193 flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
5194 flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
5195 flush_dcache_range(flush_start, flush_end);
5197 E1000_WRITE_REG(hw, TDT, tx_tail);
5199 E1000_WRITE_FLUSH(hw);
5201 invalidate_dcache_range(flush_start, flush_end);
5202 if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)
5204 if (i++ > TOUT_LOOP) {
5205 DEBUGOUT("e1000: tx timeout\n");
5208 udelay(10); /* give the nic a chance to write to the register */
5214 _e1000_disable(struct e1000_hw *hw)
5216 /* Turn off the ethernet interface */
5217 E1000_WRITE_REG(hw, RCTL, 0);
5218 E1000_WRITE_REG(hw, TCTL, 0);
5220 /* Clear the transmit ring */
5221 E1000_WRITE_REG(hw, TDH, 0);
5222 E1000_WRITE_REG(hw, TDT, 0);
5224 /* Clear the receive ring */
5225 E1000_WRITE_REG(hw, RDH, 0);
5226 E1000_WRITE_REG(hw, RDT, 0);
5228 /* put the card in its initial state */
5230 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
5237 e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6])
5240 if (hw->mac_type >= e1000_82544)
5241 E1000_WRITE_REG(hw, WUC, 0);
5243 return e1000_init_hw(hw, enetaddr);
5247 _e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6])
5251 ret_val = e1000_reset(hw, enetaddr);
5253 if ((ret_val == -E1000_ERR_NOLINK) ||
5254 (ret_val == -E1000_ERR_TIMEOUT)) {
5255 E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val);
5257 E1000_ERR(hw, "Hardware Initialization Failed\n");
5261 e1000_configure_tx(hw);
5262 e1000_setup_rctl(hw);
5263 e1000_configure_rx(hw);
5267 /******************************************************************************
5268 * Gets the current PCI bus type of hardware
5270 * hw - Struct containing variables accessed by shared code
5271 *****************************************************************************/
5272 void e1000_get_bus_type(struct e1000_hw *hw)
5276 switch (hw->mac_type) {
5277 case e1000_82542_rev2_0:
5278 case e1000_82542_rev2_1:
5279 hw->bus_type = e1000_bus_type_pci;
5285 case e1000_80003es2lan:
5288 hw->bus_type = e1000_bus_type_pci_express;
5291 status = E1000_READ_REG(hw, STATUS);
5292 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5293 e1000_bus_type_pcix : e1000_bus_type_pci;
5298 /* A list of all registered e1000 devices */
5299 static LIST_HEAD(e1000_hw_list);
5301 static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno,
5302 unsigned char enetaddr[6])
5306 /* Assign the passed-in values */
5308 hw->cardnum = cardnum;
5310 /* Print a debug message with the IO base address */
5311 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
5312 E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0);
5314 /* Try to enable I/O accesses and bus-mastering */
5315 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
5316 pci_write_config_dword(devno, PCI_COMMAND, val);
5318 /* Make sure it worked */
5319 pci_read_config_dword(devno, PCI_COMMAND, &val);
5320 if (!(val & PCI_COMMAND_MEMORY)) {
5321 E1000_ERR(hw, "Can't enable I/O memory\n");
5324 if (!(val & PCI_COMMAND_MASTER)) {
5325 E1000_ERR(hw, "Can't enable bus-mastering\n");
5329 /* Are these variables needed? */
5330 hw->fc = e1000_fc_default;
5331 hw->original_fc = e1000_fc_default;
5332 hw->autoneg_failed = 0;
5334 hw->get_link_status = true;
5335 #ifndef CONFIG_E1000_NO_NVM
5336 hw->eeprom_semaphore_present = true;
5338 hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
5340 hw->mac_type = e1000_undefined;
5342 /* MAC and Phy settings */
5343 if (e1000_sw_init(hw) < 0) {
5344 E1000_ERR(hw, "Software init failed\n");
5347 if (e1000_check_phy_reset_block(hw))
5348 E1000_ERR(hw, "PHY Reset is blocked!\n");
5350 /* Basic init was OK, reset the hardware and allow SPI access */
5353 #ifndef CONFIG_E1000_NO_NVM
5354 /* Validate the EEPROM and get chipset information */
5355 #if !defined(CONFIG_MVBC_1G)
5356 if (e1000_init_eeprom_params(hw)) {
5357 E1000_ERR(hw, "EEPROM is invalid!\n");
5360 if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
5361 e1000_validate_eeprom_checksum(hw))
5364 e1000_read_mac_addr(hw, enetaddr);
5366 e1000_get_bus_type(hw);
5368 #ifndef CONFIG_E1000_NO_NVM
5369 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ",
5370 enetaddr[0], enetaddr[1], enetaddr[2],
5371 enetaddr[3], enetaddr[4], enetaddr[5]);
5373 memset(enetaddr, 0, 6);
5374 printf("e1000: no NVM\n");
5380 /* Put the name of a device in a string */
5381 static void e1000_name(char *str, int cardnum)
5383 sprintf(str, "e1000#%u", cardnum);
5386 /**************************************************************************
5387 TRANSMIT - Transmit a frame
5388 ***************************************************************************/
5389 static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
5391 struct e1000_hw *hw = nic->priv;
5393 return _e1000_transmit(hw, txpacket, length);
5396 /**************************************************************************
5397 DISABLE - Turn off ethernet interface
5398 ***************************************************************************/
5400 e1000_disable(struct eth_device *nic)
5402 struct e1000_hw *hw = nic->priv;
5407 /**************************************************************************
5408 INIT - set up ethernet interface(s)
5409 ***************************************************************************/
5411 e1000_init(struct eth_device *nic, bd_t *bis)
5413 struct e1000_hw *hw = nic->priv;
5415 return _e1000_init(hw, nic->enetaddr);
5419 e1000_poll(struct eth_device *nic)
5421 struct e1000_hw *hw = nic->priv;
5424 len = _e1000_poll(hw);
5426 net_process_received_packet((uchar *)packet, len);
5433 /**************************************************************************
5434 PROBE - Look for an adapter, this routine's visible to the outside
5435 You should omit the last argument struct pci_device * for a non-PCI NIC
5436 ***************************************************************************/
5438 e1000_initialize(bd_t * bis)
5446 /* Find and probe all the matching PCI devices */
5447 for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
5449 * These will never get freed due to errors, this allows us to
5450 * perform SPI EEPROM programming from U-boot, for example.
5452 struct eth_device *nic = malloc(sizeof(*nic));
5453 struct e1000_hw *hw = malloc(sizeof(*hw));
5455 printf("e1000#%u: Out of Memory!\n", i);
5461 /* Make sure all of the fields are initially zeroed */
5462 memset(nic, 0, sizeof(*nic));
5463 memset(hw, 0, sizeof(*hw));
5466 /* Generate a card name */
5467 e1000_name(nic->name, i);
5468 hw->name = nic->name;
5470 ret = e1000_init_one(hw, i, devno, nic->enetaddr);
5473 list_add_tail(&hw->list_node, &e1000_hw_list);
5477 /* Set up the function pointers and register the device */
5478 nic->init = e1000_init;
5479 nic->recv = e1000_poll;
5480 nic->send = e1000_transmit;
5481 nic->halt = e1000_disable;
5488 struct e1000_hw *e1000_find_card(unsigned int cardnum)
5490 struct e1000_hw *hw;
5492 list_for_each_entry(hw, &e1000_hw_list, list_node)
5493 if (hw->cardnum == cardnum)
5499 #ifdef CONFIG_CMD_E1000
5500 static int do_e1000(cmd_tbl_t *cmdtp, int flag,
5501 int argc, char * const argv[])
5503 unsigned char *mac = NULL;
5504 struct e1000_hw *hw;
5511 /* Make sure we can find the requested e1000 card */
5512 cardnum = simple_strtoul(argv[1], NULL, 10);
5513 hw = e1000_find_card(cardnum);
5515 mac = hw->nic->enetaddr;
5517 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
5521 if (!strcmp(argv[2], "print-mac-address")) {
5522 printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
5523 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
5527 #ifdef CONFIG_E1000_SPI
5528 /* Handle the "SPI" subcommand */
5529 if (!strcmp(argv[2], "spi"))
5530 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
5538 e1000, 7, 0, do_e1000,
5539 "Intel e1000 controller management",
5540 /* */"<card#> print-mac-address\n"
5541 #ifdef CONFIG_E1000_SPI
5542 "e1000 <card#> spi show [<offset> [<length>]]\n"
5543 "e1000 <card#> spi dump <addr> <offset> <length>\n"
5544 "e1000 <card#> spi program <addr> <offset> <length>\n"
5545 "e1000 <card#> spi checksum [update]\n"
5547 " - Manage the Intel E1000 PCI device"
5549 #endif /* not CONFIG_CMD_E1000 */