2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/clock.h>
31 #include <asm/arch/imx-regs.h>
33 #include <asm/errno.h>
35 DECLARE_GLOBAL_DATA_PTR;
38 #error "CONFIG_MII has to be defined!"
41 #ifndef CONFIG_FEC_XCV_TYPE
42 #define CONFIG_FEC_XCV_TYPE MII100
46 * The i.MX28 operates with packets in big endian. We need to swap them before
47 * sending and after receiving.
50 #define CONFIG_FEC_MXC_SWAP_PACKET
56 uint8_t data[1500]; /**< actual data */
57 int length; /**< actual length */
58 int used; /**< buffer in use or not */
59 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
62 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
63 static void swap_packet(uint32_t *packet, int length)
67 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
68 packet[i] = __swab32(packet[i]);
73 * The i.MX28 has two ethernet interfaces, but they are not equal.
74 * Only the first one can access the MDIO bus.
77 static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec)
79 return (struct ethernet_regs *)MXS_ENET0_BASE;
82 static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec)
89 * MII-interface related functions
91 static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr,
94 struct eth_device *edev = eth_get_dev_by_name(dev);
95 struct fec_priv *fec = (struct fec_priv *)edev->priv;
96 struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec);
98 uint32_t reg; /* convenient holder for the PHY register */
99 uint32_t phy; /* convenient holder for the PHY */
103 * reading from any PHY's register is done by properly
104 * programming the FEC's MII data register.
106 writel(FEC_IEVENT_MII, ð->ievent);
107 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
108 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
110 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
111 phy | reg, ð->mii_data);
114 * wait for the related interrupt
116 start = get_timer(0);
117 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
118 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
119 printf("Read MDIO failed...\n");
125 * clear mii interrupt bit
127 writel(FEC_IEVENT_MII, ð->ievent);
130 * it's now safe to read the PHY's register
132 *retVal = readl(ð->mii_data);
133 debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr,
138 static void fec_mii_setspeed(struct fec_priv *fec)
141 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
142 * and do not drop the Preamble.
144 writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
145 &fec->eth->mii_speed);
146 debug("fec_init: mii_speed %08x\n",
147 readl(&fec->eth->mii_speed));
149 static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr,
152 struct eth_device *edev = eth_get_dev_by_name(dev);
153 struct fec_priv *fec = (struct fec_priv *)edev->priv;
154 struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec);
156 uint32_t reg; /* convenient holder for the PHY register */
157 uint32_t phy; /* convenient holder for the PHY */
160 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
161 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
163 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
164 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
167 * wait for the MII interrupt
169 start = get_timer(0);
170 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
171 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
172 printf("Write MDIO failed...\n");
178 * clear MII interrupt bit
180 writel(FEC_IEVENT_MII, ð->ievent);
181 debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr,
187 static int miiphy_restart_aneg(struct eth_device *dev)
189 struct fec_priv *fec = (struct fec_priv *)dev->priv;
193 * Wake up from sleep if necessary
194 * Reset PHY, then delay 300ns
197 miiphy_write(dev->name, fec->phy_id, MII_DCOUNTER, 0x00FF);
199 miiphy_write(dev->name, fec->phy_id, MII_BMCR,
204 * Set the auto-negotiation advertisement register bits
206 miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE,
207 LPA_100FULL | LPA_100HALF | LPA_10FULL |
208 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
209 miiphy_write(dev->name, fec->phy_id, MII_BMCR,
210 BMCR_ANENABLE | BMCR_ANRESTART);
212 if (fec->mii_postcall)
213 ret = fec->mii_postcall(fec->phy_id);
218 static int miiphy_wait_aneg(struct eth_device *dev)
222 struct fec_priv *fec = (struct fec_priv *)dev->priv;
225 * Wait for AN completion
227 start = get_timer(0);
229 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
230 printf("%s: Autonegotiation timeout\n", dev->name);
234 if (miiphy_read(dev->name, fec->phy_id,
235 MII_BMSR, &status)) {
236 printf("%s: Autonegotiation failed. status: 0x%04x\n",
240 } while (!(status & BMSR_LSTATUS));
244 static int fec_rx_task_enable(struct fec_priv *fec)
246 writel(1 << 24, &fec->eth->r_des_active);
250 static int fec_rx_task_disable(struct fec_priv *fec)
255 static int fec_tx_task_enable(struct fec_priv *fec)
257 writel(1 << 24, &fec->eth->x_des_active);
261 static int fec_tx_task_disable(struct fec_priv *fec)
267 * Initialize receive task's buffer descriptors
268 * @param[in] fec all we know about the device yet
269 * @param[in] count receive buffer count to be allocated
270 * @param[in] size size of each receive buffer
271 * @return 0 on success
273 * For this task we need additional memory for the data buffers. And each
274 * data buffer requires some alignment. Thy must be aligned to a specific
275 * boundary each (DB_DATA_ALIGNMENT).
277 static int fec_rbd_init(struct fec_priv *fec, int count, int size)
282 /* reserve data memory and consider alignment */
283 if (fec->rdb_ptr == NULL)
284 fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
285 p = (uint32_t)fec->rdb_ptr;
287 puts("fec_mxc: not enough malloc memory\n");
290 memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT);
291 p += DB_DATA_ALIGNMENT-1;
292 p &= ~(DB_DATA_ALIGNMENT-1);
294 for (ix = 0; ix < count; ix++) {
295 writel(p, &fec->rbd_base[ix].data_pointer);
297 writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status);
298 writew(0, &fec->rbd_base[ix].data_length);
301 * mark the last RBD to close the ring
303 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status);
310 * Initialize transmit task's buffer descriptors
311 * @param[in] fec all we know about the device yet
313 * Transmit buffers are created externally. We only have to init the BDs here.\n
314 * Note: There is a race condition in the hardware. When only one BD is in
315 * use it must be marked with the WRAP bit to use it for every transmitt.
316 * This bit in combination with the READY bit results into double transmit
317 * of each data buffer. It seems the state machine checks READY earlier then
318 * resetting it after the first transfer.
319 * Using two BDs solves this issue.
321 static void fec_tbd_init(struct fec_priv *fec)
323 writew(0x0000, &fec->tbd_base[0].status);
324 writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
329 * Mark the given read buffer descriptor as free
330 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
331 * @param[in] pRbd buffer descriptor to mark free again
333 static void fec_rbd_clean(int last, struct fec_bd *pRbd)
336 * Reset buffer descriptor as empty
339 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status);
341 writew(FEC_RBD_EMPTY, &pRbd->status);
345 writew(0, &pRbd->data_length);
348 static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
350 imx_get_mac_from_fuse(mac);
351 return !is_valid_ether_addr(mac);
354 static int fec_set_hwaddr(struct eth_device *dev)
356 uchar *mac = dev->enetaddr;
357 struct fec_priv *fec = (struct fec_priv *)dev->priv;
359 writel(0, &fec->eth->iaddr1);
360 writel(0, &fec->eth->iaddr2);
361 writel(0, &fec->eth->gaddr1);
362 writel(0, &fec->eth->gaddr2);
365 * Set physical address
367 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
369 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
375 * Start the FEC engine
376 * @param[in] dev Our device to handle
378 static int fec_open(struct eth_device *edev)
380 struct fec_priv *fec = (struct fec_priv *)edev->priv;
382 debug("fec_open: fec_open(dev)\n");
383 /* full-duplex, heartbeat disabled */
384 writel(1 << 2, &fec->eth->x_cntrl);
387 #if defined(CONFIG_MX6Q)
388 /* Enable ENET HW endian SWAP */
389 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
391 /* Enable ENET store and forward mode */
392 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
396 * Enable FEC-Lite controller
398 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
400 #if defined(CONFIG_MX25) || defined(CONFIG_MX53)
403 * setup the MII gasket for RMII mode
406 /* disable the gasket */
407 writew(0, &fec->eth->miigsk_enr);
409 /* wait for the gasket to be disabled */
410 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
413 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
414 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
416 /* re-enable the gasket */
417 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
419 /* wait until MII gasket is ready */
421 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
422 if (--max_loops <= 0) {
423 printf("WAIT for MII Gasket ready timed out\n");
429 miiphy_wait_aneg(edev);
430 miiphy_speed(edev->name, fec->phy_id);
431 miiphy_duplex(edev->name, fec->phy_id);
434 * Enable SmartDMA receive task
436 fec_rx_task_enable(fec);
442 static int fec_init(struct eth_device *dev, bd_t* bd)
445 struct fec_priv *fec = (struct fec_priv *)dev->priv;
446 uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
450 /* Initialize MAC address */
454 * reserve memory for both buffer descriptor chains at once
455 * Datasheet forces the startaddress of each chain is 16 byte
458 if (fec->base_ptr == NULL)
459 fec->base_ptr = malloc((2 + FEC_RBD_NUM) *
460 sizeof(struct fec_bd) + DB_ALIGNMENT);
461 base = (uint32_t)fec->base_ptr;
463 puts("fec_mxc: not enough malloc memory\n");
466 memset((void *)base, 0, (2 + FEC_RBD_NUM) *
467 sizeof(struct fec_bd) + DB_ALIGNMENT);
468 base += (DB_ALIGNMENT-1);
469 base &= ~(DB_ALIGNMENT-1);
471 fec->rbd_base = (struct fec_bd *)base;
473 base += FEC_RBD_NUM * sizeof(struct fec_bd);
475 fec->tbd_base = (struct fec_bd *)base;
478 * Set interrupt mask register
480 writel(0x00000000, &fec->eth->imask);
483 * Clear FEC-Lite interrupt event register(IEVENT)
485 writel(0xffffffff, &fec->eth->ievent);
489 * Set FEC-Lite receive control register(R_CNTRL):
492 /* Start with frame length = 1518, common for all modes. */
493 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
494 if (fec->xcv_type == SEVENWIRE)
495 rcntrl |= FEC_RCNTRL_FCE;
496 else if (fec->xcv_type == RGMII)
497 rcntrl |= FEC_RCNTRL_RGMII;
498 else if (fec->xcv_type == RMII)
499 rcntrl |= FEC_RCNTRL_RMII;
501 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
503 writel(rcntrl, &fec->eth->r_cntrl);
505 if (fec->xcv_type == MII10 || fec->xcv_type == MII100)
506 fec_mii_setspeed(fec);
509 * Set Opcode/Pause Duration Register
511 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
512 writel(0x2, &fec->eth->x_wmrk);
514 * Set multicast address filter
516 writel(0x00000000, &fec->eth->gaddr1);
517 writel(0x00000000, &fec->eth->gaddr2);
521 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
524 /* FIFO receive start register */
525 writel(0x520, &fec->eth->r_fstart);
527 /* size and address of each buffer */
528 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
529 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
530 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
533 * Initialize RxBD/TxBD rings
535 if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
537 fec->base_ptr = NULL;
543 if (fec->xcv_type != SEVENWIRE)
544 miiphy_restart_aneg(dev);
551 * Halt the FEC engine
552 * @param[in] dev Our device to handle
554 static void fec_halt(struct eth_device *dev)
556 struct fec_priv *fec = (struct fec_priv *)dev->priv;
557 int counter = 0xffff;
560 * issue graceful stop command to the FEC transmitter if necessary
562 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
565 debug("eth_halt: wait for stop regs\n");
567 * wait for graceful stop to register
569 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
573 * Disable SmartDMA tasks
575 fec_tx_task_disable(fec);
576 fec_rx_task_disable(fec);
579 * Disable the Ethernet Controller
580 * Note: this will also reset the BD index counter!
582 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
586 debug("eth_halt: done\n");
591 * @param[in] dev Our ethernet device to handle
592 * @param[in] packet Pointer to the data to be transmitted
593 * @param[in] length Data count in bytes
594 * @return 0 on success
596 static int fec_send(struct eth_device *dev, volatile void* packet, int length)
601 * This routine transmits one frame. This routine only accepts
602 * 6-byte Ethernet addresses.
604 struct fec_priv *fec = (struct fec_priv *)dev->priv;
607 * Check for valid length of data.
609 if ((length > 1500) || (length <= 0)) {
610 printf("Payload (%d) too large\n", length);
615 * Setup the transmit buffer
616 * Note: We are always using the first buffer for transmission,
617 * the second will be empty and only used to stop the DMA engine
619 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
620 swap_packet((uint32_t *)packet, length);
622 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
623 writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer);
625 * update BD's status now
627 * - is always the last in a chain (means no chain)
628 * - should transmitt the CRC
629 * - might be the last BD in the list, so the address counter should
630 * wrap (-> keep the WRAP flag)
632 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
633 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
634 writew(status, &fec->tbd_base[fec->tbd_index].status);
637 * Enable SmartDMA transmit task
639 fec_tx_task_enable(fec);
642 * wait until frame is sent .
644 while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
647 debug("fec_send: status 0x%x index %d\n",
648 readw(&fec->tbd_base[fec->tbd_index].status),
650 /* for next transmission use the other buffer */
660 * Pull one frame from the card
661 * @param[in] dev Our ethernet device to handle
662 * @return Length of packet read
664 static int fec_recv(struct eth_device *dev)
666 struct fec_priv *fec = (struct fec_priv *)dev->priv;
667 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
668 unsigned long ievent;
669 int frame_length, len = 0;
672 uchar buff[FEC_MAX_PKT_SIZE];
675 * Check if any critical events have happened
677 ievent = readl(&fec->eth->ievent);
678 writel(ievent, &fec->eth->ievent);
679 debug("fec_recv: ievent 0x%lx\n", ievent);
680 if (ievent & FEC_IEVENT_BABR) {
682 fec_init(dev, fec->bd);
683 printf("some error: 0x%08lx\n", ievent);
686 if (ievent & FEC_IEVENT_HBERR) {
687 /* Heartbeat error */
688 writel(0x00000001 | readl(&fec->eth->x_cntrl),
691 if (ievent & FEC_IEVENT_GRA) {
692 /* Graceful stop complete */
693 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
695 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
697 fec_init(dev, fec->bd);
702 * ensure reading the right buffer status
704 bd_status = readw(&rbd->status);
705 debug("fec_recv: status 0x%x\n", bd_status);
707 if (!(bd_status & FEC_RBD_EMPTY)) {
708 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
709 ((readw(&rbd->data_length) - 4) > 14)) {
711 * Get buffer address and size
713 frame = (struct nbuf *)readl(&rbd->data_pointer);
714 frame_length = readw(&rbd->data_length) - 4;
716 * Fill the buffer and pass it to upper layers
718 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
719 swap_packet((uint32_t *)frame->data, frame_length);
721 memcpy(buff, frame->data, frame_length);
722 NetReceive(buff, frame_length);
725 if (bd_status & FEC_RBD_ERR)
726 printf("error frame: 0x%08lx 0x%08x\n",
727 (ulong)rbd->data_pointer,
731 * free the current buffer, restart the engine
732 * and move forward to the next buffer
734 fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd);
735 fec_rx_task_enable(fec);
736 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
738 debug("fec_recv: stop\n");
743 static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
745 struct eth_device *edev;
746 struct fec_priv *fec;
747 unsigned char ethaddr[6];
751 /* create and fill edev struct */
752 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
754 puts("fec_mxc: not enough malloc memory for eth_device\n");
759 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
761 puts("fec_mxc: not enough malloc memory for fec_priv\n");
766 memset(edev, 0, sizeof(*edev));
767 memset(fec, 0, sizeof(*fec));
770 edev->init = fec_init;
771 edev->send = fec_send;
772 edev->recv = fec_recv;
773 edev->halt = fec_halt;
774 edev->write_hwaddr = fec_set_hwaddr;
776 fec->eth = (struct ethernet_regs *)base_addr;
779 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
782 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
783 start = get_timer(0);
784 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
785 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
786 printf("FEC MXC: Timeout reseting chip\n");
793 * Set interrupt mask register
795 writel(0x00000000, &fec->eth->imask);
798 * Clear FEC-Lite interrupt event register(IEVENT)
800 writel(0xffffffff, &fec->eth->ievent);
803 * Set FEC-Lite receive control register(R_CNTRL):
806 * Frame length=1518; MII mode;
808 writel((PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT) | FEC_RCNTRL_FCE |
809 FEC_RCNTRL_MII_MODE, &fec->eth->r_cntrl);
810 fec_mii_setspeed(fec);
813 sprintf(edev->name, "FEC");
816 sprintf(edev->name, "FEC%i", dev_id);
817 fec->dev_id = dev_id;
819 fec->phy_id = phy_id;
821 miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write);
825 if (fec_get_hwaddr(edev, ethaddr) == 0) {
826 debug("got MAC address from fuse: %pM\n", ethaddr);
827 memcpy(edev->enetaddr, ethaddr, 6);
840 #ifndef CONFIG_FEC_MXC_MULTI
841 int fecmxc_initialize(bd_t *bd)
845 debug("eth_init: fec_probe(bd)\n");
846 lout = fec_probe(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
852 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
856 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
857 lout = fec_probe(bd, dev_id, phy_id, addr);
862 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
864 struct fec_priv *fec = (struct fec_priv *)dev->priv;
865 fec->mii_postcall = cb;