2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/clock.h>
31 #include <asm/arch/imx-regs.h>
33 #include <asm/errno.h>
35 DECLARE_GLOBAL_DATA_PTR;
38 #error "CONFIG_MII has to be defined!"
44 uint8_t data[1500]; /**< actual data */
45 int length; /**< actual length */
46 int used; /**< buffer in use or not */
47 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
50 struct fec_priv gfec = {
51 .eth = (struct ethernet_regs *)IMX_FEC_BASE,
63 * MII-interface related functions
65 static int fec_miiphy_read(char *dev, uint8_t phyAddr, uint8_t regAddr,
68 struct eth_device *edev = eth_get_dev_by_name(dev);
69 struct fec_priv *fec = (struct fec_priv *)edev->priv;
71 uint32_t reg; /* convenient holder for the PHY register */
72 uint32_t phy; /* convenient holder for the PHY */
76 * reading from any PHY's register is done by properly
77 * programming the FEC's MII data register.
79 writel(FEC_IEVENT_MII, &fec->eth->ievent);
80 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
81 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
83 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
84 phy | reg, &fec->eth->mii_data);
87 * wait for the related interrupt
89 start = get_timer_masked();
90 while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
91 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
92 printf("Read MDIO failed...\n");
98 * clear mii interrupt bit
100 writel(FEC_IEVENT_MII, &fec->eth->ievent);
103 * it's now safe to read the PHY's register
105 *retVal = readl(&fec->eth->mii_data);
106 debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr,
111 static void fec_mii_setspeed(struct fec_priv *fec)
114 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
115 * and do not drop the Preamble.
117 writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
118 &fec->eth->mii_speed);
119 debug("fec_init: mii_speed %#lx\n",
120 fec->eth->mii_speed);
122 static int fec_miiphy_write(char *dev, uint8_t phyAddr, uint8_t regAddr,
125 struct eth_device *edev = eth_get_dev_by_name(dev);
126 struct fec_priv *fec = (struct fec_priv *)edev->priv;
128 uint32_t reg; /* convenient holder for the PHY register */
129 uint32_t phy; /* convenient holder for the PHY */
132 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
133 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
135 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
136 FEC_MII_DATA_TA | phy | reg | data, &fec->eth->mii_data);
139 * wait for the MII interrupt
141 start = get_timer_masked();
142 while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
143 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
144 printf("Write MDIO failed...\n");
150 * clear MII interrupt bit
152 writel(FEC_IEVENT_MII, &fec->eth->ievent);
153 debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr,
159 static int miiphy_restart_aneg(struct eth_device *dev)
162 * Wake up from sleep if necessary
163 * Reset PHY, then delay 300ns
166 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_MIPGSR, 0x00FF);
168 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
173 * Set the auto-negotiation advertisement register bits
175 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_ANAR,
176 PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
177 PHY_ANLPAR_10 | PHY_ANLPAR_PSB_802_3);
178 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
179 PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
184 static int miiphy_wait_aneg(struct eth_device *dev)
190 * Wait for AN completion
192 start = get_timer_masked();
194 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
195 printf("%s: Autonegotiation timeout\n", dev->name);
199 if (miiphy_read(dev->name, CONFIG_FEC_MXC_PHYADDR,
200 PHY_BMSR, &status)) {
201 printf("%s: Autonegotiation failed. status: 0x%04x\n",
205 } while (!(status & PHY_BMSR_LS));
209 static int fec_rx_task_enable(struct fec_priv *fec)
211 writel(1 << 24, &fec->eth->r_des_active);
215 static int fec_rx_task_disable(struct fec_priv *fec)
220 static int fec_tx_task_enable(struct fec_priv *fec)
222 writel(1 << 24, &fec->eth->x_des_active);
226 static int fec_tx_task_disable(struct fec_priv *fec)
232 * Initialize receive task's buffer descriptors
233 * @param[in] fec all we know about the device yet
234 * @param[in] count receive buffer count to be allocated
235 * @param[in] size size of each receive buffer
236 * @return 0 on success
238 * For this task we need additional memory for the data buffers. And each
239 * data buffer requires some alignment. Thy must be aligned to a specific
240 * boundary each (DB_DATA_ALIGNMENT).
242 static int fec_rbd_init(struct fec_priv *fec, int count, int size)
247 /* reserve data memory and consider alignment */
248 if (fec->rdb_ptr == NULL)
249 fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
250 p = (uint32_t)fec->rdb_ptr;
252 puts("fec_mxc: not enough malloc memory\n");
255 memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT);
256 p += DB_DATA_ALIGNMENT-1;
257 p &= ~(DB_DATA_ALIGNMENT-1);
259 for (ix = 0; ix < count; ix++) {
260 writel(p, &fec->rbd_base[ix].data_pointer);
262 writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status);
263 writew(0, &fec->rbd_base[ix].data_length);
266 * mark the last RBD to close the ring
268 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status);
275 * Initialize transmit task's buffer descriptors
276 * @param[in] fec all we know about the device yet
278 * Transmit buffers are created externally. We only have to init the BDs here.\n
279 * Note: There is a race condition in the hardware. When only one BD is in
280 * use it must be marked with the WRAP bit to use it for every transmitt.
281 * This bit in combination with the READY bit results into double transmit
282 * of each data buffer. It seems the state machine checks READY earlier then
283 * resetting it after the first transfer.
284 * Using two BDs solves this issue.
286 static void fec_tbd_init(struct fec_priv *fec)
288 writew(0x0000, &fec->tbd_base[0].status);
289 writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
294 * Mark the given read buffer descriptor as free
295 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
296 * @param[in] pRbd buffer descriptor to mark free again
298 static void fec_rbd_clean(int last, struct fec_bd *pRbd)
301 * Reset buffer descriptor as empty
304 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status);
306 writew(FEC_RBD_EMPTY, &pRbd->status);
310 writew(0, &pRbd->data_length);
313 static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
316 * The MX27 can store the mac address in internal eeprom
317 * This mechanism is not supported now by MX51
322 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
325 for (i = 0; i < 6; i++)
326 mac[6-1-i] = readl(&iim->iim_bank_area0[IIM0_MAC + i]);
328 return is_valid_ether_addr(mac);
332 static int fec_set_hwaddr(struct eth_device *dev)
334 uchar *mac = dev->enetaddr;
335 struct fec_priv *fec = (struct fec_priv *)dev->priv;
337 writel(0, &fec->eth->iaddr1);
338 writel(0, &fec->eth->iaddr2);
339 writel(0, &fec->eth->gaddr1);
340 writel(0, &fec->eth->gaddr2);
343 * Set physical address
345 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
347 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
353 * Start the FEC engine
354 * @param[in] dev Our device to handle
356 static int fec_open(struct eth_device *edev)
358 struct fec_priv *fec = (struct fec_priv *)edev->priv;
360 debug("fec_open: fec_open(dev)\n");
361 /* full-duplex, heartbeat disabled */
362 writel(1 << 2, &fec->eth->x_cntrl);
366 * Enable FEC-Lite controller
368 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
373 * setup the MII gasket for RMII mode
376 /* disable the gasket */
377 writew(0, &fec->eth->miigsk_enr);
379 /* wait for the gasket to be disabled */
380 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
383 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
384 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
386 /* re-enable the gasket */
387 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
389 /* wait until MII gasket is ready */
391 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
392 if (--max_loops <= 0) {
393 printf("WAIT for MII Gasket ready timed out\n");
399 miiphy_wait_aneg(edev);
400 miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR);
401 miiphy_duplex(edev->name, CONFIG_FEC_MXC_PHYADDR);
404 * Enable SmartDMA receive task
406 fec_rx_task_enable(fec);
412 static int fec_init(struct eth_device *dev, bd_t* bd)
415 struct fec_priv *fec = (struct fec_priv *)dev->priv;
418 * reserve memory for both buffer descriptor chains at once
419 * Datasheet forces the startaddress of each chain is 16 byte
422 if (fec->base_ptr == NULL)
423 fec->base_ptr = malloc((2 + FEC_RBD_NUM) *
424 sizeof(struct fec_bd) + DB_ALIGNMENT);
425 base = (uint32_t)fec->base_ptr;
427 puts("fec_mxc: not enough malloc memory\n");
430 memset((void *)base, 0, (2 + FEC_RBD_NUM) *
431 sizeof(struct fec_bd) + DB_ALIGNMENT);
432 base += (DB_ALIGNMENT-1);
433 base &= ~(DB_ALIGNMENT-1);
435 fec->rbd_base = (struct fec_bd *)base;
437 base += FEC_RBD_NUM * sizeof(struct fec_bd);
439 fec->tbd_base = (struct fec_bd *)base;
442 * Set interrupt mask register
444 writel(0x00000000, &fec->eth->imask);
447 * Clear FEC-Lite interrupt event register(IEVENT)
449 writel(0xffffffff, &fec->eth->ievent);
453 * Set FEC-Lite receive control register(R_CNTRL):
455 if (fec->xcv_type == SEVENWIRE) {
457 * Frame length=1518; 7-wire mode
459 writel(0x05ee0020, &fec->eth->r_cntrl); /* FIXME 0x05ee0000 */
462 * Frame length=1518; MII mode;
464 writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */
466 fec_mii_setspeed(fec);
469 * Set Opcode/Pause Duration Register
471 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
472 writel(0x2, &fec->eth->x_wmrk);
474 * Set multicast address filter
476 writel(0x00000000, &fec->eth->gaddr1);
477 writel(0x00000000, &fec->eth->gaddr2);
481 long *mib_ptr = (long *)(IMX_FEC_BASE + 0x200);
482 while (mib_ptr <= (long *)(IMX_FEC_BASE + 0x2FC))
485 /* FIFO receive start register */
486 writel(0x520, &fec->eth->r_fstart);
488 /* size and address of each buffer */
489 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
490 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
491 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
494 * Initialize RxBD/TxBD rings
496 if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
498 fec->base_ptr = NULL;
504 if (fec->xcv_type != SEVENWIRE)
505 miiphy_restart_aneg(dev);
513 * Halt the FEC engine
514 * @param[in] dev Our device to handle
516 static void fec_halt(struct eth_device *dev)
518 struct fec_priv *fec = &gfec;
519 int counter = 0xffff;
522 * issue graceful stop command to the FEC transmitter if necessary
524 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
527 debug("eth_halt: wait for stop regs\n");
529 * wait for graceful stop to register
531 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
535 * Disable SmartDMA tasks
537 fec_tx_task_disable(fec);
538 fec_rx_task_disable(fec);
541 * Disable the Ethernet Controller
542 * Note: this will also reset the BD index counter!
544 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
548 debug("eth_halt: done\n");
553 * @param[in] dev Our ethernet device to handle
554 * @param[in] packet Pointer to the data to be transmitted
555 * @param[in] length Data count in bytes
556 * @return 0 on success
558 static int fec_send(struct eth_device *dev, volatile void* packet, int length)
563 * This routine transmits one frame. This routine only accepts
564 * 6-byte Ethernet addresses.
566 struct fec_priv *fec = (struct fec_priv *)dev->priv;
569 * Check for valid length of data.
571 if ((length > 1500) || (length <= 0)) {
572 printf("Payload (%d) too large\n", length);
577 * Setup the transmit buffer
578 * Note: We are always using the first buffer for transmission,
579 * the second will be empty and only used to stop the DMA engine
581 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
582 writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer);
584 * update BD's status now
586 * - is always the last in a chain (means no chain)
587 * - should transmitt the CRC
588 * - might be the last BD in the list, so the address counter should
589 * wrap (-> keep the WRAP flag)
591 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
592 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
593 writew(status, &fec->tbd_base[fec->tbd_index].status);
596 * Enable SmartDMA transmit task
598 fec_tx_task_enable(fec);
601 * wait until frame is sent .
603 while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
606 debug("fec_send: status 0x%x index %d\n",
607 readw(&fec->tbd_base[fec->tbd_index].status),
609 /* for next transmission use the other buffer */
619 * Pull one frame from the card
620 * @param[in] dev Our ethernet device to handle
621 * @return Length of packet read
623 static int fec_recv(struct eth_device *dev)
625 struct fec_priv *fec = (struct fec_priv *)dev->priv;
626 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
627 unsigned long ievent;
628 int frame_length, len = 0;
631 uchar buff[FEC_MAX_PKT_SIZE];
634 * Check if any critical events have happened
636 ievent = readl(&fec->eth->ievent);
637 writel(ievent, &fec->eth->ievent);
638 debug("fec_recv: ievent 0x%x\n", ievent);
639 if (ievent & FEC_IEVENT_BABR) {
641 fec_init(dev, fec->bd);
642 printf("some error: 0x%08lx\n", ievent);
645 if (ievent & FEC_IEVENT_HBERR) {
646 /* Heartbeat error */
647 writel(0x00000001 | readl(&fec->eth->x_cntrl),
650 if (ievent & FEC_IEVENT_GRA) {
651 /* Graceful stop complete */
652 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
654 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
656 fec_init(dev, fec->bd);
661 * ensure reading the right buffer status
663 bd_status = readw(&rbd->status);
664 debug("fec_recv: status 0x%x\n", bd_status);
666 if (!(bd_status & FEC_RBD_EMPTY)) {
667 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
668 ((readw(&rbd->data_length) - 4) > 14)) {
670 * Get buffer address and size
672 frame = (struct nbuf *)readl(&rbd->data_pointer);
673 frame_length = readw(&rbd->data_length) - 4;
675 * Fill the buffer and pass it to upper layers
677 memcpy(buff, frame->data, frame_length);
678 NetReceive(buff, frame_length);
681 if (bd_status & FEC_RBD_ERR)
682 printf("error frame: 0x%08lx 0x%08x\n",
683 (ulong)rbd->data_pointer,
687 * free the current buffer, restart the engine
688 * and move forward to the next buffer
690 fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd);
691 fec_rx_task_enable(fec);
692 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
694 debug("fec_recv: stop\n");
699 static int fec_probe(bd_t *bd)
701 struct eth_device *edev;
702 struct fec_priv *fec = &gfec;
703 unsigned char ethaddr[6];
705 /* create and fill edev struct */
706 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
708 puts("fec_mxc: not enough malloc memory\n");
712 edev->init = fec_init;
713 edev->send = fec_send;
714 edev->recv = fec_recv;
715 edev->halt = fec_halt;
717 fec->eth = (struct ethernet_regs *)IMX_FEC_BASE;
720 fec->xcv_type = MII100;
723 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
724 while (readl(&fec->eth->ecntrl) & 1)
728 * Set interrupt mask register
730 writel(0x00000000, &fec->eth->imask);
733 * Clear FEC-Lite interrupt event register(IEVENT)
735 writel(0xffffffff, &fec->eth->ievent);
738 * Set FEC-Lite receive control register(R_CNTRL):
741 * Frame length=1518; MII mode;
743 writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */
744 fec_mii_setspeed(fec);
746 sprintf(edev->name, "FEC_MXC");
748 miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write);
752 if (fec_get_hwaddr(edev, ethaddr) == 0) {
753 printf("got MAC address from EEPROM: %pM\n", ethaddr);
754 memcpy(edev->enetaddr, ethaddr, 6);
760 int fecmxc_initialize(bd_t *bd)
764 debug("eth_init: fec_probe(bd)\n");
765 lout = fec_probe(bd);