1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
9 #include <linux/errno.h>
12 #include <fsl_qe.h> /* For struct qe_firmware */
14 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
16 #elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
17 #include <spi_flash.h>
18 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
22 struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
24 void *fm_muram_base(int fm_idx)
26 return muram[fm_idx].base;
29 void *fm_muram_alloc(int fm_idx, size_t size, ulong align)
36 align_mask = align - 1;
37 save = muram[fm_idx].alloc;
39 off = (ulong)save & align_mask;
41 muram[fm_idx].alloc += (align - off);
42 off = size & align_mask;
44 size += (align - off);
45 if ((muram[fm_idx].alloc + size) >= muram[fm_idx].top) {
46 muram[fm_idx].alloc = save;
47 printf("%s: run out of ram.\n", __func__);
51 ret = muram[fm_idx].alloc;
52 muram[fm_idx].alloc += size;
53 memset((void *)ret, 0, size);
58 static void fm_init_muram(int fm_idx, void *reg)
62 muram[fm_idx].base = base;
63 muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE;
64 muram[fm_idx].alloc = base + FM_MURAM_RES_SIZE;
65 muram[fm_idx].top = base + CONFIG_SYS_FM_MURAM_SIZE;
69 * fm_upload_ucode - Fman microcode upload worker function
71 * This function does the actual uploading of an Fman microcode
74 static void fm_upload_ucode(int fm_idx, struct fm_imem *imem,
75 u32 *ucode, unsigned int size)
78 unsigned int timeout = 1000000;
80 /* enable address auto increase */
81 out_be32(&imem->iadd, IRAM_IADD_AIE);
82 /* write microcode to IRAM */
83 for (i = 0; i < size / 4; i++)
84 out_be32(&imem->idata, (be32_to_cpu(ucode[i])));
86 /* verify if the writing is over */
87 out_be32(&imem->iadd, 0);
88 while ((in_be32(&imem->idata) != be32_to_cpu(ucode[0])) && --timeout)
91 printf("Fman%u: microcode upload timeout\n", fm_idx + 1);
93 /* enable microcode from IRAM */
94 out_be32(&imem->iready, IRAM_READY);
98 * Upload an Fman firmware
100 * This function is similar to qe_upload_firmware(), exception that it uploads
101 * a microcode to the Fman instead of the QE.
103 * Because the process for uploading a microcode to the Fman is similar for
104 * that of the QE, the QE firmware binary format is used for Fman microcode.
105 * It should be possible to unify these two functions, but for now we keep them
108 static int fman_upload_firmware(int fm_idx,
109 struct fm_imem *fm_imem,
110 const struct qe_firmware *firmware)
114 size_t calc_size = sizeof(struct qe_firmware);
116 const struct qe_header *hdr;
119 printf("Fman%u: Invalid address for firmware\n", fm_idx + 1);
123 hdr = &firmware->header;
124 length = be32_to_cpu(hdr->length);
126 /* Check the magic */
127 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
128 (hdr->magic[2] != 'F')) {
129 printf("Fman%u: Data at %p is not a firmware\n", fm_idx + 1,
134 /* Check the version */
135 if (hdr->version != 1) {
136 printf("Fman%u: Unsupported firmware version %u\n", fm_idx + 1,
141 /* Validate some of the fields */
142 if ((firmware->count != 1)) {
143 printf("Fman%u: Invalid data in firmware header\n", fm_idx + 1);
147 /* Validate the length and check if there's a CRC */
148 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
150 for (i = 0; i < firmware->count; i++)
152 * For situations where the second RISC uses the same microcode
153 * as the first, the 'code_offset' and 'count' fields will be
154 * zero, so it's okay to add those.
156 calc_size += sizeof(u32) *
157 be32_to_cpu(firmware->microcode[i].count);
159 /* Validate the length */
160 if (length != calc_size + sizeof(u32)) {
161 printf("Fman%u: Invalid length in firmware header\n",
167 * Validate the CRC. We would normally call crc32_no_comp(), but that
168 * function isn't available unless you turn on JFFS support.
170 crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
171 if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
172 printf("Fman%u: Firmware CRC is invalid\n", fm_idx + 1);
176 /* Loop through each microcode. */
177 for (i = 0; i < firmware->count; i++) {
178 const struct qe_microcode *ucode = &firmware->microcode[i];
180 /* Upload a microcode if it's present */
181 if (be32_to_cpu(ucode->code_offset)) {
184 printf("Fman%u: Uploading microcode version %u.%u.%u\n",
185 fm_idx + 1, ucode->major, ucode->minor,
187 code = (void *)firmware +
188 be32_to_cpu(ucode->code_offset);
189 ucode_size = sizeof(u32) * be32_to_cpu(ucode->count);
190 fm_upload_ucode(fm_idx, fm_imem, code, ucode_size);
197 static u32 fm_assign_risc(int port_id)
200 risc_sel = (port_id & 0x1) ? FMFPPRC_RISC2 : FMFPPRC_RISC1;
201 val = (port_id << FMFPPRC_PORTID_SHIFT) & FMFPPRC_PORTID_MASK;
202 val |= ((risc_sel << FMFPPRC_ORA_SHIFT) | risc_sel);
207 static void fm_init_fpm(struct fm_fpm *fpm)
212 setbits_be32(&fpm->fmfpee, FMFPEE_EHM | FMFPEE_UEC |
213 FMFPEE_CER | FMFPEE_DER);
215 /* IM mode, each even port ID to RISC#1, each odd port ID to RISC#2 */
217 /* offline/parser port */
218 for (i = 0; i < MAX_NUM_OH_PORT; i++) {
219 port_id = OH_PORT_ID_BASE + i;
220 val = fm_assign_risc(port_id);
221 out_be32(&fpm->fpmprc, val);
224 for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
225 port_id = RX_PORT_1G_BASE + i;
226 val = fm_assign_risc(port_id);
227 out_be32(&fpm->fpmprc, val);
230 for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
231 port_id = TX_PORT_1G_BASE + i;
232 val = fm_assign_risc(port_id);
233 out_be32(&fpm->fpmprc, val);
236 port_id = RX_PORT_10G_BASE;
237 val = fm_assign_risc(port_id);
238 out_be32(&fpm->fpmprc, val);
240 port_id = TX_PORT_10G_BASE;
241 val = fm_assign_risc(port_id);
242 out_be32(&fpm->fpmprc, val);
244 /* disable the dispatch limit in IM case */
245 out_be32(&fpm->fpmflc, FMFP_FLC_DISP_LIM_NONE);
247 out_be32(&fpm->fmfpee, FMFPEE_CLEAR_EVENT);
249 /* clear risc events */
250 for (i = 0; i < 4; i++)
251 out_be32(&fpm->fpmcev[i], 0xffffffff);
254 out_be32(&fpm->fpmrcr, FMFP_RCR_MDEC | FMFP_RCR_IDEC);
257 static int fm_init_bmi(int fm_idx, struct fm_bmi_common *bmi)
264 /* alloc free buffer pool in MURAM */
265 base = fm_muram_alloc(fm_idx, FM_FREE_POOL_SIZE, FM_FREE_POOL_ALIGN);
267 printf("%s: no muram for free buffer pool\n", __func__);
270 offset = base - fm_muram_base(fm_idx);
272 /* Need 128KB total free buffer pool size */
274 blk = FM_FREE_POOL_SIZE / 256;
275 /* in IM, we must not begin from offset 0 in MURAM */
276 val |= ((blk - 1) << FMBM_CFG1_FBPS_SHIFT);
277 out_be32(&bmi->fmbm_cfg1, val);
279 /* disable all BMI interrupt */
280 out_be32(&bmi->fmbm_ier, FMBM_IER_DISABLE_ALL);
282 /* clear all events */
283 out_be32(&bmi->fmbm_ievr, FMBM_IEVR_CLEAR_ALL);
286 * set port parameters - FMBM_PP_x
287 * max tasks 10G Rx/Tx=12, 1G Rx/Tx 4, others is 1
288 * max dma 10G Rx/Tx=3, others is 1
289 * set port FIFO size - FMBM_PFS_x
290 * 4KB for all Rx and Tx ports
292 /* offline/parser port */
293 for (i = 0; i < MAX_NUM_OH_PORT; i++) {
294 port_id = OH_PORT_ID_BASE + i - 1;
295 /* max tasks=1, max dma=1, no extra */
296 out_be32(&bmi->fmbm_pp[port_id], 0);
297 /* port FIFO size - 256 bytes, no extra */
298 out_be32(&bmi->fmbm_pfs[port_id], 0);
301 for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
302 port_id = RX_PORT_1G_BASE + i - 1;
303 /* max tasks=4, max dma=1, no extra */
304 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
305 /* FIFO size - 4KB, no extra */
306 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
308 /* Tx 1G port FIFO size - 4KB, no extra */
309 for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
310 port_id = TX_PORT_1G_BASE + i - 1;
311 /* max tasks=4, max dma=1, no extra */
312 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
313 /* FIFO size - 4KB, no extra */
314 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
317 port_id = RX_PORT_10G_BASE - 1;
318 /* max tasks=12, max dma=3, no extra */
319 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
320 /* FIFO size - 4KB, no extra */
321 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
324 port_id = TX_PORT_10G_BASE - 1;
325 /* max tasks=12, max dma=3, no extra */
326 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
327 /* FIFO size - 4KB, no extra */
328 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
330 /* initialize internal buffers data base (linked list) */
331 out_be32(&bmi->fmbm_init, FMBM_INIT_START);
336 static void fm_init_qmi(struct fm_qmi_common *qmi)
338 /* disable all error interrupts */
339 out_be32(&qmi->fmqm_eien, FMQM_EIEN_DISABLE_ALL);
340 /* clear all error events */
341 out_be32(&qmi->fmqm_eie, FMQM_EIE_CLEAR_ALL);
343 /* disable all interrupts */
344 out_be32(&qmi->fmqm_ien, FMQM_IEN_DISABLE_ALL);
345 /* clear all interrupts */
346 out_be32(&qmi->fmqm_ie, FMQM_IE_CLEAR_ALL);
349 /* Init common part of FM, index is fm num# like fm as above */
350 int fm_init_common(int index, struct ccsr_fman *reg)
353 #if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR)
354 void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
355 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND)
356 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
357 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
359 rc = nand_read(get_nand_dev_by_index(0),
360 (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
361 &fw_length, (u_char *)addr);
362 if (rc == -EUCLEAN) {
363 printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
364 CONFIG_SYS_FMAN_FW_ADDR, rc);
366 #elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
367 struct spi_flash *ucode_flash;
368 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
371 #ifdef CONFIG_DM_SPI_FLASH
374 /* speed and mode will be read from DT */
375 ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
378 ucode_flash = dev_get_uclass_priv(new);
380 ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
381 CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
384 printf("SF: probe for ucode failed\n");
386 ret = spi_flash_read(ucode_flash, CONFIG_SYS_FMAN_FW_ADDR,
387 CONFIG_SYS_QE_FMAN_FW_LENGTH, addr);
389 printf("SF: read for ucode failed\n");
390 spi_flash_free(ucode_flash);
392 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
393 int dev = CONFIG_SYS_MMC_ENV_DEV;
394 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
395 u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
396 u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
397 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
400 printf("\nMMC cannot find device for ucode\n");
402 printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
405 (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
408 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
409 void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
414 /* Upload the Fman microcode if it's present */
415 rc = fman_upload_firmware(index, ®->fm_imem, addr);
418 env_set_addr("fman_ucode", addr);
420 fm_init_muram(index, ®->muram);
421 fm_init_qmi(®->fm_qmi_common);
422 fm_init_fpm(®->fm_fpm);
424 /* clear DMA status */
425 setbits_be32(®->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
428 setbits_be32(®->fm_dma.fmdmmr, FMDMMR_SBER);
430 return fm_init_bmi(index, ®->fm_bmi_common);