1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2012 Freescale Semiconductor, Inc.
4 * Roy Zang <tie-fei.zang@freescale.com>
10 #include <asm/immap_85xx.h>
11 #include <asm/fsl_serdes.h>
13 u32 port_to_devdisr[] = {
14 [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
15 [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
16 [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
17 [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
18 [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
19 [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
20 [FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9,
21 [FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10,
22 [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
23 [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
24 [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
25 [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
26 [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
27 [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
28 [FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5,
29 [FM2_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC2_6,
30 [FM2_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC2_9,
31 [FM2_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC2_10,
32 [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2_1,
33 [FM2_10GEC2] = FSL_CORENET_DEVDISR2_10GEC2_2,
36 static int is_device_disabled(enum fm_port port)
38 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
39 u32 devdisr2 = in_be32(&gur->devdisr2);
41 return port_to_devdisr[port] & devdisr2;
44 void fman_disable_port(enum fm_port port)
46 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
48 setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
51 void fman_enable_port(enum fm_port port)
53 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
55 clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
58 phy_interface_t fman_port_enet_if(enum fm_port port)
60 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
61 u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
63 if (is_device_disabled(port))
64 return PHY_INTERFACE_MODE_NONE;
66 if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
67 ((is_serdes_configured(XAUI_FM1_MAC9)) ||
68 (is_serdes_configured(XAUI_FM1_MAC10)) ||
69 (is_serdes_configured(XFI_FM1_MAC9)) ||
70 (is_serdes_configured(XFI_FM1_MAC10))))
71 return PHY_INTERFACE_MODE_XGMII;
73 if ((port == FM1_DTSEC9 || port == FM1_DTSEC10) &&
74 ((is_serdes_configured(XFI_FM1_MAC9)) ||
75 (is_serdes_configured(XFI_FM1_MAC10))))
76 return PHY_INTERFACE_MODE_NONE;
78 if ((port == FM2_10GEC1 || port == FM2_10GEC2) &&
79 ((is_serdes_configured(XAUI_FM2_MAC9)) ||
80 (is_serdes_configured(XAUI_FM2_MAC10)) ||
81 (is_serdes_configured(XFI_FM2_MAC9)) ||
82 (is_serdes_configured(XFI_FM2_MAC10))))
83 return PHY_INTERFACE_MODE_XGMII;
85 #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
86 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
87 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
88 #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
89 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
90 #define FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII 0x08000000
91 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
92 /* handle RGMII first */
93 if ((port == FM2_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
94 FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII))
95 return PHY_INTERFACE_MODE_RGMII;
97 if ((port == FM1_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
98 FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII))
99 return PHY_INTERFACE_MODE_RGMII;
101 if ((port == FM2_DTSEC6) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
102 FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII))
103 return PHY_INTERFACE_MODE_RGMII;
113 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
114 return PHY_INTERFACE_MODE_SGMII;
124 if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
125 return PHY_INTERFACE_MODE_SGMII;
137 /* check lane G on SerDes1 */
138 if (is_serdes_configured(QSGMII_FM1_A))
139 return PHY_INTERFACE_MODE_QSGMII;
145 /* check lane C on SerDes1 */
146 if (is_serdes_configured(QSGMII_FM1_B))
147 return PHY_INTERFACE_MODE_QSGMII;
153 /* check lane G on SerDes2 */
154 if (is_serdes_configured(QSGMII_FM2_A))
155 return PHY_INTERFACE_MODE_QSGMII;
161 /* check lane C on SerDes2 */
162 if (is_serdes_configured(QSGMII_FM2_B))
163 return PHY_INTERFACE_MODE_QSGMII;
169 return PHY_INTERFACE_MODE_NONE;